The Intel® Desktop Board CC820 may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized
errata are documented in the Intel Desktop Board CC820 Specification Update.
This product specification applies to only standard CC820 boards with BIOS identifier
CC82010A.86A.
Changes to this specification will be published in the Intel Desktop Board CC820 Specification
Update before being incorporated into a revision of this document.
Information in this doc um ent is provided in connection wi t h Intel® products. No license, express or implied, by est oppel or
otherwise, to any intell ectual property rights is granted by this document. E x cept as provided in Intel’s Terms and
Conditions of Sale for such products, Intel assumes no liability whatsoever, and I nt el dis claims any express or implied
warranty, relating to sale and/or use of I ntel products including liability or warranties relat i ng t o f i t ness for a particular
purpose, merchantability, or infringement of any patent, copyright or other int ellec t ual propert y right. Intel products are not
intended for use in medical, l i f e saving, or life sustai ni ng appl i cations.
Intel may make changes t o specifications and produc t descriptions at any tim e, without notice.
The Intel Desktop Board CC820 may contain design defects or errors known as errata that may cause t he product to
deviate from published spec i fications. Current charac terized errata are available on request.
Contact your local Int el sales office or your distributor to obtain the latest specifications before pl acing your product order.
Copies of documents whic h hav e an orderi ng number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
†
Third-party brands and names are the property of their respective owners.
Copyright 1999, Intel Corporation. All rights reserved.
Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
power and environmental requirements, and the BIOS for the Intel Desktop Board CC820. It
describes the standard product and available manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the CC820 board and its
components to the vendors, system integrators, and other engineers and technicians who need this
level of information. It is specifically not intended for general audiences.
What This Document Contains
ChapterDescription
1A description of the hardware used on the CC820 board
2A map of the resources of the board
3The features supported by the BIOS Setup program
4The contents of the BIOS Setup program’s menus and submenus
5A description of the BIOS error messages, beep codes, POST codes, and enhanced
diagnostics
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
✏
Notes call attention to important information.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions, which if not observed, can cause personal injury.
#Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX)When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the CC820 board, and X is the instance of the particular part at that
general location. For example, J5J1 is a connector, located at 5J. It is the first connector in the
5J area.
KBKilobyte (1024 bytes)
KbitKilobit (1024 bits)
MBMegabyte (1,048,576 bytes)
MbitMegabit (1,048,576 bits)
GBGigabyte (1,073,741,824 bytes)
xxhAn address or data value ending with a lowercase h indicates a hexadecimal value.
x.x VVolts. Voltages are DC unless otherwise specified.
†
This symbol is used to indicate third-party brands and names that are the property of their
The board’s compliance level with APM, ACPI, Plug and Play, and SMBIOS.Section 1.3, page 16
†
Support for system wake up using an add-in network interface card with remote
wake up capability
Support for system wake up using an add-in telephony device, such as a modem
Allows add-in SCSI controllers to use the same LED as the onboard I/O controller
Audio/Modem Riser connector
1.1.2 Manufacturing Option
Table 2 describes the CC820 board’s manufacturing option.
Table 2.Manufacturing Option
Audio
Audio Codec ’97 (AC ’97) compatible. The audio subsystem includes Creative Labs’
ES1373 AC ’97 Digital Controller with Crystal Semiconductor’s CS4297 Stereo Audio
Codec.
Version 2.3,
August 12, 1998,
Award Software International Inc.,
Dell Computer Corporation,
Hewlett-Packard Company,
Intel Corporation,
International Business Machines
Corporation,
Phoenix Technologies Limited,
American Megatrends Inc.,
and SystemSoft Corporation.
Version 1.1,
March 1996,
Intel Corporation.
Version 1.1,
September 23, 1998,
Compaq Computer Corporation,
Intel Corporation, Microsoft
Corporation, and NEC.
Version 2.0,
December 18, 1998,
Intel Corporation.
The CC820 desktop board supports processors that have a 19.3 A maximum current draw
(2 V core), or 18.4 A maximum current draw (1.6 V core). Using a processor not in compliance
with the above guidelines can damage the processor, the CC820 board, and the power supply. See
the processor’s data sheet for current usage requirements.
The CC820 board supports a single Pentium III or Pentium II processor. The host bus speed is
automatically selected. The processor must be secured by a retention mechanism attached to the
CC820 board.
The CC820 board supports a single 242-contact slot type processor as listed in Table 4.
Table 4.Supported Processors
Processor
Type
Pentium III processor450, 500, 550, and 600100512
Pentium II processor350, 400, and 450100512
Processor Designation
(MHz)
550E, 600E, 650, and 700100256
533B and 600B133512
533EB, 600EB, 667, and 733133256
Host Bus Frequency
(MHz)
L2 Cache Size
(KB)
NOTE
✏
66 MHz host bus frequency processors are not supported in this product. A hardware lockout is
provided so that if such a processor is installed, the CC820 board will not power-up.
All supported onboard memory can be cached, up to the cachability limit of the processor. See the
To be fully compliant with all applicable Intel® SDRAM memory specifications, the CC820 board
requires DIMMs that support the Serial Presence Detect (SPD) data structure. If non-SPD
DIMMs are installed, the system will not boot properly.
The CC820 desktop board has two DIMM sockets supporting 168-pin SDRAM DIMMs. When
installing memory in the CC820 desktop board, proper memory installation guidelines should be
followed as described in Section 1.5.2.
The CC820 desktop board supports the following memory features:
• 168-pin SDRAM DIMMs with gold-plated contacts
• 100 MHz SDRAM (only)
• 64 Mbit and 128 Mbit SDRAM component density (see Table 5 below)
• Minimum system memory: 32 MB
• Maximum system memory: 512 MB
• Unbuffered single or double-sided DIMMs
• Serial Presence Detect (SPD) memory (only)
• Non-ECC and ECC DIMMs (ECC DIMMs will operate in non-ECC mode only)
• 3.3 V memory (only)
• Suspend to RAM
Table 5.Supported DIMM Sizes and Configurations (non-ECC specified)
Total Number of
SDRAM Components
DIMM Size
32 MB44M x 6464 Mbit4M x 16
64 MB88M x 6464 Mbit8M x 8
64 MB8 (double sided)8M x 6464 Mbit4M x 16
64 MB48M x 64128 Mbit8M x 16
128 MB16 (double sided)16M x 6464 Mbit8M x 8
128 MB816M x 64128 Mbit16M x 8
128 MB8 (double sided)16M x 64128 Mbit8M x 16
256 MB16 (double sided)32M x 64128 Mbit16M x 8
*Non-ECC DIMMs are specified. ECC DIMM organization will be x72 and will have up to one additional SDRA M
component for each side of DI M M
on DIMM*
Non-ECC DIMM
Organization*
SDRAM Component
Density
SDRAM
Component
Organization
1.5.1 ECC Memory
The CC820 board supports both ECC and non-ECC DIMMs, however, ECC DIMMs will operate
in non-ECC mode only.
20
Product Description
1.5.2 DIMM Installation Guidelines
CAUTION
To be fully compliant with all applicable Intel SDRAM memory specifications, the CC820 desktop
board requires DIMMs that support the Serial Presence Detect (SPD) data structure.
The CC820 board requires supported DIMMs be installed under the guidelines listed below.
• If you have one DIMM, install it in Bank 0 (the memory slot closest to the processor). If only
one DIMM is installed in Bank 1, the system will still boot, however STR will not work.
• If you have two identical DIMMs (same size, same number of sides, both single-sided or both
double-sided), install them in either bank 0 or bank 1.
• If you have two DIMMs of different sizes (e.g., a 64 MB and 128 MB DIMM), install the
larger DIMM in Bank 0, and the smaller DIMM in Bank 1.
• If you have two DIMMs of the same size and one is single-sided and one is double-sided,
install the single-sided DIMM in Bank 0 and the double-sided DIMM in bank 1.
NOTE
✏
An ECC-type DIMM may have one or two additional SDRAM devices per side for ECC bit storage.
Do not count these when determining the number of SDRAM devices on the DIMM.
Table 6 summarizes the DIMM installation guidelines given above.
Table 6.Installation Guideline Summary
Types of DIMMs to be installed…Bank 0Bank 1
One DIMMDIMM(Empty)
Two DIMMs - Same size, same number of sides (both single-
or both double-sided)
Two DIMMs - Different sizesLarger DIMMSmaller DIMM
Two DIMMs - Same size, one is single-sided and one is
double-sided
For information aboutRefer to
The
PC Serial Presence Detect Specification
Obtaining copies of PC SDRAM specificationsSection 1.3, page 16
The Intel 820 chipset consists of the following devices:
• 82820 Memory Controller Hub (MCH) with Accelerated Hub Architecture (AHA) bus
• 82801AA I/O Controller Hub (ICH) with AHA bus
• 82802AB Firmware Hub (FWH)
• 82805AA Memory Translator Hub (MTH)
The chipset provides the host, memory, AGP, and I/O interfaces shown in Figure 3.
ATA33/66USBHost Bus
820 Chipset
82805AA
Memory
Translator
Hub (MTH)
SDRAM Bus
AGP Interface
82820
Memory Controller
Hub (MCH)
AHA
Bus
82801AA I/O Controller Hub
(ICH)
SMBus
PCI Bus
AC Link
Figure 3. Intel 820 Chipset Block Diagram
For information aboutRefer toThe Intel 820 chipsethttp://developer.intel.comThe resources used by the chipsetChapter 2The chipset’s compliance with ACPI, APM, AC ‘97Section 1.3, page 16
82802AB
Firmware Hub
(FWH)
LPC Bus
OM08890
22
Product Description
1.6.1 AGP
AGP is a high-performance interface for graphics-intensive applications, such as 3D applications.
While based on the PCI Local Bus Specification, Rev. 2.1, AGP is independent of the PCI bus and
is intended for exclusive use with graphical display devices. AGP overcomes certain limitations of
the PCI bus related to handling large amount of graphics data with the following features:
• Pipelined memory read and write operations that hide memory access latency
• Demultiplexing of address and data on the bus for nearly 100 percent efficiency
For information aboutRefer to
Obtaining the
Accelerated Graphics Port Interface Specification
Section 1.3, page 16
1.6.2 USB
The CC820 board has two USB ports; one USB peripheral can be connected to each port. For
more than two USB devices, an external hub can be connected to either port. The two USB ports
are implemented with stacked back panel connectors. The CC820 board fully supports UHCI and
uses UHCI-compatible software drivers. USB features include:
• Self-identifying peripherals that can be plugged in while the computer is running
• Automatic mapping of function to driver and configuration
• Support for isochronous and asynchronous transfer types over the same set of wires
• Support for up to 127 physical devices
• Guaranteed bandwidth and low latencies appropriate for telephony, audio, and other
applications
• Error-handling and fault-recovery mechanisms built into the protocol
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
For information aboutRefer to
The location of the USB connectors on the back panelFigure 9, page 50
The signal names of the USB connectorsTable 18, page 51
The USB specification and UHCISection 1.3, page 16
The CC820 board has two independent bus-mastering IDE interfaces. These interfaces support:
• ATA 33/66
• ATAPI devices (such as CD-ROM drives)
• ATA devices using the transfer modes listed in Table 64 on page 102
The BIOS supports logical block addressing (LBA) and extended cylinder head sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
The CC820 board supports laser servo (LS-120) diskette technology through its IDE interfaces.
The LS-120 drive can be configured as a boot device by setting the BIOS Setup program’s Boot
menu to one of the following:
• ARMD-FDD (ATAPI removable media device – floppy disk drive)
• ARMD-HDD (ATAPI removable media device – hard disk drive)
For information aboutRefer to
The location of the IDE connectorsFigure 11, page 57
The signal names of the IDE connectorsTable 31, page 58
BIOS Setup program’s Boot menuTable 70, page 108
1.6.3.2 SCSI Hard Drive Activity LED Connector
The SCSI hard drive activity LED connector is a 1 x 2-pin connector that allows add-in
SCSI controller to use the same LED as the IDE controller. This connector can be connected to the
LED output of the add-in controller card. The LED will indicate when data is being read or written
using the add-in controller.
For information aboutRefer to
The location of the SCSI hard drive activity LED connectorFigure 11, page 57
The signal names of the SCSI hard drive activity LED connectorTable 30, page 58
1.6.4 Real-Time Clock, CMOS SRAM, and Battery
The real-time clock is compatible with DS1287 and MC146818 components. The clock provides a
time-of-day clock and a multicentury calendar with alarm features and century rollover. The realtime clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are reserved for
BIOS use.
A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the standby current from the power supply extends the life of the battery.
The clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
The time, date, and CMOS values can be specified in the BIOS Setup program. The CMOS values
can be returned to their defaults by using the BIOS Setup program.
24
Product Description
✏ NOTE
If the battery and AC power fail, standard defaults, not custom defaults, will be loaded into CMOS
RAM at power-on.
✏ NOTE
The recommended method of accessing the date in systems with CC820 boards is indirectly from
the Real-Time Clock (RTC) via the BIOS. The BIOS on CC820 boards contains a century checking
and maintenance feature. This feature checks the two least significant digits of the year stored in
the RTC during each BIOS request (INT 1Ah) to read the date and, if less than 80 (i.e., 1980 is the
first year supported by the PC), updates the century byte to 20. This feature enables operating
systems and applications using the BIOS date/time services to reliably manipulate the year as a
four-digit value.
For information aboutRefer to
Proper date access in systems with CC820 boardsSection 1.2, page 16
1.7 I/O Controller
The SMSC LPC47M102 I/O Controller provides the following features:
• Low pin count (LPC) interface
• 3.3V operation
• Two serial ports
• One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port
(EPP) support
• Serial IRQ interface compatible with serialized IRQ support for PCI systems
• PS/2-style mouse and keyboard interfaces
• Interface for one 1.2 MB, 1.44 MB, or 2.88 MB diskette drive
• Intelligent power management, including a programmable wake up event interface
• PCI Power Management Support
• IrDA
• Fan control:
The BIOS Setup program provides configuration options for the I/O controller.
For information aboutRefer to
SMSC LPC47M102 I/O controllerhttp://www.smsc.com
†
1.0 compliant
Two fan control outputs
Two fan tachometer inputs
The CC820 board has two 9-pin D-Sub serial port connectors located on the back panel. The serial
ports’ NS16C550-compatible UARTs support data transfers at speeds up to 115.2 kbits/sec with
BIOS support. The serial ports can be assigned as COM1 (3F8h), COM2 (2F8h), COM3 (3E8h),
or COM4 (2E8h).
For information aboutRefer to
The location of the serial port connectorsFigure 9, page 50
The signal names of the serial port connectorsTable 20, page 52
1.7.2 Infrared Support
On the front panel connector, there are four pins that support Hewlett-Packard HSDL-1000
compatible infrared (IR) transmitters and receivers. In the BIOS Setup program, Serial Port B can
be directed to a connected IR device. (In this case, the serial port B connector on the back panel
cannot be used.) The IR connection can be used to transfer files to or from portable devices like
laptops, PDAs, and printers. The Infrared Data Association (IrDA) specification supports data
transfers of 115 Kbits/sec at a distance of 1 meter.
For information aboutRefer to
The infrared port connectorTable 42, page 67
Configuring serial port B for infrared applicationsSection 4.4.3, page 99
The IrDA specificationSection 1.3, page 16
1.7.3 Parallel Port
The connector for the multimode bidirectional parallel port is a 25-pin D-Sub connector located on
the back panel. In the BIOS Setup program, the parallel port can be configured for the following:
†
• Output only (PC AT
• Bi-directional (PS/2 compatible)
• EPP
• ECP
For information aboutRefer to
The location of the parallel port connectorFigure 9, page 50
The signal names of the parallel port connectorTable 19, page 51
-compatible mode)
26
Product Description
1.7.4 Diskette Drive Controller
The I/O controller supports one diskette drive that is compatible with the 82077 diskette drive
†
controller and supports both PC-AT
For information aboutRefer to
The location of the diskette drive connectorFigure 11, page 57
The signal names of the diskette drive connectorTable 32, page 59
The supported diskette drive capacities and sizesTable 65, page 103
and PS/2 modes.
1.7.5 Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel. The +5 V lines to these
†
connectors are protected with a PolySwitch
connection after an overcurrent condition is removed.
NOTE
✏
The keyboard is supported in the bottom PS/2 connector and the mouse is supported in the top
PS/2 connector. Power to the computer should be turned off before a keyboard or mouse is
connected or disconnected.
circuit that, like a self-healing fuse, reestablishes the
The keyboard controller contains the AMI keyboard and mouse controller code, provides the
keyboard and mouse control functions, and supports password protection for power-on/reset. A
power-on/reset password can be specified in the BIOS Setup program.
The keyboard controller also supports the hot-key sequence <Ctrl><Alt><Del> for a software
reset. This key sequence resets the computer’s software by jumping to the beginning of the BIOS
code and running the power-on self-test (POST).
For information aboutRefer to
The location of the keyboard and mouse connectorsFigure 9, page 50
The signal names of the keyboard and mouse connectorsTable 17, page 51
• Power management support for APM 1.2 and ACPI 1.0 (driver dependant)
• 3-D stereo enhancement
The Enhanced PCI Audio Subsystem has additional features described in Section 1.8.2.
1.8.1 Audio/Modem Riser (AMR) Connector
The AMR is a 46-pin riser connector that supports adding modems and/or audio risers to CC820
boards. The AMR interface, utilizing an AC ’97 2.1 link, includes support for audio codec,
modem codec, and audio/modem codec devices.
82801AA
I/O Controller Hub (ICH)
AMR Connector
Figure 4. Block Diagram of Audio Subsystem (with ICH and AMR)
For information aboutRefer to
The location of the Audio/Modem Riser connectorFigure 13, page 63
The signal names of the Audio/Modem Riser connectorTable 26, page 55
The AMR specificationSection 1.3, page 16
AC ’97 Link
OM09038
28
Product Description
1.8.2 Enhanced PCI Audio Subsystem (Optional)
The CC820 board offers an optional subsystem of AC ’97 V 1.03 compliant audio features
supported by the Creative Labs ES1373 digital controller with Crystal Semiconductor CS4297 (A)
codec. The enhanced PCI audio subsystem supports the following audio connectors:
• Audio inputs:
Three analog line-level stereo inputs for connection from line in, CD and aux
Two analog line-level inputs for speakerphone
One mono microphone input
Figure 5. Block Diagram of Audio Subsystem with Analog Codec and Digital Controller
The Creative Labs ES1373 digital controller with the Crystal Semiconductor CS4297 (A) codec
support the following features:
• Creative Labs ES1373 AC ’97 V1.03 Digital Controller:
PCI 2.1 compliant
PCI bus master for PCI audio
64-voice wavetable synthesizer
†
Aureal A3D
API, Sound Blaster Pro†, Roland MPU-401 MIDI, joystick compatible
Ensoniq 3D positional audio and Microsoft DirectSound† 3D support
• Crystal Semiconductor CS4297 (A) Stereo Audio Codec:
High performance 18-bit stereo full-duplex audio codec with up to 48 kHz sampling rate
Connects to the ES1373 digital controller using a five-wire digital interface
For information aboutRefer to
Obtaining audio software and utilitiesParagraph 1.2, page 16
• ATAPI-style connectors:
CD-ROM
Telephony
Auxiliary line in
Video source line in
• Back panel audio connectors:
MIDI/Game Port
Line out
Line in
Mic in
• Audio/Modem Riser (AMR)
For information aboutRefer to
The back panel audio connectorsSection 2.8.1, page 50
NOTE
✏
Some of the audio connectors are optional and are not installed on all versions of the CC820
board.
1.8.3.1 CD-ROM (Legacy-style 2 -mm) Connector
A 1 x 4-pin legacy-style 2-mm connector connects an internal CD-ROM drive to the audio mixer.
For information aboutRefer to
The location of the legacy-style 2-mm connectorFigure 10, page 54
The signal names of the legacy-style 2 mm connectorTable 26, page 55
30
Product Description
1.8.3.2 ATAPI CD-ROM Audio Connector
A 1 x 4-pin ATAPI-style connector connects an internal ATAPI CD-ROM drive to the audio
mixer.
For information aboutRefer to
The location of the ATAPI CD-ROM connectorFigure 10, page 54
The signal names of the ATAPI CD-ROM connectorTable 27, page 56
1.8.3.3 Telephony Connector
A 1 x 4-pin ATAPI-style connector connects the monoaural audio signals of an internal telephony
device to the audio subsystem. A monaural audio-in and audio-out signal interface is necessary for
telephony applications such as speakerphones, fax/modems, and answering machines.
For information aboutRefer to
The location of the telephony connectorFigure 10, page 54
The signal names of the telephony connectorTable 28, page 56
1.8.3.4 Auxiliary Line In Connector
A 1 x 4-pin ATAPI-style connector connects the left and right channel signals of an internal audio
device to the audio subsystem.
For information aboutRefer to
The location of the auxiliary line in connectorFigure 10, page 54
The signal names of the auxiliary line in connectorTable 29, page 56
The hardware management features enable the board to be compatible with the Wired for
Management (WfM) specification. The board has several hardware management features,
including the following:
• Hardware monitor component
• Chassis intrusion detection
• Fan control and monitoring (implemented on the SMSC LPC47M102 I/O controller)
For information aboutRefer to
The WfM specificationTable 3, page 16
Fan control functions of the SMSC LPC47M102 I/O controllerSection 1.7, page 25
1.9.1 Hardware Monitor Component
The hardware monitor component provides low-cost instrumentation capabilities. The features of
the component include:
• Internal ambient temperature sensing
• Remote thermal diode sensing for direct monitoring of processor temperature (if supported in
the processor)
• Power supply monitoring (+12, +5, +3.3, +2.5, 3.3 VSB, VCCP) to detect levels above or below
acceptable values
• SMBus interface
1.9.2 Chassis Intrusion Detect Connector
The board supports a chassis security feature that detects if the chassis cover is removed and
sounds an alarm (through the onboard speaker or PC chassis speaker, if either is present). For the
chassis intrusion circuit to function, the chassis’ power supply must be connected to AC power.
The security feature uses a mechanical switch on the chassis that attaches to the chassis intrusion
detect connector. The mechanical switch is closed for normal computer operation.
For information aboutRefer to
The location of the chassis intrusion detect connectorFigure 12, page 60
The signal names of the chassis intrusion detect connectorTable 38, page 62
32
1.10 Power Management Features
Power management is implemented at several levels, including:
• Software support:
Advanced Power Management (APM)
Advanced Configuration and Power Interface (ACPI)
• Hardware support:
Power connector
Fan connectors
Wake on LAN technology
Instantly Available technology
Wake on Ring
Resume on Ring
Wake from USB
Wake on Keyboard
Wake on PME#
Product Description
1.10.1 Software Support
The software support for power management includes:
• APM
• ACPI
If the CC820 board is used with an ACPI-aware operating system, the BIOS can provide ACPI
support. Otherwise, it defaults to APM support.
1.10.1.1 APM
APM makes it possible for the computer to enter an energy-saving standby mode. The standby
mode can be initiated in the following ways:
• Time-out period specified in the BIOS Setup program
• From the operating system, such as the Standby menu item in Windows† 98
In standby mode, the CC820 board can reduce power consumption by spinning down hard drives,
and reducing power to, or turning off of, VESA DPMS-compliant monitors. Power management
mode can be enabled or disabled in the BIOS Setup program.
While in standby mode, the system retains the ability to respond to external interrupts and service
requests, such as incoming faxes or network messages. Any keyboard or mouse activity brings the
system out of standby mode and immediately restores power to the monitor.
The BIOS enables APM by default; but the operating system must support an APM driver for the
power management features to work. For example, Windows 98 supports the power management
features upon detecting that APM is enabled in the BIOS.
For information aboutRefer to
Enabling or disabling power management in the BIOS Setup programSection 4.6, page 106
The CC820 board’s compliance level with APMTable 3, page 16
1.10.1.2 ACPI
ACPI gives the operating system direct control over the power management and Plug and Play
functions of a computer. The use of ACPI with the CC820 board requires an operating system that
provides full ACPI support. ACPI features include:
• Plug and Play (including bus and device enumeration) and APM support normally contained in
the BIOS
• Power management control of individual devices, add-in boards (some add-in boards may
require an ACPI-aware driver), video displays, and hard disk drives
• Methods for achieving less than 30-watt system operation in the power-on/standby sleeping
state
• A Soft-off feature that enables the operating system to power-off the computer
• Support for multiple wake up events (see Table 9 on page 36)
• Support for a front panel power and sleep mode switch. Table 7 lists the system states based
on how long the power switch is pressed, depending on how ACPI is configured with an
ACPI-aware operating system.
Table 7.Effects of Pressing the Power Switch
…and the power switch is
If the system is in this state…
Off (ACPI G2/G5 – Soft off)Less than four secondsPower-on
On (ACPI G0 – working state)Less than four secondsSoft-off/Standby
On (ACPI G0 – working state)More than four secondsFail safe power-off
Sleep (ACPI G1–sleeping state)Less than four secondsWake up
Sleep (ACPI G1–sleeping state)More than four secondsPower-off
For information aboutRefer to
The CC820 board’s compliance level with ACPISection 1.3, page 16
pressed for…the system enters this state
(ACPI G0 – working state)
(ACPI G1 – sleeping state)
(ACPI G2/G5 – Soft off)
(ACPI G0 – working state)
(ACPI G2/G5 – Soft off)
34
Product Description
1.10.1.2.1 System States and Power States
Under ACPI, the operating system directs all system and device power state transitions. The
operating system puts devices in and out of low-power states based on user preferences and
knowledge of how devices are being used by applications. Devices that are not being used can be
turned off. The operating system uses information from applications and user settings to put the
system as a whole into a low-power state.
Table 8 lists the power states supported by the CC820 board along with the associated system
power targets. See the ACPI specification for a complete description of the various system and
power states.
Table 8.Power States and Targeted System Power
Global StatesSleeping StatesCPU StatesDevice StatesTargeted System Power*
G0 – working
state
G1 – sleeping
state
G1 – sleeping
state
G2/S5S5 – Soft off.
G3 –
mechanical off.
AC power is
disconnected
from the
computer.
*Total system power is dependent on the system configuration, including add-in boards and peripherals powered by the
system chassis’ power supply.
**Dependent on the standby power consumpt i on of wake-up devices used in the system.
S0 – workingC0 – workingD0 – working
state
S1 – CPU stoppedC1 – stop
grant
S3 – Suspend to
RAM. Context
saved to RAM.
Context not saved.
Cold boot is
required.
No power to the
system.
No powerD3 – no power
No powerD3 – no power
No powerD3 – no power for
D1, D2, D3 –
device
specification
specific.
except for wake
up logic.
except for wake
up logic.
wake up logic,
except when
provided by
battery or external
source.
Full power > 60 W
5 W < power < 30 W
Power < 5 W **
Power < 5 W **
No power to t he system so
that service can be
performed.
Table 9 lists the devices or specific events that can wake the computer from specific states.
Table 9.Wake Up Devices and Events
These devices/events can wake up the computer……from this state
Power switchS1, S3, S5
RTC alarmS1, S3, S5
LAN (through Wake on LAN connector)S5
PME#S1, S3, S5
ModemS1, S3
IR commandS1, S3
USBS1, S3
PS/2 keyboardS1, S3
NOTE
✏
The use of these wake up events from an ACPI state requires an operating system that provides full
ACPI support. In addition, software, drivers, and peripherals must fully support ACPI wake
events.
1.10.1.2.3 Plug and Play
In addition to power management, ACPI provides controls and information so that the operating
system can facilitate Plug and Play device enumeration and configuration. ACPI is used only to
enumerate and configure CC820 board devices that do not have other hardware standards for
enumeration and configuration. PCI devices on the CC820 board, for example, are not enumerated
by ACPI.
36
Product Description
1.10.2 Hardware Support
CAUTION
If the Wake on LAN and Instantly Available technology features are used, ensure that the power
supply provides adequate +5 V standby current. Failure to do so can damage the power supply.
The total amount of standby current required depends on the wake devices supported and
manufacturing options. Refer to Section 2.11.3 on page 76 for additional information.
The CC820 board provides several hardware features that support power management, including:
• Power connector
• Fan connectors
• Wake on LAN technology
• Instantly Available technology
• Wake on Ring
• Resume on Ring
• Wake from USB
• Wake from PS/2 keyboard
• PME# wakeup support
Wake on LAN technology and Instantly Available technology require power from the +5 V
standby line. The sections discussing these features describe the incremental standby power
requirements for each.
Wake on Ring and Resume on Ring enable telephony devices to access the computer when it is in
a power-managed state. The method used depends on the type of telephony device (external or
internal) and the power management mode being used (APM or ACPI).
NOTE
✏
The use of Wake on Ring, Resume on Ring, and Wake from USB technologies from an ACPI state
requires an operating system that provides full ACPI support.
1.10.2.1 Power Connector
When used with an ATX-compliant power supply that supports remote power-on/ -off, the CC820
board can turn off the system power through software control. To enable soft-off control in
software, advanced power management must be enabled in the BIOS Setup program and in the
operating system. When the system BIOS receives the correct APM command from the operating
system, the BIOS turns off power to the computer.
With soft-off enabled, if power to the computer is interrupted by a power outage or a disconnected
power cord, when power resumes, the computer returns to the power state it was in before power
was interrupted (on or off).
For information aboutRefer to
The location of the power connectorFigure 12, page 60
The signal names of the power connectorTable 35, page 61
The ATX specificationSection 1.3, page 16
The CC820 board has three fan connectors. The functions of these connectors are described in
Table 10.
Table 10.Fan Connector Descriptions
ConnectorFunction
System fan (Fa n 1)Provides +12 V DC for a system or chassis fan. The fan voltage can be switched
on or off, depending on the power management state of the computer. A
tachometer feedback connection is also provided.
Power supply fan
control (Fan 2)
Processor fan (Fan 3)Provides +12 V DC for a processor fan or active fan heatsink.
For information aboutRefer to
The location of the fan connectorsFigure 12, page 60
The signal names of the fan connectorsSection 2.8.2.3, page 60
Provides +12 V DC for a system or chassis fan. Th e fan voltage can be switched
on or off, depending on the power management state of the computer. A
tachometer feedback connection is also provided.
38
Product Description
1.10.2.3 Wake on LAN Technology
CAUTION
For Wake on LAN technology, the 5-V standby line for the power supply must be capable of
providing adequate +5 V standby current. Failure to provide adequate standby current when
implementing Wake on LAN technology can damage the power supply. Refer to Section 2.11.3 on
page 76 for additional information.
Wake on LAN technology enables remote wakeup of the computer through a network. The LAN
subsystem PCI bus network adapter monitors network traffic at the Media Independent Interface.
†
Upon detecting a Magic Packet
the computer. Depending on the LAN implementation, the CC820 board supports Wake on LAN
technology in one of two ways:
• Through the Wake on LAN technology connector (APM or ACPI S5 only)
• Through the PCI bus PME# signal (for PCI 2.2 compliant LAN designs)
The Wake on LAN technology connector can be used with PCI bus network adapters that have a
remote wake up connector, as shown in Figure 6. Network adapters that are PCI 2.2 compliant
assert the wakeup signal through the PCI bus signal PME# (pin A19 on the PCI bus connectors).
frame, the LAN subsystem asserts a wakeup signal that powers up
Network
Interface
Card
PCI Slot
Remote
Wake up
connector
Wake on
LAN
technology
connector
Motherboard
OM08827
Figure 6. Using the Wake on LAN Technology Connector
For information aboutRefer to
The location of the Wake on LAN technology connectorFigure 12, page 60
The signal names of the Wake on LAN technology connectorTable 37, page 62
For Wake on LAN technology, the 5-V standby line for the power supply must be capable of
providing adequate +5 V standby current. Failure to provide adequate standby current when
implementing Wake on LAN technology can damage the power supply. Refer to Section 2.11.3 on
page 76 for additional information.
Instantly Available technology enables the CC820 board to enter the ACPI S3 (Suspend-to-RAM)
sleep-state. While in the S3 sleep-state, the computer will appear to be off (the power supply is
off, the fans are off, and the front panel LED is amber if dual-color, or off if single-color.) When
signaled by a wake-up device or event, the system quickly returns to its last known wake state.
Table 9 on page 36 lists the devices and events that can wake the computer from the S3 state.
The CC820 board supports the PCI Bus Power Management Interface Specification. For
information on the versions of this specification, see Section 1.3. Add-in boards that also support
this specification can participate in power management and can be used to wake the computer.
The use of Instantly Available technology requires operating system support and PCI 2.2
compliant add-in cards and drivers.
The standby power indicator LED shows that power is still present at the DIMM and PCI bus
connectors, even when the computer appears to be off. Figure 7 shows the location of the standby
power indicator LED.
DS7E1
OM08894
40
Figure 7. Location of Standby Power Indicator LED
1.10.2.5 Wake on Ring
The operation of Wake on Ring can be summarized as follows:
• Powers up the computer from either the APM soft-off mode or the ACPI S3 states
• Requires two calls to access the computer:
First call restores the computer
Second call enables access (when the appropriate software is loaded)
• Detects incoming calls differently for external as opposed to internal modems:
For external modems, the CC820 board hardware monitors the Ring-Indicate (RI) input of
serial port A (serial port B does not support this feature)
For internal modems, a cable must be routed from the modem to the Wake on Ring (WOR)
connector
The Wake on Ring connector is a manufacturing option.
For information aboutRefer to
The location of the Wake on Ring connectorFigure 12, page 62
The signal names of the Wake on Ring connectorTable 39, page 61
Product Description
1.10.2.6 Resume on Ring
The operation of Resume on Ring can be summarized as follows:
• Resumes operation from either the APM sleep mode or the ACPI S1 state
• Requires only one call to access the computer
• Detects incoming call similarly for external and internal modems; does not use the Wake on
Ring connector
• Requires modem interrupt be unmasked for correct operation
1.10.2.7 Wake from USB
USB bus activity wakes the computer from an ACPI S1 or S3 state.
NOTE
✏
Wake from USB requires the use of a USB peripheral that supports Wake from USB.
1.10.2.8 Wake from PS/2 Keyboard
PS/2 keyboard activity wakes the computer from an ACPI S1 or S3 state.
1.10.2.9 PME# Wakeup Support
When the PME# signal on the PCI bus is asserted, the computer wakes from an ACPI S1 or
S3 state.
Sections 2.2 - 2.6 contain several standalone tables. Table 11 describes the System Memory Map,
Table 12 shows the I/O Map, Table 13 lists the DMA Channels, Table 14 defines the PCI
Configuration Space Map, and Table 15 describes the Interrupts. The remaining sections in this
chapter are introduced by text found with their respective section headings.
2.2 Memory Map
Table 11.System Memory Map
Address Range (decimal)Address Range (hex)SizeDescription
1024 K - 524288 K100000 - 1FFFFFFF511 MBExtended memory
960 K - 1024 KF0000 - FFFFF64 KBRuntime BIOS
896 K - 960 KE0000 - EFFFF64 KBReserved
800 K - 896 KC8000 - DFFFF96 KBAvailable high DOS memory (open
to the PCI bus)
640 K - 800 KA0000 - C7FFF160 KBVideo memory and BIOS
639 K - 640 K9FC00 - 9FFFF1 KBExtended BIOS data (movable by
One of these ranges:
0320 - 0327
0330 - 0337
0340 - 0347
0350 - 0357
03761 byteSecondary IDE channel command port
0377, bits 6:07 bitsSecondary IDE channel status port
0378 - 037F8 bytesLPT1
0388 - 038B6 bytesAdLib† (FM synthesizer)
03F0 - 03F56 bytesDiskette channel 1
03F61 bytePrimary IDE channel command port
03F8 - 03FF8 bytesCOM1
04D0 - 04D12 bytesEdge/level triggered PIC
One of these ranges:
0530 - 0537
0E80 - 0E87
0F40 - 0F47
LPTn + 4008 bytesECP port, LPTn base address + 400h
0CF8 - 0CFB**4 bytesPCI configuration address register
0CF9***1 byteTurbo and reset control register
0CFC - 0CFF4 bytesPCI configuration data register
FFA0 - FFA78 bytesPrimary bus master IDE registers
FFA8 - FFAF8 bytesSecondary bus master IDE registers
96 contiguous bytes starting on a 128-byte
divisible boundary
64 contiguous bytes starting on a 64-byte
divisible boundary
64 contiguous bytes starting on a 64-byte
divisible boundary
32 contiguous bytes starting on a 32-byte
divisible boundary
16 contiguous bytes starting on a 16-byte
divisible boundary
4096 contiguous bytes starting on a 4096-byte
divisible boundary
* Default, but can be changed to another address range.
** Dword access only
*** By t e ac cess only
8 bytesWindows Sound System
ICH (ACPI + TCO)
CC820 board resource
Onboard audio controller
ICH (USB)
ICH (SMBus)
Intel 82801AA PCI bridge
Technical Reference
✏ NOTE
Some additional I/O addresses are not available due to ICH addresses aliassing. For information
about the ICH addressing, refer to Section 1.2 on page 16.
08- or 16-bitsAudio
18- or 16-bitsAudio / parallel port
28- or 16-bitsDiskette drive
38- or 16-bitsParallel port (for ECP or EPP) / audio
48- or 16-bitsDMA controller
516-bitsOpen
616-bitsOpen
716-bitsOpen
NMII/O channel check
0Reserved, interval timer
1Reserved, keyboard buffer full
2Reserved, cascade interrupt from slave PIC
3COM2*
4COM1*
5LPT2 (Plug and Play option) / Audio / User available
6Diskette drive
7LPT1*
8Real-time clock
9Reserved for ICH system management bus
10User available
11User available
12Onboard mouse port (if present, else user available)
13Reserved, math coprocessor
14Primary IDE (if present, else user available)
15Secondary IDE (if present, else user available)
*Default, but can be changed to another IRQ
Technical Reference
2.7 PCI Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected between the
PCI bus connectors and onboard PCI devices. The PCI specification specifies how interrupts can
be shared between devices attached to the PCI bus. In most cases, the small amount of latency
added by interrupt sharing does not affect the operation or throughput of the devices. In some
special cases where maximum performance is needed from a device, a PCI device should not share
an interrupt with other PCI devices. Use the following information to avoid sharing an interrupt
with a PCI add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
• INTA: By default, all add-in cards that require only one interrupt are in this category. For
almost all cards that require more than one interrupt, the first interrupt on the card is also
classified as INTA.
• INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is
classified as INTB. (This is not an absolute requirement.)
• INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a
The ICH PCI-to-LPC bridge has four programmable interrupt request (PIRQ) input signals. All
PCI interrupt sources either onboard or from a PCI add-in card connect to one of these
PIRQ signals. Because there are only four signals, some PCI interrupt sources are electrically tied
together on the CC820 board and therefore share the same interrupt.
For example, using Table 16 as a reference, assume an add-in card using INTA is plugged into PCI
Bus Connector 4. In PCI Bus Connector 4, INTA is connected to PIRQD. Since PIRQD is already
connected to PCI Audio and the ICH USB Controller, the add-in card now shares interrupts with
these onboard interrupt sources.
Table 16 lists the PIRQ signals used in the CC820 board and shows how the signals are connected
to the PCI bus connectors and to the onboard PCI interrupt sources.
Table 16.PCI Interrupt Routing Map
ICH PIRQ Signal Name
PCI Interrupt Source
AGP ConnectorINTAINTB
ICH Audio ControllerINT
ICH Modem ControllerINT
ICH USB ControllerINT
PCI AudioINT
PCI Bus Connector 1 (J4E1)INTAINTBINTCINTD
PCI Bus Connector 2 (J4D1)INTDINTAINTBINTC
PCI Bus Connector 3 (J4C1)INTCINTDINTAINTB
PCI Bus Connector 4 (J4B1)INTBINTCINTDINTA
PCI Bus Connector 5 (J4A1)INTCINTDINTAINTB
PIRQAPIRQBPIRQCPIRQD
NOTE
✏
The ICH can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 7, 10, 11, 14,
and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt.
However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ
lines to be connected to the same IRQ signal.
48
Technical Reference
2.8 Connectors
CAUTION
Only the back panel connectors of the CC820 board have overcurrent protection. The CC820
board’s internal connectors are not overcurrent protected and should connect only to devices
inside the computer’s chassis, such as fans and internal peripherals. Do not use these connectors
to power devices external to the computer’s chassis. A fault in the load presented by the external
devices could cause damage to the computer, the interconnecting cable, and the external devices
themselves.
This section describes the CC820 board’s connectors. The connectors can be divided into three
groups, as shown in Figure 8.
Figure 9 shows the location of the back panel connectors. The back panel connectors are colorcoded in compliance with PC 99 recommendations. The figure legend below lists the colors used.
E
B
ItemDescriptionColorFor more information see:
APS/2 mouse portGreenTable 17
BPS/2 keyboard portPurpleTable 17
CUSB port 0BlackTable 18
DUSB port 1BlackTable 18
EParallel portBurgundyTable 19
FSerial port ATealTable 20
GSerial port BTealTable 20
HMIDI / Game port (optional)GoldTable 21
IAudio line out (optional)Lime greenTable 22
JAudio line in (optional)Light blueTable 23
KMic in (optional)PinkTable 24
FIJKA
GCD
H
OM08896
Figure 9. Back Panel Connectors
50
Technical Reference
NOTE
✏
The back panel audio line out connector is designed to power headphones or amplified speakers
only. Poor audio quality occurs if passive (non-amplified) speakers are connected to this output.
Table 17.PS/2 Keyboard/Mouse Connectors
PinSignal Name
1Data
2Not connected
3Ground
4Fused +5 V
5Clock
6Not connected
Table 18.USB Connectors
PinSignal Name
1+5 V (fused)
2USBP0# [USBP1#]
3USBP0 [USBP1]
4Ground
Signal names in brackets ([ ]) are for USB port 1.
Table 19.Parallel Port Connector
PinStandard Signal NameECP Signal NameEPP Signal Name
1DCD (Data Carrier Detect)
2SIN# (Serial Data In)
3SOUT# (Serial Data Out)
4DTR (Data Terminal Ready)
5Ground
6DSR (Data Set Ready)
7RTS (Request to Send)
8CTS (Clear to Send)
9RI (Ring Indicator)
Table 21.MIDI/Game Port Connector
PinSignal NamePinSignal Name
1+5 V (fused)9+5 V (fused)
2JOY410JOY6
3JOYTIME011JOYTIME2
4Ground12MIDI-OUT
5Ground13JOYTIME3
6JOYTIME114JOY7
7JOY515MIDI-IN
8+5 V (fused)
Table 22.Audio Line Out Connector
PinSignal Name
TipAudio left out
RingAudio right out
SleeveGround
Table 23.Audio Line In Connector
PinSignal Name
TipAudio left in
RingAudio right in
SleeveGround
Table 24.Mic In Connector
PinSignal Name
TipMono in
RingMic bias voltage
SleeveGround
52
2.8.2 Midboard Connectors
The midboard connectors are divided into the following functional groups:
• Audio (see page 54)
CD-ROM (legacy style 2 mm connector)
AMR (Audio/Modem Riser)
ATAPI CD-ROM
Telephony
Auxiliary line in
• Peripheral interfaces and indicators (see page 57)
SCSI LED
Secondary IDE
Primary IDE
Diskette drive
• Hardware control (see page 60)
Power supply fan control (Fan 2)
Processor fan (Fan 3)
Power
System fan (Fan 1)
Wake on LAN technology
Chassis intrusion
Wake on Ring
Figure 10 shows the location of the audio connectors.
ACDEB
1
1
1
1
Reference
ItemDescriptionColor
Designator
ACD-ROM, Legacy style, 2 mm (optional) (see Table 25)N/AJ2C1
BAMR (Audio/Modem Riser) (see Table 26)N/AJ3F1
CCD-ROM, ATAPI style (optional) (see Table 27)BlackJ1F1
DTelephony, ATAPI style (optional) (see Table 28)GreenJ2F1
EAuxiliary line in, ATAPI style (optional) (see Table 29)WhiteJ2F2
Figure 12 shows the location of the hardware control and power connectors.
BA
1
20
10
1
1
1
1
1
FEG
D
Reference
ItemDescription
Designator
APower supply fan control (Fan 2) (see Table 33)J5L1
BProcessor fan (Fan 3) (see Table 34)J2M1
CMain power (see Table 35)J6M1
DSystem fan (Fan 1) (see Table 36)J8E1
EWake on LAN technology (see Table 37)J7C2
FChassis intrusion (see Table 38)J7C1
GWake on Ring (see Table 39)J7B2
Figure 12. Hardware Control and Power Connectors
For information aboutRefer to
The power connectorSection 1.10.2.1, page 37
The functions of the fan connectorsSection 1.10.2.2, page 38
Wake on LAN technologySection 1.10.2.3, page 39
Wake on Ring technologySection 1.10.2.5, page 41
1
11
C
OM08899
60
Technical Reference
Table 33.Power Supply Fan 2 Control
Connector (J5L1)
PinSignal Name
1Ground
2+12 V
3FAN2_TACH
Table 34.Processor Fan 3 Connector (J2M1)
PinSignal Name
1Ground
2+12 Volts
3FAN3_CPU_HDR_GND_R
Table 35.Main Power Connector (J6M2)
PinSignal NamePinSignal Name
1+3.3 V11+3.3 V
2+3.3 V12-12 V
3Ground13Ground
4+5 V14PS-ON# (power supply remote on/off)
5Ground15Ground
6+5 V16Ground
7Ground17Ground
8PWRGD (Power Good)18TP_PWRCONN_18
9+5 V (Standby)19+5 V
10+12 V20+5 V
Figure 13 shows the location of the add-in board connectors. Note the following considerations for
the PCI bus connectors:
• All of the PCI bus connectors are bus master capable.
• PCI bus connector 2 has SMBus signals routed to it. This enables PCI bus add-in boards with
SMBus support to access sensor data on the CC820 board. The specific SMBus signals are as
follows:
The SMBus clock line is connected to pin A40
The SMBus data line is connected to pin A41
ABCDEF
ItemDescriptionReference Designator
APCI bus connector 5 (see Table 40)J4A1
BPCI bus connector 4 (see Table 40)J4B1
CPCI bus connector 3 (see Table 40)J4C1
DPCI bus connector 2 (see Table 40)J4D1
EPCI bus connector 1 (see Table 40)J4E1
FAGP universal connector (see Table 41)J5E1
Table 40.PCI Bus Connectors (J4A1, J4B1, J4C1, J4D1, J4E1)
PinSignal NamePinSignal NamePinSignal NamePinSignal Name
A1Ground (TRST#)* B1-12 VA32AD16B32AD17
A2+12 VB2Ground (TCK)*A33+3.3 VB33C/BE2#
A3+5 V (TMS)*B3GroundA34FRAME#B34Ground
A4+5 V (TDI)*B4no connect (TDO)*A35GroundB35IRDY#
A5+5 VB5+5 VA36TRDY#B36+3.3 V
A6INTA#B6+5 VA37GroundB37DEVSEL#
A7INTC#B7INTB#A38STOP#B38Ground
A8+5 VB8INTD#A39+3.3 VB39LOCK#
A9ReservedB9no connect (PRSNT1#)* A40Reserved **B40PERR#
A10+5 V (I/O)B10ReservedA41Reserved ***B41+3.3 V
A11ReservedB11no connect (PRSNT2#)* A42GroundB42SERR#
A12GroundB12GroundA43PARB43+3.3 V
A13GroundB13GroundA44AD15B44C/BE1#
A14+3.3 V auxB14ReservedA45+3.3 VB45AD14
A15RST#B15GroundA46AD13B46Ground
A16+5 V (I/O)B16CLKA47AD11B47AD12
A17GNT#B17GroundA48GroundB48AD10
A18GroundB18REQ#A49AD09B49Ground
A19PME#B19+5 V (I/O)A50KeyB50Key
A20AD30B20AD31A51KeyB51Key
A21+3.3 VB21AD29A52C/BE0#B52AD08
A22AD28B22GroundA53+3.3 VB53AD07
A23AD26B23AD27A54AD06B54+3.3 V
A24GroundB24AD25A55AD04B55AD05
A25AD24B25+3.3 VA56GroundB56AD03
A26IDSELB26C/BE3#A57AD02B57Ground
A27+3.3 VB27AD23A58AD00B58AD01
A28AD22B28GroundA59+5 V (I/O)B59+5 V (I/O)
A29AD20B29AD21A60REQ64C#B60ACK64C#
A30GroundB30AD19A61+5 VB61+5 V
A31AD18B31+3.3 VA62+5 VB62+5 V
*These signals (in parentheses) are optional in the PCI s pec i fication and are not currently i m pl emented.
**On PCI bus connector 2, this pin is connected to the SM Bus clock line.
*** On PCI bus connector 2, this pin is connected to the SMBus data line.
64
Technical Reference
Table 41.AGP Interface Connector (J5E1)
PinSignal NamePinSignal NamePinSignal NamePinSignal Name
Figure 14 shows the location of the front panel connectors.
A
15
16
F
Front Panel Connector
(see Table 42)
Auxiliary Front Panel
Power LED Connector
(see Table 45)
CB
1
2
151
13
G
DE
J8G2
ItemPinsDescription
A9, 11, 13,
and 15
B5 and 7Reset switch
C1 and 3Hard drive activity LED
D2 and 4Power / Sleep / Message waiting LED
E6 and 8Power switch
F10 and 12No connect
G1 and 3Auxiliary Power LED connector
5GNDGround6FPBUT_INInPower switch
7FP_RESET#InReset switch8GNDGround
9+5 VOutIR Power10N/C
11IRRXInIrDA serial input12GNDGround
13GNDGround14(pin removed)Not connected
15IRTXOutIrDA serial output16+5 VOutPower
2HDR_BLNK_
GRN
YEL
OutFront panel green
LED
OutFront panel yellow
LED
2.8.3.1 Infrared Port Connector
Serial Port B can be configured to support an IrDA module connected to pins 9, 11, 13, and 15.
For information aboutRefer to
Infrared supportSection 1.7.2, page 26
Configuring serial port B for infrared applicationsSection 4.4.3, page 99
2.8.3.2 Reset Switch Connector
Pins 5 and 7 can be connected to a momentary SPST type switch that is normally open. When the
switch is closed, the CC820 board resets and runs the POST.
2.8.3.3 Hard Drive Activity LED Connector
Pins 1 and 3 can be connected to an LED to provide a visual indicator that data is being read from
or written to a hard drive. For the LED to function properly, an IDE drive must be connected to
the onboard IDE interface. The LED will also show activity for devices connected to the SCSI
hard drive activity LED connector.
For information aboutRefer to
The SCSI hard drive activity LED connectorSection 1.6.3.2, page 24
Pins 2 and 4 can be connected to a single- or dual-colored LED. Table 43 shows the possible
states for a single-colored LED. Table 44 shows the possible states for a dual-colored LED.
To use the message waiting function, ACPI must be enabled in the operating system and a
message-capturing application must be invoked.
2.8.3.5 Power Switch Connector
Pins 6 and 8 can be connected to a front panel momentary-contact power switch. The switch must
pull the SW_ON# pin to ground for at least 50 ms to signal the power supply to switch on or off.
(The time requirement is due to internal debounce circuitry on the CC820 board.) At least two
seconds must pass before the power supply will recognize another on/off signal.
2.8.3.6 Auxiliary Front Panel Power LED Connector
This connector duplicates the signals on pins 2 and 4 of the front panel connector.
Table 45.Auxiliary Front Panel Power LED Connector (J8J2)
PinSignal NameIn/OutDescription
1HDR_BLNK_GRNOutFront panel green LED
2No connect
3HDR_BLNK_YELOutFront panel yellow LED
68
Technical Reference
2.9 Jumper Block
CAUTION
Do not move any jumper with the power on. Always turn off the power and unplug the power cord
from the computer before changing a jumper setting. Otherwise, damage to the CC820 board
could occur.
The CC820 board has one jumper block. Figure 15 shows the location of the CC820 board’s
jumper block.
This 3-pin jumper block determines the BIOS Setup program’s mode. Table 46 describes the
jumper settings for the three modes: normal, configure, and recovery.
When the CC820 board jumper is set to configuration mode and the computer is powered-up, the
BIOS compares the CPU version and the microcode version in the BIOS and reports if the two
match.
The BIOS uses current configuration information and
passwords for booting.
Configure
2-3
Recovery
None
For information aboutRefer to
How to access the BIOS Setup programSection 4.1, page 93
The maintenance menu of the BIOS Setup programSection 4.2, page 94
BIOS recoverySection 3.6, page 88
13
13
After the POST runs, Setup runs automatically. The
maintenance menu is displayed.
The BIOS attempts to recover the BIOS configuration. A
recovery diskette is required.
70
Technical Reference
2.10 Mechanical Considerations
2.10.1 Form Factor
The CC820 board is designed to fit into an ATX-form-factor chassis. Figure 16 illustrates the
mechanical form factor for the CC820 board. Dimensions are given in inches. The outer
dimensions are 8.20 inches by 12.00 inches. Location of the I/O connectors and mounting holes
are in compliance with the ATX specification (see Section 1.3).
The back panel I/O shield for the CC820 board must meet specific dimension and material
requirements. Systems based on this CC820 board need the back panel I/O shield to pass
certification testing. Figure 17 and Figure 18 show the critical dimensions of the chassisdependent I/O shield for CC820 boards with and without audio. Dimensions are given in inches,
to a tolerance of ±0.02 inches.
These figures also indicate the position of each cutout. Additional design considerations for I/O
shields relative to chassis requirements are described in the ATX specification. See Section 1.3 for
information about the ATX specification.
NOTE
✏
An I/O shield compliant with the ATX chassis specification 2.01 is available from Intel.
Table 47 lists voltage and current measurements for a computer that contains the CC820 board and
the following:
• 533 MHz Intel Pentium III processor with a 512 KB cache
• 128 MB SDRAM
• 3.5-inch diskette drive
• 1.6 GB IDE hard disk drive
• 32X IDE CD-ROM drive
This information is provided only as a guide for calculating approximate power usage with
additional resources added.
Values for the Windows 98 desktop mode are measured at 640 x 480 x 256 colors and 60 Hz
refresh rate. AC watts are measured with a typical 200 W power supply, nominal input voltage
and frequency, with true RMS wattmeter at the line input.
✏ NOTE
Actual system power consumption depends upon system configuration. The power supply should
comply with the recommendations found in the ATX Form Factor Specification document (see
Table 3 on page 16 for specification information).
Table 47.Power Usage
DC Current at:
ModeAC Power+3.3 V+5 V+12 V-12 V+5 VSB
Windows 98 APM full on57.5 W3.32 A0.630 A0.030 A0.030 A0.080 A
Windows 98 APM Suspend31.3 W3.5 A0.600 A0.160 A0.030 A0.190 A
Windows 98 ACPI S037.0 W3.32 A0.630 A0.030 A0.030 A0.080 A
Windows 98 ACPI S130.7 W3.5 A0.600 A0.160 A0.030 A0.190 A
Windows 98 ACPI S33.4 W0.0 A0.0 A0.0 A0.0 A0.060 A
2.11.2 Add-in Board Considerations
The CC820 board is designed to provide 2 A (average) of +5 V current for each add-in board. The
total +5 V current draw for add-in boards in a fully-loaded CC820 board (all seven expansion slots
filled) must not exceed 14 A.
74
Technical Reference
2.11.3 Standby Current Requirements
CAUTION
If the standby current necessary to support multiple wake events from the PCI and/or USB buses
exceeds power supply capacity, the CC820 board may lose register settings stored in memory, etc.
Calculate the standby current requirements using the steps described below.
Power supplies used with this CC820 desktop board must be able to provide enough standby
current to support the Instantly Available (ACPI S3 sleep state) configuration as outlined in
Table 48 below.
Values are determined by specifications such as PCI 2.2. Actual measured values may vary.
To estimate the amount of standby current required for a particular system configuration, standby
current requirements of all installed components must be added to determine the total standby
current requirement. Refer to the descriptions in Table 48 and review the following steps.
1. Note the total CC820 desktop board standby current requirement.
2. Add to that the total PS/2 port standby current requirement if a wake-enabled device is
connected.
3. Add, from the PCI 2.2 slots (wake enabled) row, the total number of wake-enabled devices
installed (PCI and AGP) and multiply by the standby current requirement.
4. Add, from the PCI 2.2 slots (non-wake enabled) row, the total number of wake-enabled
devices installed (PCI and AGP) and multiply by the standby current requirement.
5. Add all additional wake enabled devices’ and non-wake enabled devices’ standby current
requirements as applicable.
6. Add all the required current totals from steps 1 through 5 to determine the total estimated
standby current power supply requirement.
Table 48.Standby Current Requirements
Instantly Available Current
Support (Estimated for
integrated board components)
Instantly Available Stand-by
Current Support
•Estimated for add-on
Components
•Add to Instantly Available
total current requirement
(See instructions above)
* Dependent upon system configuration
Description
Total for CC820 board200
PS/2 Ports*345
PCI 2.2 slots (wake enabled)375
PCI 2.2 slots (non-wake enabled)20
WOL header225
AMR*150
USB Ports*607.5 (maximum for both ports)
PCI/AGP requirements are calculated by totaling the following:
• One wake-enabled device @ 375 mA, plus
• Five non wake-enabled devices @ 20 mA each, plus
USB requirements are calculated as:
• One wake-enabled device @ 500 mA
• USB hub @ 100 mA
• Three USB non wake-enabled devices connected @ 2.5 mA each
NOTE
✏
Both USB ports are capable of providing up to 500 mA during normal G0/S0 operation. Only one
USB port will support up to 500 mA of stand-by-current (wake enabled device) during G1/S3
suspended operation. The other port may provide up to 7.5 mA (three non-wake enabled devices.)
during G1/S3 suspended operation.
2.11.4 Fan Power Requirements
The CC820 Desktop Board is capable of supplying 174 mA per fan connector (maximum).
2.11.5 Power Supply Considerations
CAUTION
The 5-V standby line for the power supply must be capable of providing adequate +5 V standby
current. Failure to do so can damage the power supply. The total amount of standby current
required depends on the wake devices supported and manufacturing options. Refer to
Section 2.11.3 on page 75 for additional information.
System integrators should refer to the power usage values listed in Table 47 when selecting a
power supply for use with the CC820 board.
Measurements account only for current sourced by the CC820 board while running in idle modes
of the started operating systems.
Additional power required will depend on configurations chosen by the integrator.
The power supply must comply with the following recommendations found in the indicated
sections of the ATX form factor specification.
• The potential relation between 3.3 VDC and +5 VDC power rails (Section 4.2)
• The current capability of the +5 VSB line (Section 4.2.1.2)
• All timing parameters (Section 4.2.1.3)
• All voltage tolerances (Section 4.2.2)
For information aboutRefer to
The ATX form factor specificationSection 1.3, page 16
76
Technical Reference
2.12 Thermal Considerations
CAUTION
An ambient temperature that exceeds the CC820 board’s maximum operating temperature by 5 oC
o
C could cause components to exceed their maximum case temperature and malfunction. For
to 10
information about the maximum operating temperature, see the environmental specifications in
Section 2.14.
CAUTION
System integrators should ensure that proper airflow is maintained in the voltage regulator circuit.
The voltage regulator area can reach a temperature of up to 85
Figure 19). Failure to do so may result in damage to the voltage regulator circuit.
Figure 19 shows the locations of the thermally sensitive components.
o
C in an open chassis (item A in
A
B
C
F
D
E
OM08904
AProcessor voltage regulator area
BProcessor
CIntel 82820 MCH
DIntel
EIntel 82801AA ICH
FES1373 digital controller (optional)
Table 49 provides maximum case temperatures for CC820 board components that are sensitive to
thermal changes. Case temperatures could be affected by the operating temperature, current load,
or operating frequency. Maximum case temperatures are important when considering proper
airflow to cool the CC820 board.
450 / 100 MHzN/A85º C (max thermal junction)Pentium III
500 / 100 MHzN/A85º C (max thermal junction)
550 / 100 MHzN/A85º C (max thermal junction)
600 / 100 MHzN/A85º C (max thermal junction)
550E / 100 MHzNA82º C (max thermal junction)
600E / 100 MHzNA82º C (max thermal junction)
650 / 100 MHzNA82º C (max thermal junction)
700 / 100 MHzNA80º C (max thermal junction)
533B / 133 MHzN/A90º C (max thermal junction)
600B / 133 MHzN/A85º C (max thermal junction)
533EB / 133 MHzNA82º C (max thermal junction)
600EB / 133 MHzNA82º C (max thermal junction)
667 / 133 MHzNA82º C (max thermal junction)
733 / 133 MHzNA80º C (max thermal junction)
350 / 100 MHz75º C (max thermal plate)NAPentium II processor
400 / 100 MHz75º C (max thermal plate)NA
450 / 100 MHz75º C (max thermal plate)80º C (max thermal junction)
SECCSECC2
Maximum Processor TemperatureProcessor
2.13 Reliability
The mean time between failures (MTBF) prediction is calculated using component and
subassembly random failure rates. The calculation is based on the Bellcore Reliability Prediction
Procedure, TR-NWT-000332, Issue 4, September 1991. The MTBF prediction is used to estimate
repair rates and spare parts requirements.
The Mean Time Between Failures (MTBF) data is calculated from predicted data at 55 ºC.
CC820 board MTBF: 169013.13 hours
78
2.14 Environmental
Table 50 lists the environmental specifications for the CC820 board.
The CC820 board uses an Intel/AMI BIOS, which is stored in flash memory and can be upgraded
using a disk-based program. In addition to the BIOS, the flash memory contains the BIOS Setup
program, POST, APM, the PCI auto-configuration utility, and Plug and Play support.
The CC820 board supports system BIOS shadowing, allowing the BIOS to execute from 64-bit
onboard write-protected DRAM.
The BIOS displays a message during POST identifying the type of BIOS and a revision code. The
initial production BIOS is identified as CC82010A.86A.
When the CC820 board jumper is set to configuration mode and the computer is powered-up, the
BIOS compares the CPU version and the microcode version in the BIOS and reports if the two
match.
For information aboutRefer to
The CC820 board’s compliance level with APM and Plug and PlaySection 1.3, page 16
The Intel 82802AB Firmware Hub (FWH) includes a 4 Mbit (512 KB) symmetrical flash memory
device. Internally, the device is grouped into eight 64-KB blocks that are individually erasable,
lockable, and unlockable. Figure 20 shows the organization of the flash memory.
The last two 8 KB blocks of the fault tolerance area are the parameter blocks. These blocks
contain data such as BIOS updates, vital product data (VPD), logo, System Management BIOS
(SMBIOS) interface, and extended system configuration data (ESCD) information. The backup
block contains a copy of the fault tolerance block.
The BIOS can automatically configure PCI devices. PCI devices may be onboard or add-in cards.
Autoconfiguration lets a user insert or remove PCI cards without having to configure the system.
When a user turns on the system after adding a PCI card, the BIOS automatically configures
interrupts, the I/O space, and other system resources. Any interrupts set to Available in Setup are
considered to be available for use by the add-in card.
PCI interrupts are distributed to available ISA interrupts that have not been assigned to system
resources. The assignment of PCI interrupts to ISA IRQs is non-deterministic. PCI devices can
share an interrupt, but an ISA device cannot share an interrupt allocated to PCI or to another ISA
device. Autoconfiguration information is stored in ESCD format.
For information about the versions of PCI and Plug and Play supported by the BIOS, see
Section 1.3.
OM08376
84
Overview of BIOS Features
3.3.2 PCI IDE Support
If you select Auto in the BIOS Setup program, the BIOS automatically sets up the two
PCI IDE connectors with independent I/O channel support. The IDE interface supports hard drives
up to Ultra ATA/66 and recognizes any ATAPI devices, including CD-ROM drives, tape drives,
and Ultra DMA drives (see Section 1.3 for the supported version of ATAPI). The BIOS
determines the capabilities of each drive and configures them to optimize capacity and
performance. To take advantage of the high capacities typically available today, hard drives are
automatically configured for Logical Block Addressing (LBA) and to PIO Mode 3 or 4, depending
on the capability of the drive. You can override the auto-configuration options by specifying
manual configuration in the BIOS Setup program.
To use Ultra ATA-66 features the following items are required:
• An Ultra ATA-66 peripheral device
• An Ultra ATA-66 compatible cable
• Ultra ATA-66 operating system device drivers
NOTE
✏
Ultra ATA-66 compatible cables are backward compatible with drives using slower IDE transfer
protocols. If an Ultra ATA/66 disk drive and a disk drive using any other IDE transfer protocol are
attached to the same cable, the maximum transfer rate between the drives is 33 MB/sec.
NOTE
✏
Do not connect an ATA device as a slave on the same IDE cable as an ATAPI master device. For
example, do not connect an ATA hard drive as a slave to an ATAPI CD-ROM drive.
SMBIOS is a Desktop Management Interface (DMI) compliant method for managing computers in
a managed network.
The main component of SMBIOS is the management information format (MIF) database, which
contains information about the computing system and its components. Using SMBIOS, a system
administrator can obtain the system types, capabilities, operational status, and installation dates for
system components. The MIF database defines the data and provides the method for accessing this
®
information. The BIOS enables applications such as Intel
SMBIOS. The BIOS stores and reports the following SMBIOS information:
• BIOS data, such as the BIOS revision level
• Fixed-system data, such as peripherals, serial numbers, and asset tags
• Resource data, such as memory size, cache size, and processor speed
• Dynamic data, such as event detection and error logging
Non-Plug and Play operating systems, such as Windows NT
obtaining the SMBIOS information. The BIOS supports an SMBIOS table interface for such
operating systems. Using this support, an SMBIOS service-level application running on a nonPlug and Play operating system can obtain the SMBIOS information.
LANDesk® Client Manager to use
†
, require an additional interface for
For information aboutRefer to
The CC820 board’s compliance level with SMBIOSSection 1.3, page 16
86
Overview of BIOS Features
3.5 BIOS Upgrades
A new version of the BIOS can be upgraded from a diskette using the Intel® Flash Memory Update
utility that is available from Intel. This utility supports the following BIOS maintenance functions:
• Update the flash BIOS from a file on a diskette
• Verify that the upgrade BIOS matches the target system to prevent accidentally installing an
incompatible BIOS
• BIOS boot block update
BIOS upgrades and the Intel Flash Memory Update Utility are available from Intel through the
Intel World Wide Web site.
NOTE
✏
Please review the instructions distributed with the upgrade utility before attempting a BIOS
upgrade.
For information aboutRefer to
The Intel World Wide Web siteSection 1.2, page 16
3.5.1 Language Support
The BIOS Setup program and help messages can be supported in 32 languages. Five languages are
available in the BIOS: US English, German, Italian, French, and Spanish. The default language is
US English that is present unless another language is selected in the BIOS Setup program.
The BIOS includes extensions to support the Kanji character set and other non-ASCII character
sets. Translations of other languages may become available at a later date.
3.5.2 Custom Splash Screen
During POST, an Intel splash screen is displayed by default. This splash screen can be replaced
with a custom splash screen. A utility is available from Intel to assist with creating a custom
splash screen. The custom splash screen can be programmed into the flash memory using the
BIOS upgrade utility. Information about this capability is available on the Intel Support World
Wide Web site. See Section 1.2 for more information about this site.
Some types of failure can destroy the BIOS. For example, the data can be lost if a power outage
occurs while the BIOS is being updated in flash memory. The BIOS can be recovered from a
diskette using the BIOS recovery mode. When recovering the BIOS, be aware of the following:
• Because of the small amount of code available in the non-erasable boot block area, there is no
video support. You can only monitor this procedure by listening to the speaker or looking at
the diskette drive LED.
• The recovery process may take several minutes; larger BIOS flash memory devices require
more time.
• Two beeps and the end of activity in the diskette drive indicate successful BIOS recovery.
• A series of continuous beeps indicates a failed BIOS recovery.
To create a BIOS recovery diskette, a bootable diskette must be created and the BIOS update files
copied to it. BIOS upgrades and the Intel Flash Memory Upgrade utility are available from Intel
Customer Support through the Intel World Wide Web site.
NOTE
✏
If the computer is configured to boot from an LS-120 diskette (in the Setup program’s Removable
Devices submenu), the BIOS recovery diskette must be a standard 1.44 MB diskette not a 120 MB
diskette.
For information aboutRefer to
The BIOS recovery mode jumper settingsTable 46, page 12
The Boot menu in the BIOS Setup programSection 4.7, page 108
Contacting Intel customer supportSection 1.2, page 16
88
Overview of BIOS Features
3.7 Boot Options
In the BIOS Setup program, the user can choose to boot from a diskette drive, hard drives,
CD-ROM, or the network. The default setting is for the diskette drive to be the first boot device,
the hard drive second, and the ATAPI CD-ROM third. The fourth device is disabled.
3.7.1 CD-ROM and Network Boot
Booting from CD-ROM is supported in compliance to the El Torito bootable CD-ROM format
specification. Under the Boot menu in the BIOS Setup program, ATAPI CD-ROM is listed as a
boot device. Boot devices are defined in priority order. If the CD-ROM is selected as the boot
device, it must be the first device with bootable media.
The network can be selected as a boot device. This selection allows booting from a network add-in
card with a remote boot ROM installed.
For information aboutRefer to
The El Torito specificationSection 1.3, page 16
3.7.2 Booting Without Attached Devices
For use in embedded applications, the BIOS has been designed so that after passing the POST, the
operating system loader is invoked even if the following devices are not present:
USB legacy support enables USB devices such as keyboards, mice, and hubs to be used even when
no operating system USB drivers are in place. USB legacy support is used in accessing the BIOS
Setup program and installing an operating system that supports USB. By default, USB legacy
support is set to Auto. The Auto setting enables USB legacy support if a supported USB device is
connected to the USB port.
This sequence describes how USB legacy support operates in the Auto (default) mode.
1. When you power up the computer, USB legacy support is disabled.
2. POST begins.
3. USB legacy support is temporarily enabled by the BIOS. This allows you to use a USB
keyboard to enter the BIOS Setup program or the maintenance mode.
4. POST completes and disables USB legacy support (unless it was set to Enabled or Auto while
in the BIOS Setup program).
5. The operating system loads. While the operating system is loading, USB keyboards and mice
are not recognized (unless USB legacy support was set to Enabled or Auto while in the BIOS
Setup program). After the operating system loads the USB drivers, the USB devices are
recognized by the operating system.
To install an operating system that supports USB, enable USB Legacy support or set it to Auto in
the BIOS Setup program and follow the operating system’s installation instructions. Once the
operating system is installed and the USB drivers have been configured, USB legacy support is no
longer used. USB Legacy support can be left enabled or set to Auto in the BIOS Setup program if
needed.
Notes on using USB legacy support:
• Do not use USB devices with an operating system that does not support USB. USB legacy is
not intended to support the use of USB devices in a non-USB aware operating system.
• USB legacy support is for keyboards, mice, and hubs only. Other USB devices are not
supported.
90
Overview of BIOS Features
3.9 BIOS Security Features
The BIOS includes security features that restrict access to the BIOS Setup program and who can
boot the computer. A supervisor password and a user password can be set for the BIOS Setup
program and for booting the computer, with the following restrictions:
• The supervisor password gives unrestricted access to view and change all the Setup options in
the BIOS Setup program. This is supervisor mode.
• The user password gives restricted access to view and change Setup options in the BIOS Setup
program. This is user mode.
• If only the supervisor password is set, pressing the <Enter> key at the password prompt of the
BIOS Setup program allows the user restricted access to Setup.
• If both the supervisor and user passwords are set, users can enter either the supervisor
password or the user password to access Setup. Users have access to Setup respective to
which password is entered.
• Setting the user password restricts who can boot the computer. The password prompt will be
displayed before the computer is booted. If only the supervisor password is set, the computer
boots without asking for a password. If both passwords are set, the user can enter either
password to boot the computer.
Table 53 shows the effects of setting the supervisor password and user password. This table is for
reference only and is not displayed on the screen.
Table 53.Supervisor and User Password Functions
Supervisor
Password Set
NeitherCan change all
Supervisor
only
User onlyN/ACan change all
Supervisor
and user set
*If no password is set, any user can change all Setup options.
For information aboutRefer to
Setting user and supervisor passwordsSection 4.5, page 106
The BIOS Setup program can be used to view and change the BIOS settings for the computer. The
BIOS Setup program is accessed by pressing the <F2> key after the Power-On Self-Test (POST)
memory test begins and before the operating system boot begins. The menu bar is shown below.
Maintenance MainAdvancedSecurityPowerBootExit
Table 54 lists the BIOS Setup program menu features.
Table 54.BIOS Setup Program Menu Bar
MaintenanceMainAdvancedSecurityPowerBootExit
Selects boot
options and
power supply
controls
✏
Clears
passwords and
enables
extended
configuration
mode
NOTE
Allocates
resources for
hardware
components
Configures
advanced
features
available
through the
chipset
Sets
passwords
and security
features
Configures
power
management
features
In this chapter, all examples of the BIOS Setup Program menu bar include the maintenance menu;
however, the maintenance menu is displayed only when the board is in configuration mode.
Section 2.9 on page 69 tells how to put the board in configuration mode.
Saves or
discards
changes to
Setup
program
options
Table 55 lists the function keys available for menu screens.
Table 55.BIOS Setup Program Function Keys
BIOS Setup Program Function KeyDescription
<←> or <→>Selects a different menu screen (Moves the cursor left or right)
<↑> or <↓>Selects an item (Moves the cursor up or down)
<Tab>Selects a field (Not implemented)
<Enter>Executes command or selects the submenu
<F9>Load the default configuration values for the current menu
<F10>Save the current values and exits the BIOS Setup program
<Esc>Exits the menu
4.2 Maintenance Menu
Maintenance
MainAdvancedSecurityPowerBootExit
Extended Configuration
The menu shown in Table 56 is for clearing Setup passwords and enabling extended configuration
mode. Setup only displays this menu in configuration mode. See Section 2.9 on page 69 for
configuration mode setting information.
Table 56.Maintenance Menu
FeatureOptionsDescription
Clear All PasswordsNo optionsClears the user and administrative passwords
Extended
Configuration
CPU InformationNo optionsDisplays CPU Information.
CPU Stepping
Signature
CPU Microcode
Update Revision
• Default (default)
• User-Defined
No optionsDisplays CPU’s Stepping Signature.
No optionsDisplays CPU’s Microcode Update Revision.
User Defined allows setting system control and video memory
cache mode. If selected here, will also display in the
Advanced Menu as: “Extended Menu:
Used
.”
94
4.2.1 Extended Configuration Submenu
BIOS Setup Program
Maintenance
MainAdvancedSecurityPowerBootExit
Extended Configuration
The submenu represented by Table 57 is for setting video memory cache mode. This submenu
becomes available when User Defined is selected under Extended Configuration.
Table 57.Extended Configuration Submenu
FeatureOptionsDescription
System Control: Video
Memory Cache Mode
• USWC
• UC (default)
Selects Uncacheable Speculative Write-Combining
(USWC) video memory cache mode. Full 32 byte contents
of the Write Combining buffer are written to memory as
required. Cache lookups are not performed. Both the
video driver and the application must support Write
Combining.
Selects UnCachable (UC) video memory cache mode.
This setting identifies the video memory range as
uncacheable by the processor. Memory writes are
performed in program order. Cache lookups are not
performed. Well suited for applications not supporting
Write Combining.
4.3 Main Menu
Maintenance
Main
AdvancedSecurityPowerBootExit
Table 58 describes the Main Menu. This menu reports processor and memory information and is
for configuring the system date and system time.
Table 58.Main Menu
FeatureOptionsDescription
BIOS VersionNo optionsDisplays the version of the BIOS.
Processor TypeNo optionsDisplays processor type.
Processor SpeedNo optionsDisplays processor speed.
System Bus
Frequency
Cache RAMNo optionsDisplays the size of second-level cache and whether it is
Total MemoryNo optionsDisplays the total amount of RAM.
Processor Serial
Number
System TimeHour, minute, and
System DateDay of week
No optionsDisplays the speed of the system Front Side Bus.
SecurityPowerBootExit
PCI Configuration
Boot Configuration
Peripheral Configuration
IDE Configuration
Diskette Configuration
Event Log Configuration
Video Configuration
Table 59 describes the Advanced Menu. This menu is used for setting advanced features that are
available through the chipset.
Table 59.Advanced Menu
FeatureOptionsDescription
Extended ConfigurationUsed
Not Used (default)
PCI ConfigurationNo optionsConfigures individual PCI slot’s IRQ priority. When
Boot Settings
Configuration
Peripheral ConfigurationNo optionsConfigures peripheral ports and devices. When selected,
IDE ConfigurationNo optionsSpecifies type of connected IDE device.
Diskette ConfigurationNo optionsWhen selected, displays the Floppy Options submenu.
Event Log ConfigurationNo optionsConfigures Event Logging. When selected, displays the
Video ConfigurationNo optionsConfigures video features. When selected, displays the
No optionsConfigures Plug and Play and the Numlock key, and resets
If
Used
is highlighted,
Extended Configuration under the Maintenance Menu.
selected, displays the PCI Configuration submenu.
configuration data. When selected, displays the Boot
Configuration submenu.
displays the Peripheral Configuration submenu.
Event Log Configuration submenu.
Video Configuration submenu.
User-Defined
has been selected in
96
4.4.1 PCI Configuration Submenu
BIOS Setup Program
MaintenanceMain
Advanced
SecurityPowerBootExit
PCI Configuration
Boot Configuration
Peripheral Configuration
IDE Configuration
Diskette Configuration
Event Log Configuration
Video Configuration
The submenu represented by Table 61 is for configuring the IRQ priority of PCI slots individually.
Table 60.PCI Configuration Submenu
FeatureOptionsDescription
PCI Slot 1 IRQ Priority
PCI Slot 2 IRQ Priority
PCI Slot 3 IRQ Priority
PCI Slot 4 IRQ Priority
PCI Slot 5 IRQ Priority• Whatever is
•Auto (default)
9
10
11
•Auto (default)
9
10
11
•Auto (default)
9
10
11
•Auto (default)
9
10
11
selected in slot 3
Allows selection of IRQ priority.
Allows selection of IRQ priority.
Allows selection of IRQ priority. IRQ Priority selections for
PCI slots 3 and 5 are linked. Selections made to PCI
Slot 3 IRQ Priority are repeated in PCI Slot 5 IRQ Priority.
Allows selection of IRQ priority.
No selections can be made to PCI Slot 5 IRQ Priority.
Selections made to PCI Slot 3 repeat in PCI Slot 5.