Intel 430HX Schematics

Page# Page Title

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Index Primary CPU (Socket 7) Clock Generator Triton II controller (TXC) Synchronous Cache, Lower 256K Synchronous Cache, Upper 256K Memory Modules 0 & 1 Memory Modules 2 & 3 System ROM PIIX3 PCI IDE Interface AIP Serial Ports, Floppy, USB Parallel Ports Keyboard/Mouse Ports Battery, RTC Circuit Front Panel PCI Slots 1 and 2 PCI Slots 3 and 4 ISA Slots Pullup/Pulldown Resistors Switching Power Supply Fiducials, Holes, Spare Gates Decoupling Caps

Released Rev. B.1

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

INTEL CORP.

Title

Index

Size Document Number REV

A 82430HX B.1

Date: June 19, 1997 Sheet 1 of 24

RP72 1 8 2 7 3 6 4 5

4.7K

RP75 1 8 2 7 3 6 4 5

4.7K

1 2

R100 4.7K

1 2

R98 4.7K

1 2

R111 4.7K

1 2

R97 4.7K

R86 330

1 2

R92 10K

1 2

R87

4.7K

1 2 1 2

R93

4.7k

R99

1 2

330

HD[0..63]

4..6

1

8

7

8

V

C

O

R

E

TP001 TP009 TP008 TP010

116 102 112 101 97 96 91 90 72 55 54 36 71 35 53 17 34 52 16 69 33 51 15 68 50 48 67 47 66 46 65 45 44 63 43 62 42 61 41 60 59 2 78 20 58 39 77 38 57 76 56 94 75 100 74 99 105 109 110 115 120 119 125 129

73 70 49 64 40 95 93 130

256

185 251 206 201 192 170 306 165 286 175 257 160 180 269 190 191 196 202 186 166

195 169

179 275

146 151 152

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63

DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7

CLK

BOFF# A20# INTR NMI IGNNE# KEN# FLUSH# AHOLD EADS# BRDY# RESET INV NA# BUSCHK# WB/WT# INIT SMI# R/S# PEN# STOPCLK#

HOLD EWBE#

BRDYC# NC/MPBOFF#

NC/BHOLD NC/CHOLD NC/DHOLD

U33 P5II

HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14

TP224

330

HDPA0 HDPA1 HDPA2 HDPA3 HDPA4 HDPA5 HDPA6 HDPA7

1 2

R131

330

1

TP225 TP226 TP227 TP228

HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63

HCLKCPU

3

HA20M3V#

HFLUSHA#

HBUSCHKA# HWB/WTA#

TP003 HPENA#

HHOLDA HEWBEA#

HBRDYC#

1 1 1 1

CPUVIO

RP71 1 8 2 7 3 6 4 5

1 8 2 7 3 6 4 5

HFRCMC# HPENA# HWB/WTA#

HAPA HBUSCHKA# HFLUSHA# HSMIACT#

HA20M#

15

10

4.7K

RP69

4.7K

HBOFF#

4 10

HIGNNE#

10

HAHOLD

4

HEADS#

4

HBRDY#

4

HRESET

10

HSTPCLK#

10 4

4

HINTR

HKEN#

4

HINIT HSMI#

HDPA0 HDPA1 HDPA2 HDPA3

HDPA7 HDPA6 HDPA5 HDPA4

U27D

9 8

7407S

HNMI

HNA#

R130

1 2

1

0

3

1

0

9

2

1

0

9

8

7

4

8

V

C

O

R

E

3

2

1

3

2

1

0

9

8

1

8

1

9

8

7

6

5

4

3

V

C

O

R

E

V

C

O

R

E

CPUVCORE

1

6

5

4

8

V

C

O

R

E

NC/SUSPACK#

ADSC#

FERR# HITM# PCHK#

LOCK#

APCHK#

CACHE#

FRCMC#

IERR#

SMIACT# PM0/BP0 PM1/BP1

TRST#

PICCLK

PICD0 PICD1

PHITM#

PHIT# PBGNT# PBREQ#

UPVRM#

VCC2DET

CPUTYP

NC/TEST1 NC/TEST3

BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7#

BREQ HIT#

HLDA

PRDY

ADS# D/C# W/R# M/IO

SCYC

D/P#

283

A3

301

A4

263

A5

319

A6

282

A7

300

A8

262

A9

318

A10

281

A11

280

A12

261

A13

279

A14

260

A15

278

A16

259

A17

277

A18

258

A19

276

A20

216

A21

228

A22

211

A23

222

A24

246

A25

227

A26

221

A27

265

A28

264

A29

302

A30

245

A31

285 270

252 271 253 272 254 273 255

140 229 268 250 215

230 248

AP

225 210 200 220

PCD

267

PWT

159 231

249 287 155

274 182 135

219 139 145 149

BP2

150

BP3

126

TCK

131

TDO

132

TDI

136

TMS

141

106 111 122

199 189 205 209

181

BF0

176

BF1

212

226 266

142

171 172 320

TP083 TP019

TP086 TP018

HAPA TP085

TP092 TP012 TP013

TP084 HFRCMC# TP011

TP087 TP088 TP090 TP089

TP007 TP091 TP006 TP005 TP004

TP002 TP014 TP021

TP020 TP015 TP017 TP016

HBF0 HBF1

TP093

TP901 1 TP097

HCPUTYPA

TP094 TP095 TP096

HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HA30 HA31

HBE#0 HBE#1 HBE#2 HBE#3 HBE#4 HBE#5 HBE#6 HBE#7

1

TP198

1

TP2

1

TP208

1

TP1

1

TP207

1

TP214

1

TP12

1

TP11

1

TP206

1

TP197

HSMIACT#

1

TP209

1

TP210

1

TP211

1

TP212

1

TP220

1

TP213

1

TP221

1

TP222

1

TP223

1

TP13

1

TP7

1

TP8

TP6 TP5 TP3 TP4

TP215

TP9 TP218

TP216 TP217 TP67

1 2

R115

330

R102

330

R104

330

1 2

1 1 1 1

1

1 1 1

HA[3..31]

HADSC#

HBE#[0..7]

HFERR# HHITM#

HLOCK#

HCACHE# HADS#

HD/C# HW/R# HM/IO#

4

CORE/BUS

SPEED RATIO

CPUVIO

1 3

HBF0R HBF1R

5

1 2

3/2X 2X 3X 5/2X

R110

R114

3..6

CPUVCORE

C195

1 2

1uF

C187

1 2

1uF

C218

1 2

1uF

C209

1 2

CPUVIO

C180

1 2

C194

1 2

C221

1 2

C207

1 2

C213

1 2

C174

1 2

C157

1 2

220uF C172

1 2

0.1uF

C161

1 2

0.1uF

C159

1 2

0.1uF

C173

1 2

0.1uF

1uF

5,6

4..6

10 4

4

4 4

4..6 4

JB2

1-3,2-4 3-5,2-4 1-3,4-6 3-5,4-6

JB2

2 4 6

JB3

330

C196

1 2

C188

1 2

C186

1 2

C205

1 2

C177

1 2

C178

1 2

C179

1 2

C206

1 2

C217

1 2

C193

1 2

C154

1 2

0.1uF

C158

1 2

0.1uF

C155

1 2

0.1uF

C160

1 2

0.1uF

C163

1 2

0.1uF

C212

1 2

1uF

C219

1 2

C199

1 2

C200

1 2

C201

1 2

C162

1 2

0.1uF

C164

1 2

0.1uF

C130

1 2

0.1uF

1uF

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Size Document Number REV

C 82430HX B.1

Date: June 19, 1997Sheet 2 of 24

INTEL CORP.

PRIMARY CPU (Socket 7)

2,4..6

HA27

1 2

HA27PU

1 2

R154

8.2K

1 2

14.31818MHz

C146 10pF

HA27PD

Y1

R88

4.7K

JUMPER 1

JUMPER 2

J25

1 2 3

JP3

1 2

JUMPER 3

J30

JP3

J29

JP3

C145 10pF

PIIX3OSC

CPUVIO

2

R89

4.7K

1

3 2 1

CLKSEL_PU

CPUVIO

C143

1 2

0.1uF C147

0.1uF C142

0.1uF C136

0.1uF C144

1 2

0.1uF

L13

1 2

1.5uH

1 2

CLKSEL0 CLKSEL1

ALWAYS STUFFED

PCLK(0:3)

50MHz 60MHz 66MHz

RESERVED

1 2

STUFF WITH 9169

12 11

BCLK(0:5) JUMPER 1

RESERVED

TP24

R80

0

48MCLKFB2

48MCLKPU

1

U26B

0

9

P

Q

D

R

CLK

C

8

Q

L

74ALS74AS 1 3

25MHz 30MHz 33MHz

XTAL1 XTAL2

1

CLKGENP1

CLKVCC3

TP029

2-3 2-3 1-2 1-2

5

13 12

2 3

1 14

20 26

8

2 3

JUMPER 2 JUMPER 3

2-3 1-2 2-3 1-2

R81

1 2

22

DO NOT STUFF

U28 OE

SEL0SEL1-

X1 X2

VCC3 VCC3

VCC3 ICS9159-02S

D CLK

KBD_CLK1R

48MCLKFB1

4

P

Q

R

C

Q

L

1

ISA14MHZ

APIC14MHZ

HCLK0 HCLK1 HCLK2 HCLK3

PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5

24MHZ 12MHZ

1 2

U26A

5

6

74ALS74AS

48MFFOUT1

GND GND

R70

10K

RAWOSC

2

R78 22

1

R2

1 2

220

OSCPULLDN

1 3

12 11

U3D 74LS125S

1 2

STUFF WITH 9159

R69

22 R66

22

R61

22 R62

22 R63

22 R64

22 R68

22 R71

22 R67

22

R72

22 R75

22

TP022

OSCR

1 2

R76

22 R73

22

1

X 1-2 2-3 2-3

1 R79 22

2

PIIX3OSCR

28

RAWOSCR

27

HCLKCPUR

6

HCLKSRAM0R

7

HCLKSRAM1R

9 10

PCLK0R

15

PCLK1R

16

PCLK2R

18

PCLK3R

19

PCLKTXCR

21

PCLKPIIX3R

22

AIPCLKR

24

KBD_CLKR

25

4 23

17 11

VCC

R77

1 2

22

R74

1 2

22

R5

1 2

22

HCLKSRAM0

HCLKSRAM1

TP922

PCLK0

PCLK1

PCLK2

PCLK3

PCLKTXC

PCLKPIIX3

USBCLK

AIPCLK

KBD_CLK

10

HCLKTXC

HCLKCPU

18

19

OSC

20

4

2

6

5

4

10

12

15

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Size Document Number REV

B 82430HX B.1

Date: June 19, 1997 Sheet 3 of 24

INTEL CORP.

Clock Generator

7,8

MCAS#[0..7]

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

10

15

PIIX3INIT

KBRST#

MCAS#0 MCAS#4 MCAS#2 MCAS#6

MCAS#3 MCAS#7 MCAS#1 MCAS#5

2,3,5,6

1 8 2 7 3 6 4 5

7,8

3

2

HCACHE# 2 2

HSMIACT# 2

HADS# 2 2 2 2 2

3

HCLKTXC

RP67

10

RP68

10

HKEN#

HBRDY# HNA# HAHOLD HEADS# HBOFF#

HA[3..31]

MA[2..11]

MP[0..7]

MWE#

MD[0..63]

U2B

74HCT14S

4

7 7 8 8

R153

1 2

22

KBRST

MAA0 MAA1 MAB0 MAB1

1 2

MCAS#R0 MCAS#R1 MCAS#R2 MCAS#R3 MCAS#R4 MCAS#R5 MCAS#R6 MCAS#R7

MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11

HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HA30 HA31

MRAS#R0 MRAS#R1 MRAS#R2 MRAS#R3 TP027 TP026 TP025 TP024

MP0 MP1 MP2 MP3 MP4 MP5 MP6 MP7

MWE#R

U16A

74ALS32S

2

HLOCK#

2,5,6

HW/R#

2

HD/C#

2

HM/IO#

2

HHITM#

HBE#[0..7]

H

B

B E #

1

2

1

2

6

5

0

1

9

8

2

7

8

5

6

5

1

9

A

H

B

E

N

B

A

S

H

C

O

A

R

D

M

O

L

F

D

#

D

S

M D 6 2

1 6

M D 6 2

U27A

7407S

I

L

K

F

S

Y

#

A

D

I

#

C

N

T #

M

D

5

6

3

4

5

6

7

8

9

0

1

7

4

3

1

3

6

4

0

9

0

9

8

7

2

7

0

M

D

5

6

4

5

6

7

8

9

0

1

CPUVIO

275

A3

315

A4

252

A5

316

A6

312

A7

272

A8

271

A9

311

A10

291

A11

251

A12

310

A13

270

A14

290

A15

250

A16

309

A17

289

A18

269

A19

249

A20

273

A21

254

A22

253

A23

294

A24

293

A25

274

A26

313

A27

314

A28

255

A29

295

A30

292

A31

121

RAS0#

110

RAS1#

109

RAS2#

96

RAS3#

187

RAS4#

197

RAS5#

186

RAS6#

196

RAS7#

145

CAS0#

159

CAS1#

131

CAS2#

173

CAS3#

130

CAS4#

144

CAS5#

120

CAS6#

172

CAS7#

276

MAA0

236

MAA1

296

MAB0

256

MAB1

317

MA2

297

MA3

277

MA4

257

MA5

237

MA6

298

MA7

258

MA8

319

MA9

318

MA10

278

MA11

133

MPD0

123

MPD1

146

MPD2

113

MPD3

132

MPD4

124

MPD5

134

MPD6

122

MPD7

HINITD

MWE#

M D 6 3

5 5

M D 6 3

1 2

235

3

7

1

2

1

2

1

2

3

5

3

1

3

7

9

1

3

4

3

9

8

2

7

M

D

W

K

C

H

B

/

E

A

L

I

E

I

C

R

N

C

O

T

7

6

O

#

H

C

M

#

/

E

K

#

I

#

# N V

M

D

4

5

3

4

5

6

7

8

9

0

1

2

7

5

7

5

2

1

7

6

5

4

8

4

2

1

9

8

4

2

3

1

9

8

M

D

4

5

4

5

6

7

8

9

0

1

2

3

2

R91

330

1

HINIT

H

E

D

#

6

0

1

2

3

4

5

6

2

3

1

6

5

2

6

5

4

3

2

1

0

1

H

B

H

D

E

D

6

5

4

3

2

1

0

6

1

#

3

2

M

D

3

4

3

4

5

6

7

8

9

0

1

2

1

9

6

2

4

2

0

9

7

6

1

8

0

4

1

9

0

5

0

2

M

D

3

4

5

6

7

8

9

0

1

2

3

2

H

D

5

6

7

8

9

0

1

6

4

3

2

1

2

3

H

D

5

6

7

8

9

0

M

D

2

3

9

0

1

2

1

7

3

2

7

6

4

8

6

3

M

D

2

3

9

0

1

2

3

H

D

5

4

5

2

3

4

5

6

8

9

0

1

0

1

0

8

6

8

1

6

4

3

1

4

2

1

3

H

D

4

5

7

8

9

0

1

2

3

4

5

6

M

D

1

2

9

0

1

2

3

4

5

6

7

8

2

1

9

7

1

5

0

8

7

4

9

7

8

9

7

0

9

4

8

M

D

2

4

5

6

7

8

0

1

2

3

H

D

4

6

7

1

2

0

7

2

H D 4 6

M D 1 8

2

0

2

8

M

D

1

8

9

H

D

4

3

4

5

1

2

1

7

8

4

H

D

4

3

4

5

M

D

1

5

6

7

5

2

3

6

2

4

M

D

1

5

6

7

MRAS#R[0..3]

H

D

3

4

8

9

0

1

2

1

3

2

1

3

8

5

6

5

7

H

D

3

4

8

9

0

1

2

M

D

1

0

1

2

3

4

5

3

9

8

6

5

M

D

1

0

1

2

3

4

H

D

2

3

9

0

1

2

3

4

5

6

7

1

9

7

4

8

3

2

4

9

8

9

0

6

5

H

D

2

3

9

0

1

2

3

4

5

6

7

M

D

1

2

3

4

5

6

7

8

9

2

1

8

4

2

1

9

7

6

1

0

1

3

4

0

8

6

1

M

D

1

2

3

4

5

6

7

8

9

H D 2 8

M D 0

H D 2 8

2 0 4

H D 2 7

3 0 4

M D 0

H

D

2

6

7

2

1

0

9

2

1

H

D

2

5

6

C

A

D

V

S

#

2 7 9

MRAS#R0 MRAS#R2 MRAS#R1 MRAS#R3

H

D

2

0

1

2

3

4

5

2

1

2

0

1

0

8

3

6

1

5

3

H

D

1

2

9

0

1

2

3

4

C

G

B

C

O

W

S

E

#

2

3

2

3

9

0

5

2

9

0

9

0

1

H

D

1

0

1

2

3

4

5

6

7

8

9

2

6

8

2

6

4

6

4

2

4

1

7

8

5

8

7

6

8

7

6

4

H

D

9

1

0

1

2

3

4

5

6

7

8

T

I

O

1

2

3

4

5

6

7

8

9

0

2

3

8

3

8

0

2

0

2

1

8

2

3

4

C

T

A

G

1

9

8

3

4

5

6

7

0

RP66

1 8 2 7 3 6 4 5

10

H

D

0

1

2

3

4

5

6

7

8

9

3

2

0

8

6

1

4

8

2

5

7

H

D

6

7

8

T

I

O

0

1

2

0

6

7

0

1

C

T

A

G

0

1

2

6

5

H D 5

T W E #

2 8 0

MRAS#0 MRAS#2 MRAS#1 MRAS#3

8

5

H

D

3

4

PCLKIN

C/BE0# C/BE1# C/BE2# C/BE3#

FRAME#

DEVSEL#

IRDY# TRDY# STOP# LOCK#

REQ0# REQ1# REQ2# REQ3#

GNT0# GNT1# GNT2# GNT3#

PHLD#

PHLDA#

SERR#

TEST#

VDD5V

U23

5

7

6

H

D

0

1

2

90 15

AD0

14

AD1

33

AD2

13

AD3

52

AD4

32

AD5

12

AD6

51

AD7

11

AD8

50

AD9

30

AD10

10

AD11

49

AD12

29

AD13

9

AD14

48

AD15

47

AD16

27

AD17

7

AD18

46

AD19

26

AD20

6

AD21

45

AD22

25

AD23

66

AD24

44

AD25

24

AD26

4

AD27

23

AD28

3

AD29

22

AD30

2

AD31

31

C/BE#0

28

C/BE#1

8

C/BE#2

5

C/BE#3

86 89 87 88 91 85

PREQ#0

67

PREQ#1

69

PREQ#2

71

PREQ#3

73

PGNT#0

68

PGNT#1

70

PGNT#2

72

PGNT#3

74 64

65 92 93

239

TESTIN#

301

94

VDD5V

TXC

AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

RST#

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9

PAR

HD[0..63]

PCLKTXC

AD[0..31]

C/BE#[0..3]

PGNT#[0..3]

R37 10K

1 2

R52 10K

1 2

R57 10K

R56 100

1 2

1

C131

1.0uF

2

MRAS#[0..3]

Title

Size Document Number REV

C 82430HX B.1

Date: June 19, 1997Sheet 4 of 24

2,5,6

3

10,18,19

FRAME#

10,18,19,21

DEVSEL#

10,18,19,21

IRDY#

10,18,19,21

TRDY#

10,18,19,21

STOP#

10,18,19,21

PLOCK#

18,19,21

PREQ#0

4,18,19,21

PREQ#1

4,18,19,21

PREQ#2

4,18,19,21

PREQ#3

4,18,19,21 18,19,21

1 2

PHOLD#

10

PHLDA#

10

PAR

10,18,19,21

SERR#

10,18,19,21

5,6,10,18,19

PCIRST#

VCC

CTWE#

5

CTAG[0..10]

CBWE#

5,6

CGWE#

5,6

COE#

5,6

CCS#

5,6

CADS#

5,6

CADV#

5,6

7,8

INTEL CORP.

Triton II controller (TXC)

1 2

R54 330

5,6

VCC

CPUVIO

2..4,6

2,4,6

4,6,10,18,19

CPUVIO

1 2

2,4,6

R106

4.7K R101

4.7K R84

4.7K R95

4.7K

HD[0..63] HA[3..18]

HBE#[0..7]

HCLKSRAM1

3

4,6 4,6

4,6

HADSC#

2,6

4,6 4,6 4,6

CBURST_SEQ2

6

CBURST_SEQ1

6

CRPU1

6

CPUVIOVCC

CRPU2

6

HW/R#

PCIRST#

CADV#

CADS# CBWE# CGWE#

HA28

HA29

HA30

HA31

CCS# COE#

4

1 8 2 7 3 6 4 5

CTWE#

RP70

10K

HA18

HA28

HA29

HA30

HA31

R65

0

R107

1 2

4.7K R103

1 2

4.7K R94

4.7K R96

4.7K

U22

HA3

37

A0

HA4

36

A1

HA5

35

A2

HA6

34

A3

HA7

33

A4

32

HA8

A5

100

HA9

A6

99

HA10

A7

82

HA11

A8

81

HA12

A9

44

HA13

A10

45

HA14

A11

46

HA15

A12

47

HA16

A13

48

HA17

A14

HBE#0

93

BW1#

HBE#1

94

BW2#

HBE#2

95

BW3#

HBE#3

96

BW4#

89

CLK

98

CE#

92

CE2#

97

CE2

86

OE#

83

ADV#

84

ADSP#

85

ADSC#

87

BWE#

88

GW#

64

ZZ

31

MODE

50

NC

51

NC

1

NC

80

NC

30

NC

49

NC

32KX32 SRAM

CRPD3

1 2

U24

10

HA13 HA14 HA15 HA17 HA7 HA5 HA12 HA10 HA9

1 2

HA8 HA16 HA6 HA11

DQ1

A0

9

DQ2

A1

8

DQ3

A2

7

DQ4

A3

6

DQ5

A4

5

DQ6

A5

4

DQ7

A6

3

DQ8

A7

25

A8

24

A9

21

A10

23

A11

2

A12

26

A13

1

A14

27

WE#

20

CE#

22

OE# SRAM32KX8

52

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

VDD1 VDD2

RESET#

W/R#

NF1

NF2

FT#

11

CTAG0

12

CTAG1

13

CTAG2

15

CTAG3

16

CTAG4

17

CTAG5

18

CTAG6

19

CTAG7

HD0

53

HD1

56

HD2

57

HD3

58

HD4

59

HD5

62

HD6

63

HD7

68

HD8

69

HD9

72

HD10

73

HD11

74

HD12

75

HD13

78

HD14

79

HD15

2

HD16

3

HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31

VDD1A VDD2A

PCIRST#D HW/R#D CTAG10D NF2D

STUFFING OPTION

2

C228

1

0.01uF

12C227

1 2

6 7 8 9 12 13 18 19 22 23 24 25 28 29

16 66

38 39 42 43

14

CRPU2

1 2 1 2

0.01uF

R1450

R15210K

VCC

R1320

R1330

R1440

1 2

R1460

1 2

3.3uF

C229

HA13 HA14 HA15 HA17 HA7 HA5 HA12 HA10 HA9 HA8 HA16 HA6 HA11

1 2

2

C230

1

1uF

CPUVIO

CTAG10

CTAG10 1 2

U25

10

A0

9

A1

8

A2

7

A3

6

A4

5

A5

4

A6

3

A7

25

A8

24

A9

21

A10

23

A11

2

A12

26

A13

1

A14

27

WE#

20

CE#

22

OE# SRAM32KX8

R155

0

STUFFING OPTION

11

DQ1

12

DQ2

13

DQ3

15

DQ4

16

DQ5

17

DQ6

18

DQ7

19

DQ8

CTAG8 CTAG9 CTAG10T UNUSD11 UNUSD12 UNUSD13 UNUSD14 UNUSD15

HBE#4 HBE#5 HBE#6 HBE#7

2 R83 220

1

HA3

37

HA4

36

HA5

35

HA6

34

HA7

33 32

HA8

100

HA9

99

HA10

82

HA11

81

HA12

44

HA13

45

HA14

46

HA15

47

HA16

48

HA17

93 94 95 96

89 98 92 97 86 83 84 85

87 88 64

31 50 51 1 80 30 49

CTAG[0..10]

CTAG10

CONFIGURATION RESISTORS

U31 A0

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14

BW1# BW2# BW3# BW4#

CLK CE# CE2# CE2 OE# ADV# ADSP# ADSC#

BWE# GW# ZZ

MODE NC NC NC NC NC NC

32KX32 SRAM

RP73

10K

4,6

1 8 2 7 3 6 4 5

R82

1 2

100K

R90

4.7K

RESET#

VCC

1 2

CA18

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

VDD1 VDD2

W/R#

52

HD32

DQ0

53

HD33

DQ1

56

HD34

DQ2

57

HD35

DQ3

58

HD36

DQ4

59

HD37

DQ5

62

HD38

DQ6

63

HD39

DQ7

68

HD40

DQ8

69

HD41

DQ9

72

HD42

73

HD43

74

HD44

75

HD45

78

HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63

VDD1B VDD2B

PCIRST#C HW/R#C CTAG10C NF2C

STUFFING OPTION

2

C232

0.01uF

2 1

79 2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29

16 66

38 39 42

NF1

43

NF2

14

FT#

CPUVIO

6

1 2 1 2

C231

0.01uF1

R1560

0

R157

1 2

R1580

R1491K

R1350

R1360

C233

3.3uF 1

1 2

VCC

C234

2

1uF

1

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

CACHE CONFIG HA31 HA30 HA29 HA28

NO SRAM 256K PBSRAM 512K PBSRAM

11X X 10 1 1

0010

Title

Size Document Number REV

C 82430HX B.1

Date: June 19, 1997Sheet 5 of 24

INTEL CORP.

Synchronous Cache, Lower 256K

2..5

2,4,5

HA[3..17]

HBE#[0..7]

HCLKSRAM0

3

4,5

2,5

4,5

CBURST_SEQ1

5

4,5 4,5

4,5,10,18,19

2,4,5

4,5

5

4,5

CADV#

HADSC#

CADS#

CBWE# CGWE#

HW/R#

CTAG10

CRPU1

5

CPUVIO

CCS# CA18

COE#

1 8 2 7 3 6 4 5

PCIRST#

RP74

10K

HBE#0 HBE#1 HBE#2 HBE#3

CRPU3

HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17

CRPU3

U29

37

A0

36

A1

35

A2

34

A3

33

A4

32

A5

100

A6

99

A7

82

A8

81

A9

44

A10

45

A11

46

A12

47

A13

48

A14

93

BW1#

94

BW2#

95

BW3#

96

BW4#

89

CLK

98

CE#

92

CE2#

97

CE2

86

OE#

83

ADV#

84

ADSP#

85

ADSC#

87

BWE#

88

GW#

64

ZZ

31

MODE

50

NC

51

NC

1

NC

80

NC

30

NC

49

NC

32KX32 SRAM

CBURST_SEQ1

CRPU2 CBURST_SEQ2

37 36 35 34 33 32 100 99 82 81 44 45 46 47 48

93 94 95 96

89 98 92 97 86 83 84 85

87 88 64

31 50 51 1 80 30 49

U32

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14

BW1# BW2# BW3# BW4#

CLK CE# CE2# CE2 OE# ADV# ADSP# ADSC#

BWE# GW# ZZ

MODE NC NC NC NC NC NC

32KX32 SRAM

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

VDD1 VDD2

RESET#

W/R#

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

NF1 NF2

FT#

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

VDD1 VDD2

RESET#

W/R#

NF1

NF2

FT#

5

53 56 57 58 59 62 63 68 69 72 73 74 75 78 79 2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29

16 66

38 39 42 43

14

HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31

VDD1C VDD2C

PCIRST#B HW/R#B CTAG10B NF2B

1

2

R55 220

STUFFING OPTION

2

C236

1

0.01uF

2 1

C235

0.01uF

R1470

1 2 1 2

R1480

R1380

R1390

1 2

R1400

R1371K

C237

3.3uF

1 2

VCC

CTAG10

C238

2

1

1 1uF

HD0

52

HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17

HBE#4 HBE#5 HBE#6 HBE#7

HCLKSRAM0 CCS# CA18 CRPU3 COE# CADV# HADSC# CADS#

CRPD1

HD32

52

HD33

53

HD34

56

HD35

57

HD36

58

HD37

59

HD38

62

HD39

63

HD40

68

HD41

69

HD42

72

HD43

73

HD44

74

HD45

75

HD46

78

HD47

79

HD48

2

HD49

3

HD50

6

HD51

7

HD52

8

HD53

9

HD54

12

HD55

13

HD56

18

HD57

19

HD58

22

HD59

23

HD60

24

HD61

25

HD62

28

HD63

29

VDD1D

16

VDD2D

66

PCIRST#A 1 2

38

HW/R#A

39

CTAG10A

42

NF2A

43 14

STUFFING OPTION

C240

0.01uF

HD[0..63]

VCC

R1500

1 2 1 2

2 1

2,4,5

C239

0.01uF

R1341K

R1510

3.3uF

R1410

R1420

1 2

R1430

1 2

2 1

C241

C242

2

1

1uF

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Synchronous Cache, Upper 256K

Size Document Number REV

B 82430HX B.1

Date: June 19, 1997 Sheet 6 of 24

INTEL CORP.

DRAM POWER 5 VOLTS 3.3 VOLTS 1-3,2-4 3-5,4-6

CPUVIO

VCC

4,8

MRAS#[0..3]

MCAS#[0..7]

MA[2..11]

4,8

JB1

1 2 3 4 5 6

JB3

MODULE 1 (BANK 1)MODULE 0 (BANK 1)

MRAS#0 MRAS#1

MWE#

MCAS#0 MCAS#1 MCAS#2

MAA0

4

MAA1

4

TP23 TP923 TP25 TP26

MCAS#3

MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11

TP039

1

TP038

1

TP041

1 1

TP040

47 44

45 34 33

40 43 41 42

12 13 14 15 16 17 18 28 31 32 19 29

67 68 69 70

11 46 48 66 71

10 30 59

U18

WRAS0-

RAS1RAS2RAS3-

CAS0CAS1CAS2CAS3-

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

ID1 ID2 ID3 ID4

RES1 RES2 RES3 RES4 RES5

VCC VCC VCC

32MX36SIMV

DQ8/P0 DQ17/P1 DQ26/P2 DQ35/P3

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16

DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25

DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34

2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ9

MD0

4

MD1

6

MD2

8

MD3

20

MD4

22

MD5

24

MD6

26

MD7

49

MD8

51

MD9

53

MD10

55

MD11

57

MD12

61

MD13

63

MD14

65

MD15

3

MD16

5

MD17

7

MD18

9

MD19

21

MD20

23

MD21

25

MD22

27

MD23 MD24

50

MD25

52

MD26

54 56

MD27

58

MD28

60

MD29

62

MD30

64

MD31

36

MP0

37

MP1

35

MP2

38

MP3

MAA0 MAA1

TP27 TP28 TP29 TP30

MCAS#4 MCAS#5 MCAS#6 MCAS#7

MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11

TP105

1

TP102

1

TP101

1

TP023

1

47 44

45 34 33

40 43 41 42

12 13 14 15 16 17 18 28 31 32 19 29

67 68 69 70

11 46 48 66 71

10 30 59

U19

WRAS0-

RAS1RAS2RAS3-

CAS0CAS1CAS2CAS3-

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

ID1 ID2 ID3 ID4

RES1 RES2 RES3 RES4 RES5

VCC VCC VCC

32MX36SIMV

DQ8/P0 DQ17/P1 DQ26/P2 DQ35/P3

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16

DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25

DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34

2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ9

MD32

4

MD33

6

MD34

8

MD35

20

MD36

22

MD37

24

MD38

26

MD39

49

MD40

51

MD41

53

MD42

55

MD43

57

MD44

61

MD45

63

MD46

65

MD47

3

MD48

5

MD49

7

MD50

9

MD51

21

MD52

23

MD53

25

MD54

27

MD55 MD56

50

MD57

52

MD58

54 56

MD59

58

MD60

60

MD61

62

MD62

64

MD63

36

MP4

37

MP5

35

MP6

38

MP7

DRAMVCC

8,24

MD[0..63]

MP[0..7]

4,8

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Size Document Number REV

C 82430HX B.1

Date: June 19, 1997Sheet 7 of 24

INTEL CORP.

Memory Modules 0 & 1

4,7

MRAS#[0..3]

MCAS#[0..7]

MA[2..11]

4,7

TP41 TP42 TP43 TP44

7,24

4 4

DRAMVCC

MWE#

MAB0 MAB1

MODULE 3 (BANK 2)MODULE 2 (BANK 2)

MRAS#2 MRAS#3

U20

47

W-

44

RAS0-

45

RAS1-

34

RAS2-

33

40 43 41 42

12 13 14 15 16 17 18 28 31 32 19 29

67 68 69 70

11 46 48 66 71

10 30 59

RAS3-

CAS0CAS1CAS2CAS3-

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

ID1 ID2 ID3 ID4

RES1 RES2 RES3 RES4 RES5

VCC VCC VCC

32MX36SIMV

MCAS#0 MCAS#1 MCAS#2 MCAS#3

MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11

TP112

1

TP111

1

TP110

1

TP109

1

DQ8/P0 DQ17/P1 DQ26/P2 DQ35/P3

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16

DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25

DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34

2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ9

MD0

4

MD1

6

MD2

8

MD3

20

MD4

22

MD5

24

MD6

26

MD7

49

MD8

51

MD9

53

MD10

55

MD11

57

MD12

61

MD13

63

MD14

65

MD15

3

MD16

5

MD17

7

MD18

9

MD19

21

MD20

23

MD21

25

MD22

27

MD23 MD24

50

MD25

52

MD26

54 56

MD27

58

MD28

60

MD29

62

MD30

64

MD31

36

MP0

37

MP1

35

MP2

38

MP3

TP45 TP46 TP47 TP48

MAB0 MAB1

1 1 1 1

TP103 TP107 TP108 TP113

MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11

MCAS#4 MCAS#5 MCAS#6 MCAS#7

47 44

45 34 33

40 43 41 42

12 13 14 15 16 17 18 28 31 32 19 29

67 68 69 70

11 46 48 66 71

10 30 59

U21

WRAS0-

RAS1RAS2RAS3-

CAS0CAS1CAS2CAS3-

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

ID1 ID2 ID3 ID4

RES1 RES2 RES3 RES4 RES5

VCC VCC VCC

32MX36SIMV

DQ8/P0 DQ17/P1 DQ26/P2 DQ35/P3

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16

DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25

DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34

2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ9

MD32

4

MD33

6

MD34

8

MD35

20

MD36

22

MD37

24

MD38

26

MD39

49

MD40

51

MD41

53

MD42

55

MD43

57

MD44

61

MD45

63

MD46

65

MD47

3

MD48

5

MD49

7

MD50

9

MD51

21

MD52

23

MD53

25

MD54

27

MD55 MD56

50

MD57

52

MD58

54 56

MD59

58

MD60

60

MD61

62

MD62

64

MD63

36

MP4

37

MP5

35

MP6

38

MP7

MD[0..63] 4,7

4,7

MP[0..7]

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Size Document Number REV

C 82430HX B.1

Date: June 19, 1997Sheet 8 of 24

INTEL CORP.

Memory Modules 2 & 3

VCC

10,12,15,20,21

10,20,21

15,16

INSTALL IF 1M FLASH 1 2

INSTALL IF 2M FLASH 1 2

SA[0..19]

MEMW#

MEMR#

ROMCS#

10

U16D

12

10,16

XD[0..7]

XOE#

13

74ALS32S

SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0

1

2

U2C

5

74HCT14S

R9

0

R6

0

11

SA16/17#

6

SA16/17

SA16

SA17

R10

1 2

VCC

8.2K

J3

SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0

F002CE#

1

O

JP1

J11 1 2 3

JP3

BIOSMSB

U6

40

A17

1

A16

2

A15

3

A14

4

A13

5

A12

6

A11

36

A10

7

A9

8

A8

14

A7

15

A6

16

A5

17

A4

18

A3

19

A2

20

A1

21

A0

9

WE#

24

OE#

22

CE#

10

PWD# 28F002BXTSOP

OPTIONAL 2MB FLASH

FL2MPU

ALLOWS PROGRAMMING OF BOOT BLOCK IN MANUFACTURING

MODE POS

NORMAL 1-2

RECOVERY 2-3

25

DQ0

26

DQ1

27

DQ2

28

DQ3

32

DQ4

33

DQ5

34

DQ6

35

DQ7

13

NC

29

NC

37

NC

38

NC

11

VPP

1

C36

2

O.1uF

XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7

R14

8.2K

FL_VPP FL_PNPPU

2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12

31 24 22 30

+12V

U7 A16

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

WE# OE# CE# PWD#

28F001BX

J12 1 2 3

JP3

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

VPP

13 14 15 17 18 19 20 21

1

MODE POS

PNP

NON-PNP

XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7

1-2

2-3

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Size Document Number REV

B 82430HX B.1

Date: June 19, 1997 Sheet 9 of 24

INTEL CORP.

System ROM

PWROK

17

PCLKPIIX3

3

PIIX3OSC

3 AD[0..31]

4,18,19

C/BE#[0..3]

4,18,19

4,18,19,21

4,18,19,21 4,18,19,21

220

4,18,19,21

R51

1 2

4,18,19,21

PIRQ#[0..3]

18,19,21

11,12,15,16,20,21

12,20,21

11,21

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

DDRQ[0..1]

11

IRQ[0..15]

DRQ[0..7]

DD[0..15]

DEVSEL#

4,18,19,21

12,20,21

20,21 20,21

2

17

FRAME#

PHLDA#

4

HFERR# EXTSMI#

IOCS16# IOCHK#

0WS#

C/BE#0 C/BE#1 C/BE#2 C/BE#3

TRDY# IRDY# STOP#

PXIDSELAD18 PIRQ#0

PIRQ#1 PIRQ#2 PIRQ#3

SERR#

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15

DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7

DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 DDRQ0 DDRQ1

126 132 136

206 205 204 203 202 201 200 199 197 194 193 192 191 190 189 188 177 176 175 174 173 172 171 168 166 165 164 163 162 161 160 159

198 187 178 167

179 181 180 185

154 184 149 150 151 152 3 110

4 58 56 34 33 32 5 10 73 75 77 83 81

120 125

87 30 12 25 91 95 99

71 6 15

55 50 49 48 47 46 45 44 43 41 40 39 38 37 36 35 108 111

U15

PWROK PCICLK OSC

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

C/BEOC/BE1C/BE2C/BE3-

FRAMETRDYIRDYSTOP-

IDSEL DEVSELPIRQAPIRQBPIRQCPIRQDSERRPHLDA-

IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8IRQ9 IRQ10 IRQ11 IRQ12/M IRQ14 IRQ15

FERREXTSMI-

DREQ0 DREQ1 DREQ2 DREQ3 DREQ5 DREQ6 DREQ7

IOCS16IOCHKZEROWS-

DD0/SA8 DD1/SA9 DD2/SA10 DD3/SA11 DD4/SA12 DD5/SA13 DD6/SA14 DD7/SA15 DD8/SA16 DD9/SA17 DD10/SA18 DD11/SA19 DD12/SBHEDD13 DD14/APICCSDD15/PCSDDRQ0 DDRQ1

PIIX3_0.2

PHOLDSYSCLK

LA17/DA0 LA18/DA1

LA19/DA2 LA20/CS3P LA21/CS1P LA22/CS3S LA23/CS1S

USBP0USBP0+

USBP1USBP1+

USBCLK

MEMCS16-

SMEMW-

SMEMR-

IOCHRDY

VCC/VCC3

STPCLK-

IGNNEDACK0-

DACK1DACK2DACK3DACK5DACK6DACK7-

REFRESH-

RTCALE

BIOSCS-

RTCCSRSTDRV

DDAK0DDAK1-

PCIRST-/APICACKTESTIN-/APICREQ-

CPURST

BALE

MIRQ0

MEMW-

MEMR-

IORIOW-

SD10 SD11 SD12 SD13 SD14 SD15

INTR SMI-

SPKR

XDIR-

XOE-

KBCS-

IORDY DIORDIOW-

SOESDIR

INIT

SA[8..19]

U14 2 3 4 5 6 7 8 9

19 1

2 3 4 5 6 7 8 9

19 1

DDSAPU1

SYSCLKR

Title

Size Document Number REV

Date: June 19, 1997 Sheet 10 of 24

18

B1

17

B2

16

B3

15

B4

14

B5

13

B6

12

B7

11

B8

18

B1

17

B2

16

B3

15

B4

14

B5

13

B6

12

B7

11

B8

4 5 3 6 2 7 1 8

CLOSE = CLK/4 OPEN = CLK/3

SA8 SA15 SA14 SA13 SA12 SA11 SA10 SA9

SA16 SA17 SA18 SA19

DDSAPU2 DDSAPU3 DDSAPU4

1 2

11,15

20

INTEL CORP.

SBHE#

20,21

R50

SYSCLK

22

PIIX3

20

A1

A2

A3

A4

A5

A6

A7

A8

G

DIR

74ALS245

U17

A1

A2

A3

A4

A5

A6

A7

A8

G

DIR

74ALS245

RP57

10K

RP59

10K

U27E

7407S

J28

1

2

JP2

RSTDRV#

RSTISA

B 82430HX B.1

9,20,21

20,21

16,20,21

PWROK

1

9,10,12,15,20,21

DD0 DD7 DD6 DD5 DD4 DD3 DD2 DD1

DD14 DD15

DD8 DD9 DD10 DD11 DD12

VCC

1 8 2 7 3 6 4 5

11 10

U2A

2

74HCT14S

R32

22

R44

22

R33

22

R46

1 2

22

R42

22 R40

22

CPUVIO

VCC

RSTDRV

U11D

12 13

74ALS08S

4.7K R43

1 2

DD[0..15]

SOE# SDIR

1 2

SMEMW#

1 2

MEMR#

SMEMR#

1 2

IOR#

1 2

IOW#

DIVCLK

21

12

VCC

11

186

PAR

109 153 64 20

AEN

86 84 82 80 76 74 72

69

SA0

68

SA1

67

SA2

66

SA3

63

SA4

61

SA5

59

SA6

57

SA7

145 144

143 142

146 147 70

90 22

88 19

18 23 24

17

SD0

16

SD1

14

SD2

13

SD3

11

SD4

9

SD5

8

SD6

7

SD7

92

SD8

94

SD9

96 98 100 101 102 107

130 122

123 124 135

NMI

121 85

29 60 21 89 93 97

62

TC

31 117

141 140 148 137 138 139 28

114 113 112 115 116 119 118

127 128 134 129

SYSCLKR BALER AENR

LA17 LA18 LA19 LA20 LA21 LA22 LA23

SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7

USBP0USBP0+

USBP1USBP1+

MEMWR# SMEMWR#

MEMRR# SMEMRR#

IORR# IOWR#

SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15

PBFVCC

DACK#0 DACK#1 DACK#2 DACK#3 DACK#5 DACK#6 DACK#7

T/CR REFRESH#

SPKR XDIR#

XOE# RTCALE ROMCS# RTCCS# ROM_KB#

ICHRDY IIOR#R IIOW#R DDAK0 DDAK1

SDIR

TESTIN#

PAR PHOLD#

MEMCS16#

IOCHRDY

SD[0..15]

HINTR HSMI# HSTPCLK# HNMI HIGNNE#

17

9,16

SOE#

HRESET PCIRST#

PIIX3INIT

R34 22

LA[17..23] SA[0..7]

13 13

MIRQ0

2

20,21

16

16 9 16 15

11 11

11 11 11

11

4,18,19,21

4

1 2

BALE

20,21

R45

1 2

AEN

22

VCC

2

R48 10K

1

USBCLK MEMW#

11,21 20,21 20,21

12,20,21

2 2

2

DACK#[0..7]

R3522

1 2

2

4..6,18,19

12,20

11,20,21

9,10,12,15,20,21

INSTALL FOR PIIX

3 9,20,21

12,16,20,21

R53

1 2

0

INSTALL FOR PIIX3

R39

1 2

0

INSTALL FOR PIIX

12,20

T/C

12,20

VCC

4

DD[0..15]

10,21

DDAK1

10

DDRQ1

10,11

DDRQ0

10,11

RSTDRV#

10,15

R31

5.6K

10,12,15,16,20,21

IIOW#R

10

IIOR#R

10

LA[17..23]

10,20,21

SOE#

10

MIRQ0

10,21

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

2

1

10

LA21

LA20

LA17

LA18

LA19

LA23

LA22

2

1

ICHRDY

DDAK0 IRQ14

1 2

1 8 2 7 3 6 4 5

R30

5.6K

R28

1 2 47 R47

47 R29

47 R49

47

12 13

9 10

4 5

1 2

9 10

4 5

1 2

RP37

33

IIOWA#

IIOWB#

IIORA#

IIORB#

U12D

74ALS00S U12C

74ALS00S U11B

74ALS08S U11A

74ALS08S U11C

74ALS08S U12B

74ALS00S U12A

74ALS00S

SDDAK1 SDDRQ1 DRQ0R IRSTA#

11

8

6

3

8

6

3

CS1P#

CS3P#

DA0

DA1

DA2

CS1S#

CS3S#

RP49

1.0K

RP32

33

RP62

33

RP20

4 5

22

RP22

22

RP23

22

RP25

22

RP63

10K

RP43

22

RP46

22

RP50

22

RP54

22

RP41

33 RP36

33

DD8

3 6

DD7

2 7

DD6

1 8

DD9

4 5

DD10

3 6

DD5

2 7

DD4

1 8

DD11

4 5

DD12

3 6

DD3

2 7

DD2

1 8

DD13

4 5

DD14

3 6

DD1

2 7

DD0

1 8

DD15

VCC

4 5 3 6 2 7 1 8

DD8

4 5

DD7

3 6

DD6

2 7

DD9

1 8

4 5

DD10

3 6

DD5

2 7

DD4

1 8

DD11

4 5

DD12

3 6

DD3

2 7

DD2

1 8

DD13

4 5

DD14

3 6

DD1

2 7

DD0

1 8

DD15

DA2IDA2B IDA2A

CS3P#

VCC

4 5 3 6 2 7 1 8

IRSTA# IDA7 IDA6 IDA5 IDA4 IDA3 IDA2 IDA1 IDA0

DRQ0R IIOWA# IIORA#

SDDAK0 PINTERRUPT IDA1A IDA0A ICS1A#

HDACTA#

17

PRIMARY IDE

J20

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

IDA8 IDA9 IDA10 IDA11 IDA12 IDA13 IDA14 IDA15

PIDEPU TP116

TP117 IDA2A ICS3A#

1

TP78

1

TP76

SECONDARY IDE

IRSTB# IDB7 IDB6 IDB5 IDB4 IDB3 IDB2 IDB1 IDB0

SDDRQ1 IIOWB# IIORB#

4 5 3 6 2 7 1 8

SDDAK1 SINTERRUPT IDA1B IDA0B ICS1B#

HDACTB#

17

DD14 DD0 DD15

DD1 DD11 DD2 DD12

DD10 DD5 DD4 DD3

DD8 DD7 DD6 DD9

J23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

RP55

4.7K RP51

4.7K RP47

4.7K RP44

4.7K

IDB8 IDB9 IDB10 IDB11 IDB12 IDB13 IDB14 IDB15

SIDEPU

1

TP115 TP114 IDA2B ICS3B#

4 5 3 6 2 7 1 8

TP77

1

TP75

VCC

IDA7 IDA6

IDA5 IDA4

IDA3 IDA2

IDA1 IDA0

PIDEPU SIDEPU HDACTB# HDACTA#

IDB7 IDB6

IDB5 IDB4

IDB3 IDB2

IDB1 IDB0

1 8

ICS3B# CS3S#

2 7

IRSTB# RSTDRV#

3 6

DA2

4 5

1 8 2 7 3 6

ICS3A#

4 5

ICS1A# CS1P#

Title

Size Document Number REV

B 82430HX B.1

Date: June 19, 1997 Sheet 11 of 24

INTEL CORP.

PCI IDE Interface

9,10,15,20,21

10,16,20,21

10,20

SA[0..19]

SD[0..15]

DACK#[0..7]

10,20,21

15,16 15,16

10

10,20

3

IOCHRDY XIOW#

XIOR#

RSTDRV

AIPCLK

0WS# AEN

T/C

TP68

SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0

VCC

1

R18

4.7K 2

1

SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

IO16_PU

DRQ5 DACK#5 DRQ2 DACK#2

IRQ7 IRQ6 IRQ5 IRQ4 IRQ3

TP037

U8

17

SA10

15

SA9

12

SA8

10

SA7

8

SA6

7

SA5

5

SA4

4

SA3

3

SA2

2

SA1

1

SA0

32

SD7

31

SD6

30

SD5

29

SD4

27

SD3

26

SD2

25

SD1

24

SD0

23

NOWS-

22

IOCHRDY

21

AEN

20

IOWC-

19

IORC-

96

IO16-

6

TC

100

PPDREQ

99

PPDACK-

98

FDDREQ

97

FDDACK-

18

IRQ7

16

IRQ6

13

IRQ5

11

IRQ4

9

IRQ3

33

RSTDRV

64

X2

63

X1/OSC

82091AA

SELECTIN-

PPDIR/GCS-

DSKCHG-

HDSEL-

RDDATA-

TRK0-

WRDATA-

STEP-

DIR-

FDME1-

FDS0FDS1-

FDME0-

INDXDRVDEN1 DRVDEN0

DTRB-

RIBCTSBSOUTB RTSB-

SINB DSRBDCDB-

DTRA-

RIACTSASOUTA RTSA-

SINA DSRADCDA-

STROBEAUTOFD-

INIT-

FAULT-

ACK-

BUSY

PERROR SELECT

IDECS1IDECS0-

HEN-

DEN-

74 75 76 77

WP-

78 79

WE-

80 81 82 83 84 85 86 87 90 89

49 50 48 47 46 45 44 43

41 42 40 39 38 37 36 35

PDR7

55

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PDR6

56

PDR5

57

PDR4

58

PDR3

60

PDR2

65

PDR1

67

PDR0

69 71 70 66 61 68 54 53 52 51

PPDIR

72

TP036

91

TP035

92

TP034

94

AIPDEN#

95

2

R15 10K

1

DSKCHG#

13

SIDE1#

13

RDATA#

13

WPT#

13

TRK0#

13

WGATE#

13

WDATA#

13

STEP#

13

DIR#

13

MOTEB#

13

DRVSA#

13

DRVSB#

13

MOTEA#

13

INDEX#

13

DRATE0

13

FDDEN

13

DTR1#

DTR0#

TX0

13

RI1#

13

CTS1#

13

TX1

13

RTS1#

13

RX1

13

DSR1#

13

DCD1#

13

RI0#

13

CTS0#

13

RTS0#

13

RX0

13

DSR0#

13

DCD0#

13

STB#R

14

AFD#R

14

INIT#R

14

SLIN#R

14

ERR#

14

ACK#

14

BUSY

14

PE

14

SLCT

14

1

TP84

1

TP31

1

TP32

2

R13 10K

1

R16 10K

2

1

2

PDR[0..7]

1

R17

R12

10K

2

14

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

IRQ[0..15]

DRQ[0..7]

Title

Size Document Number REV

B 82430HX B.1

Date: June 19, 1997 Sheet 12 of 24

10,11,15,16,20,21

10,20,21

INTEL CORP.

AIP

VCC+12V

SP_RI0 SP_CTS0 SP_RXD0 SP_DTR0 SP_RTS0 SP_DSR0 SP_TXD0 SP_DCD0

SP_RI1 SP_CTS1 SP_RXD1 SP_DTR1 SP_TXD1 SP_DCD1 SP_RTS1 SP_DSR1

-12V

1 2 3 4 5 6 7 8 9 10

U10 VCC+

RA RA RA DY DY RA DY RA VCC-

GD75232SOP

U9 VCC+

RA RA RA DY DY RA DY RA VCC-

GD75232SOP

USBP1-

10

USBP1+

10

USBP0-

10

USBP0+

10

20

VCC

19

RY

18

RY

17

RY

16

DA

15

DA

14

RY

13

DA

12

RY

11

GND

20

VCC

19

RY

18

RY

17

RY

16

DA

15

DA

14

RY

13

DA

12

RY

11

GND

RI0#

12

CTS0#

12

RX0

12

DTR0#

12

RTS0#

12

DSR0#

12

TX0

12

DCD0#

12

VCC+12V

RI1#

12

CTS1#

12

RX1

12

DTR1#

12

TX1

12

DCD1#

12

RTS1#

12

DSR1#

12

VCCVCC

1

F3

F2

1.25A

2

2 USBVFB0USBVFB1 1

1

L11

2

R19

30

1

C71

2

47pF

2

R20 30

1

1 2

C79

47pF

2

R26

R21

30

1

2 L12

1 1 2

C85 47pF

1 2

C83

47pF

1 2

470pF

1 2

C82

470pF

C84

2 L10

1

1 2

470pF

C72

2

USBV0 USBD0USBD0+ USBG0 USBV1 USBD1USBD1+ USBG1

1 2

C61

470pF

L8

USB

HEADER

J19 1 2

3 4 5 6 7 8 9 10 11 12 13 14 15 16

SP_DCD0 SP_DSR0 SP_RXD0 SP_RTS0 SP_TXD0 SP_CTS0 SP_DTR0 SP_RI0

SP_DCD1 SP_DSR1 SP_RXD1 SP_RTS1 SP_TXD1 SP_CTS1 SP_DTR1 SP_RI1

USB1FB

2

L9

1

1 2

100pF

1 2

100pF

1 2

C49

1 2

C29

C55

100pF

C21

100pF

1 2

100pF

1 2

100pF

1

1 2

C74

100pF

1 2

C42

100pF

1 2

C75

100pF

1 2

C63

100pF

1 2

C45

100pF

1 2

C32

100pF

VCC

RP42

1

R22

1.0K

2

TP69

2

C56

100pF

1 2

C66

C53

100pF

1 2

C25

100pF

1 2

C38

C31

100pF

DSKCHG#

12

SIDE1#

12

RDATA#

12

WPT#

12

TRK0#

12

WGATE#

12

WDATA#

12

STEP#

12

DIR#

12

MOTEB#

12

DRVSA#

12

DRVSB#

12

MOTEA#

12

INDEX#

12

DRATE0

12

FDDEN

12

J18 1

2 3 4

COM 0

5 6

HEADER

7 8 9 10

J10 1

2 3 4

COM 1

5 6

HEADER

7 8 9 10

4 5 3 6 2 7 1 8

1K

1

TP075

FLOPPY

INTERFACE

HEADER

J21

3334 3132 2930 2728 2526 2324 2122 1920 1718 1516 1314 1112

910 78 56 34 12

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Size Document Number REV

B 82430HX B.1

Date: June 19, 1997 Sheet 13 of 24

INTEL CORP.

Serial Ports, Floppy

12

PDR[0..7]

STB#R

12

AFD#R

12

INIT#R

12

SLIN#R

12

12 12

12 12 12

ERR#

SLCT BUSY

ACK#

1

C20

2

180pF

1

C48

2

180pF

1

C16

2

VCC

2

D1

IN4148 3 PAR5VOLTS

RP4 1 8 2 7 3 6

RP2

4 5 3 6

33

RP11

33

RP13

33

2 7 1 8

4 5 3 6 2 7 1 8

PDR0 PDR1

PDR2 PDR3

PDR4 PDR5 PDR6 PDR7

PE

4 5

1K

RP8 1 8 2 7 3 6 4 5

1K

RP7 1 8 2 7 3 6 4 5

1K

RP15 1 8 2 7 3 6 4 5

1K

RP9 1 8 2 7 3 6 4 5

1K

180pF

C27

180pF

C24

180pF

C30

180pF

C28

180pF

C40

180pF

C37

180pF

1

C51

2

180pF

1 2

1

C52

2

180pF

1 2

1

C54

2

180pF

1 2

1

C62

2

180pF

1 2

1

C64

2

180pF

1 2

1

C65

2

180pF

1 2

1

C73

2

180pF

1

C41

2

180pF

STB# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 ACK# BUSY PE SLCT

PARALLEL

HEADER

J9 1 2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

AFD# ERR# INIT# SLIN#

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Size Document Number REV

B 82430HX B.1

Date: June 19, 1997 Sheet 14 of 24

INTEL CORP.

Parallel Port

RP3 1 8 2 7 3 6 4 5

4.7K

VCC

R3

220

10,11

1

12,16

9,10,12,20,21

2

12,16

3

10

KBD_CLK RSTDRV#

ROM_KB#

XIOR# XIOW#

9,16

SA2

R11 220

XD[0..7]

C12 470Pf

KEYLOCK#

KBRST# HA20M# IRQ1 IRQ12

TP90

TP91

TP92

TP93

RP1

4 5 3 6 2 7

VCC

U5

29 KBCLK# MSCLK# KB_XT1

KBDSS# EA_PD

XD0 XD1 XD2 XD3 XD4

2

XD5 XD6 XD7

1

VDD

2

TEST0

43

TEST1

3

XTAL1

4

XTAL2

5

RESET-

6

SS-

7

CS-

8

EA

9

RD-

10

A0

11

WR-

14

D0 D1 D2 D3 D4 D5 D6 D7

8242PCPL

P24/OBF

P25/IBF-

P26/DRQ

P27/DAK-

PROG SYNC

15

16

17

18

19

20

21

KBDAT#

30

P10

MSDAT#

31

P11

KB_PU1

32

P12

PASSWDCLR#

33

P13

35

P14

PU_MFGTST

36

P15

COLOR

37

P16

KEYLOCK#

38

P17

24

P20

25

P21

MSEDAT

26

P22

MSECLK

27

P23

39 40

KBDCLK

41

KBDDAT

42

VCC

28

TP042

13

PU_CLCMOS

21

1

TP95

U4A

1 2

7406S U4B

3

7406S U4C

5

7406S U4D

9

7406S

1

J4 JP2

2

JUMPER B

CLEAR PASSWORD

PASSWORD

KBDAT_FB#

C17 470pf

KBCLK_FB#

1

C18

2

470Pf

L5

2 1

L6

4

6

8

2 1

L4

2 1

L3

2 1

1 2

10K

RP5 1 8 2 7 3 6 4 5

10K

JUMPER B JUMPER

POS

MSDAT_FB#

1

C13

2

470Pf

1 8

1-2

INCLEAR

OUTNORMAL

MSCLK_FB#

1 2

17

4 2

10..12,15,16,20,21

1

TP045

1

TP046

1

TP044

1

TP043

L1

QUIETGND1

1

2

FUSE 1

KB5V_FB

1

C10

2

0.1uF

VCC

2

1

F U S E 1

2

L7

1

QUIETGND2 2

1

F1

1.25A

KEYBOARD CONNECTOR

J2 1

2 3 4 5 6 7 8 9

J1 1

2 3 4 5 6 7 8 9

MOUSE CONNECTOR

L2

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Size Document Number REV

B 82430HX B.1

Date: June 19, 1997 Sheet 15 of 24

INTEL CORP.

Keyboard/Mouse Interface

10,20,21

10,12,20,21

IOR#

IOW#

RTCCS#

10

RTCALE

10

PWROK#

17

9,10

SD[0..7]

R1

1 2

XDIR#

10

XOE#

220

R4

220

IOR#PD

2 3

U3A 74LS125S

IOW#PD

5 6

U3B 74LS125S

U16B

4 5

74ALS32S

U16C

9 10

74ALS32S

1 19

SD7

9

SD6

8

SD5

7

SD4

6

SD3

5

SD2

4

SD1

3

SD0

2

1

4

U1

DIR G

A8 A7 A6 A5 A4 A3 A2 A1

74ALS245S

XIOR#

12,15

XIOW#

12,15

6

VCC

8

XD7

11

B8 B7 B6 B5 B4 B3 B2 B1

XD6

12

XD5

13

XD4

14

XD3

15

XD2

16

XD1

17

XD0

18

1 2

R41 10K

R36

RTC_MOT

220

RTCWR#

1 2

RTCRD# RTCRST#

XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7

XD[0..7]

U13

1

MOT

13

CS-

14

AS

15

R/W-

17

DS

18

RESET-

4

AD0

5

AD1

6

AD2

7

AD3

8

AD4

9

AD5

10

AD6

11

AD7

DS12887A

9,15

IRQ-

RSV1 RSV2

23

SQW

19

2

X1

3

X2

20

BC

21 22

TP051

TP048 TP047

TP049 RTCCEIN#

TP050

1

IRQ8

1 1 1

1

TP103

10..12,15,20,21 TP100 TP101

TP99

TP104

VCC

JUMPER POS

CLEAR CMOS IN

NORMAL OUT

1

R38 10K

2

J24

2 1

JP2

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Size Document Number REV

B 82430HX B.1

Date: June 19, 1997 Sheet 16 of 24

INTEL CORP.

BATTERY;RTC CICUIT

VCC

TP888

1

TP98

R127

1 2

68

SPK2

R128

SPKR

10

1 2

2.2K

SPK1

3

Q8

1

2N3904

2

R126

68

1 2

BUZZ2

C220

0.1 uF

J36 1

2

SPEAKER

3 4

15

KEYLOCK#

VCC

R60

1 2

220

PON

1

C210

2

470pF

1

C198

2

470pF

J33 1

POWER LED

2 3

KEYLOCK

4 5

11

HDACTA#

VCC

+3_3V

3 4

-12V +12V

-5V

U27B

7407S

VCC

1

R59

220 2 HDRV1

J32

HARD DRIVE LED

HDACTB#

1 0

U3C 74LS125S

1 2 3 4

11

VCC

1

2

EXTSMI#

10

R8 10K

PWRGD1

1

C8

2

10uF

HARDDRV

U27C

5 6

7407S

POWER_GOOD

J5 1

2 3 4 5 6

J13 1

2 3 4 5 6

J22 1

2 3 4 5 6

9 8

2 1

13

1 2

C216

4.7nF

VCC

1

C149

2

0.22uF

U2F

74HCT14S

R124

100

1

3

R58

D3

220

2

1N4148

2

J31 1

EXTSMI SWITCH

2 JP2

12

U2E

11

74HCT14S

RSTSW1

J35 1

2

10

PWROKR

RESET SWITCH

R7

33

C167

470pF

+12V

J34 1

CPU COOLING FAN

2

2 1

PWROK#

1 2

PWROK

JP2

16

10

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Size Document Number REV

B 82430HX B.1

Date: June 19, 1997 Sheet 17 of 24

INTEL CORP.

Front Panel

10,19,21

4,10,19

PIRQ#[0..3]

C/BE#[0..3]

AD[0..31]

C57

0.1UF

1 2

4,18,19,21

1

C67

0.1uF

2

4,10,19,21

4,19,21

4,10,19,21

18,19,21

TP109

19,21

TP110

TP111

IRDY# DEVSEL# PLOCK#

PERR#

SERR#

ACK64S#0

PCLK0

3

PREQ#0

+3_3V

VCC

-12V J14

B1 B2

1

TP056

PIRQ#1 PIRQ#3 PCIA0 TP055

1

PCIA1

TP054

1

AD31 AD29

AD27 AD25

C/BE#3 AD23

AD21 AD19

AD17 C/BE#2

C/BE#1 AD14

AD12 AD10

AD8 AD7

AD5 AD3

AD1

B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62

CN120ED05B

+3_3V

VCC

+12V

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62

PIRQ#0 PIRQ#2

TP063 TP062

TP061

TP060 AD30

AD28 AD26

AD24 PCIA2

AD22 AD20

AD18 AD16

SDONE

AD15 AD13

AD11 AD9

C/BE#0 AD6

AD4 AD2

AD0

1 1

1

PCIRST# PGNT#0

1

AD28

R27

1 2

220

FRAME# TRDY# STOP#

SBO# PAR

REQ64S#0

TP105 TP106

TP107

4..6,10,19 4,18,19,21

TP108

4,10,19,21 4,10,19,21 4,10,19,21

19,21

4,10,19,21

18,19,21

PTRST# 19

1

R54

5.6K

2

C58

1

0.1UF

2

4,18,19,21

C68

1

0.1UF

4,10,19,21

18,19,21

TP112

4,19,21

19,21

TP118

TP113

PCLK1

3

PREQ#1

IRDY# DEVSEL# PLOCK#

PERR#

SERR#

ACK64S#1

1

TP057

PIRQ#2 PIRQ#0 PCIB0 TP058 PCIB1

TP059

AD31 AD29

AD27 AD25

C/BE#3 AD23

AD21 AD19

AD17 C/BE#2

C/BE#1 AD14

AD12 AD10

AD8 AD7

AD5 AD3

AD1

+3_3V

VCC

-12V J15

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62

CN120ED05B

+3_3V

VCC

+12V

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62

PTRST#

PIRQ#1 PIRQ#3

TP067 TP066

TP065

TP064 AD30

AD28 AD26

AD24 PCIB2

AD22 AD20

AD18 AD16

AD15 AD13

AD11 AD9

C/BE#0 AD6

AD4 AD2

AD0

1 1

1

1 AD29

1 2

TP114 TP115

TP116

PCIRST# PGNT#1

TP117

R23

220

FRAME# TRDY# STOP# SDONE

SBO# PAR

REQ64S#1

4..6,10,19 4,18,19,21

4,10,19,21 4,10,19,21 4,10,19,21 19,21

19,21

4,10,19,21

18,19,21

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Size Document Number REV

C 82430HX B.1

Date: June 19, 1997Sheet 18 of 24

INTEL CORP.

PCI Slots 0 and 1

C59

10,18,21

4,10,18

2 1

4,10,18

2 1

4,10,18,21

18,19,21

PIRQ#[0..3]

C/BE#[0..3]

AD[0..31]

PTRST#18

TP123

4,18,19,21

C69

0.1uF

4,10,18,21

4,18,21

4,10,18,21

18,21

TP124

TP125

IRDY# DEVSEL# PLOCK#

PERR#

SERR#

ACK64S#2

PCLK2

3

PREQ#2

+3_3V

VCC

-12V J16

B1 B2

1

TP071

PIRQ#3 PIRQ#1 PCIC0 TP070

1

PCIC1

TP069

1

AD31 AD29

AD27 AD25

C/BE#3 AD23

AD21 AD19

AD17 C/BE#2

C/BE#1 AD14

AD12 AD10

AD8 AD7

AD5 AD3

AD1

B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62

CN120ED05B

+3_3V

VCC

+12V

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62

PIRQ#2 PIRQ#0

TP068 TP078

TP077

TP076 AD30

AD28 AD26

AD24 PCIC2

AD22 AD20

AD18 AD16

SDONE

AD15 AD13

AD11 AD9

C/BE#0 AD6

AD4 AD2

AD0

1 1

1

PCIRST# PGNT#2

1

AD30

R24

1 2

220

FRAME# TRDY# STOP#

SBO# PAR

REQ64S#2

TP119 TP120

TP121

4..6,10,18 4,18,19,21

TP122

4,10,18,21 4,10,18,21 4,10,18,21

18,21

4,10,18,21

18,19,21

0.1UF

2

C60

1

2

C70

1

0.1UF

4,10,18,21

18,19,21

TP126

4,18,19,21

4,18,21

18,21

TP132

TP127

PCLK3

3

IRDY# DEVSEL# PLOCK#

PERR#

SERR#

ACK64S#3

1

PREQ#3

TP072

PIRQ#0 PIRQ#2 PCID0 TP073 PCID1

TP074

AD31 AD29

AD27 AD25

C/BE#3 AD23

AD21 AD19

AD17 C/BE#2

C/BE#1 AD14

AD12 AD10

AD8 AD7

AD5 AD3

AD1

+3_3V

VCC

-12V J17

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49

B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62

CN120ED05B

+3_3V

VCC

+12V

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62

PIRQ#3 PIRQ#1

TP082 TP081

TP080

TP079 AD30

AD28 AD26

AD24 PCID2

AD22 AD20

AD18 AD16

AD15 AD13

AD11 AD9

C/BE#0 AD6

AD4 AD2

AD0

1 1

1

1 AD31

1 2

TP128 TP129

TP130

PCIRST# PGNT#3

TP131

R25

220

FRAME# TRDY# STOP# SDONE

SBO# PAR

REQ64S#3

4..6,10,18 4,18,19,21

4,10,18,21 4,10,18,21 4,10,18,21 18,21

18,21

4,10,18,21

18,19,21

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Size Document Number REV

C 82430HX B.1

Date: June 19, 1997Sheet 19 of 24

INTEL CORP.

PCI Slots 2 and 3

10..12,15,16,21

10,12,21

10,12

IRQ[3..15]

DRQ[0..7]

DACK#[0..7]

RSTISA

IRQ9 DRQ2

0WS#

SMEMW# SMEMR# IOW# IOR#

DACK#3 DRQ3 DACK#1

DRQ1 REFRESH# SYSCLK

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

DACK#2 T/C BALE

OSC

MEMCS16# IOCS16#

IRQ10

IRQ11

IRQ12

IRQ15

IRQ14

DACK#0

DRQ0

DACK#5

DRQ5

DACK#6

DRQ6

DACK#7

DRQ7 MASTER#

VCC

J8 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18

CD98ED10B

A1

SD7

A2

SD6

A3

SD5

A4

SD4

A5

SD3

A6

SD2

A7

SD1

A8

SD0

A9

A10

A11

SA19

A12

SA18

A13

SA17

A14

SA16

A15

SA15

A16

SA14

A17

SA13

A18

SA12

A19

SA11

A20

SA10

A21

SA9

A22

SA8

A23

SA7

A24

SA6

A25

SA5

A26

SA4

A27

SA3

A28

SA2

A29

SA1

A30

SA0

A31

C1

C2

LA23

C2

C3

LA22

C3

C4

LA21

C4

C5

LA20

C5

C6

LA19

C6

C7

LA18

C7

C8

LA17

C8

C9

C10

C11

SD8

C11

C12

SD9

C12

C13

SD10

C13

C14

SD11

C14

C15

SD12

C15

C16

SD13

C16

C17

SD14

C17

C18

SD15

C18

IOCHK# 10,21

IOCHRDY

10,12,21

AEN

10,12

SBHE#

10,21

MEMR#

9,10,21

MEMW#

9,10,21

LA[17..23] SA[0..19] SD[0..15]

10,11,21 9,10,12,15,21 10,12,16,21

VCC

J7

B1

10

RSTISA

-5V

10

10,21

10,12

SMEMW# SMEMR#

REFRESH#

SYSCLK

MEMCS16#

IOCS16#

21

0WS#

IOW# IOR#

T/C

BALE

OSC

3

MASTER#

-12V +12V

10,12,21

10,21

10,21 10,16,21 10,16,21

10,21

IRQ9 DRQ2

DACK#3 DRQ3 DACK#1 DRQ1

IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK#2

IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK#0 DRQ0 DACK#5 DRQ5 DACK#6 DRQ6 DACK#7 DRQ7

B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18

CD98ED10B

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0

LA23 LA22 LA21 LA20 LA19 LA18 LA17

SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15

IOCHK#

IOCHRDY

-5V

-12V +12V

AEN

SBHE#

MEMR# MEMW#

RSTISA

IRQ9 DRQ2

0WS#

SMEMW# SMEMR# IOW# IOR#

DACK#3 DRQ3 DACK#1

DRQ1 REFRESH# SYSCLK

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

DACK#2 T/C BALE

OSC

MEMCS16# IOCS16#

IRQ10

IRQ11

IRQ12

IRQ15

IRQ14

DACK#0

DRQ0

DACK#5

DRQ5

DACK#6

DRQ6

DACK#7

DRQ7 MASTER#

VCC

J6

B1

A1

B2

A2

B3

A3

B4

A4

B5

A5

B6

A6

B7

A7

B8

A8

B9

A9

B10

A10

B11

A11

B12

A12

B13

A13

B14

A14

B15

A15

B16

A16

B17

A17

B18

A18

B19

A19

B20

A20

B21

A21

B22

A22

B23

A23

B24

A24

B25

A25

B26

A26

B27

A27

B28

A28

B29

A29

B30

A30

B31

A31

D1

C1

D2

C2

D3

C3

D4

C4

D5

C5

D6

C6

D7

C7

D8

C8

D9

C9

D10

C10

D11

C11

D12

C12

D13

C13

D14

C14

D15

C15

D16

C16

D17

C17

D18

C18

CD98ED10B

IOCHK#

A1 A2

SD7

A3

SD6

A4

SD5

A5

SD4

A6

SD3

A7

SD2

A8

SD1

A9

SD0 A10 A11 A12

SA19 A13

SA18 A14

SA17 A15

SA16 A16

SA15 A17

SA14 A18

SA13 A19

SA12 A20

SA11 A21

SA10 A22

SA9 A23

SA8 A24

SA7 A25

SA6 A26

SA5 A27

SA4 A28

SA3 A29

SA2 A30

SA1 A31

SA0

C1 C2

LA23 C3

LA22 C4

LA21 C5

LA20 C6

LA19 C7

LA18 C8

LA17 C9 C10 C11

SD8 C12

SD9 C13

SD10 C14

SD11 C15

SD12 C16

SD13 C17

SD14 C18

SD15

IOCHRDY

-5V

-12V +12V

AEN

SBHE#

MEMR# MEMW#

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

Title

Size Document Number REV

C 82430HX B.1

Date: June 19, 1997Sheet 20 of 24

INTEL CORP.

ISA Slots 0, 1 and 2

RP31

10K RP29

10K RP27

10K RP24

10K RP21

10K RP18

10K RP16

10K RP61

10K RP40

10K RP45

10K

RP65

2.7K

IRQ[0..15]

SA[0..19]

4 5 3 6 2 7 1 8

10..12,15,16,20

9,10,12,15,20

VCC

1 8 2 7 3 6 4 5

CPUVIO

PGNT#[0..3]

4,18,19

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

SA0 SA1 SA2

SA3 SA4 SA5 SA6

IRQ3 SA7 IRQ4 SA8

IRQ5 IRQ6 SA9 SA10

IRQ7 SA11 SA12 SA13

SA14 SA15

SA16

SA17 SA18 SA19 IRQ9

IRQ1 IRQ8

IRQ12 IRQ11 IRQ10

IRQ14 IRQ15

PGNT#3 PGNT#2 PGNT#1 PGNT#0

BALE

PU_CLCMOS

MIRQ0

SBHE#

MEMW# MEMR#

10,20

9,10,20 9,10,20

10,12,16,20

VCC

1 8 2 7 3 6 4 5

DRQ[0..7]

10,12,20

1 8 2 7 3 6 4 5

15

VCC

10,18,1910,11

4,18,19

18,19 18,19

1 8 2 7 3 6 4 5

SD[0..15]

RP10

10K RP6

10K RP52

10K RP58

10K

RP48

5.6K RP19

5.6K

PIRQ#[0..3]

RP12

2.7K

PREQ#[0..3] REQ64S#[0..3] ACK64S#[0..3]

RP30

2.7K RP33

4 5 3 6 2 7 1 8

2.7K RP38

2.7K RP64

4 5 3 6 2 7 1 8

2.7K

SD0 SD1 SD2 SD3

SD4 SD5 SD6 SD7

SD11 SD10 SD9 SD8

SD15 SD14 SD13 SD12

DRQ7 DRQ6 DRQ5 DRQ0

DRQ1 DRQ3 DRQ2

PIRQ#2 PIRQ#3 PIRQ#0 PIRQ#1

ACK64S#2 ACK64S#3

REQ64S#2 REQ64S#3 ACK64S#1 ACK64S#0

PREQ#0 REQ64S#0 REQ64S#1

PREQ#1

PREQ#3

PREQ#2

PAR

SERR#

VCC

4,10,18,19

10,11,20

RP34 1 8 2 7 3 6 4 5

2.7K

RP39 1 8 2 7 3 6 4 5

2.7K

RP17 1 8 2 7 3 6 4 5

10K

RP14 1 8 2 7 3 6 4 5

10K

RP28 1 8 2 7 3 6 4 5

2.7K

RP26 1 8 2 7 3 6 4 5

2.7K

RP35 1 8 2 7 3 6 4 5

330

RP56 1 8 2 7 3 6 4 5

330

RP60 1 8 2 7 3 6 4 5

1.0K

RP53 1 8 2 7 3 6 4 5

4.7K

LA[17..23]

LA17 LA18 LA19

LA21 LA22 LA20 LA23

Title

Size Document Number REV

Date: June 19, 1997 Sheet 21 of 24

Pullup/Pulldown Resistors

B 82430HX B.1

STOP#

IOR#

IOW#

DIVCLK SMEMR#

SMEMW#

SBO# PERR# SDONE PLOCK#

DEVSEL# TRDY# IRDY# FRAME#

IOCS16# MEMCS16# REFRESH# 0WS#

MASTER#

IOCHRDY

DD13

IOCHK#

INTEL CORP.

4,10,18,19

10,16,20

10 10,20

10,20

18,19

18,19 18,19

4,18,19

4,10,18,19 4,10,18,19 4,10,18,19

4,10,18,19

10,20

10,20 10,20

10,12,20

20

10,12,20

10,11

10,20

TP566

TP567

1 2

C191

220uF

C215

220uF

J26

VRE STD

1 2

1-2 2-3

3 JP3

CPUVIO

C183

1 2

220uF

R85

Q2 S_0

S_1 S_2 G_0

SI4410DY

LRAWVIO

D2

2 1

1N5820

Q4 S_0

S_1 G_0

SI9410DY

1 2

18.7K

R113

1 2

965

8

D_3

7

D_2

6

D_1

5

D_0

R123

1 2

0.03

R121

1 2

0.03

RAWVIO

8

D_3

7

D_2

6

D_1

5

D_0

TP52

VIO2

VCC

REF

C189

1 2

500pF

REFR

TP568

C190

1 2

3300pF

TP565

C184

1 2

120pF

R105

1 2

1.27K

LBOUT

PGND

+12V

2

VFB

10

TP053 TDRIVE SENSE

1

C203

1 2

1nF

2

C176

1

0.1uF

SENSE#

BDRIVE

TP564

14 1 9 8 16 15

VCC

U30

5

VIN PINV LBIN SHDM ITH CT BINH SGND

LTC1266XS

+12V

PWRVIN VFB_NC

TDRIVE SENSE+ SENSEBDRIVE

3

TP052 ITH

CT

C168 1uF

13 11 7 6 4

12 1 2

1

R108

1 2

1.5K

RAWVIO

L14

1 2

2.2uH

R118

1 2

100 R117

1 2

100

1 2 3 4

2 3

4

R112

+12V

Q1

1

TP033 TP032

1

COL

2

COMP V+ RTOP

LT1431CS

C223

0.1uF

RMID GNDF GNDS

1 2

3 4

1 2

33K

8

REF

TP098

7

1 6 5

1

1 2

C169

1 2

220uF

C182

1 2

220uF

R109

0

VRREF TP030

1 2

C185

220uF

C214

220uF

6.3v

2

C225

1

1uF

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

2

R129 910

CORECATH

Q7

1

CATH

2

A_0

3

A_1

TL431ACS

VCOREREFIN

8

P

7

A_3

6

A_2

1

1 2

C O M P

2

1

C222

0.01uF

R125 47K

R122

1 2

220

COREB2E

3

Q5

1

2N3904SOT23

2

1

Q6 2N3906SOT23

3

Z40DRV

2

R120 910

1

R116

1 2

22

2

R119 910

1

Z40DRVR

2

Q3 IRFZ40

1

3

JB3 1 2

3 4 5 6 7 8

JB4

1 2

C208 100uF

1

C211

2

100uF

CPU TYPE

P54C

P55C

CPUVCORE

1

C192

2

100uF

JUMPER

1-2, 3-4, 5-6, 7-8

NONE

HEAT SINK

HS1

TP028 TP031

INTEL CORP.

1

TP570

1

TP569

1

C181

2

100uF

Title

Size Document Number REV

B 82430HX B.1

Date: June 19, 1997 Sheet 22 of 24

1

2

6021PB

Switching Power Supply

MH1

1

MH9UV157 MH2

1

MH9UV157

MH4

1

MH9UV157 MH5

1

MH9UV157 MH6

1

MH9UV157

MH7

1

MH9UV157 MH8

1

MH9UV157 MH9

1

MH9UV157

H1 H120

GF1 FM200B

FM4 FM200B

FM7 FM200B

1

1 GF2

1 FM5

1 FM8

1

H2 H120

1

FM200B

1

H3 H120

1

GF3 FM200B

FM6 FM200B

FM9 FM200B

H4 H158

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

U4E

11 10

7406S

U4F

13 12

7406S

TP100

TP099

U2D

8

TP106

TP104

1

TP931

1

TP926

1

TP929

1

TP930

9

74HCT14S

U27F

13 12

7407S

SPARES

Title

Fiducials, Holes, Spare Gates

Size Document Number REV

B 82430HX B.1

Date: June 19, 1997 Sheet 23 of 24

INTEL CORP.

C112

1 2

0.1uF C111

1 2

0.1uF C26

1 2

0.1uF C6

1 2

0.1uF C44

1 2

0.1uF C100

1 2

0.1uF C139

1 2

0.1uF C5

1 2

0.1uF C104

1 2

0.1uF C19

1 2

0.1uF C137

1 2

0.1uF C120

1 2

0.1uF C103

1 2

0.1uF

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

VCCVCC

C3

1 2

0.1uF C77

1 2

0.1uF C135

1 2

0.1uF C116

1 2

0.1uF C152

1 2

0.1uF C113

1 2

0.1uF C34

1 2

0.1uF C151

1 2

0.1uF C140

1 2

0.1uF C1

1 2

0.1uF C2

1 2

0.1uF C105

1 2

0.1uF C15

1 2

0.1uF C76

1 2

0.1uF C115

1 2

0.1uF C81

1 2

0.1uF C129

1 2

0.1uF C33

1 2

0.1uF C35

1 2

0.1uF C117

1 2

0.1uF C118

1 2

0.1uF C150

1 2

0.1uF C43

1 2

0.1uF

VCC

C93

1 2

0.01uF C138

1 2

0.01uF C101

1 2

0.01uF C128

1 2

0.01uF C126

1 2

0.01uF C108

1 2

0.01uF C106

1 2

0.01uF C78

1 2

0.01uF C80

1 2

0.01uF C94

1 2

0.01uF C92

1 2

0.01uF C4

1 2

0.001uF C124

1 2

0.001uF C114

1 2

0.001uF

C11

1 2

10uF

C125

1 2

10uF

C47

1 2

10uF

C119

1 2

10uF

C39

1 2

10uF

C134

1 2

10uF

C9

1 2

100uF

+3_3V

+12V

-12V

C86

1 2

10uF

C96

1 2

0.1uF C99

1 2

0.1uF C88

1 2

0.1uF C98

1 2

0.1uF C95

1 2

0.1uF C87

1 2

0.1uF C97

1 2

0.1uF C102

1 2

0.1uF

C23

1 2

10uF

C50

1 2

0.1uF C224

1 2

0.1uF

C22

10uF

C46

0.1uF C14

0.1uF

CPUVIO

C175

1 2

100uF

C148

1 2

100uF

C170

1 2

0.1uF C153

1 2

0.1uF C156

1 2

0.1uF

C204

1 2

0.1uF

C127

1 2

0.1uF

C141

1 2

0.1uF

C171

1 2

0.1uF

C202

1 2

0.001uF C197

1 2

0.001uF C166

1 2

0.001uF C165

1 2

0.001uF

1 2

DRAMVCC

7,8

C91

1 2

0.1uF C122

1 2

0.1uF C110

1 2

0.1uF C123

1 2

0.1uF C107

1 2

0.1uF

C109

1 2

0.001uF C90

1 2

0.001uF C121

1 2

0.001uF C89

1 2

0.001uF C133

1 2

0.001uF

C132

1 2

100uF

Title

Size Document Number REV

B 82430HX B.1

Date: June 19, 1997 Sheet 24 of 24

INTEL CORP.

Decoupling Capacitors

-5V

C226

1 2

0.01uF

2

C7

1

10uF

CPUVCORECPUVIO

Root schematic for netlisting multiple flat files.

THIS DRAWING CONTAINS INFORMATION

WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

INTEL CORP.

Title

Root Schematic

Size Document Number REV

A T2 B.1

Date: June 19, 1997 Sheet 25 of 24

Intel 430HX Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual

Index

Clock Generator

Synchronous Cache, Lower 256K

Synchronous Cache, Upper 256K

Memory Modules 0 & 1

Memory Modules 2 & 3

System ROM

PIIX3

PCI IDE Interface

Front Panel

Pullup/Pulldown Resistors

Switching Power Supply

Fiducials, Holes, Spare Gates