Index
Primary CPU (Socket 7)
Clock Generator
Triton II controller (TXC)
Synchronous Cache, Lower 256K
Synchronous Cache, Upper 256K
Memory Modules 0 & 1
Memory Modules 2 & 3
System ROM
PIIX3
PCI IDE Interface
AIP
Serial Ports, Floppy, USB
Parallel Ports
Keyboard/Mouse Ports
Battery, RTC Circuit
Front Panel
PCI Slots 1 and 2
PCI Slots 3 and 4
ISA Slots
Pullup/Pulldown Resistors
Switching Power Supply
Fiducials, Holes, Spare Gates
Decoupling Caps
Released Rev. B.1
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
Title
Size Document NumberREV
C82430HXB.1
Date: June 19, 1997Sheet 2 of 24
INTEL CORP.
PRIMARY CPU (Socket 7)
2,4..6
HA27
12
HA27PU
1
2
R154
8.2K
1 2
14.31818MHz
C146
10pF
HA27PD
Y1
R88
4.7K
JUMPER 1
JUMPER 2
J25
1
2
3
JP3
1 2
1
2
JUMPER 3
J30
JP3
J29
JP3
C145
10pF
PIIX3OSC
CPUVIO
2
R89
4.7K
1
3
2
1
3
2
1
CLKSEL_PU
CPUVIO
C143
1 2
0.1uF
C147
0.1uF
C142
0.1uF
C136
0.1uF
C144
1 2
0.1uF
L13
12
1.5uH
1 2
1 2
1 2
CLKSEL0
CLKSEL1
ALWAYS STUFFED
PCLK(0:3)
50MHz
60MHz
66MHz
RESERVED
12
STUFF WITH 9169
12
11
BCLK(0:5) JUMPER 1
RESERVED
TP24
R80
0
48MCLKFB2
48MCLKPU
1
U26B
0
9
P
Q
D
R
CLK
C
8
Q
L
74ALS74AS
1
3
25MHz
30MHz
33MHz
XTAL1
XTAL2
1
CLKGENP1
CLKVCC3
TP029
2-3
2-3
1-2
1-2
5
13
12
2
3
1
14
20
26
8
2
3
JUMPER 2 JUMPER 3
2-3
1-2
2-3
1-2
R81
1 2
22
DO NOT STUFF
U28
OE
SEL0SEL1-
X1
X2
VCC3
VCC3
VCC3
VCC3
VCC3
ICS9159-02S
D
CLK
KBD_CLK1R
48MCLKFB1
4
P
Q
R
C
Q
L
1
ISA14MHZ
APIC14MHZ
HCLK0
HCLK1
HCLK2
HCLK3
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
24MHZ
12MHZ
12
U26A
5
6
74ALS74AS
48MFFOUT1
GND
GND
GND
GND
R70
10K
RAWOSC
2
R78
22
1
R2
12
220
OSCPULLDN
1
3
1211
U3D
74LS125S
12
12
12
STUFF WITH 9159
R69
22
R66
22
R61
22
R62
22
R63
22
R64
22
R68
22
R71
22
R67
22
R72
22
R75
22
TP022
OSCR
12
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R76
22
R73
22
1
X
1-2
2-3
2-3
1
R79
22
2
PIIX3OSCR
28
RAWOSCR
27
HCLKCPUR
6
HCLKSRAM0R
7
HCLKSRAM1R
9
10
PCLK0R
15
PCLK1R
16
PCLK2R
18
PCLK3R
19
PCLKTXCR
21
PCLKPIIX3R
22
AIPCLKR
24
KBD_CLKR
25
4
23
17
11
VCC
R77
1 2
22
R74
12
22
R5
12
22
HCLKSRAM0
HCLKSRAM1
TP922
PCLK0
PCLK1
PCLK2
PCLK3
PCLKTXC
PCLKPIIX3
USBCLK
AIPCLK
KBD_CLK
10
HCLKTXC
HCLKCPU
18
18
19
19
OSC
20
4
2
6
5
4
10
10
12
15
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
Title
Size Document NumberREV
B82430HXB.1
Date: June 19, 1997 Sheet 3 of 24
INTEL CORP.
Clock Generator
7,8
MCAS#[0..7]
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
Title
Synchronous Cache, Upper 256K
Size Document NumberREV
B82430HXB.1
Date: June 19, 1997 Sheet 6 of 24
INTEL CORP.
DRAM POWER
5 VOLTS 3.3 VOLTS
1-3,2-4 3-5,4-6
CPUVIO
VCC
4,8
4,8
MRAS#[0..3]
MCAS#[0..7]
MA[2..11]
4,8
4,8
JB1
1 2
3 4
5 6
JB3
MODULE 1 (BANK 1)MODULE 0 (BANK 1)
MRAS#0
MRAS#1
MWE#
MCAS#0
MCAS#1
MCAS#2
MAA0
4
MAA1
4
TP23
TP923
TP25
TP26
MCAS#3
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
TP039
1
TP038
1
TP041
1
1
TP040
47
44
45
34
33
40
43
41
42
12
13
14
15
16
17
18
28
31
32
19
29
67
68
69
70
11
46
48
66
71
10
30
59
U18
WRAS0-
RAS1RAS2RAS3-
CAS0CAS1CAS2CAS3-
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
ID1
ID2
ID3
ID4
RES1
RES2
RES3
RES4
RES5
VCC
VCC
VCC
32MX36SIMV
DQ8/P0
DQ17/P1
DQ26/P2
DQ35/P3
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ9
MD0
4
MD1
6
MD2
8
MD3
20
MD4
22
MD5
24
MD6
26
MD7
49
MD8
51
MD9
53
MD10
55
MD11
57
MD12
61
MD13
63
MD14
65
MD15
3
MD16
5
MD17
7
MD18
9
MD19
21
MD20
23
MD21
25
MD22
27
MD23
MD24
50
MD25
52
MD26
54
56
MD27
58
MD28
60
MD29
62
MD30
64
MD31
36
MP0
37
MP1
35
MP2
38
MP3
MAA0
MAA1
TP27
TP28
TP29
TP30
MCAS#4
MCAS#5
MCAS#6
MCAS#7
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
TP105
1
TP102
1
TP101
1
TP023
1
47
44
45
34
33
40
43
41
42
12
13
14
15
16
17
18
28
31
32
19
29
67
68
69
70
11
46
48
66
71
10
30
59
U19
WRAS0-
RAS1RAS2RAS3-
CAS0CAS1CAS2CAS3-
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
ID1
ID2
ID3
ID4
RES1
RES2
RES3
RES4
RES5
VCC
VCC
VCC
32MX36SIMV
DQ8/P0
DQ17/P1
DQ26/P2
DQ35/P3
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ9
MD32
4
MD33
6
MD34
8
MD35
20
MD36
22
MD37
24
MD38
26
MD39
49
MD40
51
MD41
53
MD42
55
MD43
57
MD44
61
MD45
63
MD46
65
MD47
3
MD48
5
MD49
7
MD50
9
MD51
21
MD52
23
MD53
25
MD54
27
MD55
MD56
50
MD57
52
MD58
54
56
MD59
58
MD60
60
MD61
62
MD62
64
MD63
36
MP4
37
MP5
35
MP6
38
MP7
DRAMVCC
8,24
MD[0..63]
MP[0..7]
4,8
4,8
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
Title
Size Document NumberREV
C82430HXB.1
Date: June 19, 1997Sheet 7 of 24
INTEL CORP.
Memory Modules 0 & 1
4,7
4,7
MRAS#[0..3]
MCAS#[0..7]
MA[2..11]
4,7
4,7
TP41
TP42
TP43
TP44
7,24
4
4
DRAMVCC
MWE#
MAB0
MAB1
MODULE 3 (BANK 2)MODULE 2 (BANK 2)
MRAS#2
MRAS#3
U20
47
W-
44
RAS0-
45
RAS1-
34
RAS2-
33
40
43
41
42
12
13
14
15
16
17
18
28
31
32
19
29
67
68
69
70
11
46
48
66
71
10
30
59
RAS3-
CAS0CAS1CAS2CAS3-
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
ID1
ID2
ID3
ID4
RES1
RES2
RES3
RES4
RES5
VCC
VCC
VCC
32MX36SIMV
MCAS#0
MCAS#1
MCAS#2
MCAS#3
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
TP112
1
TP111
1
TP110
1
TP109
1
DQ8/P0
DQ17/P1
DQ26/P2
DQ35/P3
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ9
MD0
4
MD1
6
MD2
8
MD3
20
MD4
22
MD5
24
MD6
26
MD7
49
MD8
51
MD9
53
MD10
55
MD11
57
MD12
61
MD13
63
MD14
65
MD15
3
MD16
5
MD17
7
MD18
9
MD19
21
MD20
23
MD21
25
MD22
27
MD23
MD24
50
MD25
52
MD26
54
56
MD27
58
MD28
60
MD29
62
MD30
64
MD31
36
MP0
37
MP1
35
MP2
38
MP3
TP45
TP46
TP47
TP48
MAB0
MAB1
1
1
1
1
TP103
TP107
TP108
TP113
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MCAS#4
MCAS#5
MCAS#6
MCAS#7
47
44
45
34
33
40
43
41
42
12
13
14
15
16
17
18
28
31
32
19
29
67
68
69
70
11
46
48
66
71
10
30
59
U21
WRAS0-
RAS1RAS2RAS3-
CAS0CAS1CAS2CAS3-
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
ID1
ID2
ID3
ID4
RES1
RES2
RES3
RES4
RES5
VCC
VCC
VCC
32MX36SIMV
DQ8/P0
DQ17/P1
DQ26/P2
DQ35/P3
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ9
MD32
4
MD33
6
MD34
8
MD35
20
MD36
22
MD37
24
MD38
26
MD39
49
MD40
51
MD41
53
MD42
55
MD43
57
MD44
61
MD45
63
MD46
65
MD47
3
MD48
5
MD49
7
MD50
9
MD51
21
MD52
23
MD53
25
MD54
27
MD55
MD56
50
MD57
52
MD58
54
56
MD59
58
MD60
60
MD61
62
MD62
64
MD63
36
MP4
37
MP5
35
MP6
38
MP7
MD[0..63] 4,7
4,7
MP[0..7]
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
Title
Size Document NumberREV
B82430HXB.1
Date: June 19, 1997 Sheet 9 of 24
INTEL CORP.
System ROM
PWROK
17
PCLKPIIX3
3
PIIX3OSC
3
AD[0..31]
4,18,19
C/BE#[0..3]
4,18,19
4,18,19,21
4,18,19,21
4,18,19,21
220
4,18,19,21
R51
12
4,18,19,21
PIRQ#[0..3]
18,19,21
11,12,15,16,20,21
12,20,21
11,21
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
Title
Size Document NumberREV
B82430HXB.1
Date: June 19, 1997 Sheet 14 of 24
INTEL CORP.
Parallel Port
RP3
1 8
2 7
3 6
4 5
4.7K
VCC
R3
220
10,11
1
12,16
9,10,12,20,21
2
12,16
3
10
KBD_CLK
RSTDRV#
ROM_KB#
XIOR#
XIOW#
9,16
SA2
R11
220
XD[0..7]
C12
470Pf
KEYLOCK#
KBRST#
HA20M#
IRQ1
IRQ12
TP90
TP91
TP92
TP93
RP1
4 5
3 6
2 7
VCC
U5
29
KBCLK#
MSCLK#
KB_XT1
KBDSS#
EA_PD
XD0
XD1
XD2
XD3
XD4
2
XD5
XD6
XD7
1
VDD
2
TEST0
43
TEST1
3
XTAL1
4
XTAL2
5
RESET-
6
SS-
7
CS-
8
EA
9
RD-
10
A0
11
WR-
14
D0
D1
D2
D3
D4
D5
D6
D7
8242PCPL
P24/OBF
P25/IBF-
P26/DRQ
P27/DAK-
PROG
SYNC
15
16
17
18
19
20
21
KBDAT#
30
P10
MSDAT#
31
P11
KB_PU1
32
P12
PASSWDCLR#
33
P13
35
P14
PU_MFGTST
36
P15
COLOR
37
P16
KEYLOCK#
38
P17
24
P20
25
P21
MSEDAT
26
P22
MSECLK
27
P23
39
40
KBDCLK
41
KBDDAT
42
VCC
28
TP042
13
PU_CLCMOS
21
1
TP95
U4A
1 2
7406S
U4B
3
7406S
U4C
5
7406S
U4D
9
7406S
1
J4
JP2
2
JUMPER B
CLEAR
PASSWORD
PASSWORD
KBDAT_FB#
C17
470pf
KBCLK_FB#
1
C18
2
470Pf
L5
21
L6
4
6
8
21
L4
21
L3
21
1
2
10K
RP5
1 8
2 7
3 6
4 5
10K
JUMPER B
JUMPER
POS
MSDAT_FB#
1
C13
2
470Pf
1 8
1-2
INCLEAR
OUTNORMAL
MSCLK_FB#
1
2
17
4
2
10..12,15,16,20,21
10..12,15,16,20,21
1
TP045
1
TP046
1
TP044
1
TP043
L1
QUIETGND1
1
2
FUSE 1
KB5V_FB
1
C10
2
0.1uF
VCC
2
1
F
U
S
E
1
2
L7
1
QUIETGND2
2
1
F1
1.25A
KEYBOARD
CONNECTOR
J2
1
2
3
4
5
6
7
8
9
J1
1
2
3
4
5
6
7
8
9
MOUSE
CONNECTOR
L2
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
Title
Size Document NumberREV
B82430HXB.1
Date: June 19, 1997 Sheet 15 of 24
INTEL CORP.
Keyboard/Mouse Interface
10,20,21
10,20,21
10,12,20,21
IOR#
IOW#
RTCCS#
10
RTCALE
10
PWROK#
17
9,10
SD[0..7]
R1
12
12
XDIR#
10
XOE#
220
R4
220
IOR#PD
2 3
U3A
74LS125S
IOW#PD
5 6
U3B
74LS125S
U16B
4
5
74ALS32S
U16C
9
10
74ALS32S
1
19
SD7
9
SD6
8
SD5
7
SD4
6
SD3
5
SD2
4
SD1
3
SD0
2
1
4
U1
DIR
G
A8
A7
A6
A5
A4
A3
A2
A1
74ALS245S
XIOR#
12,15
XIOW#
12,15
6
VCC
8
XD7
11
B8
B7
B6
B5
B4
B3
B2
B1
XD6
12
XD5
13
XD4
14
XD3
15
XD2
16
XD1
17
XD0
18
12
R41
10K
R36
RTC_MOT
220
RTCWR#
1 2
RTCRD#
RTCRST#
XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7
XD[0..7]
U13
1
MOT
13
CS-
14
AS
15
R/W-
17
DS
18
RESET-
4
AD0
5
AD1
6
AD2
7
AD3
8
AD4
9
AD5
10
AD6
11
AD7
DS12887A
9,15
IRQ-
RSV1
RSV2
23
SQW
19
2
X1
3
X2
20
BC
21
22
TP051
TP048
TP047
TP049
RTCCEIN#
TP050
1
IRQ8
1
1
1
1
TP103
10..12,15,20,21
TP100
TP101
TP99
TP104
VCC
JUMPER POS
CLEAR CMOS IN
NORMAL OUT
1
R38
10K
2
J24
2 1
JP2
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
Title
Size Document NumberREV
B82430HXB.1
Date: June 19, 1997 Sheet 16 of 24
INTEL CORP.
BATTERY;RTC CICUIT
VCC
TP888
1
TP98
R127
1 2
68
SPK2
R128
SPKR
10
1 2
2.2K
SPK1
3
Q8
1
2N3904
2
R126
68
1 2
1
2
BUZZ2
C220
0.1 uF
J36
1
2
SPEAKER
3
4
15
KEYLOCK#
VCC
R60
12
220
PON
1
C210
2
470pF
1
C198
2
470pF
J33
1
POWER LED
2
3
KEYLOCK
4
5
11
HDACTA#
VCC
+3_3V
3 4
-12V +12V
-5V
U27B
7407S
VCC
1
R59
220
2
HDRV1
J32
HARD DRIVE LED
HDACTB#
1
0
U3C
74LS125S
1
2
3
4
11
VCC
1
2
EXTSMI#
10
R8
10K
PWRGD1
1
C8
2
10uF
HARDDRV
U27C
5 6
7407S
POWER_GOOD
J5
1
2
3
4
5
6
J13
1
2
3
4
5
6
J22
1
2
3
4
5
6
9 8
2
1
13
12
C216
4.7nF
VCC
1
C149
2
0.22uF
U2F
74HCT14S
R124
100
1
3
R58
D3
220
2
1N4148
2
J31
1
EXTSMI SWITCH
2
JP2
12
U2E
11
74HCT14S
RSTSW1
J35
1
2
10
PWROKR
RESET SWITCH
R7
33
C167
470pF
+12V
J34
1
CPU COOLING FAN
2
2
1
PWROK#
1 2
PWROK
JP2
16
10
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
Title
Size Document NumberREV
C82430HXB.1
Date: June 19, 1997Sheet 20 of 24
INTEL CORP.
ISA Slots 0, 1 and 2
RP31
10K
RP29
10K
RP27
10K
RP24
10K
RP21
10K
RP18
10K
RP16
10K
RP61
10K
RP40
10K
RP45
10K
RP65
2.7K
IRQ[0..15]
SA[0..19]
4 5
3 6
2 7
1 8
10..12,15,16,20
9,10,12,15,20
VCC
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
CPUVIO
PGNT#[0..3]
4,18,19
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
SA0
SA1
SA2
SA3
SA4
SA5
SA6
IRQ3
SA7
IRQ4
SA8
IRQ5
IRQ6
SA9
SA10
IRQ7
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
IRQ9
IRQ1
IRQ8
IRQ12
IRQ11
IRQ10
IRQ14
IRQ15
PGNT#3
PGNT#2
PGNT#1
PGNT#0
BALE
PU_CLCMOS
MIRQ0
SBHE#
MEMW#
MEMR#
10,20
10,20
9,10,20
9,10,20
10,12,16,20
VCC
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
DRQ[0..7]
10,12,20
1 8
2 7
3 6
4 5
15
VCC
VCC
10,18,1910,11
4,18,19
18,19
18,19
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
SD[0..15]
RP10
10K
RP6
10K
RP52
10K
RP58
10K
RP48
5.6K
RP19
5.6K
PIRQ#[0..3]
RP12
2.7K
PREQ#[0..3]
REQ64S#[0..3]
ACK64S#[0..3]
RP30
2.7K
RP33
4 5
3 6
2 7
1 8
2.7K
RP38
2.7K
RP64
4 5
3 6
2 7
1 8
2.7K
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD11
SD10
SD9
SD8
SD15
SD14
SD13
SD12
DRQ7
DRQ6
DRQ5
DRQ0
DRQ1
DRQ3
DRQ2
PIRQ#2
PIRQ#3
PIRQ#0
PIRQ#1
ACK64S#2
ACK64S#3
REQ64S#2
REQ64S#3
ACK64S#1
ACK64S#0
PREQ#0
REQ64S#0
REQ64S#1
PREQ#1
PREQ#3
PREQ#2
PAR
SERR#
VCC
4,10,18,19
4,10,18,19
10,11,20
RP34
1 8
2 7
3 6
4 5
2.7K
RP39
1 8
2 7
3 6
4 5
2.7K
RP17
1 8
2 7
3 6
4 5
10K
RP14
1 8
2 7
3 6
4 5
10K
RP28
1 8
2 7
3 6
4 5
2.7K
RP26
1 8
2 7
3 6
4 5
2.7K
RP35
1 8
2 7
3 6
4 5
330
RP56
1 8
2 7
3 6
4 5
330
RP60
1 8
2 7
3 6
4 5
1.0K
RP53
1 8
2 7
3 6
4 5
4.7K
LA[17..23]
LA17
LA18
LA19
LA21
LA22
LA20
LA23
Title
Size Document NumberREV
Date: June 19, 1997 Sheet 21 of 24
Pullup/Pulldown Resistors
B82430HXB.1
STOP#
IOR#
IOW#
DIVCLK
SMEMR#
SMEMW#
SBO#
PERR#
SDONE
PLOCK#
DEVSEL#
TRDY#
IRDY#
FRAME#
IOCS16#
MEMCS16#
REFRESH#
0WS#
MASTER#
IOCHRDY
DD13
IOCHK#
INTEL CORP.
4,10,18,19
10,16,20
10,16,20
10
10,20
10,20
18,19
18,19
18,19
4,18,19
4,10,18,19
4,10,18,19
4,10,18,19
4,10,18,19
10,20
10,20
10,20
10,12,20
20
10,12,20
10,11
10,20
TP566
TP567
1
2
1
2
C191
220uF
C215
220uF
J26
VRE STD
1
2
1-2 2-3
3
JP3
CPUVIO
C183
1
2
220uF
R85
Q2
S_0
S_1
S_2
G_0
SI4410DY
LRAWVIO
D2
21
1N5820
Q4
S_0
S_1
G_0
SI9410DY
12
18.7K
R113
12
965
8
D_3
7
D_2
6
D_1
5
D_0
R123
12
0.03
R121
12
0.03
RAWVIO
8
D_3
7
D_2
6
D_1
5
D_0
TP52
VIO2
VCC
REF
C189
1 2
500pF
REFR
TP568
C190
1 2
3300pF
TP565
C184
1 2
120pF
R105
12
1.27K
LBOUT
PGND
+12V
2
VFB
10
TP053
TDRIVE
SENSE
1
C203
1 2
1nF
2
C176
1
0.1uF
SENSE#
BDRIVE
TP564
14
1
9
8
16
15
VCC
U30
5
VIN
PINV
LBIN
SHDM
ITH
CT
BINH
SGND
LTC1266XS
+12V
PWRVIN
VFB_NC
TDRIVE
SENSE+
SENSEBDRIVE
3
TP052
ITH
CT
C168
1uF
13
11
7
6
4
12
1
2
1
R108
12
1.5K
RAWVIO
L14
12
2.2uH
R118
12
100
R117
12
100
1
2
3
4
2
3
4
R112
+12V
Q1
1
1
TP033
TP032
1
COL
2
COMP
V+
RTOP
LT1431CS
C223
0.1uF
RMID
GNDF
GNDS
1 2
3
4
12
33K
8
REF
TP098
7
1
6
5
1
12
C169
1
2
220uF
C182
1
2
220uF
R109
0
VRREF
TP030
1
2
1
2
C185
220uF
C214
220uF
6.3v
2
C225
1
1uF
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
2
R129
910
CORECATH
Q7
1
CATH
2
A_0
3
A_1
TL431ACS
VCOREREFIN
8
P
7
A_3
6
A_2
1
1
2
C
O
M
P
2
1
C222
0.01uF
R125
47K
R122
12
220
COREB2E
3
Q5
1
2N3904SOT23
2
2
1
Q6
2N3906SOT23
3
Z40DRV
2
R120
910
1
R116
12
22
2
R119
910
1
Z40DRVR
2
Q3
IRFZ40
1
3
JB3
1 2
3 4
5 6
7 8
JB4
1
2
C208
100uF
1
C211
2
100uF
CPU
TYPE
P54C
P55C
CPUVCORE
1
C192
2
100uF
JUMPER
1-2, 3-4,
5-6, 7-8
NONE
HEAT SINK
HS1
TP028
TP031
INTEL CORP.
1
TP570
1
TP569
1
C181
2
100uF
Title
Size Document NumberREV
B82430HXB.1
Date: June 19, 1997 Sheet 22 of 24
1
1
2
2
6021PB
Switching Power Supply
MH1
1
MH9UV157
MH2
1
MH9UV157
MH4
1
MH9UV157
MH5
1
MH9UV157
MH6
1
MH9UV157
MH7
1
MH9UV157
MH8
1
MH9UV157
MH9
1
MH9UV157
H1
H120
GF1
FM200B
FM4
FM200B
FM7
FM200B
1
1 GF2
1 FM5
1 FM8
1
1
1
1
H2
H120
1
FM200B
FM200B
FM200B
1
H3
H120
1
1
1
GF3
FM200B
FM6
FM200B
FM9
FM200B
H4
H158
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
U4E
1110
7406S
U4F
1312
7406S
TP100
TP099
U2D
8
TP106
TP104
1
TP931
1
TP926
1
TP929
1
TP930
9
74HCT14S
U27F
1312
7407S
SPARES
Title
Fiducials, Holes, Spare Gates
Size Document NumberREV
B82430HXB.1
Date: June 19, 1997 Sheet 23 of 24
INTEL CORP.
C112
1 2
0.1uF
C111
1 2
0.1uF
C26
1 2
0.1uF
C6
1 2
0.1uF
C44
1 2
0.1uF
C100
1 2
0.1uF
C139
1 2
0.1uF
C5
1 2
0.1uF
C104
1 2
0.1uF
C19
1 2
0.1uF
C137
1 2
0.1uF
C120
1 2
0.1uF
C103
1 2
0.1uF
THIS DRAWING CONTAINS INFORMATION
WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
VCCVCC
C3
1 2
0.1uF
C77
1 2
0.1uF
C135
1 2
0.1uF
C116
1 2
0.1uF
C152
1 2
0.1uF
C113
1 2
0.1uF
C34
1 2
0.1uF
C151
1 2
0.1uF
C140
1 2
0.1uF
C1
1 2
0.1uF
C2
1 2
0.1uF
C105
1 2
0.1uF
C15
1 2
0.1uF
C76
1 2
0.1uF
C115
1 2
0.1uF
C81
1 2
0.1uF
C129
1 2
0.1uF
C33
1 2
0.1uF
C35
1 2
0.1uF
C117
1 2
0.1uF
C118
1 2
0.1uF
C150
1 2
0.1uF
C43
1 2
0.1uF
VCC
C93
1 2
0.01uF
C138
1 2
0.01uF
C101
1 2
0.01uF
C128
1 2
0.01uF
C126
1 2
0.01uF
C108
1 2
0.01uF
C106
1 2
0.01uF
C78
1 2
0.01uF
C80
1 2
0.01uF
C94
1 2
0.01uF
C92
1 2
0.01uF
C4
1 2
0.001uF
C124
1 2
0.001uF
C114
1 2
0.001uF
C11
1 2
10uF
C125
1 2
10uF
C47
1 2
10uF
C119
1 2
10uF
C39
1 2
10uF
C134
1 2
10uF
C9
1 2
100uF
+3_3V
+12V
-12V
C86
1 2
10uF
C96
1 2
0.1uF
C99
1 2
0.1uF
C88
1 2
0.1uF
C98
1 2
0.1uF
C95
1 2
0.1uF
C87
1 2
0.1uF
C97
1 2
0.1uF
C102
1 2
0.1uF
C23
1 2
10uF
C50
1 2
0.1uF
C224
1 2
0.1uF
C22
10uF
C46
0.1uF
C14
0.1uF
CPUVIO
C175
1 2
100uF
C148
1 2
100uF
C170
1 2
0.1uF
C153
1 2
0.1uF
C156
1 2
0.1uF
C204
1 2
0.1uF
C127
1 2
0.1uF
C141
1 2
0.1uF
C171
1 2
0.1uF
C202
1 2
0.001uF
C197
1 2
0.001uF
C166
1 2
0.001uF
C165
1 2
0.001uF
1 2
1 2
1 2
DRAMVCC
7,8
C91
1 2
0.1uF
C122
1 2
0.1uF
C110
1 2
0.1uF
C123
1 2
0.1uF
C107
1 2
0.1uF
C109
1 2
0.001uF
C90
1 2
0.001uF
C121
1 2
0.001uF
C89
1 2
0.001uF
C133
1 2
0.001uF
C132
1 2
100uF
Title
Size Document NumberREV
B82430HXB.1
Date: June 19, 1997 Sheet 24 of 24
INTEL CORP.
Decoupling Capacitors
-5V
C226
1 2
0.01uF
2
C7
1
10uF
CPUVCORECPUVIO
Root schematic for netlisting
multiple flat files.