Intel 41210 User Manual
Intel® 41210 Serial to Parallel PCI Bridge
Design Guide
May 2005
Order Number: 278801-004
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Copyright © Intel Corporation, 2005
ii Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Contents
Contents
1 About This Document ...................................................................................................................7
1.1 Terminology and Definitions .................................................................................................7
2 Introduction....................................................................................................................................9
2.1 PCI Express Interface Features............................................................................................9
2.2 PCI-X Interface Features......................................................................................................9
2.3 Power Management............................................................................................................10
2.4 SMBus Interface .................................................................................................................10
2.4.1 SMBus for configuration register initialization........................................................10
2.4.2 Microcontroller Connections to the 41210 Bridge..................................................11
2.5 JTAG...................................................................................................................................12
2.6 Related Documents ............................................................................................................12
2.7 Intel
3 Package Information ...................................................................................................................15
3.1 Package Specification ........................................................................................................15
4 Power Plane Layout ....................................................................................................................19
4.1 41210 Bridge Decoupling Guidelines .................................................................................19
4.2 Split Voltage Planes............................................................................................................21
®
41210 Serial to Parallel PCI Bridge Applications......................................................13
5 41210 Bridge Reset and Power Timing Considerations ..........................................................23
5.1 A_RST#,B_RST# and PERST# Timing Requirements ......................................................23
5.2 VCC15 and VCC33 Voltage Requirements........................................................................23
6 General Routing Guidelines .......................................................................................................25
6.1 General Routing Guidelines................................................................................................25
6.2 Crosstalk.............................................................................................................................25
6.3 EMI Considerations ............................................................................................................26
6.4 Power Distribution and Decoupling.....................................................................................27
6.4.1 Decoupling.............................................................................................................27
6.5 Trace Impedance................................................................................................................27
6.5.1 Differential Impedance...........................................................................................28
7 Board Layout Guidelines............................................................................................................29
7.1 Adapter Card Topology.. ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ....................................29
8 PCI-X Layout Guidelines.............................................................................................................31
8.1 Interrupts.............................................................................................................................31
8.1.1 Interrupt Routing for Devices Behind a Bridge.......................................................32
8.2 PCI Arbitration ....................................................................................................................32
8.2.1 PCI Resistor Compensation ..................................................................................33
8.3 PCI General Layout Guidelines ..........................................................................................33
8.3.1 PCI Pullup Resistors Not Required........................................................................34
8.4 PCI Clock Layout Guidelines ..............................................................................................35
8.5 PCI-X Topology Layout Guidelines.....................................................................................38
8.6 Intel
®
41210 Serial to Parallel PCI Bridge Design Guide Layout Analysis .........................38
Intel® 41210 Serial to Parallel PCI Bridge Design Guide iii
Contents
8.6.1 Embedded PCI-X 133 MHz ...................................................................................39
8.6.2 Embedded PCI-X 100 MHz ...................................................................................40
8.6.3 PCI-X 66 MHz Embedded Topology......................................................................41
8.6.4 PCI 66 MHz Embedded Topology.........................................................................42
8.6.5 PCI 33 MHz Embedded Mode Topology...............................................................43
9 PCI Express Layout.....................................................................................................................45
9.1 General recommendations ................................ ...... ...... ....... ...... ....... ...... ....... ...... ..............45
9.2 PCI-Express Layout Guidelines..........................................................................................46
9.3 Adapter Card Layout Guidelines.........................................................................................46
10 Circuit Implementations..............................................................................................................49
10.1 41210 Bridge Analog Voltage Filters..................................................................................49
10.1.1 PCI Analog Voltage Filters.....................................................................................50
10.1.2 PCI Express Analog Voltage Filter ........................................................................50
10.1.3 Bandgap Analog Voltage Filter..............................................................................51
10.2 Intel® 41210 Serial to Parallel PCI Bridge Reference and Compensation Pins.................53
10.2.1 SM Bus..................................................................................................................54
11 41210 Bridge Customer Reference Boards...............................................................................55
11.1 Board Stack-up..................................................................... ...... ....... ...... ....... ...... ....... .......55
11.2 Material...............................................................................................................................56
11.3 Impedance..........................................................................................................................56
11.4 Board Outline.................... ....... ...... ....... ...... ....... ...... ...... ....... ...... ........................................57
12 Design Guide Checklist ..............................................................................................................59
Figures
1 41210 Bridge Microcontroller Block Diagram .............................................................................11
2 41210 Bridge Microcontroller Connections.................................................................................11
3 41210 Bridge Block Diagram......................................................................................................12
4Intel
5 Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions..............................................15
6 Bottom View - 41210 Bridge 567-Ball FCBGA Package Dimensions ........................................16
7 Side View - 41210 Bridge 567-Ball FCBGA Package Dimensions.............................................17
8 Decoupling Placement for Core and PCI Express Voltage Planes ............................................19
9 Decoupling Placement for PCI/PCI-X 1.5V and 3.3V Voltage Planes........................................20
10 41210 Bridge Single-Layer Split Voltage Plane..........................................................................22
11 Crosstalk Effects on Trace Distance and Height........................................................................26
12 PCB Ground Layout Around Connectors ...................................................................................26
13 Cross Section of Differential Trace.............................................................................................28
14 Two-by-two Differential Impedance Matrix .................................................................................28
15 Adapter Card Stackup .............. ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ...........................30
16 PCI RCOMP ...............................................................................................................................33
17 PCI Clock Distribution and Matching Requirements...................................................................36
18 Embedded PCI-X 133 MHz Topology ........................................................................................39
19 Embedded PCI-X 100 MHz Topology ........................................................................................40
20 PCI-X 66 MHz Embedded Routing Topology.............................................................................41
21 PCI 66 MHz Embedded Topology..............................................................................................42
®
41210 Bridge Adapter Card Block Diagram......................................................................13
iv Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Contents
22 PCI 33 MHz Embedded Mode Routing Topology.......................................................................43
23 PCI Analog Voltage Filter Circuit................................................................................................50
24 PCI Express Analog Voltage Filter Circuit ..................................................................................51
25 Bandgap Analog Voltage Filter Circuit........................................................................................52
26 Reference and Compensation Circuit Implementations .............................................................53
27 Proposed Mechanical Outline of the 41210 Bridge ....................................................................57
Tables
1 Terminology and Definitions.........................................................................................................7
2 41210 Bridge Decoupling Guidelines .........................................................................................21
3 Adapter Card Stack Up, Microstrip and Stripline ........................................................................29
4 INTx Routing Table.....................................................................................................................31
5 Interrupt Binding for Devices Behind a Bridge...........................................................................32
6 PCI-X Signals .............................................................................................................................34
7 PCI/PCI-X Frequency/Mode Straps............................................................................................34
8 PCI-X Clock Layout Requirements Summary.............................................................................37
9 PCI-X Slot Guidelines.................................................................................................................38
10 Embedded PCI-X 133 MHz Routing Recommendations............................................................39
11 Embedded PCI-X 100 MHz Routing Recommendations............................................................40
12 PCI-X 66 MHz Embedded Routing Recommendations..............................................................41
13 PCI 66 MHz Embedded Table....................................................................................................42
14 PCI 33 MHz Embedded Routing Recommendations..................................................................43
15 Adapter Card Routing Recommendations..................................................................................46
16 Recommended R, L and C Values for 41210 Bridge Analog Filter Circuits ...............................49
17 SMBUs Address Configuration...................................................................................................54
18 CRB Board Stackup....................................................................................................................56
19 PCI Express Interface Signals....................................................................................................59
20 PCI/PCI-X Interface Signals .......................................................................................................60
21 Miscellaneous Signals ................................................................................................................62
22 SMBus Interface Signals ............................................................................................................62
23 Power and Ground Signals.........................................................................................................63
24 JTAG Signals......................... ....... ...... ....... ...... ....................................... ...... ....... ...... .................64
Revision History
Date Revision Description
Removed Section 5.3, VCCPE and REFCLKn/REFCLKp
May 2005 004
October 2004 003
July 2004 002 Updated Chapters 4, 5, and 12
October 2003 001
July 2003 000 First internal draft of this document.
Intel® 41210 Serial to Parallel PCI Bridge Design Guide v
Information
Added signals to Section 8.3.1
Updated Table 19, Table 20, and Table 21
Updated PCI Express operation information in Section 2.1 and
Table 19.
Added signal NC17 information in Table 21.
Updated content; second draft of this document; initial public
release of this document.
Contents
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vi Intel® 41210 Serial to Parallel PCI Bridge Design Guide
About This Document 1
This document provides layout i nformation and guide lines for designing p latform or add-in board
applications with the Intel
®
41210 Serial to Parall el PCI Br idge (also c alled the 41 210 Bridge). I t is
recommended that this document be used as a guideline. Intel r ecommen ds emp l oyi ng b est -k now n
design practices with board level simulation, signal integrity testing and validation for a robust
design.
Designers should note that this guide focuses upon specific design considerations for the 41210
Bridge and is not intended to be an all-inclusive list of all good design practices. Use this guide as
a starting point and use empirical data to optimize your particular design.
1.1 Terminology and Definitions
Table 1 provides a list of terms and definitions that may be useful when working with the 41210
Bridge product.
Table 1. Terminology and Definitions (Sheet 1 of 2)
Term Definition
Stripline
Stripline in a PCB is composed of the
conductor inserted in a dielectric with GND
planes to the top and bottom.
NOTE: An easy way to distinguish stripline
from microstrip is that you need to
strip away layers of the board to view
the trace on stripline.
Microstrip
Prepreg
Core
Intel® 41210 Serial to Parallel PCI Bridge Design Guide 7
Material used for the lamination process of manufacturing PCBs. It consists of a layer of
epoxy material that is placed between two cores. This layer melts into epoxy when heated and
forms around adjacent traces.
Material used for the lamination process of manufacturing PCBs. This material is two sided
laminate with copper on each side. The core is an internal layer that is etched.
Microstrip in a PCB is composed of the
conductor on the top layer above the dielectric
with a ground plane below
About This Document
Table 1. Terminology and Definitions (Sheet 2 of 2)
Term Definition
Layer 1: copper
Prepreg
Layer 2: GND
Core
PCB
Example of a Four-Layer Stack
SSTL_2 Series Stub Terminated Logic for 2.5 V
JEDEC Provides standards for the semiconductor industry.
A network that transmits a coupled signal to another network is aggressor network.
Aggressor
Victim A network that receives a coupled cross-talk signal from another network is a victim network.
Network The trace of a PCB that completes an electrical connection between two or more components.
Stub Branch from a trunk terminating at the pad of an agent.
CRB Customer Reference Board
Downstream
Upstream
Local memory
DWORD 32-bit data word.
Flip Chip
Mode
Conversion
PCI-E PCI-Express
Downstream refers either to the relative position of an interconnect/system element (Link/
device) as something that is farther from the Root Complex, or to a direction of information
flow, i.e., when information is flowing away from the Root Complex.
Memory subsystem on the Intel XScale
busses.
FC-BGA (flip chip-ball grid array) chip packages are designed with processor core flipped up
on the back of the chip, facing away from the PCB. This allows more efficient cooling of the
package.
Mode Conversions are due to imperfections on the interconnect which transform differential
mode voltage to common mode voltage and common mode voltage to differential voltage.
Zo
Layer 3: VCC15
Prepreg
Layer 4: copper
Zo
Victim Network
Aggressor Network
Printed circuit board.
Example manufacturing process consists of
the following steps:
• Consists of alternating layers of core and
prepreg stacked
• The finished PCB is heated and cured.
• The via holes are drilled
• Plating covers holes and outer surfaces
• Etching removes unwanted copper
• Board is tinned, coated with solder mask
and silk screened
Zo
Zo
®
core DDR SDRAM or Peripheral Bus Interface
8 Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Introduction 2
The Intel®41210 Serial to Parallel PCI Bridge integrates two PCI Express-to-PCI bridges. Each
bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compliant to
the PCI Express Specification, Revision 1.0. The two PCI bus interfaces are fully compliant to the
PCI Local Bus Specification, Revision 2.3.
2.1 PCI Express Interface Features
• PCI Express Specification, Revision 1.0b compliant.
• Support for single x8, single x4 or single x1 PCI Express operation.
• 64-bit addressing support.
• 32-bit CRC (cyclic redundancy checking) covering all transmitted data packets.
• 16-bit CRC on all link message information.
• Raw bit-rate on the data pins of 2.5 Gbit/s, resulting in a raw bandwidth per pin of 250 MB/s.
• Maximum realized bandwidth on PCI Express interface is 2 GB/s (in x8 mode) in each
direction simultaneously, for an aggregate of 4 GB/s .
2.2 PCI-X Interface Features
• PCI Local Bus Specification, Revision 2.3 compliant.
• PCI-to-PCI Bridge Specification, Revision 1.1 compliant.
• PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a compliant.
• 64-bit 66 MHz, 3.3 V, NOT 5 V tolerant.
• On Die Termination (ODT) with 8.2KΩ pull-up to 3.3V for PCI signals.
• Six external REQ/GNT Pairs for internal arbiter on segment A and B respectively.
• Programmable bus parking on either the last agent or always on Lanai.
• 2-level programmable round-robin internal arbiter with Multi-Transaction Timer (MTT)
• External PCI clock-feed support for asynchronous primary and secondary domain operation.
• 64-bit addressing for upstream and downstream transactions
• Downstream LOCK# support.
• No upstream LOCK# support.
• PCI fast Back-to-Back capable as target.
• Up to four active and four pending upstream memory read transactions
• Up to two downstream delayed (memory read, I/O read/write and configuration read/write)
transaction.
Intel® 41210 Serial to Parallel PCI Bridge Design Guide 9
Introduction
• Tunable inbound read prefetch algorithm for PCI MRM/MRL commands
• Local initialization via SMBus
• Secondary side initialization via Type 0 configuration cycles.
2.3 Power Management
• Support for PCI Express Active State Power Management (ASPM) L0s link state
• Support for PCI PM 1.1 compatible D0, D3hot and D3cold device power states
• Support for PME# event propagation on behalf of PCI devices
2.4 SMBus Interface
• Compatible with System Management Bus Specification, Revision 2.0
• Slave mode operation only.
• Full read/write access to all configuration registers
2.4.1 SMBus for configuration register initialization
• Support for local initialization of the configuration registers can be implemented using a
microcontroller via SMB. Figure 1shows this SMBus and the data transfer that occurs between
the 41210 Bridge and the microcontroller.
• Configuration Register information is stored internally in a microcontroller and the
information is transferred to the product via System Managed Bus (SMBus) protocols when
the device receives power or reset.
• The requirements of the microcontroller are as follows:
2
— Supports I
— Has at least 256 Byte of internal EEprom space
— To facilitate this programming on the Customer Reference Board a Microchip part
PIC16F876A was used.
— Code space: estimated code size is ~2K words of program space and 32 words of RAM
C and SMBus Prot ocols
10 Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Figure 1. 41210 Bridge Microcontroller Block Diagram
SMBus 2.0
Introduction
Microcontroller
Configuration
Register
Data
Intelfi 41210 Bridge
Configuration
Register
Address Space
2.4.2 Microcontroller Connections to the 41210 Bridge
The following diagram shows the SMB interface from the 41210 Bridge to the microcontroller.
Figure 2. 41210 Bridge Microcontroller Connections
3.3 V
B2707-01
SDI / SDA
SCK / SCL
RC1
RBO / INT
PIC16F876A
OSC2 / CLKOUT
20 MHz
OSC1 / CLKIN
22 pF 22 pF
B2708-01
Intelfi 41210
Bridge
CFGRETRY
CFG_RST_N
SMBDAT
SMBCLK
SMDAT
SMCLK
CFG_RETRY
CFG_RESET
Intel® 41210 Serial to Parallel PCI Bridge Design Guide 11
Introduction
2.5 JTAG
• Compliant with IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a
2.6 Related Documents
• Intel® 41210 Serial to Parallel PCI Bridge Design Specification (EDS), Revision 1.0.
• PCI Express Specification, Revision 1.0, from www.pci-sig.com.
• PCI Express Design Guide, Revision 0.5
• PCI Local Bus Specification, Revision 2.3, from www.pci-sig.com.
• PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, from www.pci-sig.com.
• IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a
• System Management Bus Specification, Revision 2.0
Figure 3. 41210 Bridge Block Diagram
PCI-Express x8
JTAG SMB Bus
fi
Intel
41210 Bridge
B_PCLKIA_PCLKI
A
Bus Arbiter
A
Clock Buffer
B
Bus Arbiter
B
Clock Buffer
A Bus PCI-X 133MHz
6 REQ/GNT Pairs
6 A_PCLKO
B Bus PCI-X 133MHz
6 REQ/GNT Pairs
6 B_PCLKO
B2709-01
12 Intel® 41210 Serial to Parallel PCI Bridge Design Guide
2.7 Intel®41210 Serial to Parallel PCI Bridge Applications
This section provides a block diagram for a typical the 41210 Bridge application. This application
shows a PCI-E adapter card with two Dual 2Gb Fibre Channel controllers. Each of the PCI-X bus
segments is connected to the Dual 2Gb Fibre Channel chip running at 133MHz. The two Dual FC
chips provides the four 2Gb/s outputs.
Figure 4. Intel
®
41210 Bridge Adapter Card Block Diagram
Introduction
I2C Micro
Controller
®
41210
Intel
Bridge
PCI-X to
PCI Express
PCI Express
(to Server)
SFP Optical
Dual 2Gb
FC
133 MHz
PCI-X
Dual 2Gb
FC
This is locally configurable from SMBus or
PCI-X interfaces (no BIOS support or Drivers
required)
SFP Optical
SFP Optical
SFP Optical
Module
Module
Module
Module
2 Gb/s
2 Gb/s
2 Gb/s
2 Gb/s
B1491-02
Intel® 41210 Serial to Parallel PCI Bridge Design Guide 13
Introduction
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14 Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Package Information 3
3.1 Package Specification
The 41210 Bridge is in a 567-ball FCBGA package, 31mm X 31mm in size, with a 1.27mm ball
pitch.
Figure 5. Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions
Han d lin g
Exclusion
Area
0.550 in.
0.550 in.
17.00 mm
21.00 mm
Die Area
17.00 mm
21.00 mm
31.00 mm
31.00 mm
Pkg_567-Ball_Top
Intel® 41210 Serial to Parallel PCI Bridge Design Guide 15
Package Information
Figure 6. Bottom View - 41210 Bridge 567-Ball FCBGA Package Dimensions
AD
AC
AB
AA
Y
W
V
U
T
4X 0.635
4X 15.500
23X 1.270
R
P
N
M
L
K
J
H
G
F
E
D
C
B
+
+
A
4681012 1618202224214
3 5 7 9 11 13 15 211 231917
23X 1.270
8X 14.605
(0.895)
29.2100
31.00 – 0.100
A
0.200
-B-
31.00 – 0.100
-A-
B2711-01
16 Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package Dimensions
Detail J
Underfill
Epoxy
Scale 5:1
FC BGA Substrate
Die
H
Detail H
Scale 5:1
1.170 – 0.085
0.600 – 0.100
J
Package Information
0.74 – 0.025
0.100 – 0.025
Die Solder
Bumps
1.940 – 0.150
BGA Solder Balls
B2712-01
Intel® 41210 Serial to Parallel PCI Bridge Design Guide 17
Package Information
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18 Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Power Plane Layout 4
This chapter provides detail s on the decoupling and voltage plan es needed to b ias the 41210 Br idge
package.
4.1 41210 Bridge Decoupling Guidelines
Table 2 lists the decoupling guidelines for the 41210 Bridge. Figure 8 and Figure 9 provide the
decoupling capacitors around the 41210 Bridge ball grid pins.
Figure 8. Decoupling Placement for Core and PCI Express Voltage Planes
B2713-01
Intel® 41210 Serial to Parallel PCI Bridge Design Guide 19
Power Plane Layout
Figure 9. Decoupling Placement for PCI/PCI-X 1.5V and 3.3V Volt age Planes
Capacitor Legend
0603-0.1 F
0603-1 F
1206-10 F
B2714-01
20 Intel® 41210 Serial to Parallel PCI Bridge D esign Guide
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