Intel 41110 User Manual
Intel® 41110 Serial to Parallel PCI Bridge
Design Guide
March 2006
Order Number: 310335-001
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Copyright © Intel Corporation, 2006
ii Intel® 41110 Serial to Parallel PCI Bridge Design Guide
Contents
Contents
1 About This Document ...................................................................................................................7
1.1 Terminology and Definitions .................................................................................................7
2 Introduction....................................................................................................................................9
2.1 PCI Express Interface Features............................................................................................9
2.2 PCI-X Interface Features......................................................................................................9
2.3 Power Management............................................................................................................10
2.4 SMBus Interface .................................................................................................................10
2.5 JTAG...................................................................................................................................12
2.6 Related Documents ............................................................................................................12
2.7 Intel® 41110 Serial to Parallel PCI Bridge Applications .....................................................13
3 Package Information ...................................................................................................................15
3.1 Package Specification ........................................................................................................15
4 Power Plane Layout ....................................................................................................................17
4.1 41110 Decoupling Guidelines......................... ...... ...... ....... ...... ....... ...... ....... .......................1 7
4.2 Split Voltage Planes............................................................................................................19
5 41110 Reset and Power Timing Considerations.......................................................................21
5.1 A_RST# and PERST# Timing Requirements.....................................................................21
5.2 VCC15 and VCC33 Voltage Requirements........................................................................21
6 General Routing Guidelines .......................................................................................................23
6.1 General Routing Guidelines................................................................................................23
6.2 Crosstalk.............................................................................................................................23
6.3 EMI Considerations ............................................................................................................24
6.4 Power Distribution and Decoupling.....................................................................................25
6.5 Trace Impedance................................................................................................................25
7 Board Layout Guidelines............................................................................................................27
7.1 Adapter Card Topology.. ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ....................................27
8 PCI-X Layout Guidelines.............................................................................................................29
8.1 Interrupts.............................................................................................................................29
8.2 PCI Arbitration ....................................................................................................................30
8.3 PCI General Layout Guidelines ..........................................................................................31
8.4 PCI Clock Layout Guidelines ..............................................................................................32
8.5 PCI-X Topology Layout Guidelines.....................................................................................35
8.6 41110 Layout Analysis............................. ....... ...... ...... ....... ....................................... ...... ....35
9 PCI Express Layout.....................................................................................................................41
9.1 General recommendations .................................................................................................41
9.2 PCI-Express Layout Guidelines..........................................................................................42
9.3 Adapter Card Layout Guidelines.........................................................................................42
10 Circuit Implementations..............................................................................................................45
10.1 41110 Analog Voltage Filters.......................... ...... ...... ....................................... ....... ...... ....45
Intel® 41110 Serial to Parallel PCI Bridge Design Guide iii
Contents
10.2 41110 Reference and Compensation Pins.........................................................................48
11 41110 Customer Reference Boards...........................................................................................51
11.1 Board Stack-up..................................... ...................................... ....... ...... ....... ...... ....... .......51
11.2 Material...............................................................................................................................52
11.3 Impedance..........................................................................................................................52
11.4 Board Outline.................... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... .................................53
12 Design Guide Checklist ..............................................................................................................55
Figures
1 Microcontroller Block Diagram....................................................................................................11
2 41110 Microcontroller Connections............................................................................................12
3 41110 Block Diagram .................................................................................................................13
4 41110 Adapter Card Block Diagram...........................................................................................14
5 41110 Bridge Package Dimensions (Top View) .........................................................................15
6 41110 Bridge Package Dimensions (Side View)........................................................................16
7 Decoupling Placement for Core and PCI Express Voltage Planes ............................................17
8 Decoupling Placement for PCI/PCI-X 1.5V and 3.3V Voltage Planes........................................18
9 41110 Bridge Single-Layer Split Voltage Plane..........................................................................20
10 Crosstalk Effects on Trace Distance and Height........................................................................24
11 PCB Ground Layout Around Connectors ...................................................................................24
12 Cross Section of Differential Trace.............................................................................................26
13 Two-by-two Differential Impedance Matrix .................................................................................26
14 Adapter Card Stackup .............. ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ...........................28
15 PCI RCOMP ...............................................................................................................................31
16 PCI Clock Distribution and Matching Requirements...................................................................33
17 Embedded PCI-X 133 MHz Topology ........................................................................................36
18 Embedded PCI-X 100 MHz Topology ........................................................................................37
19 PCI-X 66 MHz Embedded Routing Topology.............................................................................38
20 PCI 66 MHz Embedded Topology..............................................................................................39
21 PCI 33 MHz Embedded Mode Routing Topology.......................................................................40
22 PCI Analog Voltage Filter Circuit................................................................................................46
23 PCI Express Analog Voltage Filter Circuit..................................................................................47
24 Bandgap Analog Voltage Filter Circuit........................................................................................48
25 Reference and Compensation Circuit Implementations .............................................................49
26 Mechanical Outline of the 41110................................................................................................53
Tables
1 Terminology and Definitions .........................................................................................................7
2 41110 Decoupling Guidelines.....................................................................................................19
3 Adapter Card Stack Up, Microstrip and Stripline ........................................................................27
4 INTx Routing Table.....................................................................................................................29
5 Interrupt Binding for Devices Behind a Bridge...........................................................................30
6 PCI-X Signals .............................................................................................................................32
7 PCI/PCI-X Frequency/Mode Straps............................................................................................32
8 PCI-X Clock Layout Requirements Summary ............................................................................34
9 PCI-X Slot Guidelines.................................................................................................................35
iv Intel® 41110 Serial to Parallel PCI Bridge Design Guide
Contents
10 Embedded PCI-X 133 MHz Routing Recommendations............................................................36
11 Embedded PCI-X 100 MHz Routing Recommendations............................................................37
12 PCI-X 66 MHz Embedded Routing Recommendations..............................................................38
13 PCI 66 MHz Embedded Table....................................................................................................39
14 PCI 33 MHz Embedded Routing Recommendations..................................................................40
15 Adapter Card Routing Recommendations..................................................................................42
16 Recommended R, L and C Values for 41110 Analog Filter Circuits...........................................45
17 SMBUs Address Configuration...................................................................................................49
18 CRB Board Stackup....................................................................................................................51
19 PCI Express Interface Signals....................................................................................................55
20 PCI/PCI-X Interface Signals .......................................................................................................56
21 Miscellaneous Signals ................................................................................................................57
22 SMBus Interface Signals ............................................................................................................58
23 Reset Pins ..................................................................................................................................59
24 Power and Ground Signals.........................................................................................................60
25 JTAG Signals......................... ....... ...... ....... ...... ....................................... ...... ....... ...... .................61
Intel® 41110 Serial to Parallel PCI Bridge Design Guide v
Contents
Revision History
Date Revision Description
March 2006 001 Initial release.
vi Intel® 41110 Serial to Parallel PCI Bridge Design Guide
About This Document 1
This document provides layout i nformation and guide lines for designing p latform or add-in board
applications with the Intel® 41110 Serial to Parallel PCI Bridge (also called the 411 10 Bridge). It is
recommended that this document be used as a guideline. Intel recommends employing best-known
design practices with board level simulation, signal integrity testing and validation for a robust
design.
Designers should note that this guide focuses upon specific design considerations for the 41110
Bridge and is not intended to be an all-inclusive list of all good design practices. Use this guide as
a starting point and use empirical data to optimize your particular design.
1.1 Terminology and Definitions
Table 1 provides a list of terms and definitions that may be useful when working with the 41110
Bridge product.
Table 1. Terminology and Definitions (Sheet 1 of 2)
Term Definition
Stripline in a PCB is composed of the
conductor inserted in a dielectric with GND
planes to the top and bottom.
Stripline
NOTE: An easy way to distinguish stripline
from microstrip is that you need to
strip away layers of the board to view
the trace on stripline.
Microstrip
Prepreg
Core
Intel® 41110 Serial to Parallel PCI Bridge Design Guide 7
Material used for the lamination process of manufacturing PCBs. It consists of a layer of
epoxy material that is placed between two cores. This layer melts into epoxy when heated and
forms around adjacent traces.
Material used for the lamination process of manufacturing PCBs. This material is two sided
laminate with copper on each side. The core is an internal layer that is etched.
Microstrip in a PCB is composed of the
conductor on the top layer above the dielectric
with a ground plane below
About This Document
Table 1. Terminology and Definitions (Sheet 2 of 2)
Term Definition
Layer 1: copper
Prepreg
Layer 2: GND
Core
PCB
Example of a Four-Layer Stack
SSTL_2 Series Stub Terminated Logic for 2.5 V
JEDEC Provides standards for the semiconductor industry.
A network that transmits a coupled signal to another network is aggressor network.
Aggressor
Victim A network that receives a coupled cross-talk signal from another network is a victim network.
Network The trace of a PCB that completes an electrical connection between two or more components.
Stub Branch from a trunk terminating at the pad of an agent.
CRB Customer Reference Board
Downstream
Upstream
Local memory
DWORD 32-bit data word.
Flip Chip
Mode
Conversion
PCI-E PCI-Express
Downstream refers either to the relative position of an interconnect/system element (Link/
device) as something that is farther from the Root Complex, or to a direction of information
flow, i.e., when information is flowing away from the Root Complex.
Memory subsystem on the Intel XScale
busses.
FC-BGA (flip chip-ball grid array) chip packages are designed with processor core flipped up
on the back of the chip, facing away from the PCB. This allows more efficient cooling of the
package.
Mode Conversions are due to imperfections on the interconnect which transform differential
mode voltage to common mode voltage and common mode voltage to differential voltage.
Zo
Layer 3: VCC15
Prepreg
Layer 4: copper
Zo
Victim Network
Aggressor Network
Printed circuit board.
Example manufacturing process consists of
the following steps:
• Consists of alternating layers of core and
prepreg stacked
• The finished PCB is heated and cured.
• The via holes are drilled
• Plating covers holes and outer surfaces
• Etching removes unwanted copper
• Board is ti nned, coated with solder mask
and silk screened
Zo
Zo
®
processor DDR SDRAM or Peripheral Bus Interface
8 Intel® 41110 Serial to Parallel PCI Bridge Design Guide
Introduction 2
The Intel® 411 1 0 Serial to Parallel PCI Bridge integrates a PCI Express-to-PCI bridge. The bridge
follows the PCI-to-PCI Bridge programming model. The PCI Express port is compliant to the PCI
Express Specification, Revision1.0. The PCI bus interface is fully compliant to the PCI Lo cal Bus
Specification, Revision 2.3.
2.1 PCI Express Interface Features
• PCI Express Specification, Revision 1.0b compliant.
• Support for single x8, single x4 or single x1 PCI Express operation.
• 64-bit addressing support.
• 32-bit CRC (cyclic redundancy checking) covering all transmitted data packets.
• 16-bit CRC on all link message information.
• Raw bit-rate on the data pins of 2.5 Gbit/s, resulting in a raw bandwidth per pin of 250 MB/s.
• Maximum realized bandwidth on PCI Express interface is 2 GB/s (in x8 mode) in each
direction simultaneously, for an aggregate of 4 GB/s.
2.2 PCI-X Interface Features
• PCI Local Bus Specification, Revision 2.3 compliant.
• PCI-to-PCI Bridge Specification, Revision 1.1 compliant.
• PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a compliant.
• 64-bit 66 MHz, 3.3 V, NOT 5 V tolerant.
• On Die Termi nati on (ODT) with 8.2KΩ pull-up to 3.3V for PCI signals.
• Six external REQ/GNT Pairs for internal arbiter on the PCIX bus segment respectively.
• Programmable bus parking on either the last agent or always on Int el® 41 1 10 S erial to Parallel
PCI Bridge.
• 2-level programmable round-robin internal arbiter with Multi-Transaction Timer (MTT)
• External PCI clock-feed support for asynchronous primary and secondary domain operation.
• 64-bit addressing for upstream and downstream transactions
• Downstream LOCK# support.
• No upstream LOCK# support.
• PCI fast Back-to-Back capable as target.
• Up to four active and four pending upstream memory read transactions
Intel® 41110 Serial to Parallel PCI Bridge Design Guide 9
Introduction
• Up to two downstream delayed (memory read, I/O read/write and configuration read/write)
transaction.
• Tunable inbound read prefetch algorithm for PCI MRM/MRL commands
• Local initialization via SMBus
• Secondary side initialization via Type 0 configuration cycles.
2.3 Power Management
• Support for PCI Express Active State Power Management (ASPM) L0s link state
• Support for PCI PM 1.1 compatible D0, D3hot and D3cold device power states
• Support for PME# event propagation on behalf of PCI devices
2.4 SMBus Interface
• Compatible with System Management Bus Specification, Revision 2.0
• Slave mode operation only.
• Full read/write access to all configuration registers
2.4.1 SMBus for configuration register initialization
• Support for local initialization of the configuration registers can be implemented using a
microcontroller via SMB. Figure 1shows this SMBus and the data transfer that occurs between
the 41110 and the microcontroller.
• Configuration Register information is stored internally in a microcontroller and the
information is transferred to the product via System Managed Bus (SMBus) protocols when
the device receives power or reset.
• The requirements of the microcontroller are as follows:
— Supports I
— Has at least 256 Byte of internal EEprom space
— To facilitate this programming on the Customer Reference Board a Microchip part
PIC16F876A was used.
— Code space: estimated code size is ~2K words of program s pace and 32 words of RAM
2
C and SMBus Prot ocols
10 Intel® 41110 Serial to Parallel PCI Bridge Design Guide
Figure 1. Micro c ontro l ler Block Diag ra m
Introduction
Se rial to P ar a lle l
PCI Bridge
2.4.2 Microcontroller Connections to the 41110
Figure 2 shows the SMB interface from the 41110 to the microcontroller.
Intel® 41110 Serial to Parallel PCI Bridge Design Guide 11
Introduction
Figure 2. 41110 Microcontroller Connections
Serial to
Parallel PCI
Bridge
2.5 JTAG
• Compliant with IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a
2.6 Related Documents
• .
• PCI Express Specification, Revision 1.0, from www.pci-s ig.com.
• PCI Express Design Guide, Revision 0.5
• PCI Local Bus Specification, Revision 2.3, from www.pci-sig.com.
• PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, from www.pci-sig.com.
• IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a
• System Management Bus Specification, Revision 2.0
12 Intel® 41110 Serial to Parallel PCI Bridge Design Guide
Figure 3. 41110 Block Diagram
Introduction
Serial to Parallel
PCI Bridge
2.7 Intel® 41110 Serial to Parallel PCI Bridge Applications
This section provides a block diagram for a typical the 41110 application. This application shows a
PCI-E adapter card with two Dual 2Gb Fibre Channel controllers. Each of the PCI-X bus segmen ts
is connected to the Dual 2Gb Fibre Channel chip running at 133MHz. The two Dual FC chips
provides the four 2Gb/s outputs.
Intel® 41110 Serial to Parallel PCI Bridge Design Guide 13
Introduction
Figure 4. 41110 Adapter Card Block Diagram
Serial to Pa rallel
PCI Bridge
14 Intel® 41110 Serial to Parallel PCI Bridge Design Guide
Package Information 3
3.1 Package Specification
The 41110 Bridge is in a 567-ball FCBGA package, 31mm X 31mm in size, with a 1.27mm ball
pitch (see Figure 5 and Figure 6).
Figure 5. 41110 Bridge Package Dimensions (T o p View)
Handling
Exclusion
0. 547 in.
Area
0. 247 in.
0. 200 in.
0. 291 in.
0. 491 in.
17. 00 mm
21. 00 mm
31. 00 mm
Die
Keepout
Area
17. 00 mm 21 . 00 mm 31 . 00 mm
Intel® 41110 Serial to Parallel PCI Bridge Design Guide 15
Package Information
Figure 6. 41110 Bridge Package Dimensions (Side View)
Substrate
2.445±0.102 mm
2.010±0.099 mm
0.435±0.025 mm
Se e Note 3
Notes:
1. Primary datum -C- and seating plan are defined by the spherical crowns of the solder balls (shown before motherboard attach).
2. All dimensions and tolerances conform to ANSI Y14.5M-1994
3. BGA has a pre-SMT height of 0.5 mm and post-SMT height of 0.41-0.46 mm
4. Shown before motherboard attach; FCBGA has a convex (dom e shape) orientation before reflow and is expected to have a slightly
concave (bowl shaped) orientation after reflow.
0.84±0.05 mm
Decoup
Cap
Die
Seating Plane
0.7 mm Max
0.20
See Note 4.
0.20
Se e Note 1
Note: Primary datum -C- and seating plane are defined by the spherical crowns of the solder balls.
Note: All dimensions and tolerance s conform t o ANSI Y14.5M -1982
-C-
16 Intel® 41110 Serial to Parallel PCI Bridge Design Guide
Power Plane Layout 4
This chapter provides details on the decoupling and voltage planes needed to bias the 41110
package.
4.1 41110 Decoupling Guidelines
Table 2 lists the decoupling guidelines for the 41110. Figure 7 and Figure 8 provide the decoupling
capacitors around the 41110 ball grid pins.
Figure 7. Decoupling Placement for Core and PCI Express Voltage Planes
B2713-01
Intel® 41110 Serial to Parallel PCI Bridge Design Guide 17
Power Plane Layout
Figure 8. Decoupling Placement for PCI/PCI-X 1.5V and 3.3V Volt age Planes
Capacitor Legend
0603-0.1 F
0603-1 F
1206-10 F
B2714-01
18 Intel® 41110 Serial to Parallel PCI Bridge Design Guide
T a ble 2. 41110 Decoupling Guidelines
Power Plane Layout
Vol tage Plane Voltage
PCI/PCI-X
Voltage
PCI/PCI-X
Voltage
PCI/PCI-X
Voltage
Core Voltage 1.5V VCC15 0.1 0603 200 2.0 5
Core Voltage 1.5V VCC15 1.0 0805 200 2.3 5
Core Voltage 1.5V VCC15 10 1206 200 1.9 2
PCI Express
Voltage
PCI Express
Voltage
PCI Express
Voltage
3.3V VCC33 0.1 0603
3.3V VCC33 1.0 0603
3.3V VCC33 10 1206
1.5V VCCPE 0.1 0603 200 2.0 3
1.5V VCCPE 1 0805 200 2.3 4
1.5V VCCPE 10 1206 200 1.9 2
41110
Bridge
Pins
C
(uF)
Package
ESR
(mΩ)
50-
300
50-
300
50-
300
ESL
(nH)
1.0-
3.0
1.0-
3.0
1.0-
3.0
Caps
# of
5
As close as design
2
41110 Bridge BGA
As close as design
3
41110 Bridge BGA
As close as design
41110 BridgeBGA
As close as design
41110 Bridge BGA
As close as design
41110 Bridge BGA
As close as design
41110 Bridge BGA
Location
Beneath 41110
Bridge BGA
rules will allow to
rules will allow to
Beneath 41110
Bridge BGA
rules will allow to
rules will allow to
Beneath41110
Bridge BGA
rules will allow to
rules will allow to
4.2 Split Voltage Planes
There are two 1.5V voltage planes that supply power to the 4111 0:
• VCC15:1.5V ±5% (1.5V core voltage)
• VCCPE:1.5V ±3% (1.5V PCI Express voltage)
The 41110 Bridge core (VCC15), PCI-Express (VCCPE) voltages should be supplied by t wo
separate voltage regulators or a single regulator. If VCC15 and VCCPE is supplied by a single
voltage regulator the power planes should be split as shown in Figure 9.
Intel® 41110 Serial to Parallel PCI Bridge Design Guide 19
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