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Sale for such products.
Intel retains the right to make changes to these specifications at any time, without notice. Microcontroller products may have
minor variations to this specification known as errata.
*Other brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents whi ch have a n orderi ng nu mber a nd are referenced i n this documen t, or o ther Inte l lite rature, ma y be
obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
E-1Instruction Set Summary.. ............................... ........................................................ .... E-2
E-2Fields Within Instructions...........................................................................................E-23
E-3Encoding of Operand Length (w) Field......................................................................E-24
E-4Encoding of reg Field When w Field is not Present in Instruction............................. E-24
E-5Encoding of reg Field When w Field is Present in Instruction...................................E-25
E-6Encoding of the Segment Register (sreg) Field.........................................................E-25
E-7Encoding of 16-bit Address Mode with “mod r/m” Byte.............................................E-27
E-8Encoding of 32-bit Address Mode with “mod r/m” Byte (No s-i-b Byte Present)........E-28
E-9Encoding of 32-bit Address Mode (“mod r/m” Byte and s-i-b Byte Present)..............E-29
E-10Encoding of Operation Direction (d) Field.................................................................E-30
E-11Encoding of Sign-Extend (s) Field............................................................................. E-30
E-12Encoding of Conditional Test (tttn) Field.. ................................................................. E-30
E-13When Interpreted as Control Regist er Fiel d ............ .. ..... ..... ..... .. ..... ..... ..... .. ..... ..... .... E-31
E-14When Interpreted as Debug Register Field...............................................................E-31
E-15When Interpreted as Test Register Field...................................................................E-31
xxiii
GUIDE TO THIS
MANUAL
1
CHAPT ER 1
GUIDE TO THIS MANUAL
This manual describes the Intel386™ EX Embedded Processor. It is intended for use by hardware
designers familiar wi th the pri nciples o f microprocess ors and wit h the Inte l386 pr ocessor arc hitecture.
This chapter is organized as follows:
• Manual Contents (see below )
• Notational Conventions (page 1-3 )
• Special Terminology (page 1-4)
• Related Documents (page 1-5)
• Electronic Support Systems (page 1-6)
• Technical Support (page 1-7)
• Product Literature (page 1-8)
1.1MANUAL CONTENTS
This manual contains 1 8 chapters and 5 appendixe s, a glossar y, and an index. This section summarizes the contents of the remaining chapters and appendixes. The remainder of this chapter describes notational conventions and special terminology used throughou t th e manual and provides
references to related documentation.
Chapter 2 — Architectur al Overvi ew — describes the device features and some potential applications.
Chapter 3 — Core Overview — describes the differences between this device and the Intel386
SX processor core.
Chapter 4 — System Register Organization — describes the organization of the sys tem registers, the I/O address space, address decoding, an d addressing modes.
Chapter 5 — Device Configuration — explains how to configure the device for various applications.
Chapter 6 — Bus Interface Unit — describes the bus interface logic, bus states, bus cycles, and
instruction pipelining.
Chapter 7 — System Management Mode — describes Intel’s System Management Mode
(SMM).
Chapter 8 — Clock and Power Management Unit — describes the clock generation circuitry,
power manageme nt mo des, and system re se t logic.
1-1
™
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
Chapter 9 — Interrupt Control Unit — describes the interrupt sources and priority options and
explains how to program the interrupt control unit.
Chapter 10 — Timer/Counter Unit — describes the time r/cou nters and thei r available co unt
formats and operating modes.
Chapter 11 — Asynchronous Serial I/O (SIO) Unit — explains how to use the universal asynchronous receiver/transmitters (UARTs) to transmit and receive serial data.
Chapter 12 — DMA Controller — describes how the enhanced direct memory access controller
allows internal and external devices to transfer data directly to and from the system and explains
how bus control is arbitrat ed.
Chapter 13 — Synchronous Serial I/O (SSIO) Uni t — explains how to transmit an d receive
data synchronously.
Chapter 14 — Chip-select Unit — explains how to use the chip-select channels to access various external memory and I/O devices.
Chapter 15 — Refresh Control Uni t — describes how the refresh control unit generates periodic refresh requests and refresh addresses to simplify the interface to dynamic memory devices.
Chapter 16 — Input/Output Ports — describes the general-purpose I/O ports and explains how
to configure each pin to serve either as an I/O pin or as a pin controlled by an internal peripheral.
Chapter 17 — Watchdog Timer Unit — explains how to use the watchdog timer unit as a software watchdog, bus monitor, or general-purpose timer.
Chapter 18 — JTAG Test-logic Unit — des cribes t he i n dependent test-logic unit and expl ains
how to test the device logic and board-level connections.
Appendix A — Signal Descriptions — describes the device pins and signals and lists pin states
after a system reset and during powerdown, idle, and hold.
Appendix B — Com patib ility wi th P C/AT* Architecture — descri bes t he w ays in whic h the
device is compatible with the standard PC/AT architecture and the ways in which it departs from
the standard.
Appendix C — Example Code Header Files — contains the header files called by the code examples that are included in several chapters of this manual.
Appendix D — System Register Quick Referen ce — contains an alphabetical li st of registers.
Appendix E — Instruction Set Summary — lists all instructions and their clock counts.
Glossary — define s terms with spec ia l meaning used th r oughout this manual.
Index — lists key topics with page number references.
1-2
GUIDE TO THIS MANUAL
1.2NOTATIONAL CONV E NTI ONS
The following notations are used throughout this manual.
#The pound symbol (#) appended to a signal name indicates that the signal
is active low.
VariablesVariables a re shown in italics. Variables must be replaced with correct
values.
New TermsNew terms are shown in italics. See the Glossary for a brief definition of
commonly used t erms.
InstructionsInstruction mnemonics are shown in upper case. When you are
programming, instructions are not case sensitive. You may use either
upper or lower case.
NumbersHexadecima l numbers are represented b y a string of hexadecimal digits
followed by the character H. A zero prefix is added to numbers that begin
with A through F. (For example, FF is shown as 0FF H.) Decimal and
binary numbers are represented by their customary notations. (That is,
255 is a decimal number and 1111 1111 is a binary number. In some cases,
the letter B is added for clarity.)
Units of MeasureThe following abbreviations are used to represent units of measure:
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
Register BitsWhen the text refers t o more that one bit, the range m ay appear as two
numbers separated b y a colon (exa mpl e: 7:0 or 15:0). The first bit shown
(7 or 15 in the example) is the most-significant bit and the second bit
shown (0) is the least-significant bit.
Register Nam esRegister names are shown in upper case. If a register name contains a
lowercase, italic character, it represents more than one register. For
example, PnCFG represents three registers: P1CFG, P2CFG, and P3CFG.
Signal NamesSignal names are shown in upper case. When several signals share a
common name, an individual signal is represented by the signal name
followed by a number, while the group is represented by the signal name
followed by a variabl e (n). F or exampl e, the lowe r chi p-sel ec t signals are
named CS0#, CS1#, CS2#, and so o n; they are coll ectively calle d CSn#.
A pound symbol (#) appended to a signa l name identifies an act ive-low
signal. Port pins a re represented by the port abbreviation, a pe riod, and
the pin num ber (e.g., P1.0, P1.1).
1.3SPECIAL TERMINOLOGY
The following terms have special meanings in this manual.
Assert and DeassertThe terms assert and deassert refer to the act of making a signal
active and inactive, respect ive ly. The active polarity (high/low) is
defined by the signal name. Active-low signals are designated by a
pound symbol (#) suffix; a ctive-high signals have no suf fix. To assert
RD# is to drive it low; to assert HOLD is to drive it high; to deassert
RD# is to drive it high; to deassert HOLD is to drive it lo w.
DOS I/O AddressIntegrated peripheral s that are compati ble with PC/AT system
architecture can be mapped into DOS (o r PC/AT) addresses 0H–
03FFH. In this manual, the terms DOS address and PC/AT address
are synonymous.
Expanded I/O AddressAll peripheral registers reside at I/O addresses 0F000H–0FFFFH.
PC/AT-compat ible integrat ed periphe rals can also be mapped into
DOS (or PC/AT) address space (0H–03FFH).
PC/AT AddressIntegrated peripheral s that are compati ble with PC/AT system
architecture can be mapped into PC/ AT (or DOS) addresses 0H–
03FFH. In this manual, the terms DOS address and PC/AT address
are synonymous.
Processor and CPUProcessor refers to the Intel386 EX process or inc luding the
integrated peripherals. CPU refers to the processor core, which is
based on the static Intel3 86 SX processor.
1-4
GUIDE TO THIS MANUAL
Reserved BitsReserved bits are not used in this device, but they may be used in
future implement ations. Follow thes e guidel ine s to ensure
compatibility wit h future devices:
• Avoid any software dependence on the state of undefined
register bits.
• Use a read-modify-write sequence to load registers.
• Mask undefined bits when testing the val ues of define d bits.
• Do not depend on the state of undefined bits when storing
undefined bits to memory or to another register.
• Do not depend on the ability to retain information written to
undefined bits.
Set and ClearThe te rms set and clear refer to the value of a bit or the act of giving
it a value. If a bit is set, its value is “1”; setting a bit gives it a “1”
value . If a bit is clear, its value is “0”; clearing a bit gives it a “0”
value.
1.4RELATED DOCUMENTS
The following documents contain addit iona l informati on that is usef ul in designing system s that
incorporate the Intel386 EX processor. To order documents, please call Intel Literature Fulfillment (1-800-548-4725 in the U.S. and Canada; +44(0) 1793-431155 in Europe).
Document NameOrder Number
Intel386™ EX Embedded Microprocessor
Intel386™ SX Micropro cessor
Intel386™ SX Micropro cessor Programmer’s Ref er ence Manual
Intel386™ SX Micropro cessor Hardware Reference Manual
Development Tools
Buyer’s Guide for the Intel386 ™ Em bedd ed Proce s sor Famil y
Intel386™ EX Microprocessor Pin Multiplexing Map
You may also want to refer to Standard 1149.1—1990, IEEE Standard Test Access Port and
Boundary-Scan Architecture and its supplement, Standard 1149.1a—1993.
1-5
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
1.5ELECTRONIC SUPPORT SYSTEMS
Intel’ s FaxBack* service and application BBS provide up-to-date technical information. Intel also
maintains several forums on CompuServe and offers a variety of information on the World Wide
Web. These systems are available 24 hours a day , 7 days a week, providing technical information
whenever you need it.
1.5.1FaxBack Service
FaxBack is an on-demand publishing system that sends documents to your fax machine. You can
get product announcements, change notifications, product literature, device characteristics, design recommendations , and quality and reliabili ty information from F axBack 24 hours a day, 7
days a week.
Think of the FaxB ac k servi ce as a lib rary of techni ca l doc ument s t hat you can ac cess wi th your
phone. Just dial the telephone number and respond to the system prompts. After you select a document, the system sends a copy to your fax machine .
Each document has an order number and is listed in a subject catalog. The first time you use FaxBack, you should order the approp riate subject catalogs to get a complete list of document ord er
numbers. Catalogs are updated twice monthly . In addition, daily update catalogs list the title, status, and order number of each document that has been added, revised, or delet ed durin g the past
eight weeks. To receive the update for a subject catalog, enter the subject catalog number followed by a zero. For example, for the complete microcontroller and flash catalog, request document number 2; fo r the daily updat e to the microcontroller and flash catalog, req uest document
number 20.
The following catalogs and information are available at the time of publication:
1.Solutions OEM subscription form
2.Microcontroller and flash catalog
3.Development tools catalog
4.Systems catalog
5. Multimedia catalo g
®
6.Multibus and iRMX
1-6
software catalog and BBS file listings
GUIDE TO THIS MANUAL
7.Microprocessor, PCI, and peripheral catalog
8.Quality and reliability and change notification catalog
The bulletin b oard system (BBS) lets you download files to your computer. The application BBS
has the latest ApBUILDER software, hyperte xt manual s and datas heets, softwa re drivers, fi rmware upgrades, code examples, application notes and utilities, and quality and reliability data.
The system supports 1200- through 19200-baud modems. Typical modem settings are 14400
baud, no parity, 8 data bits, and 1 stop bit (14400, N, 8, 1).
To access the BB S, use a terminal program to dial the telephone number given bel ow for your
area; once you are connec ted, respond to th e system prompts. During your first session, enter your
name and location. The system operator wi ll set up your access acc o unt within 24 hours. At that
time, you can access the files on the BBS.
503-264-7999 U.S., Canada , Japan, Asia Pac ific (up to 19. 2 Kbau d)
44(0)1793-432955 Europe
NOTE
If you have problems accessing the BBS, use the se settings for your modem:
2400, N, 8, 1. Refer to your terminal software documentation for instructio ns
on changing these settings.
1.5.3CompuServe Forums
The CompuServe forums provide a means for you to gather information, share discoveries, and
debate issues. Type “go intel” for access. For information about CompuServe access and service
fees, call CompuServe at 1-800-848-8199 (U.S.) or 614-529-1340 (outside the U.S.).
1.5.4World Wide Web
We offer a variety o f information t hrough the World Wide Web (http://www.intel.com/). Select
“Embedded Design Product s” from the Intel home page.
1.6TECHNICAL SUPPO RT
In the U.S. and Canada, technical support representatives are availabl e to answer your questions
between 5 a.m. and 5 p.m. PST . You can also fax your questions to us. (Please include your voice
telephone number and indicate whether you prefer a response b y phone or by fax). Outside the
U.S. and Canada, please contac t your local distribut or.
1-800-628-8686U.S. and Canada
916-356-7599U.S. and Canada
916-356-6100 (fax)U.S. and Canada
1-7
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
1.7P RO D UCT LITERA T URE
You can order product literature from the following Intel literature centers.
The Intel386™ EX embedded processor (F igure 2-1) is based on the static Intel386 SX processor.
This highly integrated device retains those personal computer functions that are useful in embedded applications and inte grates peri pherals that are typically n eeded in embe dded syst ems. The
Intel386 EX processor provides a PC-compatible de velopm ent pla tform in a devi ce t hat is opti -
mized for embedded applications. Its integrated peripherals and power management options
make the Intel386 EX processor ideal for portable systems.
The integrated peripherals of the Intel386 EX processor are compatible with the standard desktop
PC. This allows existing PC software, inc luding most of the industry’s leading desktop and embedded operating systems, to be easily implemented on an Intel386 EX processor-based platform.
Using PC-compatible peripherals also allows for the developm ent a n d debugging of appli cation
software on a standard PC platform.
Typical appl ications using the Intel386 EX processor incl ude automated manu facturing equipment, cellular telephones, telecommunications equipment, fax machines, hand-held data loggers,
high-precision industrial flow controllers, interactive t elevision, medical equipment , modems,
and smart copiers.
This chapter is organized as follows:
• Intel386 EX Embedded Processor Core (see below)
• Integrated Peripherals (page 2-3)
2.1Intel386 EX EMBEDDE D P ROCE SS ORCORE
The Intel386 EX processor conta ins a modul ar, fully static Intel386 CX central p rocessing unit
(CPU). The Intel3 86 CX processor is an enhanc ed Intel386 SX processor wi th the addition of
System Management Mode (SMM) and two additional address lines. The Intel386 EX processor
has a 16-bit data bus and a 26-bit address bus, supporting up to 64 Mbyte s of memory address
space and 64 Kbytes of I/O address space. The performance of the Intel386 EX processor closely
reflects the Intel386 SX CPU performance at the same speeds.
Chapter 3, “CORE OVERVIEW” describes differences between the Intel3 86 EX processor core
and the Intel386 SX proc ess or. Ple ase refe r to the I ntel386™ SX Microprocessor Programmer ’sReference Manual (order number 24 0331) for ap plications and system programming information; descriptions of protected, real, and virtual-8086 modes; and details on the instruction set.
2-1
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
Data
Address
Bus Interface
Unit
Chip-select
JTAG Unit
Unit
Intel386™ CX Core
Core Enhancements
- A20 Gate
- CPU Reset
- SMM
INTR
Address
Data
Clock and Power
Management Unit
DRAM Refresh
Control Unit
Watchdog Timer Unit
Bus Monitor
Asynchronous Serial I/O
2 channels
(16450 compatible)
Synchronous Serial I/O
1 channel, full duplex
Timer/counter Unit
3 channels
(82C54 compatible)
I/O Ports
Interrupt Control Unit
DMA Controller
2 channels
(8237A compatible)
and Bus Arbiter Unit
A2849-02
2-2
Figure 2-1. Intel386™ EX Embedded Processor Block Diagram
ARCHITECTURAL OVERVIEW
2.2INTEGRATED PERIPHERALS
The Intel386 EX processor integr ates both PC-compatible peripherals (Table 2-1) and peripherals
that are specific to embe d ded applicat ions (Table 2-2).
Table 2-1. PC-compatible Peripherals
NameDescription
Interrup t
Control Unit
(ICU)
Timer/counter
Unit (TCU)
Asynchronous
Serial I/O
(SIO) Unit
Direct Memory
Access
(DMA)
Controller
Consists of two 82C59A programmable interrupt controllers (PICs) configured as master
and slave. You may cascade up to six external 82C59A PICs to expand the external
interrupt lines to 52. Refer to Chapt er 9, “INTERRUPT CONTROL UNIT.”
Provides three independent 16-bit down counters. The programmable TCU is
functionally equivalent to three 82C54 counter/timers with enhancements to allow
remapping of peripheral addresses and interrupt assignments. Refer to Chapter 10,
“TIMER/COUNTER UNI T.”
Features two independent universal asynchronous receiver and transmitter (UART)
units which are functiona lly equi vale nt to Nationa l Semicon du ctor’s NS16450. Each
channel contains a baud-rate generator, transmitter, receiver, and modem control unit.
Receive and transmi t interrupt signals can be connected to the ICU controller an d DMA
controller. Refer to Chapter 11, “ASYNCHRONOUS SERIAL I/O UNIT.”
Transfers internal or external data between any combination of memory and I/O devices
for the entire 26-bit address bus. The two independent channels operate in 16- or 8-bit
bus mode. Buffer chaining allows data to be transferred into noncontiguous memory
buffer s. The DM A cha nn els can be tied to any of the serial devices to support high data
rates, minimizing processor interruptions. Provides a special two-cycle mode that uses
only one channel for memory-to-memory transfers. Bus arbitration logic resolves priority
conflicts betwe en the DMA chann el s, the refre sh contro l un it, and an externa l bus
master. SIO and SSIO interrupts can be connected to DMA for high-speed transfers.
Backward compatible with 8237A. Refer to Chapter 12, “DMA CONTROLLE R.”
2-3
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
The Intel386 EX processor provides a mechanism for system management with a
combination of hardwa re and CPU microcode enhancem en ts. An external ly genera te d
system management interrupt (SMI#) allows the execution of system-wide routines that are
independent and transparent to the operating system. The system management mode
(SMM) architectur al extensions to the Intel386 CPU are described in Chapter 7, “SYSTEM
MANAGEMENT MODE.”
An external clock source provides the input frequency. The clock and power management
unit generates separate internal clock signals for core and peripherals (half the input
frequency), divides the internal clock by two for baud clock inputs to the SIO and SSIO, and
divides the internal clock by a programmable divisor to provide a prescaled clock signal
(various frequen ci es) for the TCU and SSIO.
Power management provides idle and powerdown modes (idle stops the CPU clock but
leaves the peripheral clocks running; powerdown stops both CPU and peripheral clocks).
An external clockout signal is also provided. Refer to Chapter 8, “CLOCK AND POWER
MANAGEMENT UNIT.”
Provides simultaneous, bidirectional high speed serial I/O. Consists of a transmit channel, a
receive channel, and a baud rate generator. Built-in protocols are not included, because
these can be emulated using the CPU. SSIO interru pt s can be connecte d to the DMA unit
for high-speed transfers. Refer to Chapter 13, “SYNCHRONOUS SERIAL I/O UNIT.”
Programmable, eight-channel CSU allows direct access to up to eight devices. Each
channel can operate in 16- or 8-bit bus mode and can generate up to 31 wait states. The
CSU can interface with the fastest memory or the slowest peripheral device. The minimum
address block for memory a ddress-con fig ure d channe ls is 2 K byte s. The size of these
address blocks can be increased by powers of 2 Kbytes for memory addresses and by
multiples of 2 bytes for I/O addresses. Supports SMM memory addressing and provides
ready generation and programmable wait states. Refer to Chapter 14, “CHIP-SELECT
UNIT.”
Provides a means to generate periodic refresh requests and refresh addresses. Consists of
a programmable interva l timer unit, a control unit, and an address generation unit. Bus
arbitration logic ensure s th at refr esh reque st s have the high est priority. The refresh contr ol
unit (RCU) is provided for applications that use DRAMs with a simple EPLD-based DRAM
controller or PSRAMs that do not need a separate controller. Refer to Chapter 15,
“REFRESH CONTROL UNIT.”
Three I/O ports facilita te data tra nsfe r between the proces sor and surroundi ng system
circuitry. The Intel386 EX processor is unique in that several functi on s are multip lexed with
each other or with I/O ports. This ensures m axim u m use of availabl e pins and main tain s a
small package. Each multiplexed pin is individually programmable for peripheral or I/O
function. Refer to Chapter 16, “INPUT/OUTPUT PORTS.”
When enabled, the WDT functions as a general purpose 32-bit timer, a software timer, or a
bus monitor. Refer to Chapter 17, “WATCHDOG TIMER UNIT.”
The test-logic unit simplifies board-level testing. Consists of a test access port and a
boundary-scan register . Fully compliant with Standard 1149.1–1990,
Access Port and Boundary-Scan Architecture
Refer to Chapter 18, “JTAG TEST-LOGIC UNIT.”
and its supplement, Standard 1149 .1a–1993.
IEEE Standard Test
2-4
CORE OVERVIEW
3
CHAPT ER 3
CORE OVERVIEW
The Intel386™ EX processor core is based upon the Inte l386 CX pro ce ssor, which is an enhanced
version of the In tel386 SX processor. This chapter describes the Intel386 CX processor enhancements over the Intel386 SX processor, internal architecture of the Intel386 CX processor, and the
core interface on the Intel386 EX processor.
The Intel386 CX processor, based on the Intel386 SX processor, adds system management mode
and two additional address lines for a total of 26 address lines.
3.1.1System Management Mode
The Intel386 CX processor core provides a mechanism for system management with a combination of hardware a nd CPU microcode e nhance ments. An external ly generated Syst em M anagement Interrupt (SM I#) allows the execution of system wide r outine s whic h are i nde pendent an d
transparent to t he operat ing syst em. T he Syst em Mana geme nt M ode (SM M) a rchit ect ure ext en sions to the Intel386 SX processor consist of the followi ng elem ents :
• Interrupt input pin (SMI#) to invoke SMM
• One output pin to identify execution state (SMIACT#)
• One new instruction (RSM, executa ble only from SMM) to exit SMM
• SMM also added one to four execution clocks to the following inst ructions: IN, INS, REP
INS, OUT, REP OUT, POPA , HALT, MOV CR0, and SRC. INTR and NMI also need an
additional two clocks for interrupt latency. These cycles were added due to the microcode
modification for the SMM implementation. Refer to Appendix E for the exact execution
times. Otherwise, 1 00% of the Intel386 SX processor inst r uctions exec ute on the Intel386
CX processor core.
Please refer to Chapter 7 for more details on System Mana gement M ode.
3.1.2Additional Address Lines
T wo additional address lines were added to the Intel386 CX processor core for a total of 26. This
expands the physical address space from 16 Mbytes to 64 Mbytes.
3-1
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
3.2I ntel 386 CX PROCESS OR INTE RNAL ARCHITE CTURE
The internal architecture of the Intel386 CX processor consists of functional units that operate in
parallel. Fetchin g, decoding, execution, memory management and bus accesses for several instructions are performed sim ultaneously. This paralle l operation is called pipelined instruct ion
processing. With pipelining, each instruction is performed in stages, and the processing of several
instructions at different stages may overlap, as shown in Figure 3-1. The pipelined processing of
the Intel386 CX processor results in higher performance and enhanced throughput rate over nonpipelined processors.
Elapsed Time
Typical
Processor
Intel386™ SX CPU/Intel376™ CPU
386™ SX CPU/376™ CPU
Bus Unit
Decode
Execution
Fetch 1Decode 1Execute 1Fetch 2Decode 2Execute 2
Fetch 1
Unit
Unit
MMU
Fetch 2Fetch 3
Decode 1Decode 2Decode 3Decode 4Decode 5
Execute 1
Fetch 4
Addr &
MMU
Store
Result 1
Execute 2Execute 3Execute 4
Fetch 5Fetch 6
Addr &
MMU
Figure 3-1. Instruction Pipelining
A2850-01
3-2
Figure 3-2 shows the internal architecture of the Intel38 6 CX processor.
Figure 3-2. The Intel386™ CX Processor Internal Block Diagram
A2851-02
3-3
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
The six functional units of the Intel386 CX processor are:
• Core Bus Unit
• Instruction Prefet c h Unit
• Instruction Dec ode Unit
• Execution Unit
• Segmentation Unit
• Paging Unit
3.2.1Core Bus Unit
The Core Bus Unit provides t he inte rface betwe en the proce ssor a nd its en vironment. It accept s
internal requests for instruction fetches (from the Instruction Prefetch Unit) and data transfers
(from the Execution Unit), and prioritizes the requests. At the same time, it generates or processes
the signals to perform the c urre nt bus cycl e. These signal s include t he address, data, and cont rol
outputs for accessing exte rnal memory and I/O. The Core Bus Unit also control s the interface to
external bus masters and coprocessors.
3.2.2Instruction Prefetch Unit
The Instruction Prefetch Unit performs the program look ahead function of the CPU. When the
Core Bus Unit is not performing bus cycles to execute an instruction, the Instruction Prefetch Unit
uses the Core Bus Unit to fetch sequenti all y along the instruc tio n byte stream . These prefe tched
instructions are stored in the Instruction Queue to awai t processing by the Instruction Dec ode
Unit.
Instruction prefetches a re given a lower priority than data transfers; assumin g zero wai t state
memory access, prefetch activity never delays execution. On the other hand, when there is no data
transfer requested, prefetching uses bus cycles that would otherwise be idle.
3.2.3Instruction Decode Unit
The Instruction De code Unit takes instruct ion stream byt es from the Prefetch Queue and translates them into mic rocode. The decoded inst ructions a re the n stored in a three-deep Inst ruction
Queue (FIFO) to await processing by the Execution Unit. Immediate data and opcode offsets are
also taken from the Prefet ch Q ueue. The dec ode u nit works in parallel with the other units and
begins decoding when there is a free slot in the FIFO and there are bytes in the prefetch queue.
Opcodes can be decoded at a rate of one byte per clock. Immediate data and offsets can be decoded in one clock regardless of their length.
3-4
CORE OVERVIEW
3.2.4Execution Unit
The Executio n Unit executes the instruc tio ns fr om the Instruction Queue and there f ore com mu nicates with all other units required to complete the instruction. The functions of its three subunits
are given below.
• The Control Unit contains microcode and special parallel har dware that spee ds multiply,
divide, and effective address ca lcula tio n.
• The Data Unit contains the (Arit hme tic Logic Unit) ALU, a file of eight 32-bit general-
purpose registers, and a 64-bit barrel shifter (which performs multiple bit shifts in one
clock). The Data Unit performs data operations requested b y the Control Unit.
• The Protection Test Unit che cks for segmenta tion violations u nder the control of the
microcode.
To speed the e xecution of memory referenc e instruct ions, the Exec ution Uni t partially o verlaps
the execution of any memory reference instr uction with the previous instruct ion.
3.2.5Segmentation Unit
The Segmentation Unit translates logical addresses into linear addresses at the request of the Execution Unit. The on-chip Segment Des cript or Cac he store s the currentl y used segme nt descriptors to speed this translation. At the same time it performs the translation, the Segmentation Unit
checks for bus-cycle segmentation violations. (These checks are separate from the static segmentation violation checks pe rformed by the Protection Test Unit.) The translated linear address is
truncated to a 24-bit physical address.
3.2.6Paging Unit
When the Intel386 CX processor paging mechanism is enabled, the Paging Unit translates linear
addresses generated by the Se gmentation Unit or the Instruction Prefetch Unit into physi cal addresses. (When paging is not enabled, the physical ad dress is the same as the linear address, and
no translation is necessa r y.) The Page Descriptor Cache stores rece ntly used Pa ge Direc tory a nd
Page Table entries in its Translation Lookaside Buffer (TLB) to speed this translation. The Paging
Unit forwards physical addresses to the Core Bus Unit to perform memory and I/O accesses.
3-5
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
3.3CORE Intel386 EX PROCE S SOR INT ER FACE
The Intel386 EX processor peripherals are connected to the Intel386 CX processor core through
an internal Bus Interface Unit (BIU). The BIU controls interna l peripheral accesse s and external
memory and I/O accesses. Because it has the BIU betwe en the Intel386 CX pr ocessor core and
the external bus, the Intel386 EX proces sor bus timings are n ot identical to those of the Inte l386
CX processor or Intel386 SX processor.
The Intel386 CX processor numeric co processor interface is maintained and brought out to the
Intel386 EX processor pins. T he same I/O addresses used on the Intel386 SX processor are used
on the Intel386 EX processor, even though there are more address lines. The A23 line is high for
coprocessor cycles. Refer t o “Interface To Intel387™ SX Math Coprocessor” on page 6-3 8 for
more details.
3-6
SYSTEM
REGISTER
ORGANIZATION
4
CHAPT ER 4
SYSTEM REGISTER ORGANIZATION
This chapter provides an overview of the system registers incorporated in the Intel386™ EX processor, focusing o n register organiza tion from an address architecture viewpoint. The chapters
that cover the individual peripheral s desc ribe the registers in deta il.
This chapter is organized as follows:
• Overview (see below)
• I/O Address Space for PC/AT Systems (page 4-2)
• Expanded I/O Address Space (page 4-3)
• Organization of Peripheral Regist ers (page 4 -5)
• I/O Address Decodin g Techniques (page 4-6)
• Addressin g Modes (pa ge 4-9)
• Peripheral Register Addresses (page 4-15)
4.1OVERVIEW
The Intel386 EX processor has register resources in the following categories:
• Intel386 processor core architecture registers:
— General purpose registers
— Segment regi ster s
— Instruct ion pointe r and flags
— Control registers
— System address regist ers (protected mode)
— Debug registers
— Test re g i s ters
• Intel386 EX processor peripheral registers:
— Configura tio n space control regist ers
— Interrupt cont rol unit regist ers
— Timer/co u nter u nit registers
— DMA unit registers (8237A-compat ible and enhanced function registers)
— Asynchronous serial I/O (SIO) registers
— Clock genera tio n selector registers
4-1
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
— Power manageme nt control registers
— Chip-sel ect u nit control regist ers
— Refresh control unit registers
— Watchdog timer control registers
— Synchronous serial I/O control registers
— Parallel I/O port control registers
4.1.1Intel3 86 Processo r Core Archi tecture Reg ister s
These registers are a superset of the 8086 and 80286 processor registers. All 16-bit 8086 and
80286 registers are contained within the 32-bit Intel386 processor core registers. A detailed description of the Int el386 proce ssor arc hitecture ba se regis ters can be found in the Intel386™ SXMicroprocessor Programmer’s Reference Manual (order number 240331).
4.1.2Intel386 EX Processor Peripheral Register s
The Intel386 EX processor conta ins so m e periphe rals tha t are comm o n and compat ibl e with the
*
PC/AT
system architecture and others that are useful for embedded applications. The peripheral
registers control access to these peripherals and enable you to configure on-chip system resources
such as timer/counters, power management, chip selects, and watchdog timer.
All peripheral registers reside physically in the expanded I/O address space (address es 0F000H–
0FFFFH). Peripherals that are compatible with PC/AT system architecture ca n also be mapped
into DOS I/O address space (addresses 0H–03FFH, 10-bit decode). The following rules apply for
accessing peripheral registers after a system reset:
• Registers within the DOS I/O address space are accessible.
• Registers within the expanded I/O address space are accessible only after the expanded I/O
address space is enabled.
4.2I/O ADDRES S SPACE FOR PC/AT SYST E MS
The Intel386 EX processor’s I/O address space is 64 Kbytes. On PC/AT platforms, the DOS operating system and applications assume that only 1 Kbyte of the total 64-Kbyte I/O address space
is used. The first 256 bytes (addresses 00000H–00FFH) are reserved for platform (motherboard)
I/O resources such as the interrupt and DMA controllers, and the remaining 768 bytes (add resses
0100H–03FFH) are available for “general” I/O peripheral card resources. Since only 1 K byte of
the address space is supported, add-on I/O peri pheral cards typically deco de only the lower 10
address lines. Because the upper address lines are not decoded, the 256 platform address locations
and the 768 bus address locations are repeated 64 times (on 1-Kbyte boundaries), covering the
entire 64-Kbyte address space. (See Figure 4- 1.)
Generally, add-on I/O peripheral cards do not use the I/O addresses reserved for the platform resources. Software running on the platform can use any of the 64 repetitions of the 256 address
locations reserved for accessing platform resources.
4-2
General Slot I/O
Platform I/O (Reserved)
General Slot I/O
Platform I/O (Reserved)
General Slot I/O
Platform I/O (Reserved)
SYSTEM REGISTER ORGANIZATION
FFFFH (64K)
FD00H
FC00H (63K)
0C00H (3K)
0900H
0800H (2K)
0500H
0400H (1K)
General Slot I/O
0100H (256)
Platform I/O (Reserved)
0000H (0)
A2498-01
Figure 4-1. PC/AT I/O Address Space (10-bit Decode)
4.3EXPANDED I/O ADDRESS SPACE
The Intel386 EX processor’s I/O address scheme is similar to that of the Extended Industry Standard Architecture (EISA) bus and the Enhanced - Industry Standard Architecture (E-ISA) bus.
Both standards maintain backward software compa tibility with the ISA architecture. The ISA
Platform I/O (0-100H) is accessed with a 16-bit address decode and is located in the first 256 I/O
locations. The General Slot I/O that is typically used by add-in boards is repeated throughout the
64 K b yte I/O address range due t o the ir 10 -bit only de code. This allows 6 3 of the 6 4 repe tition s
of the first 256 address locations of every 1 Kbyte block to be allocated to specific slots. Each slot
is 4 Kbyte in size, allowing for a total of 16 slots. The partitioning is such that four groups of 256
address locations are assigned to each slot, for a total of 1024 specific address locations per slot.
4-3
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
(See Figure 4-2.) Thus, each slot has 1 Kbyte addresses (in four 256-byte segments) that can potentially contain extended periphera l regis ters.
General Slot I/O
Slot 15
General Slot I/O
Slot 15
General Slot I/O
Slot 15
General Slot I/O
Slot 15
General Slot I/O
Slot 1
General Slot I/O
Slot 1
General Slot I/O
Slot 1
General Slot I/O
Slot 1
General Slot I/O
Slot 0
General Slot I/O
Slot 0
General Slot I/O
Slot 0
General Slot I/O
Slot 0
ISA Platform I/O
FFFFH (64K)
FC00H (63K)
F800H (62K)
F400H (61K)
F000H (60K)
1FFFH (8K)
1C00H (7K)
1800H (6K)
1400H (5K)
1000H (4K)
0C00H (3K)
0800H (2K)
0400H (1K)
0000H (0K)
4-4
A2499-02
Figure 4-2. Expanded I/O Address Space (16-bit Decode)
SYSTEM REGISTER ORGANIZATION
The Intel386 EX processor use s slot 15 for the registers needed for integrated peripherals. Using
this slot avoids conflicts with other devices in an EISA system, since EISA systems typically do
not use slot 15.
4.4O RGANI ZAT IO N OF PERIPHE RAL RE GI STERS
The registers associated with the integrated peripherals are physically located in slot 15 of the I/O
space. There are sixteen 4 Kbyte address slots in I/O spa ce . Slot 0 refers to 0H–0FFFH; slot 1 5
refers to 0F000H–0FFFFH. Table 4-1 shows the address map for the peripheral registers in slot
15. Note that the I/O addresses fall in address ranges 0F000H–0F0FFH, 0F400H–0F4FFH, and
0F800H–0F8FFH; utilizing the u nique sets of 256 I/O addresse s in Slot 15.
Table 4-1. Peripheral Register I/O Address Map in Slot 15
Register Des crip tionI/O Address Range
DMA Controller 10F000H–0F01FH
Master Int erru pt Contro ll er0F020 H–0F03FH
Programmable Interval Timer0F040H–0F05FH
DMA Page Registers0F080H–0F09FH
Slave Interrupt Controller0F0A0H –0F0BFH
Math Coprocessor0F0F0H –0F0 FFH
Chip Select Unit0F400H–0F47FH
Synchronous Serial I/O Unit0F480H–0F49FH
DRAM Refresh Control Unit0F4A0H–0F4BFH
Watchdog Timer Unit0 F 4C0H –0F4CFH
Asynchronous Serial I/O Channel 0 (COM1)0F4F8H –0F4FFH
Clock Generation and Power Management Unit0F800H–0F80FH
External/Internal Bus Interface Unit0F810H –0F81FH
Chip Configuration Registers0F820H–0F 83FH
Parallel I/O Ports0F860H–0F87FH
Asynchronous Serial I/O Channel 1 (COM2)0F8F8H– 0F8FFH
4-5
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
4.5I/O ADDRESS DECODING TECHNIQUES
One of the key features of the Inte l386 EX processor is that it is configurabl e for compatibility
with the standard PC/AT archit ecture. In a PC/AT system , the platform I/O resources are located
in the slot 0 I/O address space. For the Intel386 EX processor, this means that PC/AT-compatible
internal peripherals s hould be re flect ed in sl ot 0 of the I/ O spa ce fo r DOS operatin g syst em an d
application software to access and manipulate them properly.
This discussion leads to the concepts of DOS I/O space and expanded I/O space. DOS I/O Space DOS I/O space refers to the lower 1 Kbyte of I/O addresses, where
only PC/AT-compatible peripherals can be mapped.
Expanded I/O SpaceExpanded I/O space refers to the top 4 Kb ytes of I/O addresses,
where all peripheral regi sters are phys ically loca t ed. The rem ainde r
of this section explains how special I/O address decoding schemes
manipulate register addresse s within these two I/O spaces.
4.5.1Address Configuration Register
I/O address locations 22H and 23H in DOS I/O space offer a special case. These address locations
are not used to access any peripheral registers in a PC/AT system. The Intel386 SL microprocessor and other integrated PC solutions use them to enable extra address space required for configuration registers specific to these products. On the Intel386 EX processor, these address locations
are used to hide the peri p heral regi sters in the e xpanded I/O spac e. The e x panded I/O space can
be enabled (registers visible) or disabled (registers hidden).
The 16-bit register a t I/O location 22H can a lso be used t o control mapping of various internal
peripherals in I/O address space. This register, REMAPCFG, is defined in Figure 4-3.
The remap bits of this register control whether the internal PC compatible peripherals are mapped
into the DOS I/O space. Setting the peripheral bit makes the peripheral accessible only i n expanded I/O space. Clearin g the peri p heral bit makes the periphera l acc essi ble in both DOS I/O space
and expanded I/O space. To access the REMAPCFG register, you must first enable the expanded
I/O address spa ce as des cri bed i n t he ne xt section. At reset, this regis ter is c leare d, mapping internal PC/AT-compatible periphe rals into DOS I/O space.
4-6
SYSTEM REGISTER ORGANIZATION
Address Configuration Register
REMAPCFG
158
ESE——— ————
70
—S1RS0RISRIMRDR—TR
Bit
Number
15ESE0 = Disables expanded I/O space
14–7—Reserved.
6S1R0 = Makes serial channel 1 (COM2) accessible in both DOS I/O space
5S0R0 = Makes serial channel 0 (COM1) accessible in both DOS I/O space
4ISR0 = Makes the slave 82C59A interrupt controller accessible in both DOS
3IMR0 = Makes the master 82C59A interrupt controller accessible in both
2DR0 = Makes the DMA address accessible in both DOS I/O space and
1—Reserved.
0TR0 = Makes the timer control unit accessible in both DOS I/O space and
Bit
Mnemonic
1 = Enables expan ded I/O s pace
and expanded I/O space
1 = Remaps serial channel 1 (COM2) address into expanded I/O space
and expanded I/O space
1 = Remaps serial channel 0 (COM1) address into expanded I/O space
I/O space and expanded I/O space
1 = Remaps slave 82C59A interrupt controller address into expanded
I/O space
DOS I/O space and expanded I/O space
1 = Remaps master 82C59A interrupt controller address into expanded
I/O space
expanded I/O space
1 = Remaps DMA address into expanded I/O space
expanded I/O space
1 = Remaps timer control unit address into expanded I/O space
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
4.5.2Enabling and Disabling the E xpan ded I/O Space
The Intel386 EX processor’s expan ded I/O space is enabled by a specific write sequence to I/O
addresses 22H and 23H (Figure 4-4). Once the expanded I/O space is enabled, internal peripherals (timers, DM A, inte rrupt controlle rs and serial co mmuni cation channe ls) can be mapped out
of DOS I/O space (using the R EMAPCFG re gister) an d registe rs associated with othe r internal
peripherals (such as the chip-select unit, power management unit, watchdog timer) can be accessed.
4.5.2.1Programming REMAPCFG Example
The expanded I/O space enabl e (ESE) bit in the RE MAPCFG re gister can be set only by three
sequential write operations to I/O addresses 22H and 23H as described in Figure 4-4. Once ESE
is set, REMAPCFG and a ll the on-chip registers in the expanded I/ O address range 0F000H–
0FFFFH can be accessed. The remap bits in REMAPCFG are still in effect even after the ESE bit
is cleared.
;;disable interrupts
CLI
; Enable expanded I/O space of Intel386(tm) EX processor
; for peripheral initialization.
MOV AX, 08000H; Enable expanded I/O space
OUT 23H, AL; and unlock the re-map bits
XCHG AL, AH
OUT 22H, AL
OUT 22H, AX
;; at this point PC/AT peripherals can be mapped out
;; For example,
;; Map out the on-chip DMA channels from the DOS I/O space (slot 0)
MOV AL, 04H
OUT 22H, AL
; Disables expanded I/O space
MOV AL, 00H
OUT 23H, AL
;; Re-enable Interrupts
STI
Figure 4-4. Setting the ESE Bit Code Example
The REMAPCFG register is write-protected until the expanded I/O space is enabled. When the
enabling writ e sequence is executed, it sets the ESE bi t. A program can check this bit to see
whether it has access to the expanded I/O spa ce registers . Cleari ng the ESE bit disabl es the expanded I/O space. This can be d one by a byte write with a value of 0 to I/O address 23H. This
again locks the REMAPCFG register and ma kes it read-only.
4-8
SYSTEM REGISTER ORGANIZATION
4.6ADDRESSING MODES
Combinations of the v a lue of ESE bit and t he indivi d ual remap bit s in the REM APC FG regi ster
yield four different peripheral addressing modes for I/O address decoding.
4.6.1DOS-compatible Mode
DOS-compatible mode is achieved by clearing ESE and all the peripheral remap bits. In this
mode, all PC/AT-compatible peripheral s are mapped into the DOS I/O space. Only address lines
A9:0 are decoded for internal pe ripherals. Acc esses to PC/AT-compatible peripheral s are vali d,
while all other internal periphera ls are inacc essibl e (see Figu re 4-5).
This mode is useful for accessing the internal timer , interrupt controller, serial I/O ports, or DMA
controller in a DOS-compatible environment.
4-9
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
REMAPCFG
Register
3FFH
23H
22H
On-chip UART-0
On-chip UART-1
On-chip 8259A-2
On-chip Timer
0
0
00000000
On-chip 8259A-1
FFFFH
F000H
Expanded I/O Space
4-10
0H
On-chip DMA
Shaded area indicates that
expanded I/O space peripherals
Note:
DOS I/O Space
are not accessible
Figure 4-5. DOS-Compatible Mode
A2495-02
SYSTEM REGISTER ORGANIZATION
4.6.2Nonintrusive DOS Mode
This mode is achieved by first setting t he ESE bit (using the t hree sequent ial write s), setting the
individual peripherals’ re map bits, and the n clearing the ES E bit. Periphera ls whose remap bit s
are set are mapped out of DOS I/O spac e. L ike DOS-com patible mode, only address lines A 9:0
are decod ed internally. This mode is useful for connecting an external peripheral instead of using
the integrated peripheral. F or example, a sys tem might use an external 8237A DMA rather t han
using the internal DMA unit. For this configuration, set the ESE bit, set the remap bit associated
with the DMA unit and then clear the ESE bit. In this case, the external 8237A is accessible i n
the DOS I/O space, while the internal DMA can be accessed only after the expanded I/O space is
enabled. (See Figure 4-6.)
4.6.3Enhanced DOS Mode
This mode is achieved b y set ting the ES E bit and clearing all PC/AT-compatible peripherals’
remap bits. Address lines A15:0 are decoded internally. The expanded I/O space is enabled an d
the PC/AT-com patible inter nal peripherals are accessi ble in either DOS I/O space or e xpanded
I/O space. (See Figure 4-7.) If an applica tion frequently require s the additiona l peripherals, but
at the same time wants to maintain DOS c ompat ibility for ease of devel opme nt, this is the most
useful mode.
4.6.4Non-DOS Mode
This mode is achieved by setting the ESE bit and setting all peripherals’ remap bits. Address lines
A15:0 are decoded internal ly. The expanded I/O space is enabled and all peripherals can be accessed only in expanded I/O space. This mode is useful for systems that don’t require DOS compatibility and have other custom peri phe ral s in slot 0 of the I/O space. (See Figure 4-8.)
For all DOS peripherals, the lower 10 bits in the DOS I/O space and in the expanded I/O space
are identical (except the UART s, whose lower 8 bits are identical). This makes correlation of their
respective offsets in DOS and expanded I/ O spaces easie r. Also, the UARTs have fixed I/O addresses. This differs from standard PC/AT configurations, in which these address ranges are programmable.
4-11
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
REMAPCFG
Register
3FFH
23H
22H
On-chip UART-0
On-chip UART-1
On-chip 8259A-2
On-chip Timer
0
0
00000010
On-chip 8259A-1
FFFFH
F000H
Expanded I/O Space
4-12
0H
Internal DMA
DOS I/O Space
Note:
Shaded area indicates that the on-chip
DMA and expanded I/O space
peripherals are not accessible
Figure 4-6. Example of Nonintrusive DOS-Compatible Mode
A2496-02
SYSTEM REGISTER ORGANIZATION
REMAPCFG
Register
3FFH
23H
22H
On-chip UART-2
On-chip UART-1
On-chip 8259A-2
On-chip Timer
1
0
00000000
Other Peripherals
UART-0
UART-1
Timer
8259A-2
8259A-1
On-chip DMA
FFFFH
F000H
0H
On-chip 8259A-1
Expanded I/O Space
On-chip DMA
DOS I/O Space
Figure 4-7. Enhanced DOS Mode
A2501-02
4-13
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
3FFH
Other Peripherals
FFFFH
UART-0
UART-1
Timer
REMAPCFG
Register
4-14
23H
1
22H
01111011
0
0H
DOS I/O Space
Figure 4-8. NonDOS Mode
8259A-2
8259A-1
On-chip DMA
Expanded I/O Space
F000H
A2502-02
SYSTEM REGISTER ORGANIZATION
4.7PERIPHERAL REGISTER ADDRESSES
Table 4- 2 lists the addresse s and names of all user-accessible peripheral registers. I/O R egister s
can be accessed as bytes or words. Word accesses to byte registers result in two sequential 8-bit
I/O transfers. The default (reset) value of each register is shown in the Rese t Value column. An X
in this column signifies that the register bits are undefined. Some address values do not access
registers, but are deco ded to provide a logic control signal. These addresses are listed as Not aregis ter in the Rese t colum n.
Table 4-2. Peripheral Register Addresses (Sheet 1 of 6)
Expa nded
Address
F000H0000HByteDMA0TAR0/1 (Note 1)XX
F001H00 01HByteDM A0BYC0 /1 (Not e 1)XX
F002H0002HByteDMA1TAR0/1 (Note 1)XX
F003H00 03HByteDM A1BYC0 /1 (Not e 1)XX
F004H0004HReserved
F005H0005HReserved
F006H0006HReserved
F007H0007HReserved
F008H0008HByt eDM ACM D1/DMASTS0 0H
F009H0009HB yteDM ASRR00H
F00AH000AHByteDMAMSK04H
F00BH000B HByteDMAM OD 100H
F00CH000CHB yteDM ACL RBPNot a register
F00DH000DHB yteDMACLRNot a reg ister
F00EH00 0E HByteDMACL RMS KNot a register
F00FH000FHByteDMAGRPM SK03H
F010HByteDM A0REQ0/1X X
F011HByteDMA0 REQ2/3X X
F012HByteDM A1REQ0/1X X
F013HByteDM A1REQ2/3X X
F014HReserved
F015HReserved
F016HReserved
F017HReserved
NOTES:
1. Byte pointer in flip-flop in DMA determines which register is accessed.
2. Shaded rows indicate reserved areas.
PC/AT
Address
Access Type
(Byte/Word)
DMA Controller and Bus Arbiter
Register NameReset Value
4-15
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
Table 4-2. Peripheral Register Addresses (Sheet 2 of 6)
1. Byte pointer in flip-flop in DMA determines which register is accessed.
2. Shaded rows indicate reserved areas.
PC/AT
Address
Access Type
(Byte/Word)
Asynchro nous Seri al I/O Chan ne l 1 (COM2)
Register NameReset Value
4-20
DEVICE
CONFIGURATION
5
CHAPT ER 5
DEVICE CONF IGU RATION
The Intel386™ EX processor provides many possible signal to pin connections as well as peripheral to peripheral connections. This chapter des cribes the available configurat ions and how to
configure them.
This chapter is organized as follows:
• Introduction (see below)
• Peripheral Configuration (page 5-3)
• Pin Configuration (page 5-23)
• Device Configuration Procedure (page 5-28)
• Configuration Example (page 5-28)
5.1INTRO DUCTI ON
Device configuration is the process of setting up the microprocessor’s on-chip periphera ls
particular system design. Specifically, device configuration consists of programming registers to
connect peripheral signals to the package pins and interconnect the peri p heral s. The peri phe ral s
include the following:
• DMA Controller (DMA)
• Interrupt Control Unit (ICU)
†
for a
• Timer/counter Unit (TCU)
• Asynchronous Serial I/O Units (SIO0, SIO1)
• Synchronous Serial I/O Unit (SSIO)
• Refresh Control Unit (RCU)
• Chip-select Unit (CS U)
• Watchdog Timer Unit (WDT)
In addition, the pin c o n figuration regi st ers c ontrol connections from the coproce ssor t o t he c ore
and pin connections t o the bus arbiter.
†
In this chapter, the terms “peripheral” and “on-chip peripheral” are used intercha ngeably. An “off-chip peripheral” is
external to the Intel386 EX processor.
5-1
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
Figure 5-1 shows Peripheral A and its connections to other peripherals and the package pins. The
“Internal Connection Logic” provides three kinds of connections:
• Connections between peripherals
• Connections to package pins via multiplexers
• Direct connections to package pins without mul tiple xer s
The internal connection logic is controlled by the Peripheral A configuration register.
Each pin multiplexer (“Pin Mux”) connect s one of two internal signals to a pin. One is a periph-
eral signal. The second signal can be an I/O port s ignal or a s ignal from/to another peripheral. The
pin multiplexers are c ontr olled by the pi n configurat ion regi sters. Some input-only pins with out
multiplexers (“Shared Pins w/o Muxes”) are routed to two different peripherals. Your design
should use only one of the inputs and disable or ignore the input going to the second peripheral.
Together, the peripheral configurat ion registers and the pin configuration regi sters allow you to
select the peripherals to be used, to i nterconnect them as your design requi res, and to bring se lected signals to the packa ge pins.
Peripherals B, C, D, ...
5-2
Microprocessor
Peripheral A
Peripheral A
Configuration
Register
Pin
Muxes
Internal
Connection
Logic
Control
Pin Configuration Registers
Figure 5-1. Peripheral and Pin Connections
Control
Pins
with
Muxes
Shared Pins
w/o Muxes
A2535-01
DEVICE CONFIGURATION
5.2PERIPHERAL CONFIGURATION
This section describes the c onfiguratio n of each on-chip peripheral. For mo re detailed information on the peripheral itself, see the chapt er desc ribing that periphera l.
The symbology used for signals that share a device pin is shown in Figure 5-2. Of the two signal
names by a pin, the upper signal is associated with the periphera l in the figure. The lower signal
in parentheses is the alternat e signal , which connec ts to a different peri p heral o r the co re. When
a pin has a multiplexer, it is shown as a switch, and the register bit that co ntrols it is noted above
the switch.
5.2.1DMA Controller, Bus Arbiter, and Refresh Unit Configuration
Figure 5-2 shows the DMA controller, bus arbiter, and refresh unit configuration. Requests for a
DMA data transfer are shown as inputs to the multiplexer:
• A serial I/O transmitter (TXEDM A 0, TXEDMA1) or receiver (RBF DM A0, RB FDMA 1 )
• A synchronous serial I/O transmitter (SSTBE) or receiver (SSRBF)
• A timer (OUT1, OUT2)
• An external source (DRQ0, DRQ1)
The inputs are selected by the DMA configuration register (see Figure 5-3).
5.2.1.1Using The DMA Unit with External Devices
For each DMA channel, three bits in the DMA configurat ion regi ster (Figure 5-3) select the external request input or one of seven request inputs from the peripherals. Another bit enables or
disables that channel’s DMA acknowledge signal (DACKn#) at the device pin. Enable the
DACKn# signal only when you are using the external request signal (DRQn) and need DACKn#.
The acknowledge signals are not routed to the on-chip peripherals, and therefore, these peripherals cannot initiate single-cycle (fly- by) DMA transfers.
An external bus master cannot talk direc tly t o internal perip heral m odules beca use the ext ernal
address lines are outputs only. However, an external device could use a DMA channel to transfer
data to or from an internal peripheral because the DMA generates the addresses. This transaction
would be a two-cycle DMA bus transaction.
5.2.1.2DMA Service to an SIO or SSIO Peripheral
A DMA unit is useful for servicing an SIO o r SSIO peripheral operatin g at a high baud rate. At
high baud rates, the interrupt response time of the core may be too long to a llow the serial
channels to use an interrupt to service the receive-buffer-full condition. By the time the interrupt
service routine (ISR) is ready to transfer the receive-buf fer data to memory, new data would have
been loaded into the buffer. The issue is the interrupt latency which is the amount of time the
processor takes from recognizing the interrupt to executing the first line of code in the ISR. This
interrupt latency needs to be calculated to determine if an ISR can handle the high baud rate. If
the Interrupt Latency is too high, da ta transfers to and from the seri al channe ls can occ ur within
a few bus cycles of the time that a serial unit is ready to move data by using a n appropriately
5-3
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
configured DMA channel. SIO and SSIO inputs to t he DMA a re selected by the DMA configuration register (Figure 5-3).
5.2.1.3Using The Timer To Init iate DMA Transfers
A timer output (OUT1, OUT2) can initiate periodic data transfers by the DMA. A DMA channel
is programmed for the transfer, then a timer output pulse triggers the transfer. The most useful
DMA and timer combinati ons for this type of transfer are the periodic timer modes (mode 2 and
mode 3) with the DMA block-transfer mode programmed. See Chapter 10, “TIMER/COUNTER
UNIT,” and Chapter 12, “DMA CONTROLLER,” for more information on how to program the
peripherals.
5.2.1.4Limitatio n s Due To Pin Signal Multiplexing
Pin signal multiplexing can preclude the simultaneous use of a DMA channel and another peripheral or specific peripheral signal (see Figure 5-2). For example , using DMA channel 1 with an
external req uester device precludes using SIO channel 1 due to the multiplexed signa l pai rs
DRQ1/RXD1 and DACK1#/T XD1. P lease refe r to the Intel386™ EX Microprocessor Pin Mul-tiplexin g Map (O rder Number 272587) for a complete diagram of mul tiplexed signals.
Figure 5-2. Configuration of DMA, Bus Arbiter, and Refresh Unit
5-5
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
DMA Configuration
DMACFG
(read/write)
70
D1MSKD1REQ2D1REQ1D1 REQ0D0MSKD0RE Q2D0REQ1D0RE Q0
Bit
Number
7D1MSKDMA Acknowledge 1 Mask:
6–4D1REQ2:0DMA Channel 1 Request Connecti on :
3D0MSKDMA Acknowledge 0 Mask:
2–0D0REQ2:0DMA Channel 0 Request Connecti on :
Bit
Mnemonic
0 = DMA channel 1’s acknowledge (DMAACK1#) signal is not masked.
1 = Masks DMA channel 1’s acknowledge (DMAACK1 #) sign al. Useful
when channel 1’s request (DREQ1) input is connected to an internal
peripheral.
Connects one of the eight possible hardware sources to channel 1’s
request input (DREQ1).
000 = DRQ1 pin (external peripheral)
001 = SIO channel 1’s receive buffer full signal (RBFDMA1)
010 = SIO channel 0’s transmit buf fer empty signal (TXEDMA0)
011 = SSIO receive holding buffer full signal (SSRBF)
100 = TCU counter 2’s output signal (OUT2)
101 = SIO channel 0’s receive buffer full signal (RBFDMA0)
110 = SIO channel 1’s transmit buf fer empty signal (TXEDMA1)
111 = SSIO transmit holding buffer empty signal (SSTBE)
0 = DMA channel 0’s acknowledge (DMAACK0#) signal is not masked.
1 = Masks DMA channel 0’s acknowledge (DMAACK0 #) sign al. Useful
when channel 0’s request (DREQ0) input is connected to an internal
peripheral.
Connects one of the eight possible hardware sources to channel 0’s
request input (DREQ0).
000 = DRQ0 pin (external peripheral)
001 = SIO channel 0’s receive buffer full signal (RBFDMA0)
010 = SIO channel 1’s transmit buf fer empty signal (TXEDMA1)
011 = SSIO transmit holding buffer empty signal (SSTBE)
100 = TCU counter 1’s output signal (OUT1)
101 = SIO channel 1’s receive buffer full signal (RBFDMA1)
110 = SIO channel 0’s transmit buf fer empty signal (TXEDMA0)
111 = SSIO receive holding buffer full signal (SSRBF )
Expanded Addr:
ISA Addr:
Reset State:
Function
F830H
—
00H
5-6
Figure 5-3. DMA Configuration Register (DMACFG)
DEVICE CONFIGURATION
5.2.2Interrupt Control Unit Configuration
The interrupt control unit (ICU) comprises two 82C59A interrupt control lers connected in cascade, as shown in Figure 5-4. (See Chapter 9 for more information.) Figure 5-5 describes the interrupt configuration register (INTCFG).
The ICU receives requests from eight internal sourc es:
• Three outputs from the timer/cou nter unit (OUT2:0)
• An output from each of the serial I/O units (SIOINT1:0)
• An output from the synchronous serial I/O unit (SSIOINT)
• An output from the DMA unit (DMAINT)
• An output from the WDT unit (WDTOUT#)
In addition, the ICU controls the interrupt sources on ten external pins:
• INT3:0 (multiplexed with I/O port signals P3.5:2) are enabled or disabled by the P3CFG
register (see Figure 5-18).
• INT7:4 share their package pins with four TCU inputs: TMRGATE1, TMRCLK1,
TMRGATE0, and TMR C LK 0. These signal pairs are not mult ipl exed; however, the pin
inputs are enabled or disabled by the INTCFG register.
• INT9:8 share their pins with TMROUT1, TMROUT0, P3.1, P3.0
The three cascade outputs (CAS2:0) should be enabled when an external 82C59A module is connected to one of the INT9:8 or INT3:0 signals. The cascade outputs are ORed with address lines
A18:16. See “Interrupt Acknowledge Cycle” on page 6-23 for details.
Use Tables 5-1 and 5-2 to configure the functionality of the master 82C59A ’s IR3, IR4 inputs, and
the associated external pins.
5-7
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
Table 5-1. Master’s IR 3 Connections
FunctionINT CFG.6MCR1.3P3CFG.1
IR3 connected to SIOINT1
P3.1 selected at pin (P3. 1)
IR3 connected to SIOINT1
OUT1 connected to pin (TMROUT1)
IR3 internally driven low
P3.1 selected at pin (P3. 1)
IR3 connected to pin (INT8 )101
IR3 connected to SIOINT1
P3.1 selected at pin (P3. 1)
IR3 connected to SIOINT1
pin (INT8) must not be left floating
NOTE: X is a don’t care
0X0
0X1
100
110
111
Table 5-2. Master’s IR 4 Connections
FunctionINT CFG.5MCR0.3P3CFG.0
IR4 connected to SIOINT0
P3.0 selected at pin (P3. 0)
IR4 connected to SIOINT0
OUT0 connected to pin (TMROUT0)
IR4 internally driven low
P3.0 selected at pin (P3. 0)
IR4 connected to pin (INT9 )101
IR4 connected to SIOINT0
P3.0 selected at pin (P3. 0)
IR4 connected to SIOINT0
pin (INT9) must not be left floating
NOTE: X is a don’t care
5-8
0X0
0X1
100
110
111
DEVICE CONFIGURATION
INTR
(to
core)
8259A
Master
INT
CAS2:0
INT
8259A
CAS2:0
Slave
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
IR0
IR1
IR2
IR3
P3CFG.2
INTCFG.6
INTCFG.5
P3CFG.3
P3CFG.4
P3CFG.5
INTCFG.0
INTCFG.1
OUT0 (TCU)
0
V
SS
1
0
SIOINT1
1
0
SIOINT0
1
V
0
SS
1
V
0
SS
1
V
0
SS
1
V
0
SS
1
SSIOINT
0
1
OUT1(TCU)
OUT2(TCU)
To/From I/O Port 3
MCR1.3
SIOINT1
1
0
OUT1(TCU)
MCR0.3
SIOINT0
1
0
OUT0(TCU)
To/From I/O Port 3
To/From I/O Port 3
To/From I/O Port 3
To TCU
To TCU
INTCFG.6
1
1
P3.1
0
INTCFG.5
1
0
1
1
1
P3CFG.2
0
P3CFG.1
1
1
P3.0
P3CFG.3
0
P3CFG.4
0
P3CFG.5
0
0
P3GFG.0
0
INT0
(P3.2)†
INT8
TMROUT1
(P3.1)
INT9
TMROUT0
(P3.0)
INT1
(P3.3)
INT2
(P3.4)
INT3
(P3.5)
INT4
(TMRCLK0)
INT5
(TMRGATE0)
INTCFG.4
INTCFG.7
A18:16
DMAINT
To TCU
To TCU
INT6
(TMRCLK1)
INT7
(TMRGATE1)
CAS2:0
(A18:16)
IR4
IR5
0
1
INTCFG.2
IR6
IR7
3
0
1
V
SS
0
1
WDTOUT#
V
INTCFG.3
V
SS
0
1
SS
0
1
† Alternate pin signals are in parentheses
Heavier lines indicate multiple signals.
Figure 5-4. Interrupt Control Unit Configuration
A2522-03
5-9
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
Interrupt Configuration
INTCFG
(read/write)
Expanded Addr:
ISA Addr:
Reset State:
F832H
—
00H
70
CEIR3IR4SWAPIR6IR5/IR4IR1IR0
Bit
Number
Bit
Mnemonic
Function
7CECascade Enable:
0 = Disables the cascade signals CAS2:0 from appearing on the A18:16
address lines during interrupt acknowledge cycles.
1 = Enables the cascade signals CAS2:0, providing access to external
slave 82C59A devices. The cascade signals are used to address
specific slaves. If enabled, slave IDs appear on the A18:16 address
lines during interrupt acknowledge cycles, but are high during idle
cycles.
6IR3Internal Master IR3 Connection:
See Table 5-1 on page 5-8 for all the IR3 configuration options.
5IR4Internal Master IR4 Connection:
See Table 5-2 on page 5-8 for all the IR4 configuration options.
4SWAPINT6/DMAINT Connection:
0 = Connects DMAINT to the slave IR4. Connects INT6 to the slave IR5.
1 = Connects the INT6 pin to the slave IR4. Connects DMAINT to the slave
IR5.
3IR6Internal Slave IR6 Connection:
0 = Connects V
1 = Connects the INT7 pin to the slave IR6 signal.
to the slave IR6 signal.
SS
2IR5/IR4Intern al Slave IR4 or IR5 Con ne ct io n:
These depend on whether INTCFG.4 is set or clear.
0 = Connects V
1 = Connects either the INT6 pin or DMAINT to the slave IR5 signal.
to the slave IR5 signal.
SS
1IR1Internal Slave IR1 Connection:
0 = Connects the SSIO interrupt signa l (SSIOINT ) to the slave IR1 signal .
1 = Connects the INT5 pin to the slave IR1 signal.
0IR0Internal Slave IR0 Connection:
0 = Connects V
1 = Connects the INT4 pin to the slave IR0 signal.
to the slave IR0 signal.
SS
5-10
Figure 5-5. Interrupt Configur ation Register (I NTCFG)
DEVICE CONFIGURATION
5.2.3Timer/counter Unit Configuration
The three-channel Timer/counter Unit (TCU) and its configuration register (TMRCFG) are
shown in Figure 5-6 and Figure 5-7. The clock inputs can be external signals (TMRCLK2:0) or
the on-chip programmable clock (PSCLK). All clock inputs can be held low by programming bits
in the TMRCFG regi ster. The gate inputs can be control led through software using TM RCFG .6
and the appropriate GTnCON bits in the TMRCFG register. Several of the timer signals go to the
interrupt control unit (see Figure 5-4).
The Timer/counter0 and Timer/counter1 sig nals are selected individually. In contrast, the Timer/counter2 signals (TMRCLK2, TMRGA TE2, TMROUT2) are selected as a group. Note that using the Timer/counter2 signals precludes use of the coprocessor signals (PEREQ, BUSY#, and
ERRO R#).
The CLKINn and GATEn inputs of Timer/counte r0 and Timer/counter1 are routed dire ctly to
shared input pins, TMRCLK0/INT4, TMRCLK1/INT6, TMRGATE0/INT5 and
TMRGATE1/INT7. The OUTn inputs of these two counters can be connected to pins
TMROUT0/INT9/ P3.0 and TMROUT1/INT8/P3.1 respec tively, using bits in regis ters P3CFG
and INTCFG.
5-11
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
Timer/Counter
Unit
CLKIN0
TMRCFG.6
GATE0
0
1
TMRCFG.1
OUT0
CLKIN1
TMRCFG.6
GATE1
0
1
TMRCFG.3
OUT1
CLKIN2
TMRCFG.6
GATE2
0
1
TMRCFG.5
OUT2
† Alternate pin signals are in parentheses.
TMRCFG.7
TMRCFG.0
0
1
TMRCFG.1
To ICU
To/From I/O Port 3
TMRCFG.2
0
1
TMRCFG.3
To ICU, DMA
To/From I/O Port 3
TMRCFG.4
0
1
TMRCFG.5
To ICU, DMA
PSCLK
0
1
PSCLK
0
1
PSCLK
To Core
0
1
To Core
To ICU
V
CC
To ICU
To ICU
V
CC
To ICU
V
CC
To Core
1
1
1
1
1
P3CFG.0
0
P3CFG.1
0
PINCFG.5
0
0
0
TMRCLK0
(INT4)†
TMRGATE0
(INT5)
TMROUT0
(INT9)
(P3.0)
TMRCLK1
(INT6)
TMRGATE1
(INT7)
TMROUT1
(INT8)
(P3.1)
TMRCLK2
(PEREQ)
TMRGATE2
(BUSY#)
TMROUT2
(ERROR#)
A2517-03
5-12
Figure 5-6. Timer/Counter Unit Configuration
DEVICE CONFIGURATION
.
Timer Configuration
TMRCFG
(read/write)
70
TMRDISSWGTENGT2CONCK2CONGT1CONCK1CONGT0CONCK0CON
Expanded Addr:
ISA Addr:
Reset State:
F834H
—
00H
Bit
Number
Bit
Mnemonic
7TMRDISTimer Disable:
0 = Enables the CLKIN
1 = Disables the CLKIN
6SWGTENSoftware GATE
n
Enable
0 = Connects GA T E
1 = Enables GT2CON, GT1CON, and GT0CON to control the
connections to GATE2, GATE1 and GATE0 respectively.
5GT2CONGate 2 Connection:
SWGTENGT2CON
00
01Connects GATE2 to the TMRGATE2 pin.
10Turns GATE2 off.
11Turns GATE2 on.
4CK2CONClock 2 Connection:
0 = Connects CLKIN2 to the internal PSCLK signal.
1 = Connects CLKIN2 to the TMRCLK2 pin.
3GT1CONGate 1 Connection:
SWGTENGT1CON
00
01Connects GATE1 to the TMRGATE1 pin.
10Turns GATE1 off.
11Turns GATE1 on.
2CK1CONClock 1 Connection:
0 = Connects CLKIN1 to the internal PSCLK signal.
1 = Connects CLKIN1 to the TMRCLK1 pin.
1GT0CONGate 0 Connection:
SWGTENGT0CON
00
01Connects GATE0 to the TMRGATE1 pin.
10Turns GATE0 off.
11Turns GATE0 on.
0CK0CONClock 0 Connection:
0 = Connects CLKIN0 to the internal PSCLK signal.
1 = Connects CLKIN0 to the TMRCLK0 pin.
Function
n
signals.
n
signals.
n
to either the VCC pin or the TMRGATEn pin.
Connects GATE2 to V
Connects GATE1 to V
Connects GATE0 to V
CC.
CC.
CC.
Figure 5-7. Timer Configuration Re gister (TMR CFG)
5-13
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
5.2.4Asynchronous Serial I/O Config ur atio n
Figures 5-8 and 5-9 show the asynchronous serial I/O unit configuration, consisting of channels
SIO0 and SIO1. Each channel has one output (SIOINT0, SIOINT 1) to the i nter rupt control unit
(see Figure 5- 4) and two outputs to the DMA unit. (These signals do not go to package pins.)
SIOINTn is active when any one of the SIO status signals (receiver line st atus, receiver buffer
full, transmit buffer empty, modem status) is set and enabled. All SIO0 pins are multiplexed with
I/O port signals.
Using SIO1 precludes using DMA channel 1 for external DMA requests due to the multiplexing
of the transmit and receive signals with DMA signal s (RXD1/ DRQ 1, TXD1/DAC K1#).
NOTE
Using SIO1 modem signals RTS1 #, DSR1#, DTR1#, and RI 1# precludes use
of the SSIO unit.
5-14
DEVICE CONFIGURATION
SIO0
BCLKIN
Receive Data
SIOINT0
RBFDMA0
TXEDMA0
Transmit Data
Clear to Send
Request to Send
Data Set Ready
SIOCFG.0
0
1
To ICU
To DMA
To DMA
SIOCFG.6
0
1
0
1
SERCLK
To/From I/O Port 3
To/From I/O Port 2
To/From I/O Port 2
To/From I/O Port 2
To/From I/O Port 1
To/From I/O Port 1
1
1
1
1
1
1
P3CFG.7
0
P2CFG.5
0
P2CFG.6
0
P2CFG.7
0
P1CFG.1
0
P1CFG.3
0
COMCLK
(P3.7)†
RXD0
(P2.5)
TXD0
(P2.6)
CTS0#
(P2.7)
RTS0#
(P1.1)
DSR0#
(P1.3)
Data Carrier
Detect
0
1
Data Terminal
Ready
Ring Indicator
0
1
† Alternate pin signals are in parentheses.
Figure 5-8. Serial I/O Unit 0 Configuration
To/From I/O Port 1
To/From I/O Port 1
To/From I/O Port 1
V
CC
1
1
1
P1CFG.0
0
P1CFG.2
0
P1CFG.4
0
DCD0#
(P1.0)
DTR0#
(P1.2)
RI0#
(P1.4)
A2521-02
5-15
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
SIO1
BCLKIN
Receive Data
SIOINT1
RBFDMA1
TXEDMA1
Transmit Data
Clear to Send
Request to Send
Data Set Ready
SIOCFG.1
0
1
To ICU
To DMA
To DMA
SIOCFG.7
0
1
0
1
SERCLK
To/From I/O Port 3
To DMA
From DMA
To/From DMA
From SSIO
To/From SSIO
1
1
1
1
P3CFG.7
0
PINCFG.2
0
PINCFG.3
0
PINCFG.0
0
COMCLK
(P3.7)†
RXD1
(DRQ1)
TXD1
(DACK1#)
CTS1#
(EOP#)
RTS1#
(SSIOTX)
DSR1#
(STXCLK)
Data Carrier
Detect
Data Terminal
Ready
Ring Indicator
† Alternate pin signals are in parentheses.
Figure 5-9. Serial I/O Unit 1 Configuration
5-16
0
To DMA
1
PINCFG.1
1
To/From SSIO
0
1
V
CC
To SSIO
0
DCD1#
(DRQ0)
DTR1#
(SRXCLK)
RI1#
(SSIORX)
A2519-02
DEVICE CONFIGURATION
SIO and SSIO Configuration
SIOCFG
(read/w rite)
70
S1MS0M———SSB SRCS 1BSR CS0BSRC
Bit
Number
7S1MSIO1 Modem Signal Con nections:
6S0MSIO0 Modem Signal Con nections:
5–3—Reserved. These bits are undefined; for compatibility with future devices,
2SSBSRCSSIO Baud-rate Generator Clock Source:
1S1BSRCSIO1 Baud-rate Generator Clock Source:
0S0BSRCSIO0 Baud-rate Generator Clock Source:
Bit
Mnemonic
0 = Connects the SIO1 modem input signals to the package pins.
1 = Connects the SIO1 modem input signals internally.
0 = Connects the SIO0 modem input signals to the package pins.
1 = Connects the SIO0 modem input signals internally.
do not modify these bits.
0 = Connects the internal PSCLK signal to the SSIO baud-rate
generator.
1 = Connects the internal SERCLK signal to the SSIO baud-rate
generator.
0 = Connects the COMCLK pin to the SIO1 baud-rate generat or.
1 = Connects the internal SERCLK signal to the SIO1 baud-rate
generator.
0 = Connects the COMCLK pin to the SIO0 baud-rate generat or.
1 = Connects the internal SERCLK signal to the SIO0 baud-rate
generator.
Expanded Addr:
ISA Addr:
Reset State:
Function
F836H
—
00H
Figure 5-10. SIO and SSIO Configuration Register (SIOCFG)
5-17
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
5.2.5Synchronous Serial I/O Configuration
The synchronous serial I/O unit (SSIO) is shown in Figure 5-11. Its single configuration register
bit is in the SIOCFG register (Figure 5-10). The transmit buffer empty and receive buffer full signals (SSTBE and SSRB F) go to the DMA unit (Fig ure 5-2), and an interrupt signal (SSIOINT)
goes to the ICU (Figure 5-4). Depending on the settings in the SSIOCON1 register (see Chapter
13), SSIOINT is asserted for one of two condit ions: the receive buffer is full or the transmit buffer
is empty. Note that using the SSIO signals precludes the use of four of the SIO1 modem signals.
SSIO
BCLKIN
SSTBE
SSRBF
SSIOINT
Receive Data
Transmit Data
Transmit Clock
Receive Clock
*Alternate pin signals are in parentheses.
SIOCFG.2
0
1
Figure 5-11. SSIO Unit Configur ation
PSCLK
SERCLK
To DMA
To DMA
To ICU
To SIO1
From SIO1
To SIO1
From SSIO1
0
0
PINCFG.0
1
PINCFG.1
1
SSIORX
(RI1#)*
SSIOTX
(RTS1#)
STXCLK
(DSR1#)
SRXCLK
(DTR1#)
A2518-02
5-18
DEVICE CONFIGURATION
5.2.6Chip-select Unit and Clock and Power Managem en t Unit Config urati on
Figure 5-12 shows the multiplexing of signal s of the Chip-select Unit and the Clock and Power
Manageme nt U nit.
The Chip-select signals, CS6# and CS5# are multiplexed wit h the REFRESH# signal from the
Refresh Control Unit and the DACK0# si gnal from the DMA Unit, respectively. Bits 6 and 4 in
the PINCFG register (see Figure 5-15) control these multiplexers . CS3#, CS2#, CS1# and CS0#
are multiplexed with I/O Port 2 signal s, P2.3, P2.2, P2.1 and P2.0, respectivel y. Bits 4:0 in the
P2CFG register (see Figure 5-17) control these multiplexers.
The PWRDOWN o utput signal of the Clock and Power Manage ment Unit is multiplexed wit h
I/O Port 3 signal, P3.6. Bit 6 in the P3C FG register (see Figure 5-18) controls this multiple xe r.
5-19
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
CSU
CS0#
CS1#
CS2#
CS3#
CS4#
CS5#
CS6#
Clock and
Power
Management
Unit
To/From I/O Port 2
To/From I/O Port 2
To/From I/O Port 2
To/From I/O Port 2
To/From I/O Port 2
DACK0# (DMA)
REFRESH# (RCU)
P2CFG.0
1
0
P2CFG.1
1
0
P2CFG.2
1
0
P2CFG.3
1
0
P2CFG.4
1
0
PINCFG.4
1
0
PINCFG.6
1
0
CSO#
(P2.0)
CS1#
(P2.1)
CS2#
(P2.2)
CS3#
(P2.3)
CS4#
(P2.4)
CS5#
(DACK0#)
CS6#
(REFRESH#)
P3CFG.6
PWRDOWN
To/From I/O Port 3
1
0
PWRDOWN
(P3.6)
Figure 5-12. Configuration of Chip-select Unit and Clock and Power Management Unit
5-20
A3380-01
DEVICE CONFIGURATION
5.2.7Core Configuration
Three coprocessor signals (ER ROR #, PERE Q, and B USY# in Figure 5-13) ca n be routed to the
core, as determined by bit 5 of the PINCFG register (see Figure 5-15). Due to signal multiplexing
at the pins, the coprocessor and Timer/counter2 can not be used simult ane ously.
Core
ERROR#
PEREQ
BUSY#
RESET
PINCFG.5
0
1
0
1
0
1
From TCU
V
CC
To TCU
V
SS
To TCU
V
CC
From Chip RESET Pin
PINCFG.5
0
1
0
1
0
1
RESET Timing
Generation
PORT92.1
ERROR#
(TMROUT2)†
PEREQ
(TMRCLK2)
BUSY#
(TMRGATE2)
PORT92.0
A20
LOCK#
To/From I/O Port 1
† Alternate pin signals are in parentheses.
Figure 5-13. Core Configuration
1
0
To Chip-select Unit
and A20 Pin
P1CFG.5
LOCK#
(P1.5)
A2520-02
5-21
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
Setting bit 0 in the PORT92 register (see Figure 5-14) resets the core without resetting the peripherals. Unlike the RESET pin, which is as ynchronous and can be used to synchronize internal
clocks to CLK2, this core-only reset is synchronized with the on-chip clocks and does not affect
the on-chip cloc k synchronization. After the CPU-R ESET this bit is still set to 1. It must be
cleared and then set to cause another core-only reset.
Clearing bit 1 in the PORT92 register forces address line A20 to 0. This bit affects only addresses
generated by the core; ad dresses generate d by the DMA an d the refresh cont rol unit are not af fected.
Port 92 Configuration
PORT92
(read/write)
70
——————A20GCPURST
Bit
Number
7–2—Reserved. These bits are undefined; for compatibility with future devices,
1A20GA20 Grounded:
0CPURSTCPU Reset:
Bit
Mnemonic
do not modify these bits.
0 = Clearing this bit for ce s ad dre ss l in e A20 to 0. This bit affect s
addresses generated only by the core. Addresses generated by the
DMA and the Refresh Unit are not affected by this bit.
1 = Setting this bit leaves core-generated addresses unmodified.
0 = Clearing this bit performs no operation.
1 = Setting this bit resets the core without resetting the peripherals.
This bit must be cleared bef ore issui ng anothe r rese t.
Expanded Addr:
ISA Addr:
Reset State:
Function
F092H
0092H
XXXXXX10B
Figure 5-14. Port 92 Configuration Register (PORT92)
5-22
DEVICE CONFIGURATION
5.3PI N CONFIGURATION
Most of the microprocessor’s package pins support two peripheral functions. Some of these pins
are routed to two peripheral in puts with out the use of a multiplex er. These input-signal pairs are
listed in Table 5-3. The pin is connected to both peripheral inputs.
The remaining pins supporting two signals have multiplexers. For each such pin, a bit in a pin
configuration register enable s one of the signals. Table 5-9 lists the bits in each of the four pin
configuration registers. These abbreviated register tables are discussed in “Configuration Example” on pa g e 5- 28.
When configuring ports to use INT8 or INT9, first set the appropriate INTCFG bit, then the
P3CFG bit. Setting the bits in this order avoids any potential contention on INT8 or INT9.
Table 5-3. Signal Pairs on Pins without a Multiplexer
NamesSignal Descriptions
DRQ0/
DCD1#
DRQ1/
RXD1
DSR1#/
STXCLK
RI1#/
SSIORX
TMRCLK0/
INT4
TMRGATE0/
INT5
TMRCLK1/
INT6
TMRGATE1/
INT7
DMA Externa l Requ es t 0 indicate s that an off-chip periphe ral require s DMA service.
Data Carrier Detect SIO1 indic a tes that the modem or dat a set has d etecte d the
asynchronous serial channel’s data carrier.
DMA Externa l Requ es t1 indicates that an off-chip peripheral requires DMA service.
Receive Data SIO 1 accepts serial data from the modem or data set to the
asynchronous serial channel SIO1.
Data Set Ready SIO1 indicates that the modem or data set is ready to establish a
communication link with asynchronous serial channel SIO1.
SSIO Transmit Clock synch ronizes dat a being sent by the synchronous serial port.
Ring Indicator SIO1 indicates that the modem or data set has received a telephone
ringin g signal.
SSIO Receive Seri al D ata accepts serial data (most-significant bit first) being sent to
the synchrono us serial port.
Timer/Counter0 Clock Input can serve as an externa l cloc k input for timer/co unter0 .
(The tim er / co unters can also be clocked internally.)
Interrupt 4 is an undedicat ed exte rn al inter rup t.
Timer/Counter0 Gate Input can control timer/counter0’s counting (enable, disable, or
trigger, depending on the programmed mode).
Interrupt 5 is an undedicated external interrupt.
Timer/Counter1 Clock Input can serve as an externa l cloc k input for timer/co unter1 .
(The tim er / co unters can also be clocked internally.)
Interrupt 6 is an undedicated external interrupt.
Timer/Counter1 Gate Input can control timer/counter1’s counting (enable, disable, or
trigger, depending on the programmed mode).
Interrupt 7 is an undedicated external interrupt.
5-23
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
Pin Configuration
PINCFG
(read/write)
70
—PM6PM5PM4PM3PM2PM 1PM 0
Bit
Number
7—Reserved. This bit is undefined; for compatibility with future devices, do
6PM6Pin M od e:
5PM5Pin M od e:
4PM4Pin M od e:
3PM3Pin M od e:
2PM2Pin M od e:
1PM1Pin M od e:
0PM0Pin M od e:
Bit
Mnemonic
not modify this bit.
0 = Selects CS6# at the package pin.
1 = Selects REFRESH# at the package pin.
0 = Selects the coprocessor signals, PEREQ, BUSY#, and ERROR#, at
the package pins.
1 = Selects the timer control unit signals, TMROUT2, TMRCLK2, and
TMRGATE2, at the package pins.
0 = Selects DACK0# at the package pin.
1 = Selects CS5# at the package pin.
0 = Selects EOP# at the package pin.
1 = Selects CTS1# at the package pin.
0 = Selects DACK1# at the package pin.
1 = Selects TXD1 at the package pin.
0 = Selects SRXCLK at the package pin.
1 = Selects DTR1# at the package pin.
0 = Selects SSIOTX at the package pin.
1 = Selects RTS1# at the package pin.
Expanded Addr:
ISA Addr:
Reset State:
Function
F826H
—
00H
5-24
Figure 5-15. Pin Configuration Register (PINCFG)
DEVICE CONFIGURATION
Port 1 Configuration
P1CFG
(read/write)
70
PM7PM6PM 5P M4PM 3PM 2PM1PM0
Bit
Number
7PM7Pin M od e:
6PM6Pin M od e:
5PM5Pin M od e:
4PM4Pin M od e:
3PM3Pin M od e:
2PM2Pin M od e:
1PM1Pin M od e:
0PM0Pin M od e:
Bit
Mnemonic
0 = S elects P1.7 at t he package pin.
1 = Selects HLDA at the package pin.
0 = S elects P1.6 at t he package pin.
1 = Selects HOLD at the package pin.
0 = S elects P1.5 at t he package pin.
1 = Selects LOCK# at the package pin.
0 = S elects P1.4 at t he package pin.
1 = Selects RI0# at the package pin.
0 = S elects P1.3 at t he package pin.
1 = Selects DSR0# at the package pin.
0 = S elects P1.2 at t he package pin.
1 = Selects DTR0# at the package pin.
0 = S elects P1.1 at t he package pin.
1 = Selects RTS0# at the package pin.
0 = S elects P1.0 at t he package pin.
1 = Selects DCD0# at the package pin.
Expanded Addr:
ISA Addr:
Reset State:
Function
F820H
—
00H
Figure 5-16. Port 1 Configuration Register (P1CFG)
5-25
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
Port 2 Configuration
P2CFG
(read/write)
70
PM7PM6PM 5P M4PM 3PM 2PM1PM0
Bit
Number
7PM7Pin M od e:
6PM6Pin M od e:
5PM5Pin M od e:
4PM4Pin M od e:
3PM3Pin M od e:
2PM2Pin M od e:
1PM1Pin M od e:
0PM0Pin M od e:
Bit
Mnemonic
0 = S elects P2.7 at t he package pin.
1 = Selects CTS0# at the package pin.
0 = S elects P2.6 at t he package pin.
1 = Selects TXD0 at the package pin.
0 = S elects P2.5 at t he package pin.
1 = Selects RXD0 at the package pin.
0 = S elects P2.4 at t he package pin.
1 = Selects CS4# at the package pin.
0 = S elects P2.3 at t he package pin.
1 = Selects CS3# at the package pin.
0 = S elects P2.2 at t he package pin.
1 = Selects CS2# at the package pin.
0 = S elects P2.1 at t he package pin.
1 = Selects CS1# at the package pin.
0 = S elects P2.0 at t he package pin.
1 = Selects CS0# at the package pin.
Expanded Addr:
ISA Addr:
Reset State:
Function
F822H
—
00H
5-26
Figure 5-17. Port 2 Configuration Register (P2CFG)
DEVICE CONFIGURATION
Port 3 Configuration
P3CFG
(read/write)
70
PM7PM6PM 5P M4PM 3PM 2PM1PM0
Bit
Number
7PM7Pin M od e:
6PM6Pin M od e:
5PM5Pin M od e:
4PM4Pin M od e:
3PM3Pin M od e:
2PM2Pin M od e:
1PM1Pin M od e:
0PM0Pin M od e:
Bit
Mnemonic
0 = S elects P3.7 at t he package pin.
1 = Selects COMCLK at the package pin.
0 = S elects P3.6 at t he package pin.
1 = Selects PWRDOWN at the package pin.
0 = S elects P3.5 at t he package pin.
1 = Connects master IR7 to the package pin (INT3).
0 = S elects P3.4 at t he package pin.
1 = Connects master IR6 to the package pin (INT2).
0 = S elects P3.3 at t he package pin.
1 = Connects master IR5 to the package pin (INT1).
0 = S elects P3.2 at t he package pin.
1 = Connects master IR1 to the package pin (INT0).
See Table 5-1 on page 5-8 for all the PM1 configuration options.
See Table 5-1 on page 5-8 for all the PM0 configuration options.
Expanded Addr:
ISA Addr:
Reset State:
Function
F824H
—
00H
Figure 5-18. Port 3 Configuration Register (P3CFG)
5-27
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