Intel 386 User Manual

Intel386™ EXTB Embedded Microprocessor  Intel386 Embedded Microprocessor

™

EXTC

Intel386™ EX Embedded Microprocessor User’s Manual

™

Intel386 EX

Embedded

Microprocessor

User’s Manual

1996

Information in this document is provided in connection with Intel products. Intel assumes no liabilit y whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.

Intel retains the right to make changes to these specifications at any time, without notice. Microcontroller products may have minor variations to this specification known as errata.

*Other brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order. Copies of documents whi ch have a n orderi ng nu mber a nd are referenced i n this documen t, or o ther Inte l lite rature, ma y be

obtained from:

Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641

or call 1-800-548-4725

CHAPTER 1

GUIDE TO THIS MANUAL

1.1 MANUAL CONTENTS................................................................................................... 1-1

1.2 NOTATIONAL CONVENTIONS..................................................................................... 1-3

1.3 SPECIAL TERMINOLOGY............................................................................................ 1-4

1.4 RELATED DOCUMENTS.............................................................................................. 1-5

1.5 ELECTRONIC SUPPORT SYSTEMS ........................................................................... 1-6

1.5.1 FaxBack Service . ......................................................................................................1-6

1.5.2 Bulletin Board System (BBS) ....................................................................................1-7

1.5.3 CompuServe Forums ................................................................................................1-7

1.5.4 World Wide Web .......................................................................................................1-7

1.6 TECHNICAL SUPPORT................................................................................................ 1-7

1.7 PRODUCT LITERATURE.............................................................................................. 1-8

CHAPTER 2

ARCHITECTURAL OVERVIEW

2.1 Intel386 EX EMBEDDED PROCESSOR CORE............................................................ 2-1

2.2 INTEGRATED PERIPHERALS...................................................................................... 2-3

CHAPTER 3

CORE OVERVIEW

3.1 Intel386 CX PROCESSOR ENHANCEMENTS............................................................. 3-1

3.1.1 System Management Mode ......................................................................................3-1

3.1.2 Additional Address Lines ..........................................................................................3-1

3.2 Intel386 CX PROCESSOR INTERNAL ARCHITECTURE............................................ 3-2

3.2.1 Core Bus Unit ............. ...............................................................................................3-4

3.2.2 Instruction Prefetc h Unit .. ............ ................. ............... ............ ............ ................. ..... 3-4

3.2.3 Instruction Decode Unit .............................................................................................3-4

3.2.4 Execution Unit ...........................................................................................................3-5

3.2.5 Segmentation Unit ....................................................................................................3-5

3.2.6 Paging Unit .................................................. ............................................................. 3-5

3.3 CORE Intel386 EX PROCESSOR INTERFACE............................................................ 3-6

CHAPTER 4

SYSTEM REGISTER ORGANIZATION

4.1 OVERVIEW ................................................................................................................... 4-1

4.1.1 Intel386 Processor Core Architecture Registers .......................................................4-2

4.1.2 Intel386 EX Processor Peripheral Registers .............................................................4-2

4.2 I/O ADDRESS SPACE FOR PC/AT SYSTEMS ............................................................ 4-2

4.3 EXPANDED I/O AD DRESS SPACE.............................................................................. 4-3

4.4 ORGANIZATION OF PERIPHERAL REGISTERS........................................................ 4-5

4.5 I/O ADDRESS DECODING TECHNIQUES................................................................... 4-6

4.5.1 Address Configuration Register ................................................................................4-6

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Intel386™ EX MICROPROCESSOR USER’S MANUAL

4.5.2 Enabling and Disabling the Expanded I/O Space .....................................................4-8

4.5.2.1 Programming REMAPCFG Example ...................................................................4-8

4.6 ADDRESSING MODES................................................................................................. 4-9

4.6.1 DOS-compatible Mode ..............................................................................................4-9

4.6.2 Nonintrusive DOS Mode .........................................................................................4-11

4.6.3 Enhanced DOS Mode .............................................................................................4-11

4.6.4 Non-DOS Mode ......................................................................................................4-11

4.7 PERIPHERAL REGISTER ADDRESSES.................................................................... 4-15

CHAPTER 5

DEVICE CONFIGURATION

5.1 INTRODUCTION........................................................................................................... 5-1

5.2 PERIPHERAL CONFIGURATION................................................................................. 5-3

5.2.1 DMA Controller, Bus Ar biter, and Refresh Unit Configuration ..................................5-3

5.2.1.1 Using The DMA Unit with External Devices .........................................................5-3

5.2.1.2 DMA Service to an SIO or SSIO Peripheral .........................................................5-3

5.2.1.3 Using The Timer To Initiate DMA Transfers ......................................................... 5-4

5.2.1.4 Limitations Due To Pin Signal Multiplexing ..........................................................5-4

5.2.2 Interrupt Control Unit Co nfiguratio n .................. ............... ....... ............ ............... ....... 5- 7

5.2.3 Timer/counter Unit Configuration ............................................................................5-11

5.2.4 Asynchronous Serial I/O Configuration . ....... ............... ....... ............... ............ ....... ... 5-14

5.2.5 Synchronous Serial I/O Configurati on ........................ ..... ....... ..... ....... ..... ........ .... ... 5-18

5.2.6 Chip-select Unit and Clock and Power Management Unit Configurati on ............. ...5-19

5.2.7 Core Configuration ..................................................................................................5-21

5.3 PIN CONFIGURATION................................................................................................ 5-23

5.4 DEVICE CONFIGURATION PROCEDURE................................................................ 5-28

5.5 CONFIGURATION EXAMPLE..................................................................................... 5-28

5.5.1 Example Design Requirements ...............................................................................5-28

5.5.2 Example Design Solution ........................................................................................5-29

CHAPTER 6

BUS INTERFACE UNIT

6.1 OVERVIEW ................................................................................................................... 6-1

6.1.1 Bus Signal Descriptions ............................................................................................6-3

6.2 BUS OPERATION......................................................................................................... 6-5

6.2.1 Bus States .................................................................................................................6-7

6.2.2 Pipelining ..................................................................................................................6-8

6.2.3 Data Bus Transfers and Operand Alignment ............................................................6-9

6.2.4 Ready Logic ............................................................................................................6-10

6.3 BUS CYCLES.............................................................................................................. 6-13

6.3.1 Read Cycle .............................................................................................................6-13

6.3.2 Write Cycle .......... ...................... ................... ...................... ................. ....................6-16

6.3.3 Pipelined Cycle .......................................................................................................6-19

CONTENTS

6.3.4 Interrupt Acknowledge Cycle ..................................................................................6-23

6.3.5 Halt/Shutdown Cycle ...............................................................................................6-26

6.3.6 Refresh Cycle .........................................................................................................6-28

6.3.7 BS8 Cycle ............................................................................................................... 6-31

6.3.7.1 Write Cycles ....................................................................................................... 6-31

6.3.7.2 Read Cycles .......................................................................................................6-31

6.4 BUS LOCK................................................................................................................... 6-34

6.4.1 Locked Cycle Activators ..........................................................................................6-34

6.4.2 Locked Cycle Timing ...............................................................................................6-34

6.4.3 LOCK# Signal Duration ........................................................................................ ...6-35

6.5 EXTERNAL BUS MASTER SUPPORT (USING HOLD, HLDA).................................. 6-35

6.5.1 HOLD/HLDA Timing ................................................................................................6-36

6.5.2 HOLD Signal Latency .............................................................................................6-37

6.6 DESIGN CONSIDERATIONS...................................................................................... 6-38

6.6.1 Interface To Intel387™ SX Math Coprocessor .......................................................6-38

6.6.1.1 System Configuration .........................................................................................6-39

6.6.1.2 Software Considerations ....................................................................................6-40

6.6.2 SRAM/FLASH Interface ..........................................................................................6-41

6.6.3 PSRAM Interface ....................................................................................................6-42

6.6.4 Paged DRAM Interface ........................................................................................... 6-43

6.6.5 Non-Paged DRAM Interface ...................................................................................6-44

CHAPTER 7

SYSTEM MANAGEMENT MODE

7.1 SYSTEM MANAGEMENT MODE OVERVIEW............................................................. 7-1

7.2 SMM HARDWARE INTERFACE ................................................................................... 7-1

7.2.1 System Management Interrupt Input (SMI#) .............................................................7-1

7.2.2 SMM Active Output (SMIACT#) ................................................................................7-2

7.2.3 System Management RAM (SMRAM) ......................................................................7-2

7.3 SYSTEM MANAGEMENT MODE PROGRAMMING AND CONFIGURATION............. 7-3

7.3.1 Register Status During SMM ....................................... ..............................................7-3

7.3.2 System Management Interrupt ..................................................................................7-4

7.3.2.1 SMI# Priority . ......... ............... ............ ....... ............... ............ .......... ............ ............7-7

7.3.2.2 System Management Interrupt During HALT Cycle ............................................. 7-8

7.3.2.3 HALT Restart .......................................................................................................7-9

7.3.2.4 System Management Interrupt During I/O Instruction ........... ....... ..... ....... ..... .......7-9

7.3.2.5 I/O Restart ................................................................................................ ..........7-10

7.3.3 SMM Handler Interruption .......................................................................................7-10

7.3.3.1 Interrupt During SMM Handler ...........................................................................7-10

7.3.3.2 HALT During SMM Handler ................................................................................ 7-11

7.3.3.3 Idle Mode and Powerdown Mode During SMM ..................................................7-12

7.3.3.4 SMI# During SMM Operation .............................................................................7-12

7.3.4 SMRAM Programming ............................................................................................7-12

7.3.4.1 Chip-select Unit Support for SMRAM .................................................................7-12

Intel386™ EX MICROPROCESSOR USER’S MANUAL

7.3.4.2 SMRAM State Dump Area ................................................................................. 7-14

7.3.5 Resume Instruction (RSM) ......................................................................................7-15

7.4 THE Intel386 EX PROCESSOR IDENTIFIER REGISTERS ....................................... 7-15

7.5 PROGRAMMING CONSIDERATIONS........................................................................ 7-16

7.5.1 System Management Mode Code Example ............................................................7-16

CHAPTER 8

CLOCK AND POWER MANAGEMENT UNIT

8.1 OVERVIEW ................................................................................................................... 8-1

8.1.1 Clock Generation Logic .............................................................................................8-1

8.1.2 Power Management Logic ........................................................................................8-3

8.1.2.1 SMM Interaction with Power Management Modes ........................... ....................8-4

8.1.2.2 Bus Interface Unit Operation During Idle Mode ....................................................8-5

8.1.2.3 Watchdog Timer Unit Operation During Idle Mode ..............................................8-5

8.1.3 Clock and Power Management Register s and Signals .............................................8-6

8.2 CONTROLLING THE PSCLK FREQUENCY................................................................ 8-7

8.3 CONTROLLING POWER MANAGEMENT MODES ..................................................... 8-8

8.3.1 Idle Mode ..................................................................................................................8-9

8.3.2 Powerdown Mode ...................................................................................................8-10

8.3.3 Ready Generation During HALT .............................................................................8-10

8.4 DESIGN CONSIDERATIONS...................................................................................... 8-11

8.4.1 Reset Considerations ..............................................................................................8-11

8.4.2 Power-up Considerations ........................................................................................8-12

8.4.2.1 Built-in Self Test .............. ....... ............... ............ .......... ............ ............ .......... ..... 8-12

8.4.2.2 JTAG Reset ........................................................................................................8-12

8.4.3 Powerdown Mode and Idle Mode Considerations ...................................................8-13

8.5 PROGRAMMING CONSIDERATIONS........................................................................ 8-13

8.5.1 Clock and Power Management Unit Code Example ...............................................8-13

CHAPTER 9

INTERRUPT CONTROL UNIT

9.1 OVERVIEW ................................................................................................................... 9-1

9.2 ICU OPERATION........................................................................................................... 9-4

9.2.1 Interrupt Sources ............................................................... ................. ......................9-4

9.2.2 Interrupt Priority ................... ....... .......... ....... ........ ....... ....... .......... ....... .......... ....... ..... 9-6

9.2.2.1 Assigning an Interrupt Level ......................... ........................................................9-6

9.2.2.2 Determining Priority ..............................................................................................9-7

9.2.3 Interrupt Vectors . ................................................................................ ...................... 9-8

9.2.4 Interrupt Process .......................................................................................................9-9

9.2.5 Poll Mode ................................................................................................................9-14

9.3 REGISTER DEFINITI ONS................................. .......................................................... 9-15

9.3.1 Port 3 Configuration Register (P3CFG) ..................................................................9-18

9.3.2 Interrupt Configuration Register (INTCFG) .............................................................9-19

CONTENTS

9.3.3 Initialization Command Word 1 (ICW1) ...................................................................9-20

9.3.4 Initializatio n Command Word 2 (ICW2) ...................................................................9-21

9.3.5 Initializatio n Command Word 3 (ICW3) ...................................................................9-22

9.3.6 Initializatio n Command Word 4 (ICW4) ...................................................................9-24

9.3.7 Operation Command Word 1 (OCW1) .. ..................................................................9-25

9.3.8 Operation Command Word 2 (OCW2) .. ..................................................................9-26

9.3.9 Operation Command Word 3 (OCW3) .. ..................................................................9-27

9.3.10 Interrupt Request Register (IRR) ......................................................................... ...9-28

9.3.11 In-Service Register (ISR) .................................. .......... ............ ............ .......... ..........9-28

9.3.12 Poll Status Byte (POLL) ..........................................................................................9-28

9.4 DESIGN CONSIDERATIONS...................................................................................... 9-29

9.4.1 Interrupt Acknowledge Cycle ..................................................................................9-29

9.4.2 Interrupt Detection . ............................................................ ..................................... 9-29

9.4.3 Spurious Interrupts ..................................................................................................9-30

9.4.4 Cascading Interrupt Controllers .......................................................... ....................9-30

9.5 PROGRAMMING CONSIDERATIONS........................................................................ 9-32

9.5.1 Interrupt Control Unit Co de Examples ....................................................................9-32

CHAPTER 10

TIMER/COUNTER UNIT

10.1 OVERVIEW ................................................................................................................. 10-1

10.1.1 TCU Signals and Registers .....................................................................................10-3

10.2 TCU OPERATION ....................................................................................................... 10-5

10.2.1 Mode 0 – Interrupt on Terminal Count ....................................................................10-6

10.2.2 Mode 1 – Hardware Retriggerable One-shot ..........................................................1 0-8

10.2.3 Mode 2 – Rate Generator .....................................................................................10-10

10.2.4 Mode 3 – Square Wave ........................................................................................10-12

10.2.5 Mode 4 – Software-triggered Strobe .....................................................................10-16

10.2.6 Mode 5 – Hardware-triggered Strobe ....................................................................10-18

10.3 REGISTER DEFINITIONS .. ....................................................................................... 10-20

10.3.1 Configuring the Input and Output Signals .............................................................10-20

10.3.1.1 Hardware Control of GATE

10.3.1.2 Software Control of GATE

10.3.2 Initializing the Counters ... ...................... ...................... ...................... ................. ... 10-24

10.3.3 Writing the Counters .............................................................................................10-26

10.3.4 Reading the Counter .............................................................................................10-27

10.3.4.1 Simple Read .....................................................................................................10-27

10.3.4.2 Counter-latch Command . .................................................................................10-27

10.3.4.3 Read-back Command ......................................................................................10-30

10.4 PROGRAMMING CONSIDERATIONS...................................................................... 10-33

10.4.1 Timer/Counter Unit Code Examples .....................................................................10-34

............................................................................10-20

..............................................................................10-20

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Intel386™ EX MICROPROCESSOR USER’S MANUAL

CHAPTER 11

ASYNCHRONOUS SERIAL I/O UNIT

11.1 OVERVIEW ................................................................................................................. 11-1

11.1.1 SIO Signals .............................................................................................................11-3

11.2 SIO OPERATION ........................................................................................................ 11-4

11.2.1 Baud-rate Ge nerator .................................. ............ ............ .......... ............ ............ ... 1 1-4

11.2.2 SIO

11.2.3 SIO

11.2.4 Modem Control .....................................................................................................11-12

11.2.5 Diagnostic Mode ...................................................................................................11-12

11.2.6 SIO Interrupt and DMA Sources ...........................................................................11-13

11.2.6.1 SIO Interrupt Sources ......................................................................................11-13

11.2.6.2 SIO DMA sources . ........................................................................................... 11-13

11.2.7 External UART Support ........................................................................................11-14

11.3 REGISTER DEFINITIONS .. ....................................................................................... 11-15

11.3.1 Pin and Port Configuration Registers (PI NCFG and P

11.3.2 SIO and SSIO Configuration Register (SIOCFG) .................................................11-21

11.3.3 Divisor Latch Registers (DLL

11.3.4 Transmit Buffer Register (TBR

11.3.5 Receive Buffer Register (RBR

11.3.6 Serial Line Control Register (LCR

11.3.7 Serial Line Status Register (LSR

11.3.8 Interrupt Enable Register (IER

11.3.9 Interrupt ID Register (IIR

11.3.10 Modem Control Register (MCR

11.3.11 Modem Status Register (MSR

11.3.12 Scratch Pad Register (SCR

11.4 PROGRAMMING CONSIDERATIONS...................................................................... 11-32

11.4.1 Asynchronous Serial I/O Unit Code Examples ......................................................11-33

Transmitter .....................................................................................................11-6

Receiver .........................................................................................................11-9

CFG [n = 1–3]) ................11-17

and DLHn) ............................................................11-22

) ............. .. .. ..........................................................11-23

) ...........................................................................11-24

) ......................................................................11-25

) .......................................................................11-26

) ...........................................................................11-27

) .................................................................................... 11-28

) ..........................................................................11-29

) ...........................................................................11-31

) ...............................................................................11-32

CHAPTER 12

DMA CONTROLLER

12.1 OVERVIEW ................................................................................................................. 12-1

12.1.1 DMA Terminology ...................................................................................................12-3

12.1.2 DMA Signals ...........................................................................................................12-4

12.2 DMA OPERATION ....................................................................................................... 12-5

12.2.1 DMA Transfers ........................................................................................................12-5

12.2.2 Bus Cycle Options for Data Transfers .....................................................................12-5

12.2.2.1 Fly-By Mode .......................................................................................................12-5

12.2.2.2 Two-Cycle Mode ................................................................................................12-6

12.2.2.3 Programmable DMA Transfer Direction .............................................................12-6

12.2.2.4 Ready Generation For DMA Cycles ...................................................................12-7

12.2.2.5 DMA Usage of the 4-Byte Temporary Register ..................................................12-7

12.2.3 Starting DMA Transfers ....................................................................................... ...12-9

viii

CONTENTS

12.2.4 Bu s Control Arbit ration .. ..... .. ..... .. ..... ... .. ..... .. ..... ... ..... .. ..... .. ..... ... ..... .. .. ..... ..... ... .. .....12-9

12.2.5 Ending DMA Transfers ..........................................................................................12-10

12.2.6 Buffer-transfer Modes ...........................................................................................12-12

12.2.6.1 Single Buffer-Transfer Mode ............................................................................12-12

12.2.6.2 Autoinitialize Buffer-Transfer Mode ..................................................................12-12

12.2.6.3 Chaining Buffer-Transfer Mode ........................................................................12-12

12.2.7 Data-transfer Modes .............................................................................................12-13

12.2.7.1 Single Data-transfer Mode ...............................................................................12-14

12.2.7.2 Block Data-transfer Mode ................................................................................12-18

12.2.7.3 Demand Data-transfer Mode ............................................................................12-21

12.2.8 Cascade Mode ......................................................................................................12-25

12.2.9 DMA Interrupts ......................................................................................................12-26

12.2.10 8237A Compatibility .............................. ................................................................12-27

12.3 REGISTER DEFINITIONS .. ....................................................................................... 12-28

12.3.1 Pin Configuration Register (PINCFG) ...................................................................12-31

12.3.2 DMA Configuration Register (DMACFG) ..............................................................12-32

12.3.3 Channel Registers ................................................................................................12-33

12.3.4 Overflow Enable Register (DMAOVFE) ................................................................12-34

12.3.5 Command 1 Register (DMACMD1) .......................................................................12-35

12.3.6 Status Register (DMASTS) ...................................................................................12-36

12.3.7 Command 2 Register (DMACMD2) .......................................................................12-37

12.3.8 Mode 1 Register (DMAMOD1) ..............................................................................12-38

12.3.9 Mode 2 Register (DMAMOD2) ..............................................................................12-40

12.3.10 Software Request Register (DMASRR) ................................................................12-42

12.3.11 Channel Mask and Group Mask Registers (DMAMSK and DMAGRPMSK) .........12-44

12.3.12 Bus Size Register (DMABSR) ...............................................................................12-46

12.3.13 Chaining Register (DMACHR) ..............................................................................12-47

12.3.14 Interrupt Enable Register (DMAIEN) ..................................................................... 12-48

12.3.15 Interrupt Status Register (DMAIS) ........................................................................12-49

12.3.16 Software Commands ............................................................................................12-50

12.4 DESIGN CONSIDERATIONS .................................................................................... 12-50

12.5 PROGRAMMING CONSIDERATIONS...................................................................... 12-50

12.5.1 DMA Controller Code Examples ...........................................................................12-51

CHAPTER 13

SYNCHRONOUS SERIAL I/O UNIT

13.1 OVERVIEW ................................................................................................................. 13-1

13.1.1 SSIO Signals ...........................................................................................................13-4

13.2 SSIO OPERATION...................................................................................................... 13-5

13.2.1 Baud-rate Ge nerator .................................. ............ ............ .......... ............ ............ ... 1 3-5

13.2.2 Transmitter .............................................................................................................. 13-6

13.2.2.1 Transmit Mode using Enable Bit ........................................................................13-7

13.2.2.2 Autotransmit Mode ......................................... ..................................................13-12

13.2.2.3 Slave Mode ......................................................................................................13-12

Intel386™ EX MICROPROCESSOR USER’S MANUAL

13.2.3 Receiver ................................................................................................................13-12

13.3 REGISTER DEFINITIONS .. ....................................................................................... 13-16

13.3.1 Pin Configuration Register (PINCFG) ...................................................................13-17

13.3.2 SIO and SSIO Configuration Register (SIOCFG) .................................................13-18

13.3.3 Prescale Clock Register (CLKPRS) ......................................................................13-19

13.3.4 SSIO Baud-rate Control Register (SSIOBAUD) .......... ...................... ................... . 13-20

13.3.5 SSIO Baud-rate Count Down Register (SSIOCTR) ..............................................13-21

13.3.6 SSIO Control 1 Register (SSIOCON1) ............................. ................... ................. .13-21

13.3.7 SSIO Control 2 Register (SSIOCON2) ............................. ................... ................. .13-23

13.3.8 SSIO Transmit Holding Buffer (SSIOTBUF) .........................................................13-24

13.3.9 SSIO Receive Holding Buffer (SSIORBUF) ..........................................................13-25

13.4 DESIGN CONSIDERATIONS .................................................................................... 13-25

13.5 PROGRAMMING CONSIDERATIONS...................................................................... 13-26

13.5.1 SSIO Example Code .............................................................................................13-26

CHAPTER 14

CHIP-SELECT UNIT

14.1 OVERVIEW ................................................................................................................. 14-1

14.2 CSU UPON RESET..................................................................................................... 14-2

14.3 CSU OPERATION....................................................................................................... 14-2

14.3.1 Defining a Channel’s Address Block .......................................................................14-2

14.3.2 System Management Mode Support ....................................................................14-10

14.3.3 Bus Cycle Length Control ................................................ ................... ................. .14-11

14.3.4 Bus Size Control ................................................................................................... 14-11

14.3.5 Overlapping Regions ............................................................................................14-11

14.4 REGISTER DEFINITIONS .. ....................................................................................... 14-13

14.4.1 Pin Configuration Register (PINCFG) ...................................................................14-15

14.4.2 Port 2 Configuration Register (P2CFG) ................................................................14-16

14.4.3 Chip-select Address Registers ..............................................................................14-17

14.4.4 Chip-select Mask Registers ..................................................................................14-19

14.5 DESIGN CONSIDERATIONS .................................................................................... 14-21

14.6 PROGRAMMING CONSIDERATIONS...................................................................... 14-22

14.6.1 Chip-Select Unit Code Example ............................................................................14-22

CHAPTER 15

REFRESH CONTROL UNIT

15.1 DYNAMIC MEMORY CONTROL................................................................................. 15-1

15.1.1 Refresh Methods .....................................................................................................15-1

15.2 REFRESH CONTROL UNIT OVERVIEW ................................................................... 15-2

15.2.1 RCU Signals ...........................................................................................................1 5-4

15.2.2 Refresh Intervals .....................................................................................................15-4

CONTENTS

15.2.3 Refresh Addresses ................................................................................................. 15-4

15.2.4 Bu s Arbitration ......... .. ..... ..... ... .. ..... .. ..... ... .... ... .. ..... ..... ... .... ... .. ..... ..... .. ... ..... .. ..... .. ...15-5

15.3 RCU OPERATION....................................................................................................... 15-5

15.4 REGISTER DEFINITIONS .. ......................................................................................... 15-6

15.4.1 Refresh Clock Interval Register (RFSCIR) . .. ...........................................................15-7

15.4.2 Refresh Control Register (RFSCON) ......................................................................15-8

15.4.3 Refresh Base Address Register (RFSBAD) ............................................................15-9

15.4.4 Refresh Address Register (RFSADD) ...................................................................15-10

15.5 DESIGN CONSIDERATIONS .................................................................................... 15-11

15.6 PROGRAMMING CONSIDERATIONS...................................................................... 15-14

15.6.1 Refresh Control Unit Example Code ..................................................................... 15-14

CHAPTER 16

INPUT/OUTPUT PORTS

16.1 OVERVIEW ................................................................................................................. 16-1

16.1.1 Port Fu nctio nality ....... ..... ........ .... ........ ....... ..... ....... ..... ....... ..... ........ .... ........ ....... .....16-2

16.2 REGISTER DEFINITIONS .. ......................................................................................... 16-6

16.2.1 Pin Configuration .............................................................................. .. ....................16-7

16.2.2 Initializati o n Se quence ..........................................................................................16-10

16.3 DESIGN CONSIDERATIONS .................................................................................... 16-10

16.3.1 Pin Status During and After Reset .............................. ...................... ................... .16-10

16.4 PROGRAMMING CONSIDERATIONS...................................................................... 16-11

16.4.1 I/O Ports Code Example .......................................................................................16-11

CHAPTER 17

WATCHDOG TIMER UNIT

17.1 OVERVIEW ................................................................................................................. 17-1

17.1.1 WDT Signals .. .........................................................................................................17-3

17.2 WATCHDOG TIMER UNIT OPERATION.................................................................... 17-3

17.2.1 Idle and Powerdown modes ....................................................................................17-4

17.2.2 General-purpose Timer Mode ... .. ............................................................................17-4

17.2.3 Software Watchdog Mode .......................................................................................1 7-5

17.2.4 Bus Monitor Mode ................................................................................................... 1 7-5

17.3 DISABLING THE WDT ................................................................................................ 17-6

17.4 REGISTER DEFINITIONS .. ......................................................................................... 17-7

17.5 DESIGN CONSIDERATIONS .................................................................................... 17-12

17.6 PROGRAMMING CONSIDERATIONS...................................................................... 17-12

17.6.1 Writing to the WDT Reload Registers (WDTRLDH and WDTRLDL) ....................17-12

17.6.2 Minimum Counter Reload Value ...........................................................................17-12

17.6.3 Watchdog Timer Unit Code Examples ..................................................................17-12

Intel386™ EX MICROPROCESSOR USER’S MANUAL

CHAPTER 18

JTAG TEST-LOGIC UNIT

18.1 OVERVIEW ................................................................................................................. 18-1

18.2 TEST-LOGIC UNIT OPERATION................................................................................ 18-3

18.2.1 Test Access Port (TAP) ..........................................................................................18-3

18.2.2 Test Access Port (TAP) Controller ..........................................................................18-4

18.2.3 Instruction Register (IR) .......................................................... ............ ................. ... 1 8-7

18.2.4 Data Registers ........................................................................................................18-8

18.3 TESTING................................................................................................................... 18-10

18.3.1 Identifying the Device ............................................................................................18-10

18.3.2 Bypassing Devices on a Board .............................................................................18-10

18.3.3 Sampling Device Operation and Preloading Data .................................................18-10

18.3.4 Testing the Interconnections (EXTEST) ................................................................18-10

18.3.5 Disabling the Output Drivers .................................................................................18-11

18.4 TIMING INFORMATION ............................................................................................ 18-12

18.5 DESIGN CONSIDERATIONS .................................................................................... 18-14

APPENDIX A

SIGNAL DESCRIPTIONS

APPENDIX B

COMPATIBILITY WITH THE PC/AT* ARCHITECTURE

B.1 HARDWARE DEPARTURES FROM PC/AT SYSTEM ARCHITECTURE................... B-1

B.1.1 DMA Unit .......................................................................... ...................................... B-1

B.1.2 Industry Standard Bus (ISA) Signals ...................................................................... B-2

B.1.3 Interrupt Control Unit .............................................................................................. B-4

B.1.4 SIO Units ................................................................................................................ B-4

B.1.5 CPU-only Reset ......................................................................................................B-4

B.1.6 HOLD, HLDA Pins ..................................................................................................B-4

B.1.7 Port B ...................................................................................................................... B-5

B.2 SOFTWARE CONSIDERATIONS FOR A PC/AT SYSTEM ARCHITECTURE............ B-5

B.2.1 Embedded Basic Input Outp ut System (BIOS) ... ............................. ....................... B-5

B.2.2 Embedded Disk Operating System (DOS) ................. ....... ............... ............ ........... B-5

B.2.3 Microsoft* Windows* .......................................... .....................................................B-5

APPENDIX C

EXAMPLE CODE HEADER FILES

C.1 REGISTER DEFINITIONS FOR CODE EXAMPLES ................................................... C-1

C.2 EXAMPLE CODE DEFINES......................................................................................... C-6

xii

CONTENTS

APPENDIX D

SYSTEM REGISTER QUICK REFERENCE

D.1 PERIPHERAL REGISTER ADDRESSES..................................................................... D-1

D.2 CLKPRS ....................................................................................................................... D-7

D.3 CS D.4 CS D.5 CS D.6 CS D.7 DLL

D.8 DMABSR .................................................................................................................... D-13

D.9 DMACFG.................................................................................................................... D-14

D.10 DMACHR.................................................................................................................... D-15

D.11 DMACMD1.................................................................................................................. D-16

D.12 DMACMD2.................................................................................................................. D-17

D.13 DMAGRPMSK ............................................................................................................ D-18

D.14 DMAIEN...................................................................................................................... D-19

D.15 DMAIS ........................................................................................................................ D-20

D.16 DMAMOD1 ................................................................................................................. D-21

D.17 DMAMOD2 ................................................................................................................. D-22

D.18 DMAMSK.................................................................................................................... D-23

D.19 DMA

D.20 DMAOVFE.................................................................................................................. D-25

D.21 DMASRR.................................................................................................................... D-26

D.22 DMASTS ..................................................................................................................... D-27

D.23 ICW1 (MASTER AND SLAVE) ................................................................................... D-28

D.24 ICW2 (MASTER AND SLAVE) ................................................................................... D-29

D.25 ICW3 (MASTER)......................................................................................................... D-29

D.26 ICW3 (SLAVE)............................................................................................................ D-30

D.27 ICW4 (MASTER AND SLAVE) ................................................................................... D-30

D.28 IDCODE...................................................................................................................... D-31

D.29 IER D.30 IIR

D.31 INTCFG ...................................................................................................................... D-34

D.32 IR. ............................................................................................................................... D-35

D.33 LCR D.34 LSR D.35 MCR D.36 MSR

ADH (UCSADH)........ ............................................................................................. D-8

ADL (UCSADL)...................................................................................................... D-9

MSKH (UCSMSKH)............................................................................................. D-10

MSKL (UCSMSKL) .............................................................................................. D-11

AND DLHn........................................................................................................ D-12

BYCn, DMAnREQn AND DMAnTARn.............................................................. D-24

............................................................................................................................ D-32

............................................................................................................................. D-33

........................................................................................................................... D-36

........................................................................................................................... D-37

.......................................................................................................................... D-38

.......................................................................................................................... D-39

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Intel386™ EX MICROPROCESSOR USER’S MANUAL

D.37 OCW1 (MASTER AND SLAVE).................................................................................. D-40

D.38 OCW2 (MASTER AND SLAVE).................................................................................. D-41

D.39 OCW3 (MASTER AND SLAVE).................................................................................. D-42

D.40 P1CFG ........................................................................................................................ D-43

D.41 P2CFG ........................................................................................................................ D-44

D.42 P3CFG ........................................................................................................................ D-45

D.43 PINCFG...................................................................................................................... D-46

D.44 P D.45 P D.46 P

D.47 POLL (MASTER AND SLAVE)................................................................................... D-49

D.48 PORT92. ..................................................................................................................... D-50

D.49 PWRCON ................................................................................................................... D-51

D.50 RBR

D.51 REMAPCFG ............................................................................................................... D-53

D.52 RFSADD..................................................................................................................... D-54

D.53 RFSBAD..................................................................................................................... D-54

D.54 RFSCIR ...................................................................................................................... D-55

D.55 RFSCON..................................................................................................................... D-55

D.56 SCR

D.57 SIOCFG...................................................................................................................... D-57

D.58 SSIOBAUD ................................................................................................................. D-58

D.59 SSIOCON1 ................................................................................................................. D-59

D.60 SSIOCON2 ................................................................................................................. D-60

D.61 SSIOCTR.................................................................................................................... D-61

D.62 SSIORBUF ................................................................................................................. D-61

D.63 SSIOTBUF.................................................................................................................. D-62

D.64 TBR

D.65 TMRCFG .................................................................................................................... D-63

D.66 TMRCON.................................................................................................................... D-64

D.67 TMR

D.68 UCSADH..................................................................................................................... D-67

D.69 UCSADL..................................................................................................................... D-67

D.70 UCSMSKH.................................................................................................................. D-67

D.71 UCSMSKL .................................................................................................................. D-67

D.72 WDTCNTH AND WDTCNTL....................................................................................... D-68

D.73 WDTRLDH AND WDTRLDL....................................................................................... D-69

D.74 WDTSTATUS.............................................................................................................. D-70

DIR......................................................................................................................... D-47

LTC......................................................................................................................... D-48

PIN ......................................................................................................................... D-48

n ..........................................................................................................................

.......................................................................................................................... D-56

........................................................................................................................... D-62

.......................................................................................................................... D-65

D-52

xiv

CONTENTS

APPENDIX E

INSTRUCTION SET SUMMARY

E.1 INSTRUCTIO N ENCODING AND CLOCK COUNT SUMMARY.................................. E-1

E.2 INSTRUCTIO N ENCODING ....................................................................................... E-22

E.2.1 32-bit Extensions of the Instruction Set ................................................................ E-23

E.2.2 Encoding of Instruction Fields ...............................................................................E-24

E.2.2.1 Encoding of Operand Length (w) Field .........................................................E-24

E.2.2.2 Encoding of the General Register (reg) Field ............................................. .. E-24

E.2.2.3 Encoding of the Segment Register (sreg) Field ............................................ E-25

E.2.2.4 Encoding of Address Mode .......................................................................... E-26

E.2.2.5 Encoding of Operation Direction (d) Field .. .................................................. E-30

E.2.2.6 Encoding of Sign-Extend (s) Field ................................................................E-30

E.2.2.7 Encoding of Conditional Test (tttn) Field .................................................... .. E-30

E.2.2.8 Encoding of Control or Debug or Test Regist er (eee) Field .... .. ................... E-31

GLOSSARY

INDEX

Intel386™ EX MICROPROCESSOR USER’S MANUAL

FIGURES

Figure Page

2-1 Intel386™ EX Embedded Processor Block Diagram ...................................................2-2

3-1 Instruction Pipelining ..... ............... ............ ............ ................. ............... ............ ............3-2

3-2 The Intel386™ CX Processo r Internal Block Diagram.................................................3-3

4-1 PC/AT I/O Address Space (10-bit Decode) . ................................................................. 4-3

4-2 Expanded I/O Address Space (16-bit Decode)............................................................4-4

4-3 Address Configuration Register (REMAPCFG)............................................................4-7

4-4 Setting the ESE Bit Code Example ..............................................................................4-8

4-5 DOS-Compatible Mode ..............................................................................................4-10

4-6 Example of Nonintrusive DOS-Compatible Mode ...................................................... 4-12

4-7 Enhanced DOS Mode ................................................................................................4-13

4-8 NonDOS Mode...........................................................................................................4-14

5-1 Peripheral and Pin Connections...................................................................................5-2

5-2 Configuration of DMA, Bus Arbiter, and Refresh Unit ...................................... ............ 5-5

5-3 DMA Configuration Register (DMACFG)......................................................................5-6

5-4 Interrupt Control Unit C onfigurati o n........................... .......... ....... .......... ....... .......... .......5-9

5-5 Interrupt Configuration Register (INTCFG).... .......................................................... ...5-10

5-6 Timer/Counter Unit Configuration...............................................................................5-12

5-7 Timer Configuration Register (TMRCFG) ...................................................................5-13

5-8 Serial I/O Unit 0 Configuration....................................................................................5-15

5-9 Serial I/O Unit 1 Configuration....................................................................................5-16

5-10 SIO and SSIO Configuration Register (SIOCFG) .......................................................5-17

5-11 SSIO Unit Configuration.............................................................................................5-18

5-12 Configuration of Chip-select Unit and Clock and Power Management Unit...............5-20

5-13 Core Configuration .....................................................................................................5-21

5-14 Port 92 Configuration Register (PORT92)..................................................................5-22

5-15 Pin Configuration Register (PINCFG).........................................................................5-24

5-16 Port 1 Configuration Register (P1CFG)......................................................................5-25

5-17 Port 2 Configuration Register (P2CFG)......................................................................5-26

5-18 Port 3 Configuration Register (P3CFG)......................................................................5-27

6-1 Basic External Bus Cycles............................................................................................6-6

6-2 Simplified Bus State Diagram (Does Not Include Address Pipelining or Hold states)..6-8

6-3 Ready Logic ...............................................................................................................6-11

6-4 Basic Internal and External Bus Cycles...................................................................... 6-12

6-5 Nonpipelined Address Read Cycles...........................................................................6-15

6-6 Nonpipelined Address Write Cycles ...........................................................................6-18

6-7 Complete Bus States (Including Pipelined Address)..................................................6-20

6-8 Pipelined Address Cycles...........................................................................................6-21

6-9 Interrupt Acknowledge Cycles. ...................................................................................6-25

6-10 Halt Cycle...................................................................................................................6-27

6-11 Basic Refresh Cycle...................................................................................................6-29

6-12 Refresh Cycle During HOLD/HLDA............................................................................6-30

6-13 16-bit Cycles to 8-bit Devices (Using BS8#)............................................................... 6-33

6-14 LOCK# Signal During Address Pipelining ..................................................................6-35

6-15 Intel386 EX Processor to Intel387 SX Math Coprocessor Interface...........................6-39

xvi

CONTENTS

FIGURES

Figure Page

6-16 Intel386 EX Processor to SRAM/FLASH Interface.....................................................6-41

6-17 Intel386 EX Processor to PSRAM Interface...............................................................6-42

6-18 Intel386 EX Processor to Paged DRAM Interface......................................................6-43

6-19 Intel386 EX Processor and Non-Paged DRAM Interface...........................................6-44

7-1 Standard SMI# .............................................................................................................7-5

7-2 SMIACT# Latency .......................................................................................................7-6

7-3 SMI# During HALT ......................................................................................................7-8

7-4 SMI# During I/O Instruction.................................................................... ................. ..... 7-9

7-5 SMI# Timing...............................................................................................................7-10

7-6 Interrupted SMI# Service............................................................................................7-11

7-7 HALT During SMM Handler........................................................................................ 7-12

8-1 Clock and Power Management Unit Connections........................................................8-2

8-2 Clock Synchronization..................................................................................................8-3

8-3 SMM Interaction with Idle and Powerdown Modes.......................................................8-5

8-4 Clock Prescale Register (CLKPRS).............................................................................8-7

8-5 Power Control Regist er (PWRCON).................................... .. .......................................8-8

8-6 Timing Diagram, Entering and Leaving Idle Mode.......................................................8-9

8-7 Timing Diagram, Entering and Leaving Powerdown Mode ........................................8-11

8-8 Reset Synchronization Circuit....................................................................................8-12

9-1 Interrupt Control Unit C onfigurati o n........................... .......... ....... .......... ....... .......... .......9-3

9-2 Methods for Changing the Default Interrupt Structure..................................................9-7

9-3 Interrupt Process – Master Request from Non-slave Source.....................................9-11

9-4 Interrupt Process – Slave Request . ............................................................................9-12

9-5 Interrupt Process – Master Request from Slave Source............................................9-13

9-6 Port 3 Configuration Register (P3CFG)......................................................................9-18

9-7 Interrupt Configuration Register (INTCFG).... .......................................................... ...9-19

9-8 Initializatio n Command Word 1 Register (ICW1)........................................................9-20

9-9 Initialization Command Word 2 Register (ICW2)........................................................9-21

9-10 Initialization Command Word 3 Register (ICW3 – Master).........................................9-22

9-11 Initialization Command Word 3 Register (ICW3 – Slave)........................................... 9-23

9-12 Initialization Command Word 4 Register (ICW4)........................................................9-24

9-13 Operation Command Word 1 (OCW1) .......................................................................9-25

9-14 Operation Command Word 2 (OCW2) .......................................................................9-26

9-15 Operation Command Word 3 (OCW3) .......................................................................9-27

9-16 Poll Status Byte (POLL) .............................................................................................9-28

9-17 Interrupt Acknowledge Cycle......................................................................................9-29

9-18 Spurious Interrupts.....................................................................................................9-30

9-19 Cascading External 82C59A Interrupt Controllers......................................................9-31

10-1 Timer/Counter Unit Signal Connections.....................................................................10-2

10-2 Mode 0 – Basic Operation..........................................................................................10-7

10-3 Mode 0 – Disabling the Count....................................................................................10-7

10-4 Mode 0 – Writing a New Count...................................................................................10-8

10-5 Mode 1 – Basic Operation..........................................................................................10-9

10-6 Mode 1 – Retriggering the One-shot..........................................................................10-9

xvii

Intel386™ EX MICROPROCESSOR USER’S MANUAL

FIGURES

Figure Page

10-7 Mode 1 – Writing a New Count.................................................................................10-10

10-8 Mode 2 – Basic Operation........................................................................................10-11

10-9 Mode 2 – Disabling the Count..................................................................................10-11

10-10 Mode 2 – Writing a New Count.................................................................................10-12

10-11 Mode 3 – Basic Operation (Even Count)................................................ ..................10-13

10-12 Mode 3 – Basic Operation (Odd Count)...................................................................10-14

10-13 Mode 3 – Disabling the Count..................................................................................10-14

10-14 Mode 3 – Writing a New Count (With a Trigger).......................................................10-15

10-15 Mode 3 – Writing a New C ount (Without a Trigger)..................................................10-15

10-16 Mode 4 – Basic Operation........................................................................................10-16

10-17 Mode 4 – Disabling the Count..................................................................................10-17

10-18 Mode 4 – Writing a New Count.................................................................................10-17

10-19 Mode 5 – Basic Operation........................................................................................10-18

10-20 Mode 5 – Retriggering the Strobe................... ......................................................... 10-19

10-21 Mode 5 – Writing a New Count Value ......................................................................10-19

10-22 Timer C onfiguration Register (TMRCFG).................................................................10-21

10-23 Port 3 Configuration Register (P3CFG).......................... ..........................................10-22

10-24 Pin Configuration Register (PINCFG).......................................................................10-23

10-25 Timer Control Register (TMRCON – Control Word Format).....................................10-25

10-26 Timer

10-27 Timer C ontrol Register (TMRCON – Counter-latch Format) ....................................10-28

10-28 Timer

10-29 Timer Co ntrol Register (TMRCON – Read-back Format). .......................................10-30

10-30 Timer

11-1 Serial I/O Unit 1 Configuration............. .......................................................................11-2

11-2 SIO 11-3 SIO 11-4 SIO 11-5 SIO 11-6 SIO

11-7 Pin Configuration Register (PINCFG).. .....................................................................11-17

11-8 Port 1 Configuration Register (P1CFG)....................................................................11-18

11-9 Port 2 Configuration Register (P2CFG)....................................................................11-19

11-10 Port 3 Configuration Register (P3CFG).......................... ..........................................11-20

11-11 SIO and SSIO Configuration Register (SIOCFG).....................................................11-21

11-12 Divisor Lat ch Registers (DLL 11-13 Transmit Buffer Register (TBR 11-14 Receive Buffer Register (RBR 11-15 Serial Line Control Register (LCR 11-16 Serial Line Status Register (LSR 11-17 Interrupt Enable Register (IER 11-18 Interrupt ID Register (IIR

11-19 Modem Control Signals – Diagnostic Mode Connections ........................................11-29

11-20 Modem Control Signals – Internal Connections.......................................................11-29

Baud-rate Generator Clock Sources.................................................................11-4

Transmitter ........................................................................................................11-7

Data Transmission Process Flow......................................................................11-8

Receiver............................................................................................................11-9

Data Reception Process Flow.........................................................................11-11

and DLHn) ...............................................................11-22

)..............................................................................11-23

)...............................................................................11-24

).........................................................................11-25

)...........................................................................11-26

)..............................................................................11-27

).......................................................................................11-28

xviii

CONTENTS

FIGURES

Figure Page

11-21 Modem Control Register (MCR 11-22 Modem Status Register (MSR 11-23 Scratch Pad Register (SCR

12-1 DMA Unit Block Diagram .. ..........................................................................................12-2

12-2 DMA Temporary Buffer Operation for a Read Transfer..............................................12-8

12-3 DMA Temporary Buffer Operation for A Write Transfer .............................................12-8

12-4 Start of a Two-cycle DMA Trans fe r Initi ated by DRQ

12-5 Changing the Priority of the DMA Channel and External Bus Requests..................12-10

12-6 Buffer Transfer Ended by an Expired Byte Count ....................................................12-11

12-7 Buffer Transfer Ended by the EOP# Input................................................................12-11

12-8 Single Data-transfer Mode with Single Buffer-transfer Mode...................................12-15

12-9 Single Data-transfer Mode with Autoinitialize Buffer-transfer Mode.........................12-16

12-10 Single Data-transfer Mode with Chaining Buffer-transfer Mode...............................12-17

12-11 Block Data-transfer Mode with Single Buffer-transfer Mode ....................................12-19

12-12 Block Data-transfer Mo de with Autoinitialize Buffer-tr ansfer Mode. .........................12-20

12-13 Buffer Transfer Suspended by the Deactivation of DRQ

12-14 Demand Data-transfer Mode with Single Buffer-transfer Mode................................12-22

12-15 Demand Data-transfer Mode with Autoinitialize Buffer-transfer Mode... ..................12-23

12-16 Demand Data-transfer Mode with Chaining Buffer-transfer Mode...........................12-24

12-17 Cascade Mode.........................................................................................................12-26

12-18 Pin Configuration Register (PINCFG).......................................................................12-31

12-19 DMA Configuration Register (DMACFG)..................................................................12-32

12-20 DMA Channel Address and Byte Count Registers

(DMA

REQn, DMAnTARn, DMAnBYCn).................................................................12-33

12-21 DMA Overflow Enable Register (DMAOVFE)...........................................................12-34

12-22 DMA Command 1 Register (DMACMD1).................................................................12-35

12-23 DMA Status Register (DMASTS)..............................................................................12-36

12-24 DMA Command 2 Register (DMACMD2).................................................................12-37

12-25 DMA Mode 1 Register (DMAMOD1) ........................................................................ 12-39

12-26 DMA Mode 2 Register (DMAMOD2) ........................................................................ 12-41

12-27 DMA Software Request Register (DMASRR – write format)....................................12-42

12-28 DMA Software R equest Register (DMASRR – read format)....................................12-43

12-29 DMA Channel Mask Register (DMAMSK)................................................................12-44

12-30 DMA Group Channel Mask Register (DMAGRPMSK).............................................12-45

12-31 DMA Bus Si ze Register (DMABSR) .........................................................................12-46

12-32 DMA Chaining Register (DMACHR).........................................................................12-47

12-33 DMA Interrupt Enable Register (DMAIEN)...............................................................12-48

12-34 DMA Interrupt Status Register (DMAIS)...................................................................12-49

13-1 Transmitter and Receiver in Master Mode .................................................................13-2

13-2 Transmitter in Master Mode, Receiver in Slave Mode................................................13-2

13-3 Transmitter in Slave Mode, Receiver in Master Mode................................................13-3

13-4 Transmitter and Receiver in Slave Mode...................................................................13-3

13-5 Clock Sources for the Baud-rate Generator.. ................. ...................... ................. ..... 13-5

13-6 SSIO Transmitter with Autotransmit Mode Enabled...................................................13-7

).............................................................................11-30

)...............................................................................11-31

)...................................................................................11-32

...............................................12-9

........................................12-21

xix

Intel386™ EX MICROPROCESSOR USER’S MANUAL

FIGURES

Figure Page

13-7 SSIO Transmitter with Autotransmit Mode Disabled..................................................13-8

13-8 Transmit Data by Polling............................................................................................13-9

13-9 Interrupt Service Routine for Transmitting Data Using Interrupts.............................13-10

13-10 Transmitter Master Mode, Single Word Transfer (Enabled when Clock is High)..... 13-11

13-11 Transmitter Master Mode, Single Word Transfer (Enabled when Clock is Low)......13-11

13-12 Re ceive Data by Polling ...........................................................................................13-13

13-13 Interrupt Service Routine for Receiving Data Using Interrupts................................. 13-14

13-14 Re ceiver Master Mode, Single Word Transfer .........................................................13-15

13-15 Pin Configuration Register (PINCFG).......................................................................13-17

13-16 SIO and SSIO Configuration Register (SIOCFG).....................................................13-18

13-17 Clock Prescale Register (CLKPRS) .........................................................................13-19

13-18 SSIO Baud-rate Control Register (SSIOBAUD).................................................... ... 13-20

13-19 SSIO B aud-rate Count Down Register (SSIOCTR)..................................................13-21

13-20 SSIO Control 1 Register (SSIOCON1)................................................. ................... . 13-22

13-21 SSIO Control 2 Register (SSIOCON2)................................................. ................... . 13-23

13-22 SSIO Transmit Holding Buffer (SSIOTBUF).............................................................13-24

13-23 SSIO R eceive Holding Buffer (SSIORBUF) .......................... ................................... 13-25

14-1 Channel Address Comparison Logic..........................................................................14-3

14-2 Determining a Channel’s Address Block Size............................................................14-4

14-3 Bus Cycle Length Adju stments for Overlapping Regions.........................................14-12

14-4 Pin Configuration Register (PINCFG).. .....................................................................14-15

14-5 Port 2 Configuration Register (P2CFG)....................................................................14-16

14-6 Chip-select High Address Register (CS 14-7 Chip-select Low Address Register (CS 14-8 Chip-select High Mask Registers (CS 14-9 Chip-select Low Mask Registers (CS

15-1 Refresh Control Unit Connections..............................................................................15-3

15-2 Refresh Clock Interval Register (RFSCIR).................................................................15-7

15-3 Refresh Control Register (RFSCON) .. .......................................................................15-8

15-4 Refresh Base Address Register (RFSBAD)...............................................................15-9

15-5 Refresh Address Register (RFSADD)...................................................................... 15-10

15-6 Connections to Ensure Refresh of All Rows in an 8-Bit Wide PSRAM Device ........15-11

15-7 RAS# Only Refresh Logic: Paged Mode..................................................................15-13

15-8 RAS# Only Refresh Logic: Non-Paged Mode. .........................................................15-14

16-1 I/O Port Block Diagram...............................................................................................16-2

16-2 Logic Diagram of a Bi-directional Port........................................................................16-3

16-3 Port 16-4 Port Direction Register (P 16-5 Port Data Latch Register (P 16-6 Port Pin State Register (P

17-1 Watchdog Timer Unit Connections............................................................................. 17-2

17-2 WDT Counter Value Registers (WDTCNTH and WDTCNTL).... ................................17-8

17-3 WDT Status Register (WDTSTATUS)........................................................................17-9

Configuration Register (PnCFG) ......................................................................16-7

DIR) ...................... ................................ ...........................16- 8

LTC)..............................................................................16-8

PIN) .......... ................................ .......................................16-9

ADH, UCSADH) .......................................14-17

ADL, UCSADL) .........................................14-18

MSKH, UCSMSKH).....................................14-19

MSKL, UCSMSKL).......................................14-20

CONTENTS

FIGURES

Figure Page

17-4 WDT Reload Value Registers (WDTRLDH and WDTRLDL)....................................17-10

17-5 Power Control Register (PWRCON).........................................................................17-11

18-1 Test Logic Unit Connections ......................................................................................18-2

18-2 TAP Controller (Finite-State Machine)......................................................... ..... ..... .. ...18-6

18-3 Instruction Register (IR)........... ............ ................. ............... ................. ............ ..........18-7

18-4 Identification Code Register (IDCODE).... ..................................................................18-8

18-5 Internal and External Timing for Loading the Instructi on Register............................18-12

18-6 Internal and External Timing for Loading a Data Register........................................18-13

B-1 Derivation of AEN Signal in a Typical PC/AT System ................................................. B-3

B-2 Derivation of AEN Signal for Intel386™ EX processor-based Systems......................B-3

E-1 General Instruction Format.......................................... ..............................................E-22

xxi

Intel386™ EX MICROPROCESSOR USER’S MANUAL

TABLES

Table Page

2-1 PC-compatible Peripherals...........................................................................................2-3

2-2 Embedded Application-specific Peripherals.................................................................2-4

4-1 Peripheral Register I/O Address Map in Slot 15 ... ........................................................4-5

4-2 Peripheral Register Addresses ...................................................................................4-15

5-1 Master’s IR3 Connections............................................................................................5-8

5-2 Master’s IR4 Connections............................................................................................5-8

5-3 Signal Pairs on Pins without a Multiplexer............................................................... ...5-23

5-4 Example Pin Configuration Registers......................................................................... 5-30

5-5 Example DMACFG Configuration Register................................................................5-31

5-6 Example TMRCFG Configuration Register. ...............................................................5-32

5-7 Example INTCFG Configuration Register ..................................................................5-33

5-8 Example SIOCFG Configuration Register..................................................................5-33

5-9 Pin Configuration Register Design Woksheet ............................................................5-34

5-10 DMACFG Register Design Worksheet.......................................................................5-35

5-11 TMRCFG Register Design Worksheet .......................................................................5-36

5-12 INTCFG Register Design Worksheet .........................................................................5-37

5-13 SIOCFG Register Design Worksheet.........................................................................5-37

6-1 Bus Interface Unit Signals............................................................................................6-3

6-2 Bus Status Definitions ........ ............ ................. ............... ............ ............ ................. ..... 6-5

6-3 Sequence of Nonaligned Bus Transfers.....................................................................6-10

7-1 CR0 Bits Cleared Upon Entering SMM ........................................................................7-3

7-2 SMM Processor State Initialization Values...................................................................7-4

7-3 Relative Priority of Exceptions and Interrupts...............................................................7-7

8-1 Clock and Power Management Register s ....................................................................8-6

8-2 Clock and Power Management Signals........................................................................8-6

9-1 82C59A Master and Slave Interrupt Sources...............................................................9-5

9-2 ICU Registers.............................................................................................................9-16

10-1 TCU Signals...............................................................................................................10-3

10-2 TCU Associated Registers.........................................................................................10-4

10-3 Operations Caused by GATE

10-4 GATEn Connection Options.....................................................................................10-20

10-5 Minimum and Maximum Init ial Counts......................................................................10-26

10-6 Results of Multiple Read-back Commands Without Reads......................................10-33

11-1 SIO Signals ................................................................................................................11-3

11-2 Maximum and Minimum Output Bit Rates............ ......................................................1 1-5

11-3 Divisor Values for Common Bit Rates........................................................................11-5

11-4 Status Signal Priorities and Sourc es. ....................................................................... 11-13

11-5 SIO Registers...........................................................................................................11-15

11-6 Access to Multiplexed Registers...............................................................................11-16

12-1 DMA Signals...............................................................................................................12-4

12-2 Operations Performed During Tr ansfer ......................................................................12-6

12-3 DMA Registers .........................................................................................................12-28

12-4 DMA Software Commands.......................................................................................12-50

13-1 SSIO Signals..............................................................................................................13-4

n...................................................................................10-6

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CONTENTS

TABLES

Table Page

13-2 Maximum and Minimum Baud-rate Output Frequencies............................................13-6

13-3 SSIO Registers.........................................................................................................13-16

14-1 CSU Signals.............................................................................................................14-13

14-2 CSU Registers..........................................................................................................14-14

15-1 RCU Signals...............................................................................................................15-4

15-2 RCU Registers ............................................................... ............................................15-6

16-1 Pin Multiplexing ..........................................................................................................16-5

16-2 I/O Port Registers.......... ........ .....................................................................................16-6

16-3 Control Register Valu es for I/O Port Pin Configurati o ns........ .......... ....... ........ ....... ..... 1 6-7

17-1 WDT Signals ..............................................................................................................17-3

17-2 WDT Registers...................................................................... .....................................17-7

18-1 Test Access Port Dedicated Pins...............................................................................18-3

18-2 TAP Controller State Descriptions ..............................................................................18-4

18-3 Example TAP Controller State Selections.................................................................. 18-5

18-4 Test-logic Unit Instructions.........................................................................................18-7

18-5 Boundary-scan Register Bit Assignments..................................................................18-9

A-1 Signal Description Abbreviations.................................................................................A-1

A-2 Description of Signals Available at the Device Pins.. .................................................. A-2

A-3 Pin State Abbreviations............................................................................................... A-8

A-4 Pin States After Reset and During Idle, Powerdown, and Hold...................................A-9

D-1 Peripheral Register Addresses....................................................................................D- 1

E-1 Instruction Set Summary.. ............................... ........................................................ .... E-2

E-2 Fields Within Instructions...........................................................................................E-23

E-3 Encoding of Operand Length (w) Field......................................................................E-24

E-4 Encoding of reg Field When w Field is not Present in Instruction............................. E-24

E-5 Encoding of reg Field When w Field is Present in Instruction...................................E-25

E-6 Encoding of the Segment Register (sreg) Field.........................................................E-25

E-7 Encoding of 16-bit Address Mode with “mod r/m” Byte.............................................E-27

E-8 Encoding of 32-bit Address Mode with “mod r/m” Byte (No s-i-b Byte Present)........E-28

E-9 Encoding of 32-bit Address Mode (“mod r/m” Byte and s-i-b Byte Present)..............E-29

E-10 Encoding of Operation Direction (d) Field.................................................................E-30

E-11 Encoding of Sign-Extend (s) Field............................................................................. E-30

E-12 Encoding of Conditional Test (tttn) Field.. ................................................................. E-30

E-13 When Interpreted as Control Regist er Fiel d ............ .. ..... ..... ..... .. ..... ..... ..... .. ..... ..... .... E-31

E-14 When Interpreted as Debug Register Field...............................................................E-31

E-15 When Interpreted as Test Register Field...................................................................E-31

xxiii

GUIDE TO THIS MANUAL

CHAPT ER 1

GUIDE TO THIS MANUAL

This manual describes the Intel386™ EX Embedded Processor. It is intended for use by hardware designers familiar wi th the pri nciples o f microprocess ors and wit h the Inte l386 pr ocessor arc hitecture.

This chapter is organized as follows:

• Manual Contents (see below )

• Notational Conventions (page 1-3 )

• Special Terminology (page 1-4)

• Related Documents (page 1-5)

• Electronic Support Systems (page 1-6)

• Technical Support (page 1-7)

• Product Literature (page 1-8)

1.1 MANUAL CONTENTS

This manual contains 1 8 chapters and 5 appendixe s, a glossar y, and an index. This section summarizes the contents of the remaining chapters and appendixes. The remainder of this chapter describes notational conventions and special terminology used throughou t th e manual and provides references to related documentation.

Chapter 2 — Architectur al Overvi ew — describes the device features and some potential applications.

Chapter 3 — Core Overview — describes the differences between this device and the Intel386 SX processor core.

Chapter 4 — System Register Organization — describes the organization of the sys tem registers, the I/O address space, address decoding, an d addressing modes.

Chapter 5 — Device Configuration — explains how to configure the device for various applications.

Chapter 6 — Bus Interface Unit — describes the bus interface logic, bus states, bus cycles, and instruction pipelining.

Chapter 7 — System Management Mode — describes Intel’s System Management Mode (SMM).

Chapter 8 — Clock and Power Management Unit — describes the clock generation circuitry, power manageme nt mo des, and system re se t logic.

1-1

™

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

Chapter 9 — Interrupt Control Unit — describes the interrupt sources and priority options and explains how to program the interrupt control unit.

Chapter 10 — Timer/Counter Unit — describes the time r/cou nters and thei r available co unt formats and operating modes.

Chapter 11 — Asynchronous Serial I/O (SIO) Unit — explains how to use the universal asynchronous receiver/transmitters (UARTs) to transmit and receive serial data.

Chapter 12 — DMA Controller — describes how the enhanced direct memory access controller allows internal and external devices to transfer data directly to and from the system and explains how bus control is arbitrat ed.

Chapter 13 — Synchronous Serial I/O (SSIO) Uni t — explains how to transmit an d receive data synchronously.

Chapter 14 — Chip-select Unit — explains how to use the chip-select channels to access various external memory and I/O devices.

Chapter 15 — Refresh Control Uni t — describes how the refresh control unit generates periodic refresh requests and refresh addresses to simplify the interface to dynamic memory devices.

Chapter 16 — Input/Output Ports — describes the general-purpose I/O ports and explains how to configure each pin to serve either as an I/O pin or as a pin controlled by an internal peripheral.

Chapter 17 — Watchdog Timer Unit — explains how to use the watchdog timer unit as a software watchdog, bus monitor, or general-purpose timer.

Chapter 18 — JTAG Test-logic Unit — des cribes t he i n dependent test-logic unit and expl ains how to test the device logic and board-level connections.

Appendix A — Signal Descriptions — describes the device pins and signals and lists pin states after a system reset and during powerdown, idle, and hold.

Appendix B — Com patib ility wi th P C/AT* Architecture — descri bes t he w ays in whic h the device is compatible with the standard PC/AT architecture and the ways in which it departs from the standard.

Appendix C — Example Code Header Files — contains the header files called by the code examples that are included in several chapters of this manual.

Appendix D — System Register Quick Referen ce — contains an alphabetical li st of registers. Appendix E — Instruction Set Summary — lists all instructions and their clock counts. Glossary — define s terms with spec ia l meaning used th r oughout this manual. Index — lists key topics with page number references.

1-2

GUIDE TO THIS MANUAL

1.2 NOTATIONAL CONV E NTI ONS

The following notations are used throughout this manual. # The pound symbol (#) appended to a signal name indicates that the signal

is active low.

Variables Variables a re shown in italics. Variables must be replaced with correct

values.

New Terms New terms are shown in italics. See the Glossary for a brief definition of

commonly used t erms.

Instructions Instruction mnemonics are shown in upper case. When you are

programming, instructions are not case sensitive. You may use either upper or lower case.

Numbers Hexadecima l numbers are represented b y a string of hexadecimal digits

followed by the character H. A zero prefix is added to numbers that begin with A through F. (For example, FF is shown as 0FF H.) Decimal and binary numbers are represented by their customary notations. (That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is added for clarity.)

Units of Measure The following abbreviations are used to represent units of measure:

A amps, amperes Gbyte gigabytes Kbyte kilobytes KΩ kilo-ohms mA milliamps, milliamperes Mbyte megabytes MHz megahertz ms milliseconds mW milliwatts ns nanoseconds pF picofarads W watts Vvolts

µA microamps, microamperes µF microfarads µs microseconds µW microwatts

1-3

+ 661 hidden pages

Intel 386 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

1.1 MANUAL CONTENTS

1.2 NOTATIONAL CONV E NTI ONS