Intel 5, 3400 Datasheet

Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Datasheet

January 2012

Document Number: 322169-004

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2 Datasheet

Contents

1Introduction............................................................................................................ 43

1.1 About This Manual............................................................................................. 43

1.2 Overview ......................................................................................................... 47

1.2.1 Capability Overview............................................................................. 49

1.3 Intel® 5 Series Chipset and Intel® 3400 Series Chipset SKU Definition ..................... 55

1.4 Reference Documents ........................................................................................ 57

2 Signal Description ................................................................................................... 59

2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 61

2.2 PCI Express* .................................................................................................... 61

2.3 Firmware Hub Interface...................................................................................... 62

2.4 PCI Interface .................................................................................................... 63

2.5 Serial ATA Interface........................................................................................... 65

2.6 LPC Interface.................................................................................................... 68

2.7 Interrupt Interface ............................................................................................ 68

2.8 USB Interface ................................................................................................... 69

2.9 Power Management Interface.............................................................................. 71

2.10 Processor Interface............................................................................................ 74

2.11 SMBus Interface................................................................................................ 74

2.12 System Management Interface............................................................................ 75

2.13 Real Time Clock Interface................................................................................... 75

2.14 Miscellaneous Signals ........................................................................................ 76

2.15 Intel® High Definition Audio Link ......................................................................... 77

2.16 Controller Link .................................................................................................. 78

2.17 Serial Peripheral Interface (SPI) .......................................................................... 78

2.18 Intel® Quiet System Technology and Thermal Reporting......................................... 79

2.19 JTAG Signals .................................................................................................... 80

2.20 Clock Signals .................................................................................................... 80

2.21 LVDS Signals (Mobile only)................................................................................. 82

2.22 Analog Display /CRT DAC Signals ........................................................................ 83

2.23 Intel® Flexible Display Interface (FDI).................................................................. 84

2.24 Digital Display Signals........................................................................................ 84

2.25 General Purpose I/O Signals ............................................................................... 87

2.26 Manageability Signals ........................................................................................ 90

2.27 Power and Ground Signals.................................................................................. 91

2.28 Pin Straps ........................................................................................................ 93

2.28.1 Functional Straps ................................................................................ 93

2.28.2 External RTC Circuitry.......................................................................... 97

3PCH Pin States......................................................................................................... 99

3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 99

3.2 Output and I/O Signals Planes and States........................................................... 101

3.3 Power Planes for Input Signals .......................................................................... 112

4System Clocks....................................................................................................... 119

5 Functional Description........................................................................................... 123

5.1 DMI-to-PCI Bridge (D30:F0) ............................................................................. 123

5.1.1 PCI Bus Interface .............................................................................. 123

5.1.2 PCI Bridge As an Initiator ................................................................... 123

5.1.3 Parity Error Detection and Generation .................................................. 125

5.1.4 PCIRST# .......................................................................................... 126

5.1.5 Peer Cycles ...................................................................................... 126

5.1.6 PCI-to-PCI Bridge Model..................................................................... 127

5.1.7 IDSEL to Device Number Mapping ....................................................... 127

5.1.2.1 Memory Reads and Writes .................................................... 124

5.1.2.2 I/O Reads and Writes .......................................................... 124

5.1.2.3 Configuration Reads and Writes ............................................ 124

5.1.2.4 Locked Cycles..................................................................... 124

5.1.2.5 Target / Master Aborts......................................................... 124

5.1.2.6 Secondary Master Latency Timer........................................... 124

5.1.2.7 Dual Address Cycle (DAC) .................................................... 124

5.1.2.8 Memory and I/O Decode to PCI............................................. 125

Datasheet 3

5.1.8 Standard PCI Bus Configuration Mechanism...........................................127

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) .....................................127

5.2.1 Interrupt Generation ..........................................................................128

5.2.2 Power Management............................................................................128

5.2.2.1 S3/S4/S5 Support ...............................................................128

5.2.2.2 Resuming from Suspended State ...........................................129

5.2.2.3 Device Initiated PM_PME Message..........................................129

5.2.2.4 SMI/SCI Generation .............................................................129

5.2.3 SERR# Generation ............................................................................. 130

5.2.4 Hot-Plug ...........................................................................................130

5.2.4.1 Presence Detection ..............................................................130

5.2.4.2 Message Generation............................................................. 131

5.2.4.3 Attention Button Detection....................................................131

5.2.4.4 SMI/SCI Generation .............................................................132

5.3 Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 132

5.3.1 GbE PCI Express* Bus Interface...........................................................134

5.3.1.1 Transaction Layer ................................................................134

5.3.1.2 Data Alignment ...................................................................134

5.3.1.3 Configuration Request Retry Status........................................134

5.3.2 Error Events and Error Reporting .........................................................135

5.3.2.1 Data Parity Error .................................................................135

5.3.2.2 Completion with Unsuccessful Completion Status .....................135

5.3.3 Ethernet Interface .............................................................................135

5.3.3.1 Intel® 5 Series Chipset and Intel® 3400 Series Chipset

82577/82578 PHY Interface .................................................. 135

5.3.4 PCI Power Management ......................................................................136

5.3.4.1 Wake Up ............................................................................136

5.3.5 Configurable LEDs .............................................................................138

5.3.6 Function Level Reset Support (FLR)......................................................138

5.3.6.1 FLR Steps ...........................................................................139

5.4 LPC Bridge (with System and Management Functions) (D31:F0).............................139

5.4.1 LPC Interface ....................................................................................139

5.4.1.1 LPC Cycle Types ..................................................................140

5.4.1.2 Start Field Definition ............................................................ 141

5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR).................................141

5.4.1.4 Size ...................................................................................141

5.4.1.5 SYNC .................................................................................142

5.4.1.6 SYNC Time-Out ...................................................................142

5.4.1.7 SYNC Error Indication...........................................................142

5.4.1.8 LFRAME# Usage ..................................................................142

5.4.1.9 I/O Cycles .......................................................................... 143

5.4.1.10 Bus Master Cycles................................................................143

5.4.1.11 LPC Power Management .......................................................143

5.4.1.12 Configuration and PCH Implications........................................143

5.5 DMA Operation (D31:F0) ..................................................................................144

5.5.1 Channel Priority.................................................................................144

5.5.1.1 Fixed Priority ......................................................................144

5.5.1.2 Rotating Priority ..................................................................145

5.5.2 Address Compatibility Mode ................................................................145

5.5.3 Summary of DMA Transfer Sizes ..........................................................145

5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count

by Words............................................................................145

5.5.4 Autoinitialize .....................................................................................146

5.5.5 Software Commands ..........................................................................146

5.6 LPC DMA ........................................................................................................147

5.6.1 Asserting DMA Requests ..................................................................... 147

5.6.2 Abandoning DMA Requests.................................................................. 148

5.6.3 General Flow of DMA Transfers ............................................................ 148

5.6.4 Terminal Count.................................................................................. 148

5.6.5 Verify Mode ......................................................................................149

5.6.6 DMA Request De-assertion..................................................................149

5.6.7 SYNC Field / LDRQ# Rules ..................................................................150

5.7 8254 Timers (D31:F0) ...................................................................................... 150

5.7.1 Timer Programming ........................................................................... 151

5.7.2 Reading from the Interval Timer ..........................................................152

5.7.2.1 Simple Read .......................................................................152

5.7.2.2 Counter Latch Command ...................................................... 152

4 Datasheet

5.8 8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 153

5.7.2.3 Read Back Command........................................................... 152

5.8.1 Interrupt Handling............................................................................. 154

5.8.1.1 Generating Interrupts .......................................................... 154

5.8.1.2 Acknowledging Interrupts..................................................... 154

5.8.1.3 Hardware/Software Interrupt Sequence ................................. 155

5.8.2 Initialization Command Words (ICWx).................................................. 155

5.8.2.1 ICW1................................................................................. 155

5.8.2.2 ICW2................................................................................. 156

5.8.2.3 ICW3................................................................................. 156

5.8.2.4 ICW4................................................................................. 156

5.8.3 Operation Command Words (OCW)...................................................... 156

5.8.4 Modes of Operation ........................................................................... 156

5.8.4.1 Fully Nested Mode ............................................................... 156

5.8.4.2 Special Fully-Nested Mode.................................................... 157

5.8.4.3 Automatic Rotation Mode (Equal Priority Devices).................... 157

5.8.4.4 Specific Rotation Mode (Specific Priority) ................................ 157

5.8.4.5 Poll Mode ........................................................................... 157

5.8.4.6 Edge and Level Triggered Mode............................................. 158

5.8.4.7 End of Interrupt (EOI) Operations ......................................... 158

5.8.4.8 Normal End of Interrupt ....................................................... 158

5.8.4.9 Automatic End of Interrupt Mode........................................... 158

5.8.5 Masking Interrupts ............................................................................ 159

5.8.5.1 Masking on an Individual Interrupt Request ............................ 159

5.8.5.2 Special Mask Mode .............................................................. 159

5.8.6 Steering PCI Interrupts ...................................................................... 159

5.9 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 160

5.9.1 Interrupt Handling............................................................................. 160

5.9.2 Interrupt Mapping ............................................................................. 160

5.9.3 PCI / PCI Express* Message-Based Interrupts ....................................... 161

5.9.4 IOxAPIC Address Remapping .............................................................. 161

5.9.5 External Interrupt Controller Support ................................................... 161

5.10 Serial Interrupt (D31:F0) ................................................................................. 162

5.10.1 Start Frame...................................................................................... 162

5.10.2 Data Frames..................................................................................... 163

5.10.3 Stop Frame ...................................................................................... 163

5.10.4 Specific Interrupts Not Supported Using SERIRQ ................................... 163

5.10.5 Data Frame Format ........................................................................... 164

5.11 Real Time Clock (D31:F0)................................................................................. 165

5.11.1 Update Cycles................................................................................... 165

5.11.2 Interrupts ........................................................................................ 166

5.11.3 Lockable RAM Ranges ........................................................................ 166

5.11.4 Century Rollover ............................................................................... 166

5.11.5 Clearing Battery-Backed RTC RAM ....................................................... 166

5.12 Processor Interface (D31:F0) ............................................................................ 168

5.12.1 Processor Interface Signals and VLW Messages ..................................... 168

5.12.1.1 A20M# (Mask A20) / A20GATE ............................................. 168

5.12.1.2 INIT (Initialization) .............................................................. 169

5.12.1.3 FERR# (Numeric Coprocessor Error) ...................................... 169

5.12.1.4 NMI (Non-Maskable Interrupt) .............................................. 170

5.12.1.5 Processor Power Good (PROCPWRGD).................................... 170

5.12.2 Dual-Processor Issues........................................................................ 170

5.12.2.1 Usage Differences ............................................................... 170

5.12.3 Virtual Legacy Wire (VLW) Messages.................................................... 170

5.13 Power Management (D31:F0) ........................................................................... 171

5.13.1 Features .......................................................................................... 171

5.13.2 PCH and System Power States ............................................................ 171

5.13.3 System Power Planes......................................................................... 173

5.13.4 SMI#/SCI Generation ........................................................................ 173

5.13.4.1 PCI Express* SCI ................................................................ 176

5.13.4.2 PCI Express* Hot-Plug ......................................................... 176

5.13.5 C-States .......................................................................................... 176

5.13.6 Dynamic PCI Clock Control (Mobile Only).............................................. 176

5.13.6.1 Conditions for Checking the PCI Clock.................................... 177

5.13.6.2 Conditions for Maintaining the PCI Clock................................. 177

5.13.6.3 Conditions for Stopping the PCI Clock .................................... 177

5.13.6.4 Conditions for Re-Starting the PCI Clock................................. 177

Datasheet 5

5.13.7 Sleep States .....................................................................................178

5.13.6.5 LPC Devices and CLKRUN# ...................................................178

5.13.7.1 Sleep State Overview...........................................................178

5.13.7.2 Initiating Sleep State ...........................................................178

5.13.7.3 Exiting Sleep States .............................................................179

5.13.7.4 PCI Express* WAKE# Signal and PME Event Message ............... 181

5.13.7.5 Sx-G3-Sx, Handling Power Failures ........................................181

5.13.8 Event Input Signals and Their Usage ....................................................181

5.13.8.1 PWRBTN# (Power Button) ....................................................182

5.13.8.2 RI# (Ring Indicator) ............................................................183

5.13.8.3 PME# (PCI Power Management Event)....................................183

5.13.8.4 SYS_RESET# Signal.............................................................183

5.13.8.5 THRMTRIP# Signal...............................................................183

5.13.9 ALT Access Mode ............................................................................... 184

5.13.9.1 Write Only Registers with Read Paths in ALT Access Mode ......... 185

5.13.9.2 PIC Reserved Bits ................................................................187

5.13.9.3 Read Only Registers with Write Paths in ALT Access Mode ......... 187

5.13.10 System Power Supplies, Planes, and Signals..........................................187

5.13.10.1 Power Plane Control with SLP_S3#,

SLP_S4#, SLP_S5#, SLP_M# and SLP_LAN# .......................... 187

5.13.10.2 SLP_S4# and Suspend-To-RAM Sequencing ............................ 188

5.13.10.3 PWROK Signal..................................................................... 188

5.13.10.4 BATLOW# (Battery Low) (Mobile Only) ...................................188

5.13.10.5 SLP_LAN# Pin Behavior........................................................189

5.13.10.6 RTCRST# and SRTCRST# .....................................................189

5.13.11 Clock Generators ............................................................................... 189

5.13.12 Legacy Power Management Theory of Operation ....................................190

5.13.12.1 APM Power Management (Desktop Only).................................190

5.13.12.2 Mobile APM Power Management (Mobile Only) ......................... 190

5.13.13 Reset Behavior..................................................................................190

5.14 System Management (D31:F0) ..........................................................................192

5.14.1 Theory of Operation ........................................................................... 193

5.14.1.1 Detecting a System Lockup...................................................193

5.14.1.2 Handling an Intruder............................................................193

5.14.1.3 Detecting Improper Flash Programming..................................193

5.14.1.4 Heartbeat and Event Reporting using SMLink/SMBus ................ 193

5.14.2 TCO Modes .......................................................................................194

5.14.2.1 TCO Legacy/Compatible Mode ............................................... 194

5.14.2.2 Advanced TCO Mode ............................................................195

5.15 General Purpose I/O (D31:F0)...........................................................................197

5.15.1 Power Wells ......................................................................................197

5.15.2 SMI# SCI and NMI Routing .................................................................197

5.15.3 Triggering.........................................................................................197

5.15.4 GPIO Registers Lockdown ................................................................... 197

5.15.5 Serial POST Codes Over GPIO..............................................................198

5.15.5.1 Theory of operation .............................................................198

5.15.5.2 Serial Message Format .........................................................199

5.16 SATA Host Controller (D31:F2, F5).....................................................................200

5.16.1 SATA Feature Support........................................................................201

5.16.2 Theory of Operation ........................................................................... 202

5.16.2.1 Standard ATA Emulation.......................................................202

5.16.2.2 48-Bit LBA Operation ...........................................................202

5.16.3 SATA Swap Bay Support.....................................................................202

5.16.4 Hot Plug Operation.............................................................................202

5.16.4.1 Low Power Device Presence Detection ....................................202

5.16.5 Function Level Reset Support (FLR)......................................................203

5.16.6 Intel

5.16.5.1 FLR Steps ...........................................................................203

®

Rapid Storage Technology Configuration...................................... 203

5.16.6.1 Intel® Rapid Storage Manager RAID Option ROM ..................... 204

5.16.7 Power Management Operation.............................................................204

5.16.7.1 Power State Mappings ..........................................................204

5.16.7.2 Power State Transitions........................................................205

5.16.7.3 SMI Trapping (APM)............................................................. 206

5.16.8 SATA Device Presence........................................................................206

5.16.9 SATA LED .........................................................................................207

5.16.10 AHCI Operation .................................................................................207

5.16.11 SGPIO Signals................................................................................... 207

6 Datasheet

5.16.11.1 Mechanism......................................................................... 207

5.16.11.2 Message Format.................................................................. 208

5.16.11.3 LED Message Type .............................................................. 209

5.16.11.4 SGPIO Waveform ................................................................ 210

5.16.12 External SATA................................................................................... 211

5.17 High Precision Event Timers.............................................................................. 211

5.17.1 Timer Accuracy ................................................................................. 211

5.17.2 Interrupt Mapping ............................................................................. 212

5.17.3 Periodic vs. Non-Periodic Modes .......................................................... 212

5.17.4 Enabling the Timers........................................................................... 213

5.17.5 Interrupt Levels ................................................................................ 213

5.17.6 Handling Interrupts ........................................................................... 214

5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors........................... 214

5.18 USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 215

5.18.1 EHC Initialization............................................................................... 215

5.18.1.1 BIOS Initialization ............................................................... 215

5.18.1.2 Driver Initialization.............................................................. 215

5.18.1.3 EHC Resets ........................................................................ 215

5.18.2 Data Structures in Main Memory ......................................................... 215

5.18.3 USB 2.0 Enhanced Host Controller DMA................................................ 216

5.18.4 Data Encoding and Bit Stuffing............................................................ 216

5.18.5 Packet Formats ................................................................................. 216

5.18.6 USB 2.0 Interrupts and Error Conditions............................................... 216

5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads ............................ 217

5.18.7 USB 2.0 Power Management............................................................... 217

5.18.7.1 Pause Feature..................................................................... 217

5.18.7.2 Suspend Feature................................................................. 217

5.18.7.3 ACPI Device States.............................................................. 218

5.18.7.4 ACPI System States............................................................. 218

5.18.8 USB 2.0 Legacy Keyboard Operation .................................................... 218

5.18.9 USB 2.0 Based Debug Port ................................................................. 219

5.18.9.1 Theory of Operation............................................................ 219

5.18.10 EHCI Caching ................................................................................... 224

5.18.11 USB Pre-Fetch Based Pause ................................................................ 224

5.18.12 Function Level Reset Support (FLR) ..................................................... 224

5.18.12.1 FLR Steps .......................................................................... 224

5.18.13 USB Overcurrent Protection ................................................................ 225

5.19 Integrated USB 2.0 Rate Matching Hub .............................................................. 226

5.19.1 Overview ......................................................................................... 226

5.19.2 Architecture ..................................................................................... 226

5.20 SMBus Controller (D31:F3)............................................................................... 227

5.20.1 Host Controller ................................................................................. 227

5.20.1.1 Command Protocols............................................................. 228

5.20.2 Bus Arbitration.................................................................................. 231

5.20.3 Bus Timing ....................................................................................... 232

5.20.3.1 Clock Stretching.................................................................. 232

5.20.3.2 Bus Time Out (The PCH as SMBus Master).............................. 232

5.20.4 Interrupts / SMI#.............................................................................. 232

5.20.5 SMBALERT# ..................................................................................... 233

5.20.6 SMBus CRC Generation and Checking................................................... 233

5.20.7 SMBus Slave Interface ....................................................................... 234

5.20.7.1 Format of Slave Write Cycle.................................................. 234

5.20.7.2 Format of Read Command.................................................... 236

5.20.7.3 Slave Read of RTC Time Bytes .............................................. 238

5.20.7.4 Format of Host Notify Command ........................................... 238

5.21 Thermal Management ...................................................................................... 240

5.21.1 Thermal Sensor ................................................................................ 240

5.21.1.1 Internal Thermal Sensor Operation........................................ 240

5.21.2 Thermal Reporting Over System Management Link 1 Interface (SMLink1) . 241

5.21.2.1 Supported Addresses........................................................... 242

5.21.2.2 I

2

C Write Commands to the Intel® ME ................................... 243

5.21.2.3 Block Read Command .......................................................... 243

5.21.2.4 Read Data Format ............................................................... 245

5.21.2.5 Thermal Data Update Rate ................................................... 246

5.21.2.6 Temperature Comparator and Alert ....................................... 247

5.21.2.7 BIOS Set Up....................................................................... 248

5.21.2.8 SMBus Rules....................................................................... 249

Datasheet 7

5.22 Intel® High Definition Audio Overview (D27:F0)...................................................252

5.21.2.9 Case for Considerations........................................................250

5.22.1 Intel® High Definition Audio Docking (Mobile Only) ................................ 252

5.22.1.1 Dock Sequence ...................................................................252

5.22.1.2 Exiting D3/CRST# when Docked ............................................253

5.22.1.3 Cold Boot/Resume from S3 When Docked ...............................254

5.22.1.4 Undock Sequence ................................................................254

5.22.1.5 Normal Undock....................................................................254

5.22.1.6 Surprise Undock ..................................................................255

5.22.1.7 Interaction Between Dock/Undock and Power Management

States................................................................................255

5.22.1.8 Relationship between HDA_DOCK_RST# and HDA_RST# .......... 255

5.23 Intel® Active Management Technology 6.0 (Intel® AMT) .......................................256

5.23.1 Intel® AMT6.x and ASF 2.0 Features ....................................................257

5.23.2 Intel® AMT Requirements ................................................................... 257

5.24 Serial Peripheral Interface (SPI) ........................................................................258

5.24.1 SPI Supported Feature Overview ......................................................... 258

5.24.1.1 Non-Descriptor Mode ...........................................................258

5.24.1.2 Descriptor Mode ..................................................................258

5.24.1.3 Device Partitioning...............................................................260

5.24.2 Flash Descriptor ................................................................................260

5.24.2.1 Descriptor Master Region......................................................262

5.24.3 Flash Access .....................................................................................263

5.24.3.1 Direct Access Security ..........................................................263

5.24.3.2 Register Access Security.......................................................263

5.24.4 Serial Flash Device Compatibility Requirements .....................................264

5.24.4.1 PCH SPI Based BIOS Requirements........................................264

5.24.4.2 Integrated LAN Firmware SPI Flash Requirements....................264

5.24.4.3 Intel® Management Engine Firmware SPI Flash Requirements ...265

5.24.4.4 Hardware Sequencing Requirements ......................................265

5.24.5 Multiple Page Write Usage Model.......................................................... 266

5.24.5.1 Soft Flash Protection ............................................................266

5.24.5.2 BIOS Range Write Protection.................................................267

5.24.5.3 SMI# Based Global Write Protection .......................................267

5.24.6 Flash Device Configurations ................................................................267

5.24.7 SPI Flash Device Recommended Pinout.................................................267

5.24.8 Serial Flash Device Package ................................................................268

5.24.8.1 Common Footprint Usage Model ............................................268

5.24.8.2 Serial Flash Device Package Recommendations ........................ 268

5.25 Intel® Quiet System Technology (Intel® QST) (Desktop Only) ............................... 269

5.25.1 PWM Outputs .................................................................................... 269

5.25.2 TACH Inputs .....................................................................................269

5.26 Feature Capability Mechanism ...........................................................................269

5.27 PCH Display Interfaces and Intel® Flexible Display Interconnect.............................270

5.27.1 Analog Display Interface Characteristics................................................ 270

5.27.1.1 Integrated RAMDAC .............................................................271

5.27.1.2 DDC (Display Data Channel) .................................................271

5.27.2 Digital Display Interfaces ....................................................................271

5.27.2.1 LVDS (Mobile only) ..............................................................271

5.27.2.2 LVDS Pair States .................................................................272

5.27.2.3 Single Channel versus Dual Channel Mode .............................. 273

5.27.2.4 Panel Power Sequencing.......................................................273

5.27.2.5 LVDS DDC ..........................................................................274

5.27.2.6 High Definition Multimedia Interface .......................................274

5.27.2.7 Digital Video Interface (DVI) .................................................275

5.27.2.8 Display Port* ......................................................................275

5.27.2.9 Embedded DisplayPort..........................................................275

5.27.2.10 DisplayPort Aux Channel.......................................................276

5.27.2.11 DisplayPort Hot-Plug Detect (HPD)......................................... 276

5.27.2.12 Integrated Audio over HDMI and DisplayPort ........................... 276

5.27.2.13 Serial Digital Video Out (SDVO) .............................................276

5.27.2.14 Control Bus.........................................................................277

5.27.3 Mapping of Digital Display Interface Signals ..........................................278

5.27.4 Multiple Display Configurations ............................................................279

5.27.5 High-bandwidth Digital Content Protection (HDCP) ................................. 279

5.27.6 Intel

®

Flexible Display Interconnect .....................................................280

5.28 Intel® Virtualization Technology ........................................................................ 280

8 Datasheet

5.28.1 Intel® VT-d Objectives....................................................................... 280

5.28.2 Intel® VT-d Features Supported .......................................................... 280

5.28.3 Support for Function Level Reset (FLR) in Intel® 5 Series

Chipset and Intel® 3400 Series Chipset................................................ 281

5.28.4 Virtualization Support for PCH’s IOxAPIC .............................................. 281

5.28.5 Virtualization Support for High Precision Event Timer (HPET)................... 281

5.29 Intel® 5 Series Chipset and Intel® 3400 Series Chipset Platform Clocks.................. 282

5.29.1 Platform Clocking Requirements.......................................................... 282

6 Ballout Definition................................................................................................... 283

6.1 PCH Desktop Ballout ........................................................................................ 283

6.2 PCH Ballout Mobile Ballout................................................................................ 294

6.3 PCH Ballout Small Form Factor Ballout ............................................................... 306

7 Package Information ............................................................................................. 319

7.1 PCH package (Desktop Only) ............................................................................ 319

7.2 PCH package (Mobile Only)............................................................................... 321

7.3 PCH package (Mobile SFF Only)......................................................................... 323

8 Electrical Characteristics ....................................................................................... 325

8.1 Thermal Specifications ..................................................................................... 325

8.1.1 Desktop Storage Specifications and Thermal Design Power (TDP) ............ 325

8.1.2 Mobile Storage Specifications and Thermal Design Power (TDP)............... 325

8.2 Absolute Maximum and Minimum Ratings ........................................................... 326

8.3 Intel® 5 Series Chipset and Intel® 3400 Series Chipset Power Supply range ........... 327

8.4 General DC Characteristics ............................................................................... 327

8.5 Display DC Characteristics ................................................................................ 340

8.6 AC Characteristics ........................................................................................... 342

8.7 Power Sequencing and Reset Signal Timings ....................................................... 360

8.8 Power Management Timing Diagrams................................................................. 363

8.9 AC Timing Diagrams ........................................................................................ 366

9 Register and Memory Mapping............................................................................... 377

9.1 PCI Devices and Functions................................................................................ 378

9.2 PCI Configuration Map ..................................................................................... 379

9.3 I/O Map ......................................................................................................... 379

9.3.1 Fixed I/O Address Ranges .................................................................. 379

9.3.2 Variable I/O Decode Ranges ............................................................... 382

9.4 Memory Map................................................................................................... 383

9.4.1 Boot-Block Update Scheme................................................................. 385

10 Chipset Configuration Registers............................................................................. 387

10.1 Chipset Configuration Registers (Memory Space)................................................. 387

10.1.1 V0CTL—Virtual Channel 0 Resource Control Register .............................. 390

10.1.2 V0STS—Virtual Channel 0 Resource Status Register ............................... 390

10.1.3 V1CTL—Virtual Channel 1 Resource Control Register .............................. 391

10.1.4 V1STS—Virtual Channel 1 Resource Status Register ............................... 391

10.1.5 CIR0—Chipset Initialization Register 0.................................................. 391

10.1.6 CIR1—Chipset Initialization Register 1.................................................. 392

10.1.7 REC—Root Error Command Register .................................................... 392

10.1.8 ILCL—Internal Link Capabilities List Register ......................................... 392

10.1.9 LCAP—Link Capabilities Register .......................................................... 393

10.1.10 LCTL—Link Control Register................................................................ 393

10.1.11 LSTS—Link Status Register................................................................. 394

10.1.12 BCR—Backbone Configuration Register................................................. 394

10.1.13 RPC—Root Port Configuration Register ................................................. 394

10.1.14 DMIC—DMI Control Register ............................................................... 396

10.1.15 RPFN—Root Port Function Number and Hide for PCI

Express* Root Ports Register .............................................................. 396

10.1.16 FLRSTAT—FLR Pending Status Register ................................................ 397

10.1.17 CIR5—Chipset Initialization Register 5.................................................. 398

10.1.18 TRSR—Trap Status Register................................................................ 398

10.1.19 TRCR—Trapped Cycle Register ............................................................ 398

10.1.20 TWDR—Trapped Write Data Register.................................................... 399

10.1.21 IOTRn—I/O Trap Register (0–3) .......................................................... 399

10.1.22 DMC—DMI Miscellaneous Control Register ............................................ 400

10.1.23 CIR6—Chipset Initialization Register 6.................................................. 400

10.1.24 DMC2—DMI Miscellaneous Control Register 2........................................ 400

Datasheet 9

10.1.25 TCTL—TCO Configuration Register........................................................401

10.1.26 D31IP—Device 31 Interrupt Pin Register ...............................................402

10.1.27 D30IP—Device 30 Interrupt Pin Register ...............................................403

10.1.28 D29IP—Device 29 Interrupt Pin Register ...............................................403

10.1.29 D28IP—Device 28 Interrupt Pin Register ...............................................404

10.1.30 D27IP—Device 27 Interrupt Pin Register ...............................................405

10.1.31 D26IP—Device 26 Interrupt Pin Register ...............................................406

10.1.32 D25IP—Device 25 Interrupt Pin Register ...............................................406

10.1.33 D22IP—Device 22 Interrupt Pin Register ...............................................407

10.1.34 D31IR—Device 31 Interrupt Route Register...........................................407

10.1.35 D30IR—Device 30 Interrupt Route Register...........................................408

10.1.36 D29IR—Device 29 Interrupt Route Register...........................................409

10.1.37 D28IR—Device 28 Interrupt Route Register...........................................410

10.1.38 D27IR—Device 27 Interrupt Route Register...........................................411

10.1.39 D26IR—Device 26 Interrupt Route Register...........................................412

10.1.40 D25IR—Device 25 Interrupt Route Register...........................................413

10.1.41 D24IR—Device 24 Interrupt Route Register...........................................414

10.1.42 D22IR—Device 22 Interrupt Route Register...........................................415

10.1.43 OIC—Other Interrupt Control Register ..................................................416

10.1.44 PRSTS—Power and Reset Status ..........................................................417

10.1.45 CIR7—Chipset Initalization Register 7 ................................................... 417

10.1.46 CIR8—Chipset Initialization Register 8 ..................................................418

10.1.47 CIR9—Chipset Initialization Register 9 ..................................................418

10.1.48 CIR10—Chipset Initialization Register 10 ..............................................418

10.1.49 CIR13—Chipset Initialization Register 13 ..............................................418

10.1.50 CIR14—Chipset Initialization Register 14 ..............................................418

10.1.51 CIR15—Chipset Initialization Register 15 ..............................................419

10.1.52 CIR16—Chipset Initialization Register 16 ..............................................419

10.1.53 CIR17—Chipset Initialization Register 17 ..............................................419

10.1.54 CIR18—Chipset Initialization Register 18 ..............................................419

10.1.55 CIR19—Chipset Initialization Register 19 ..............................................419

10.1.56 CIR20—Chipset Initialization Register 20 ..............................................420

10.1.57 CIR21—Chipset Initialization Register 21 ..............................................420

10.1.58 CIR22—Chipset Initialization Register 22 ..............................................420

10.1.59 RC—RTC Configuration Register...........................................................421

10.1.60 HPTC—High Precision Timer Configuration Register ................................421

10.1.61 GCS—General Control and Status Register ............................................422

10.1.62 BUC—Backed Up Control Register ........................................................424

10.1.63 FD—Function Disable Register .............................................................425

10.1.64 CG—Clock Gating Register ..................................................................427

10.1.65 FDSW—Function Disable SUS Well Register ...........................................428

10.1.66 FD2—Function Disable 2 Register.........................................................428

10.1.67 MISCCTL—Miscellaneous Control Register .............................................429

10.1.68 USBOCM1—Overcurrent MAP Register 1................................................430

10.1.69 USBOCM2—Overcurrent MAP Register 2................................................431

10.1.70 RMHWKCTL—Rate Matching Hub Wake Control Register .......................... 432

11 PCI-to-PCI Bridge Registers (D30:F0).................................................................... 435

11.1 PCI Configuration Registers (D30:F0) .................................................................435

11.1.1 VID—Vendor Identification Register (PCI-PCI—D30:F0) .......................... 436

11.1.2 DID—Device Identification Register (PCI-PCI—D30:F0) ........................... 436

11.1.3 PCICMD—PCI Command Register (PCI-PCI—D30:F0).............................. 436

11.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0).......................................437

11.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0).........................439

11.1.6 CC—Class Code Register (PCI-PCI—D30:F0)..........................................439

11.1.7 PMLT—Primary Master Latency Timer Register

(PCI-PCI—D30:F0).............................................................................440

11.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) .............................. 440

11.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0) ...................................440

11.1.10 SMLT—Secondary Master Latency Timer Register

(PCI-PCI—D30:F0).............................................................................441

11.1.11 IOBASE_LIMIT—I/O Base and Limit Register

(PCI-PCI—D30:F0).............................................................................441

11.1.12 SECSTS—Secondary Status Register (PCI-PCI—D30:F0) .........................442

11.1.13 MEMBASE_LIMIT—Memory Base and Limit Register

(PCI-PCI—D30:F0).............................................................................443

10 Datasheet

11.1.14 PREF_MEM_BASE_LIMIT—Prefetchable Memory Base

and Limit Register (PCI-PCI—D30:F0).................................................. 443

11.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits

Register (PCI-PCI—D30:F0)................................................................ 444

11.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits

Register (PCI-PCI—D30:F0)................................................................ 444

11.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) ....................... 444

11.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0)........................ 444

11.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0) ............................... 445

11.1.20 SPDH—Secondary PCI Device Hiding Register

(PCI-PCI—D30:F0) ............................................................................ 447

11.1.21 DTC—Delayed Transaction Control Register

(PCI-PCI—D30:F0) ............................................................................ 447

11.1.22 BPS—Bridge Proprietary Status Register

(PCI-PCI—D30:F0) ............................................................................ 449

11.1.23 BPC—Bridge Policy Configuration Register

(PCI-PCI—D30:F0) ............................................................................ 450

11.1.24 SVCAP—Subsystem Vendor Capability Register

(PCI-PCI—D30:F0) ............................................................................ 451

11.1.25 SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0) ..................... 451

12 Gigabit LAN Configuration Registers ...................................................................... 453

12.1 Gigabit LAN Configuration Registers

(Gigabit LAN—D25:F0)..................................................................................... 453

12.1.1 VID—Vendor Identification Register

(Gigabit LAN—D25:F0)....................................................................... 454

12.1.2 DID—Device Identification Register

(Gigabit LAN—D25:F0)....................................................................... 454

12.1.3 PCICMD—PCI Command Register

(Gigabit LAN—D25:F0)....................................................................... 455

12.1.4 PCISTS—PCI Status Register

(Gigabit LAN—D25:F0)....................................................................... 456

12.1.5 RID—Revision Identification Register

(Gigabit LAN—D25:F0)....................................................................... 457

12.1.6 CC—Class Code Register

(Gigabit LAN—D25:F0)....................................................................... 457

12.1.7 CLS—Cache Line Size Register

(Gigabit LAN—D25:F0)....................................................................... 457

12.1.8 PLT—Primary Latency Timer Register

(Gigabit LAN—D25:F0)....................................................................... 457

12.1.9 HT—Header Type Register

(Gigabit LAN—D25:F0)....................................................................... 457

12.1.10 MBARA—Memory Base Address Register A

(Gigabit LAN—D25:F0)....................................................................... 458

12.1.11 MBARB—Memory Base Address Register B

(Gigabit LAN—D25:F0)....................................................................... 458

12.1.12 MBARC—Memory Base Address Register C

(Gigabit LAN—D25:F0)....................................................................... 459

12.1.13 SVID—Subsystem Vendor ID Register

(Gigabit LAN—D25:F0)....................................................................... 459

12.1.14 SID—Subsystem ID Register

(Gigabit LAN—D25:F0)....................................................................... 459

12.1.15 ERBA—Expansion ROM Base Address Register

(Gigabit LAN—D25:F0)....................................................................... 459

12.1.16 CAPP—Capabilities List Pointer Register

(Gigabit LAN—D25:F0)....................................................................... 460

12.1.17 INTR—Interrupt Information Register

(Gigabit LAN—D25:F0)....................................................................... 460

12.1.18 MLMG—Maximum Latency/Minimum Grant Register

(Gigabit LAN—D25:F0)....................................................................... 460

12.1.19 CLIST 1—Capabilities List Register 1

(Gigabit LAN—D25:F0)....................................................................... 460

12.1.20 PMC—PCI Power Management Capabilities Register

(Gigabit LAN—D25:F0)....................................................................... 461

12.1.21 PMCS—PCI Power Management Control and Status

Register (Gigabit LAN—D25:F0) .......................................................... 462

Datasheet 11

12.1.22 DR—Data Register

(Gigabit LAN—D25:F0) .......................................................................463

12.1.23 CLIST 2—Capabilities List Register 2

(Gigabit LAN—D25:F0) .......................................................................463

12.1.24 MCTL—Message Control Register

(Gigabit LAN—D25:F0) .......................................................................463

12.1.25 MADDL—Message Address Low Register

(Gigabit LAN—D25:F0) .......................................................................464

12.1.26 MADDH—Message Address High Register

(Gigabit LAN—D25:F0) .......................................................................464

12.1.27 MDAT—Message Data Register

(Gigabit LAN—D25:F0) .......................................................................464

12.1.28 FLRCAP—Function Level Reset Capability

(Gigabit LAN—D25:F0) .......................................................................464

12.1.29 FLRCLV—Function Level Reset Capability Length and Version

(Gigabit LAN—D25:F0) .......................................................................465

12.1.30 DEVCTRL—Device Control (Gigabit LAN—D25:F0) ..................................465

13 LPC Interface Bridge Registers (D31:F0) ...............................................................467

13.1 PCI Configuration Registers (LPC I/F—D31:F0) ....................................................467

13.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) ........................... 468

13.1.2 DID—Device Identification Register (LPC I/F—D31:F0)............................ 468

13.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)..............................469

13.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0) .................................... 470

13.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ......................... 471

13.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) .......................... 471

13.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) ..................................471

13.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0).................................471

13.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) .........................471

13.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0) ............................... 472

13.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0)..........................472

13.1.12 CAPP—Capability List Pointer Register (LPC I/F—D31:F0) ........................ 472

13.1.13 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)........................472

13.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F—D31:F0) ............................473

13.1.15 GPIOBASE—GPIO Base Address Register

(LPC I/F—D31:F0) ............................................................................. 473

13.1.16 GC—GPIO Control Register (LPC I/F—D31:F0) .......................................474

13.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0) ............................................................................. 475

13.1.18 SIRQ_CNTL—Serial IRQ Control Register

(LPC I/F—D31:F0) ............................................................................. 476

13.1.19 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0) ............................................................................. 477

13.1.20 LPC_IBDF—IOxAPIC Bus:Device:Function Register

(LPC I/F—D31:F0) ............................................................................. 477

13.1.21 LPC_HnBDF—HPET n Bus:Device:Function Register

(LPC I/F—D31:F0) ............................................................................. 478

13.1.22 LPC_I/O_DEC—I/O Decode Ranges Register

(LPC I/F—D31:F0) ............................................................................. 479

13.1.23 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) ............................. 480

13.1.24 GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0) ............................................................................. 481

13.1.25 GEN2_DEC—LPC I/F Generic Decode Range 2 Register

(LPC I/F—D31:F0) ............................................................................. 481

13.1.26 GEN3_DEC—LPC I/F Generic Decode Range 3 Register

(LPC I/F—D31:F0) ............................................................................. 482

13.1.27 GEN4_DEC—LPC I/F Generic Decode Range 4 Register

(LPC I/F—D31:F0) ............................................................................. 482

13.1.28 ULKMC—USB Legacy Keyboard / Mouse Control

Register (LPC I/F—D31:F0) ................................................................483

13.1.29 LGMR—LPC I/F Generic Memory Range Register

(LPC I/F—D31:F0) ............................................................................. 484

13.1.30 FWH_SEL1—Firmware Hub Select 1 Register

(LPC I/F—D31:F0) ............................................................................. 485

13.1.31 FWH_SEL2—Firmware Hub Select 2 Register

(LPC I/F—D31:F0) ............................................................................. 486

12 Datasheet

13.1.32 FWH_DEC_EN1—Firmware Hub Decode Enable

Register (LPC I/F—D31:F0) ................................................................ 487

13.1.33 BIOS_CNTL—BIOS Control Register

(LPC I/F—D31:F0)............................................................................. 489

13.1.34 FDCAP—Feature Detection Capability ID

Register (LPC I/F—D31:F0)................................................................ 490

13.1.35 FDLEN—Feature Detection Capability Length

Register (LPC I/F—D31:F0)................................................................ 490

13.1.36 FDVER—Feature Detection Version

Register (LPC I/F—D31:F0)................................................................ 490

13.1.37 FDVCT—Feature Vector Register

(LPC I/F—D31:F0)............................................................................. 491

13.1.38 RCBA—Root Complex Base Address Register

(LPC I/F—D31:F0)............................................................................. 491

13.2 DMA I/O Registers........................................................................................... 492

13.2.1 DMABASE_CA—DMA Base and Current Address Registers ....................... 493

13.2.2 DMABASE_CC—DMA Base and Current Count Registers .......................... 494

13.2.3 DMAMEM_LP—DMA Memory Low Page Registers.................................... 494

13.2.4 DMACMD—DMA Command Register ..................................................... 495

13.2.5 DMASTA—DMA Status Register ........................................................... 495

13.2.6 DMA_WRSMSK—DMA Write Single Mask Register .................................. 496

13.2.7 DMACH_MODE—DMA Channel Mode Register ........................................ 497

13.2.8 DMA Clear Byte Pointer Register.......................................................... 498

13.2.9 DMA Master Clear Register ................................................................. 498

13.2.10 DMA_CLMSK—DMA Clear Mask Register ............................................... 498

13.2.11 DMA_WRMSK—DMA Write All Mask Register ......................................... 499

13.3 Timer I/O Registers ......................................................................................... 499

13.3.1 TCW—Timer Control Word Register...................................................... 500

13.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register ....................... 502

13.3.3 Counter Access Ports Register............................................................. 503

13.4 8259 Interrupt Controller (PIC) Registers ........................................................... 503

13.4.1 Interrupt Controller I/O MAP............................................................... 503

13.4.2 ICW1—Initialization Command Word 1 Register..................................... 504

13.4.3 ICW2—Initialization Command Word 2 Register..................................... 505

13.4.4 ICW3—Master Controller Initialization Command

Word 3 Register ................................................................................ 505

13.4.5 ICW3—Slave Controller Initialization Command

Word 3 Register ................................................................................ 506

13.4.6 ICW4—Initialization Command Word 4 Register..................................... 506

13.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)

Register ........................................................................................... 507

13.4.8 OCW2—Operational Control Word 2 Register ......................................... 507

13.4.9 OCW3—Operational Control Word 3 Register ......................................... 508

13.4.10 ELCR1—Master Controller Edge/Level Triggered Register ........................ 509

13.4.11 ELCR2—Slave Controller Edge/Level Triggered Register .......................... 510

13.5 Advanced Programmable Interrupt Controller (APIC)............................................ 511

13.5.1 APIC Register Map............................................................................. 511

13.5.2 IND—Index Register .......................................................................... 511

13.5.3 DAT—Data Register ........................................................................... 512

13.5.4 EOIR—EOI Register ........................................................................... 512

13.5.5 ID—Identification Register .................................................................. 513

13.5.6 VER—Version Register ....................................................................... 513

13.5.7 REDIR_TBL—Redirection Table............................................................ 514

13.6 Real Time Clock Registers................................................................................. 516

13.6.1 I/O Register Address Map................................................................... 516

13.6.2 Indexed Registers ............................................................................. 517

13.6.2.1 RTC_REGA—Register A ........................................................ 518

13.6.2.2 RTC_REGB—Register B (General Configuration)....................... 519

13.6.2.3 RTC_REGC—Register C (Flag Register)................................... 520

13.6.2.4 RTC_REGD—Register D (Flag Register) .................................. 520

13.7 Processor Interface Registers............................................................................ 521

13.7.1 NMI_SC—NMI Status and Control Register............................................ 521

13.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)

Register ........................................................................................... 522

13.7.3 PORT92—Fast A20 and Init Register .................................................... 522

13.7.4 COPROC_ERR—Coprocessor Error Register ........................................... 522

13.7.5 RST_CNT—Reset Control Register........................................................ 523

Datasheet 13

13.8 Power Management Registers (PM—D31:F0) .......................................................524

13.8.1 Power Management PCI Configuration Registers

(PM—D31:F0) ...................................................................................524

13.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register

(PM—D31:F0) .....................................................................524

13.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register

(PM—D31:F0) .....................................................................525

13.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register

(PM—D31:F0) .....................................................................527

13.8.1.4 GEN_PMCON_LOCK—General Power Management Configuration

Lock Register ......................................................................529

13.8.1.5 Chipset Initialization Register 4 (PM—D31:F0) ......................... 530

13.8.1.6 BM_BREAK_EN Register (PM—D31:F0) ...................................530

13.8.1.7 PMIR—Power Management Initialization Register (PM—D31:F0) . 531

13.8.1.8 GPIO_ROUT—GPIO Routing Control Register

(PM—D31:F0) .....................................................................531

13.8.2 APM I/O Decode ................................................................................531

13.8.2.1 APM_CNT—Advanced Power Management Control Port Register . 532

13.8.2.2 APM_STS—Advanced Power Management Status Port Register... 532

13.8.3 Power Management I/O Registers ........................................................532

13.8.3.1 PM1_STS—Power Management 1 Status Register .....................533

13.8.3.2 PM1_EN—Power Management 1 Enable Register ......................536

13.8.3.3 PM1_CNT—Power Management 1 Control Register.................... 537

13.8.3.4 PM1_TMR—Power Management 1 Timer Register ..................... 538

13.8.3.5 PM1_TMR—Power Management 1 Timer Register ..................... 538

13.8.3.6 GPE0_STS—General Purpose Event 0 Status Register ...............539

13.8.3.7 GPE0_EN—General Purpose Event 0 Enables Register ............... 541

13.8.3.8 SMI_EN—SMI Control and Enable Register .............................. 543

13.8.3.9 SMI_STS—SMI Status Register..............................................545

13.8.3.10 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register ...............547

13.8.3.11 ALT_GP_SMI_STS—Alternate GPI SMI Status Register .............. 548

13.8.3.12 UPRWC—USB Per-Port Registers Write Control.........................548

13.8.3.13 GPE_CNTL—General Purpose Control Register .........................549

13.8.3.14 DEVACT_STS—Device Activity Status Register ......................... 550

13.8.3.15 PM2_CNT—Power Management 2 Control Register.................... 550

13.9 System Management TCO Registers ................................................................... 551

13.9.1 TCO_RLD—TCO Timer Reload and Current Value Register .......................551

13.9.2 TCO_DAT_IN—TCO Data In Register ....................................................552

13.9.3 TCO_DAT_OUT—TCO Data Out Register................................................ 552

13.9.4 TCO1_STS—TCO1 Status Register........................................................552

13.9.5 TCO2_STS—TCO2 Status Register........................................................554

13.9.6 TCO1_CNT—TCO1 Control Register ......................................................555

13.9.7 TCO2_CNT—TCO2 Control Register ......................................................556

13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ....................................556

13.9.9 TCO_WDCNT—TCO Watchdog Control Register ......................................557

13.9.10 SW_IRQ_GEN—Software IRQ Generation Register ..................................557

13.9.11 TCO_TMR—TCO Timer Initial Value Register ..........................................557

13.10 General Purpose I/O Registers...........................................................................558

13.10.1 GPIO_USE_SEL—GPIO Use Select Register............................................ 559

13.10.2 GP_IO_SEL—GPIO Input/Output Select Register ....................................559

13.10.3 GP_LVL—GPIO Level for Input or Output Register .................................. 560

13.10.4 GPO_BLINK—GPO Blink Enable Register................................................560

13.10.5 GP_SER_BLINK—GP Serial Blink Register ..............................................561

13.10.6 GP_SB_CMDSTS—GP Serial Blink Command

Status Register..................................................................................562

13.10.7 GP_SB_DATA—GP Serial Blink Data Register .........................................562

13.10.8 GPI_NMI_EN—GPI NMI Enable Register ................................................563

13.10.9 GPI_NMI_STS—GPI NMI Status Register...............................................563

13.10.10 GPI_INV—GPIO Signal Invert Register ..................................................563

13.10.11 GPIO_USE_SEL2—GPIO Use Select 2 Register .......................................564

13.10.12 GP_IO_SEL2—GPIO Input/Output Select 2 Register................................564

13.10.13 GP_LVL2—GPIO Level for Input or Output 2 Register .............................. 565

13.10.14 GPIO_USE_SEL3—GPIO Use Select 3 Register .......................................566

13.10.15 GP_IO_SEL3—GPIO Input/Output Select 3 Register................................567

13.10.16 GP_LVL3—GPIO Level for Input or Output 3 Register .............................. 568

13.10.17 GP_RST_SEL1—GPIO Reset Select Register...........................................569

13.10.18 GP_RST_SEL2—GPIO Reset Select Register...........................................569

14 Datasheet

13.10.19 GP_RST_SEL3—GPIO Reset Select Register .......................................... 570

14 SATA Controller Registers (D31:F2)....................................................................... 571

14.1 PCI Configuration Registers (SATA–D31:F2)........................................................ 571

14.1.1 VID—Vendor Identification Register (SATA—D31:F2) ............................. 573

14.1.2 DID—Device Identification Register (SATA—D31:F2).............................. 573

14.1.3 PCICMD—PCI Command Register (SATA–D31:F2).................................. 573

14.1.4 PCISTS—PCI Status Register (SATA–D31:F2)........................................ 574

14.1.5 RID—Revision Identification Register (SATA—D31:F2)............................ 575

14.1.6 PI—Programming Interface Register (SATA–D31:F2).............................. 575

14.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h ....... 575

14.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h ....... 576

14.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h ....... 576

14.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ..................................... 576

14.1.8 BCC—Base Class Code Register

(SATA–D31:F2SATA–D31:F2) ............................................................. 577

14.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F2) ................................................................................ 577

14.1.10 HTYPE—Header Type Register

(SATA–D31:F2) ................................................................................ 577

14.1.11 PCMD_BAR—Primary Command Block Base Address

Register (SATA–D31:F2) .................................................................... 577

14.1.12 PCNL_BAR—Primary Control Block Base Address

Register (SATA–D31:F2) .................................................................... 578

14.1.13 SCMD_BAR—Secondary Command Block Base Address

Register (IDE D31:F2) ....................................................................... 578

14.1.14 SCNL_BAR—Secondary Control Block Base Address

Register (IDE D31:F2) ....................................................................... 578

14.1.15 BAR—Legacy Bus Master Base Address Register

(SATA–D31:F2) ................................................................................ 579

14.1.16 ABAR/SIDPBA1—AHCI Base Address Register/Serial ATA

Index Data Pair Base Address (SATA–D31:F2) ...................................... 579

14.1.16.1 When SCC is not 01h ........................................................... 579

14.1.16.2 When SCC is 01h ................................................................ 580

14.1.17 SVID—Subsystem Vendor Identification Register

(SATA–D31:F2) ................................................................................ 580

14.1.18 SID—Subsystem Identification Register (SATA–D31:F2) ......................... 580

14.1.19 CAP—Capabilities Pointer Register (SATA–D31:F2)................................. 580

14.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2) ................................... 581

14.1.21 INT_PN—Interrupt Pin Register (SATA–D31:F2)..................................... 581

14.1.22 IDE_TIM—IDE Timing Register (SATA–D31:F2) ..................................... 581

14.1.23 SIDETIM—Slave IDE Timing Register (SATA–D31:F2)............................. 582

14.1.24 SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F2) ................................................................................ 582

14.1.25 SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F2) ................................................................................ 582

14.1.26 IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F2) ................................................................................ 583

14.1.27 PID—PCI Power Management Capability Identification

Register (SATA–D31:F2) .................................................................... 583

14.1.28 PC—PCI Power Management Capabilities Register

(SATA–D31:F2) ................................................................................ 584

14.1.29 PMCS—PCI Power Management Control and Status

Register (SATA–D31:F2) .................................................................... 585

14.1.30 MSICI—Message Signaled Interrupt Capability

Identification Register (SATA–D31:F2) ................................................. 586

14.1.31 MSIMC—Message Signaled Interrupt Message

Control Register (SATA–D31:F2) ......................................................... 586

14.1.32 MSIMA—Message Signaled Interrupt Message

Address Register (SATA–D31:F2) ........................................................ 588

14.1.33 MSIMD—Message Signaled Interrupt Message

Data Register (SATA–D31:F2)............................................................. 588

14.1.34 MAP—Address Map Register (SATA–D31:F2) ......................................... 589

14.1.35 PCS—Port Control and Status Register (SATA–D31:F2)........................... 590

14.1.36 SCLKCG—SATA Clock Gating Control Register ....................................... 592

14.1.37 SCLKGC—SATA Clock General Configuration Register ............................. 593

14.1.38 SIRI—SATA Indexed Registers Index Register ....................................... 594

Datasheet 15

14.1.39 FLRCID—FLR Capability ID Register (SATA–D31:F2) ............................... 594

14.1.40 FLRCLV—FLR Capability Length and Version

Register (SATA–D31:F2)....................................................................595

14.1.41 FLRC—FLR Control Register (SATA–D31:F2)..........................................595

14.1.42 ATC—APM Trapping Control Register (SATA–D31:F2)..............................596

14.1.43 ATS—APM Trapping Status Register (SATA–D31:F2)............................... 596

14.1.44 SP Scratch Pad Register (SATA–D31:F2)...............................................596

14.1.45 BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ........................597

14.1.46 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ..................... 599

14.1.47 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ..................... 599

14.2 Bus Master IDE I/O Registers (D31:F2)...............................................................600

14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) .......................601

14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2)............................. 602

14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Register (D31:F2)..............................................................................603

14.2.4 AIR—AHCI Index Register (D31:F2) .....................................................603

14.2.5 AIDR—AHCI Index Data Register (D31:F2)............................................603

14.3 Serial ATA Index/Data Pair Superset Registers.....................................................604

14.3.1 SINDX—Serial ATA Index Register (D31:F2)..........................................604

14.3.2 SDATA—Serial ATA Data Register (D31:F2)...........................................605

14.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2) .........................605

14.3.2.2 PxSCTL—Serial ATA Control Register (D31:F2) ........................606

14.3.2.3 PxSERR—Serial ATA Error Register (D31:F2) ........................... 607

14.4 AHCI Registers (D31:F2) ..................................................................................608

14.4.1 AHCI Generic Host Control Registers (D31:F2)....................................... 609

14.4.1.1 CAP—Host Capabilities Register (D31:F2) ............................... 609

14.4.1.2 GHC—Global PCH Control Register (D31:F2)............................ 611

14.4.1.3 IS—Interrupt Status Register (D31:F2)...................................612

14.4.1.4 PI—Ports Implemented Register (D31:F2)...............................613

14.4.1.5 VS—AHCI Version Register (D31:F2)......................................614

14.4.1.6 CCC_CTL—Command Completion Coalescing Control

Register (D31:F2)................................................................614

14.4.1.7 CCC_Ports—Command Completion Coalescing Ports

Register (D31:F2)................................................................615

14.4.1.8 EM_LOC—Enclosure Management Location Register (D31:F2) .... 615

14.4.1.9 EM_CTRL—Enclosure Management Control Register (D31:F2) .... 616

14.4.1.10 VS—AHCI Version Register (D31:F2) ......................................617

14.4.1.11 VSP—Vendor Specific Register (D31:F2) .................................617

14.4.1.12 RSTF—Intel® RST Feature Capabilities Register .......................617

14.4.2 Port Registers (D31:F2)......................................................................619

14.4.2.1 PxCLB—Port [5:0] Command List Base Address Register

(D31:F2) ............................................................................ 623

14.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper

32-Bits Register (D31:F2)..................................................... 623

14.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2) .............. 624

14.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits

Register (D31:F2)................................................................624

14.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2).................625

14.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2) ................ 626

14.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2)......................628

14.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2)................. 631

14.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2) .......................631

14.4.2.10 PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2) .......... 632

14.4.2.11 PxSCTL—Port [5:0] Serial ATA Control Register (D31:F2).......... 633

14.4.2.12 PxSERR—Port [5:0] Serial ATA Error Register (D31:F2) ............634

14.4.2.13 PxSACT—Port [5:0] Serial ATA Active Register (D31:F2) ........... 635

14.4.2.14 PxCI—Port [5:0] Command Issue Register (D31:F2) ................636

15 SATA Controller Registers (D31:F5) .......................................................................637

15.1 PCI Configuration Registers (SATA–D31:F5) ........................................................637

15.1.1 VID—Vendor Identification Register (SATA—D31:F5) .............................. 638

15.1.2 DID—Device Identification Register (SATA—D31:F5) ..............................638

15.1.3 PCICMD—PCI Command Register (SATA–D31:F5) ..................................639

15.1.4 PCISTS—PCI Status Register (SATA–D31:F5) ........................................ 640

15.1.5 RID—Revision Identification Register (SATA—D31:F5) ............................640

15.1.6 PI—Programming Interface Register (SATA–D31:F5) ..............................641

15.1.7 SCC—Sub Class Code Register (SATA–D31:F5)......................................641

16 Datasheet

15.1.8 BCC—Base Class Code Register

(SATA–D31:F5SATA–D31:F5) ............................................................. 641

15.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F5) ................................................................................ 642

15.1.10 PCMD_BAR—Primary Command Block Base Address

Register (SATA–D31:F5) .................................................................... 642

15.1.11 PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F5) ................................................................................ 642

15.1.12 SCMD_BAR—Secondary Command Block Base Address

Register (IDE D31:F5) ....................................................................... 643

15.1.13 SCNL_BAR—Secondary Control Block Base Address

Register (IDE D31:F5) ....................................................................... 643

15.1.14 BAR—Legacy Bus Master Base Address Register

(SATA–D31:F5) ................................................................................ 644

15.1.15 SIDPBA—SATA Index/Data Pair Base Address Register

(SATA–D31:F5) ................................................................................ 644

15.1.16 SVID—Subsystem Vendor Identification Register

(SATA–D31:F5) ................................................................................ 645

15.1.17 SID—Subsystem Identification Register (SATA–D31:F5) ......................... 645

15.1.18 CAP—Capabilities Pointer Register (SATA–D31:F5)................................. 645

15.1.19 INT_LN—Interrupt Line Register (SATA–D31:F5) ................................... 645

15.1.20 INT_PN—Interrupt Pin Register (SATA–D31:F5)..................................... 645

15.1.21 IDE_TIM—IDE Timing Register (SATA–D31:F5) ..................................... 646

15.1.22 SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F5) ................................................................................ 646

15.1.23 SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F5) ................................................................................ 647

15.1.24 IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F5) ................................................................................ 647

15.1.25 PID—PCI Power Management Capability Identification

Register (SATA–D31:F5) .................................................................... 648

15.1.26 PC—PCI Power Management Capabilities Register

(SATA–D31:F5) ................................................................................ 648

15.1.27 PMCS—PCI Power Management Control and Status

Register (SATA–D31:F5) .................................................................... 649

15.1.28 MAP—Address Map Register (SATA–D31:F5) ......................................... 650

15.1.29 PCS—Port Control and Status Register (SATA–D31:F5)........................... 651

15.1.30 SATACR0—SATA Capability Register 0 (SATA–D31:F5) ........................... 652

15.1.31 SATACR1—SATA Capability Register 1 (SATA–D31:F5) ........................... 652

15.1.32 FLRCID—FLR Capability ID Register (SATA–D31:F5) .............................. 652

15.1.33 FLRCLV—FLR Capability Length and Value

Register (SATA–D31:F5) .................................................................... 653

15.1.34 FLRCTRL—FLR Control Register (SATA–D31:F5) .................................... 653

15.1.35 ATC—APM Trapping Control Register (SATA–D31:F5) ............................. 654

15.1.36 ATC—APM Trapping Control Register (SATA–D31:F5) ............................. 654

15.2 Bus Master IDE I/O Registers (D31:F5) .............................................................. 655

15.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5) ....................... 656

15.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5) ............................ 657

15.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Register (D31:F5) ............................................................................. 657

15.3 Serial ATA Index/Data Pair Superset Registers .................................................... 658

15.3.1 SINDX—SATA Index Register (D31:F5) ................................................ 658

15.3.2 SDATA—SATA Index Data Register (D31:F5) ........................................ 658

15.3.2.1 PxSSTS—Serial ATA Status Register (D31:F5)......................... 659

15.3.2.2 PxSCTL—Serial ATA Control Register (D31:F5)........................ 660

15.3.2.3 PxSERR—Serial ATA Error Register (D31:F5)........................... 661

16 EHCI Controller Registers (D29:F0, D26:F0) .......................................................... 663

16.1 USB EHCI Configuration Registers

(USB EHCI—D29:F0, D26:F0) ........................................................................... 663

16.1.1 VID—Vendor Identification Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 664

16.1.2 DID—Device Identification Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 665

16.1.3 PCICMD—PCI Command Register

(USB EHCI—D29:F0, D26:F0) ............................................................. 665

Datasheet 17

16.1.4 PCISTS—PCI Status Register

(USB EHCI—D29:F0, D26:F0)..............................................................666

16.1.5 RID—Revision Identification Register

(USB EHCI—D29:F0, D26:F0)..............................................................667

16.1.6 PI—Programming Interface Register

(USB EHCI—D29:F0, D26:F0)..............................................................667

16.1.7 SCC—Sub Class Code Register

(USB EHCI—D29:F0, D26:F0)..............................................................667

16.1.8 BCC—Base Class Code Register

(USB EHCI—D29:F0, D26:F0)..............................................................668

16.1.9 PMLT—Primary Master Latency Timer Register

(USB EHCI—D29:F0, D26:F0)..............................................................668

16.1.10 HEADTYP—Header Type Register

(USB EHCI—D29:F0, D26:F0)..............................................................668

16.1.11 MEM_BASE—Memory Base Address Register

(USB EHCI—D29:F0, D26:F0)..............................................................669

16.1.12 SVID—USB EHCI Subsystem Vendor ID Register

(USB EHCI—D29:F0, D26:F0)..............................................................669

16.1.13 SID—USB EHCI Subsystem ID Register

(USB EHCI—D29:F0, D26:F0)..............................................................669

16.1.14 CAP_PTR—Capabilities Pointer Register

(USB EHCI—D29:F0, D26:F0)..............................................................670

16.1.15 INT_LN—Interrupt Line Register

(USB EHCI—D29:F0, D26:F0)..............................................................670

16.1.16 INT_PN—Interrupt Pin Register

(USB EHCI—D29:F0, D26:F0)..............................................................670

16.1.17 PWR_CAPID—PCI Power Management Capability ID

Register (USB EHCI—D29:F0, D26:F0) .................................................670

16.1.18 NXT_PTR1—Next Item Pointer #1 Register

(USB EHCI—D29:F0, D26:F0)..............................................................671

16.1.19 PWR_CAP—Power Management Capabilities Register

(USB EHCI—D29:F0, D26:F0)..............................................................671

16.1.20 PWR_CNTL_STS—Power Management Control/

Status Register (USB EHCI—D29:F0, D26:F0) ....................................... 672

16.1.21 DEBUG_CAPID—Debug Port Capability ID Register

(USB EHCI—D29:F0, D26:F0)..............................................................673

16.1.22 NXT_PTR2—Next Item Pointer #2 Register

(USB EHCI—D29:F0, D26:F0)..............................................................673

16.1.23 DEBUG_BASE—Debug Port Base Offset Register

(USB EHCI—D29:F0, D26:F0)..............................................................673

16.1.24 USB_RELNUM—USB Release Number Register

(USB EHCI—D29:F0, D26:F0)..............................................................673

16.1.25 FL_ADJ—Frame Length Adjustment Register

(USB EHCI—D29:F0, D26:F0)..............................................................674

16.1.26 PWAKE_CAP—Port Wake Capability Register

(USB EHCI—D29:F0, D26:F0)..............................................................675

16.1.27 LEG_EXT_CAP—USB EHCI Legacy Support Extended

Capability Register (USB EHCI—D29:F0, D26:F0)...................................676

16.1.28 LEG_EXT_CS—USB EHCI Legacy Support Extended

Control / Status Register (USB EHCI—D29:F0, D26:F0) ..........................677

16.1.29 SPECIAL_SMI—Intel Specific USB 2.0 SMI Register

(USB EHCI—D29:F0, D26:F0)..............................................................679

16.1.30 ACCESS_CNTL—Access Control Register

(USB EHCI—D29:F0, D26:F0)..............................................................680

16.1.31 EHCIIR1—EHCI Initialization Register 1

(USB EHCI—D29:F0, D26:F0)..............................................................681

16.1.32 EHCIIR2—EHCI Initialization Register 2 (USB EHCI—D29:F0, D26:F0) ...... 681

16.1.33 FLR_CID—Function Level Reset Capability ID

Register (USB EHCI—D29:F0, D26:F0) ................................................682

16.1.34 FLR_NEXT—Function Level Reset Next Capability Pointer

Register (USB EHCI—D29:F0, D26:F0) ................................................682

16.1.35 FLR_CLV—Function Level Reset Capability Length and

Version Register (USB EHCI—D29:F0, D26:F0)...................................... 683

16.1.36 FLR_CTRL—Function Level Reset Control Register

(USB EHCI—D29:F0, D26:F0)..............................................................683

16.1.37 FLR_STS—Function Level Reset Status Register

(USB EHCI—D29:F0, D26:F0)..............................................................684

18 Datasheet

16.1.38 EHCIIR3—EHCI Initialization Register 3 (USB EHCI—D29:F0, D26:F0) ...... 684

16.1.39 EHCIIR4—EHCI Initialization Register 4 (USB EHCI—D29:F0, D26:F0) ...... 684

16.2 Memory-Mapped I/O Registers.......................................................................... 685

16.2.1 Host Controller Capability Registers ..................................................... 685

16.2.1.1 CAPLENGTH—Capability Registers Length Register ................... 686

16.2.1.2 HCIVERSION—Host Controller Interface Version Number

Register............................................................................. 686

16.2.1.3 HCSPARAMS—Host Controller Structural Parameters Register.... 686

16.2.1.4 HCCPARAMS—Host Controller Capability Parameters

Register............................................................................. 687

16.2.2 Host Controller Operational Registers................................................... 688

16.2.2.1 USB2.0_CMD—USB 2.0 Command Register............................. 689

16.2.2.2 USB2.0_STS—USB 2.0 Status Register................................... 692

16.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register ................... 694

16.2.2.4 FRINDEX—Frame Index Register ........................................... 695

16.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment

Register............................................................................. 695

16.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address

Register............................................................................. 696

16.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address

Register............................................................................. 696

16.2.2.8 CONFIGFLAG—Configure Flag Register ................................... 697

16.2.2.9 PORTSC—Port N Status and Control Register .......................... 697

16.2.3 USB 2.0-Based Debug Port Registers ................................................... 701

16.2.3.1 CNTL_STS—Control/Status Register....................................... 702

16.2.3.2 USBPID—USB PIDs Register ................................................. 704

16.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register ..................... 704

16.2.3.4 CONFIG—Configuration Register............................................ 704

17 Intel® High Definition Audio Controller Registers (D27:F0) ................................... 705

17.1 Intel® High Definition Audio PCI Configuration

Space (Intel® High Definition Audio—D27:F0)..................................................... 705

17.1.1 VID—Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0).................................. 707

17.1.2 DID—Device Identification Register

(Intel® High Definition Audio Controller—D27:F0).................................. 707

17.1.3 PCICMD—PCI Command Register

(Intel® High Definition Audio Controller—D27:F0).................................. 708

17.1.4 PCISTS—PCI Status Register

(Intel® High Definition Audio Controller—D27:F0).................................. 709

17.1.5 RID—Revision Identification Register

(Intel® High Definition Audio Controller—D27:F0).................................. 710

17.1.6 PI—Programming Interface Register

(Intel® High Definition Audio Controller—D27:F0).................................. 710

17.1.7 SCC—Sub Class Code Register

(Intel

®

High Definition Audio Controller—D27:F0).................................. 710

17.1.8 BCC—Base Class Code Register

(Intel® High Definition Audio Controller—D27:F0).................................. 710

17.1.9 CLS—Cache Line Size Register

(Intel® High Definition Audio Controller—D27:F0).................................. 710

17.1.10 LT—Latency Timer Register

(Intel® High Definition Audio Controller—D27:F0).................................. 711

17.1.11 HEADTYP—Header Type Register

(Intel® High Definition Audio Controller—D27:F0).................................. 711

17.1.12 HDBARL—Intel® High Definition Audio Lower Base Address

Register (Intel® High Definition Audio—D27:F0).................................... 711

17.1.13 HDBARU—Intel® High Definition Audio Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0).................................. 711

17.1.14 SVID—Subsystem Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0).................................. 712

17.1.15 SID—Subsystem Identification Register

(Intel

®

High Definition Audio Controller—D27:F0).................................. 712

17.1.16 CAPPTR—Capabilities Pointer Register

(Intel® High Definition Audio Controller—D27:F0).................................. 712

17.1.17 INTLN—Interrupt Line Register

(Intel® High Definition Audio Controller—D27:F0).................................. 713

Datasheet 19

17.1.18 INTPN—Interrupt Pin Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 713

17.1.19 HDCTL—Intel® High Definition Audio Control Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 713

17.1.20 HDINIT1—Intel® High Definition Audio Initialization
Register 1 (Intel® High Definition

Audio Controller—D27:F0) ..................................................................713

17.1.21 TCSEL—Traffic Class Select Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 714

17.1.22 DCKCTL—Docking Control Register (Mobile Only)

(Intel® High Definition Audio Controller—D27:F0) .................................. 714

17.1.23 DCKSTS—Docking Status Register (Mobile Only)

(Intel® High Definition Audio Controller—D27:F0) .................................. 715

17.1.24 PID—PCI Power Management Capability ID Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 715

17.1.25 PC—Power Management Capabilities Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 716

17.1.26 PCS—Power Management Control and Status Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 716

17.1.27 MID—MSI Capability ID Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 717

17.1.28 MMC—MSI Message Control Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 717

17.1.29 MMLA—MSI Message Lower Address Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 718

17.1.30 MMUA—MSI Message Upper Address Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 718

17.1.31 MMD—MSI Message Data Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 718

17.1.32 PXID—PCI Express* Capability ID Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 718

17.1.33 PXC—PCI Express* Capabilities Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 719

17.1.34 DEVCAP—Device Capabilities Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 719

17.1.35 DEVC—Device Control Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 720

17.1.36 DEVS—Device Status Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 721

17.1.37 VCCAP—Virtual Channel Enhanced Capability Header

(Intel® High Definition Audio Controller—D27:F0) .................................. 721

17.1.38 PVCCAP1—Port VC Capability Register 1

(Intel® High Definition Audio Controller—D27:F0) .................................. 722

17.1.39 PVCCAP2—Port VC Capability Register 2
(Intel

®

High Definition Audio Controller—D27:F0) .................................. 722

17.1.40 PVCCTL—Port VC Control Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 722

17.1.41 PVCSTS—Port VC Status Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 723

17.1.42 VC0CAP—VC0 Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 723

17.1.43 VC0CTL—VC0 Resource Control Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 724

17.1.44 VC0STS—VC0 Resource Status Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 724

17.1.45 VCiCAP—VCi Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 725

17.1.46 VCiCTL—VCi Resource Control Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 725

17.1.47 VCiSTS—VCi Resource Status Register
(Intel

®

High Definition Audio Controller—D27:F0) .................................. 726

17.1.48 RCCAP—Root Complex Link Declaration Enhanced
Capability Header Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 726

17.1.49 ESD—Element Self Description Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 726

20 Datasheet

17.1.50 L1DESC—Link 1 Description Register

(Intel® High Definition Audio Controller—D27:F0).................................. 727

17.1.51 L1ADDL—Link 1 Lower Address Register

(Intel® High Definition Audio Controller—D27:F0).................................. 727

17.1.52 L1ADDU—Link 1 Upper Address Register

(Intel® High Definition Audio Controller—D27:F0).................................. 727

17.2 Intel® High Definition Audio Memory Mapped Configuration Registers

(Intel® High Definition Audio—D27:F0) .............................................................. 728

17.2.1 GCAP—Global Capabilities Register

(Intel® High Definition Audio Controller—D27:F0).................................. 732

17.2.2 VMIN—Minor Version Register

(Intel® High Definition Audio Controller—D27:F0).................................. 732

17.2.3 VMAJ—Major Version Register

(Intel® High Definition Audio Controller—D27:F0).................................. 732

17.2.4 OUTPAY—Output Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0).................................. 733

17.2.5 INPAY—Input Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0).................................. 733

17.2.6 GCTL—Global Control Register

(Intel® High Definition Audio Controller—D27:F0).................................. 734

17.2.7 WAKEEN—Wake Enable Register

(Intel® High Definition Audio Controller—D27:F0).................................. 735

17.2.8 STATESTS—State Change Status Register

(Intel® High Definition Audio Controller—D27:F0).................................. 735

17.2.9 GSTS—Global Status Register

(Intel® High Definition Audio Controller—D27:F0).................................. 736

17.2.10 OUTSTRMPAY—Output Stream Payload Capability

Register (Intel® High Definition Audio Controller—D27:F0) ..................... 736

17.2.11 INSTRMPAY—Input Stream Payload Capability

Register (Intel® High Definition Audio Controller—D27:F0) ..................... 737

17.2.12 INTCTL—Interrupt Control Register

(Intel® High Definition Audio Controller—D27:F0).................................. 737

17.2.13 INTSTS—Interrupt Status Register

(Intel® High Definition Audio Controller—D27:F0).................................. 738

17.2.14 WALCLK—Wall Clock Counter Register

(Intel® High Definition Audio Controller—D27:F0).................................. 739

17.2.15 SSYNC—Stream Synchronization Register

(Intel® High Definition Audio Controller—D27:F0).................................. 739

17.2.16 CORBLBASE—CORB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0).................................. 740

17.2.17 CORBUBASE—CORB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0).................................. 740

17.2.18 CORBWP—CORB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0).................................. 740

17.2.19 CORBRP—CORB Read Pointer Register

(Intel

®

High Definition Audio Controller—D27:F0).................................. 741

17.2.20 CORBCTL—CORB Control Register

(Intel® High Definition Audio Controller—D27:F0).................................. 741

17.2.21 CORBST—CORB Status Register

(Intel® High Definition Audio Controller—D27:F0).................................. 742

17.2.22 CORBSIZE—CORB Size Register

Intel® High Definition Audio Controller—D27:F0)................................... 742

17.2.23 RIRBLBASE—RIRB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0).................................. 742

17.2.24 RIRBUBASE—RIRB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0).................................. 743

17.2.25 RIRBWP—RIRB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0).................................. 743

17.2.26 RINTCNT—Response Interrupt Count Register

(Intel® High Definition Audio Controller—D27:F0).................................. 744

17.2.27 RIRBCTL—RIRB Control Register

(Intel

®

High Definition Audio Controller—D27:F0).................................. 744

17.2.28 RIRBSTS—RIRB Status Register

(Intel® High Definition Audio Controller—D27:F0).................................. 745

17.2.29 RIRBSIZE—RIRB Size Register

(Intel® High Definition Audio Controller—D27:F0).................................. 745

Datasheet 21

17.2.30 IC—Immediate Command Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 745

17.2.31 IR—Immediate Response Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 746

17.2.32 ICS—Immediate Command Status Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 746

17.2.33 DPLBASE—DMA Position Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 747

17.2.34 DPUBASE—DMA Position Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 747

17.2.35 SDCTL—Stream Descriptor Control Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 748

17.2.36 SDSTS—Stream Descriptor Status Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 750

17.2.37 SDLPIB—Stream Descriptor Link Position in Buffer

Register (Intel® High Definition Audio Controller—D27:F0)......................751

17.2.38 SDCBL—Stream Descriptor Cyclic Buffer Length Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 751

17.2.39 SDLVI—Stream Descriptor Last Valid Index Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 752

17.2.40 SDFIFOW—Stream Descriptor FIFO Watermark Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 752

17.2.41 SDFIFOS—Stream Descriptor FIFO Size Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 753

17.2.42 SDFMT—Stream Descriptor Format Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 754

17.2.43 SDBDPL—Stream Descriptor Buffer Descriptor List
Pointer Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 755

17.2.44 SDBDPU—Stream Descriptor Buffer Descriptor List
Pointer Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0) .................................. 755

18 SMBus Controller Registers (D31:F3) .....................................................................757

18.1 PCI Configuration Registers (SMBus—D31:F3) ..................................................... 757

18.1.1 VID—Vendor Identification Register (SMBus—D31:F3)............................757

18.1.2 DID—Device Identification Register (SMBus—D31:F3) ............................ 758

18.1.3 PCICMD—PCI Command Register (SMBus—D31:F3) ...............................758

18.1.4 PCISTS—PCI Status Register (SMBus—D31:F3) .....................................759

18.1.5 RID—Revision Identification Register (SMBus—D31:F3) .......................... 759

18.1.6 PI—Programming Interface Register (SMBus—D31:F3) ........................... 760

18.1.7 SCC—Sub Class Code Register (SMBus—D31:F3) ...................................760

18.1.8 BCC—Base Class Code Register (SMBus—D31:F3)..................................760

18.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0

Register (SMBus—D31:F3).................................................................760

18.1.10 SMBMBAR1—D31_F3_SMBus Memory Base Address 1

Register (SMBus—D31:F3).................................................................761

18.1.11 SMB_BASE—SMBus Base Address Register

(SMBus—D31:F3) ..............................................................................761

18.1.12 SVID—Subsystem Vendor Identification Register

(SMBus—D31:F2/F4) .........................................................................761

18.1.13 SID—Subsystem Identification Register

(SMBus—D31:F2/F4) .........................................................................762

18.1.14 INT_LN—Interrupt Line Register (SMBus—D31:F3)................................. 762

18.1.15 INT_PN—Interrupt Pin Register (SMBus—D31:F3) ..................................762

18.1.16 HOSTC—Host Configuration Register (SMBus—D31:F3)...........................763

18.2 SMBus I/O and Memory Mapped I/O Registers..................................................... 764

18.2.1 HST_STS—Host Status Register (SMBus—D31:F3) ................................. 765

18.2.2 HST_CNT—Host Control Register (SMBus—D31:F3)................................766

18.2.3 HST_CMD—Host Command Register (SMBus—D31:F3) ...........................768

18.2.4 XMIT_SLVA—Transmit Slave Address Register

(SMBus—D31:F3) ..............................................................................768

18.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3) ..................................768

18.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3) ..................................768

18.2.7 Host_BLOCK_DB—Host Block Data Byte Register

(SMBus—D31:F3) ..............................................................................769

22 Datasheet

18.2.8 PEC—Packet Error Check (PEC) Register

(SMBus—D31:F3).............................................................................. 769

18.2.9 RCV_SLVA—Receive Slave Address Register

(SMBus—D31:F3).............................................................................. 770

18.2.10 SLV_DATA—Receive Slave Data Register (SMBus—D31:F3) .................... 770

18.2.11 AUX_STS—Auxiliary Status Register (SMBus—D31:F3)........................... 770

18.2.12 AUX_CTL—Auxiliary Control Register (SMBus—D31:F3) .......................... 771

18.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register

(SMBus—D31:F3).............................................................................. 771

18.2.14 SMBus_PIN_CTL—SMBus Pin Control Register

(SMBus—D31:F3).............................................................................. 772

18.2.15 SLV_STS—Slave Status Register (SMBus—D31:F3)................................ 772

18.2.16 SLV_CMD—Slave Command Register (SMBus—D31:F3).......................... 773

18.2.17 NOTIFY_DADDR—Notify Device Address Register

(SMBus—D31:F3).............................................................................. 773

18.2.18 NOTIFY_DLOW—Notify Data Low Byte Register

(SMBus—D31:F3).............................................................................. 774

18.2.19 NOTIFY_DHIGH—Notify Data High Byte Register

(SMBus—D31:F3).............................................................................. 774

19 PCI Express* Configuration Registers.................................................................... 775

19.1 PCI Express* Configuration Registers

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)................................................... 775

19.1.1 VID—Vendor Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 777

19.1.2 DID—Device Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 777

19.1.3 PCICMD—PCI Command Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 778

19.1.4 PCISTS—PCI Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 779

19.1.5 RID—Revision Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 780

19.1.6 PI—Programming Interface Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 780

19.1.7 SCC—Sub Class Code Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 780

19.1.8 BCC—Base Class Code Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 780

19.1.9 CLS—Cache Line Size Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 781

19.1.10 PLT—Primary Latency Timer Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 781

19.1.11 HEADTYP—Header Type Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 781

19.1.12 BNUM—Bus Number Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 782

19.1.13 SLT—Secondary Latency Timer

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 782

19.1.14 IOBL—I/O Base and Limit Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 782

19.1.15 SSTS—Secondary Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 783

19.1.16 MBL—Memory Base and Limit Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 784

19.1.17 PMBL—Prefetchable Memory Base and Limit Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 784

19.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits

Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/

F6/F7/F6/F7) .................................................................................... 785

19.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits

Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/

F6/F7/F6/F7) .................................................................................... 785

19.1.20 CAPP—Capabilities List Pointer Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 785

19.1.21 INTR—Interrupt Information Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ........................... 786

Datasheet 23

19.1.22 BCTRL—Bridge Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) ............................ 787

19.1.23 CLIST—Capabilities List Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................788

19.1.24 XCAP—PCI Express* Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................788

19.1.25 DCAP—Device Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................789

19.1.26 DCTL—Device Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................790

19.1.27 DSTS—Device Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................791

19.1.28 LCAP—Link Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................791

19.1.29 LCTL—Link Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................793

19.1.30 LSTS—Link Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................794

19.1.31 SLCAP—Slot Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................795

19.1.32 SLCTL—Slot Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................796

19.1.33 SLSTS—Slot Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................797

19.1.34 RCTL—Root Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................798

19.1.35 RSTS—Root Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................798

19.1.36 DCAP2—Device Capabilities 2 Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................799

19.1.37 DCTL2—Device Control 2 Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................799

19.1.38 LCTL2—Link Control 2 Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................800

19.1.39 MID—Message Signaled Interrupt Identifiers Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................800

19.1.40 MC—Message Signaled Interrupt Message Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................800

19.1.41 MA—Message Signaled Interrupt Message Address

Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)......................... 801

19.1.42 MD—Message Signaled Interrupt Message Data Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................801

19.1.43 SVCAP—Subsystem Vendor Capability Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................801

19.1.44 SVID—Subsystem Vendor Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................801

19.1.45 PMCAP—Power Management Capability Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................802

19.1.46 PMC—PCI Power Management Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................802

19.1.47 PMCS—PCI Power Management Control and Status

Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)......................... 803

19.1.48 MPC2—Miscellaneous Port Configuration Register 2

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................804

19.1.49 MPC—Miscellaneous Port Configuration Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................805

19.1.50 SMSCS—SMI/SCI Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................807

19.1.51 RPDCGEN—Root Port Dynamic Clock Gating Enable

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................808

19.1.52 PECR1—PCI Express* Configuration Register 1

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................808

19.1.53 UES—Uncorrectable Error Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................809

19.1.54 UEM—Uncorrectable Error Mask

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .....................................810

24 Datasheet

19.1.55 UEV—Uncorrectable Error Severity

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)..................................... 811

19.1.56 CES—Correctable Error Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)..................................... 812

19.1.57 CEM—Correctable Error Mask Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)..................................... 812

19.1.58 AECC—Advanced Error Capabilities and Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)..................................... 813

19.1.59 RES—Root Error Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)..................................... 813

19.1.60 PECR2—PCI Express* Configuration Register 2

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)..................................... 814

19.1.61 PEETM—PCI Express* Extended Test Mode Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)..................................... 814

19.1.62 PEC1—PCI Express* Configuration Register 1

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)..................................... 814

20 High Precision Event Timer Registers .................................................................... 815

20.1 Memory Mapped Registers................................................................................ 815

20.1.1 GCAP_ID—General Capabilities and Identification Register ...................... 817

20.1.2 GEN_CONF—General Configuration Register.......................................... 817

20.1.3 GINTR_STA—General Interrupt Status Register ..................................... 818

20.1.4 MAIN_CNT—Main Counter Value Register ............................................. 818

20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register .................. 819

20.1.6 TIMn_COMP—Timer n Comparator Value Register.................................. 821

21 Serial Peripheral Interface (SPI) ........................................................................... 823

21.1 Serial Peripheral Interface Memory Mapped Configuration Registers ....................... 823

21.1.1 BFPR –BIOS Flash Primary Region Register

(SPI Memory Mapped Configuration Registers) ...................................... 824

21.1.2 HSFS—Hardware Sequencing Flash Status Register

(SPI Memory Mapped Configuration Registers) ...................................... 825

21.1.3 HSFC—Hardware Sequencing Flash Control Register

(SPI Memory Mapped Configuration Registers) ...................................... 827

21.1.4 FADDR—Flash Address Register

(SPI Memory Mapped Configuration Registers) ...................................... 827

21.1.5 FDATA0—Flash Data 0 Register

(SPI Memory Mapped Configuration Registers) ...................................... 828

21.1.6 FDATAN—Flash Data [N] Register

(SPI Memory Mapped Configuration Registers) ...................................... 828

21.1.7 FRAP—Flash Regions Access Permissions Register

(SPI Memory Mapped Configuration Registers) ...................................... 829

21.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register

(SPI Memory Mapped Configuration Registers) ...................................... 830

21.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register

(SPI Memory Mapped Configuration Registers) ...................................... 830

21.1.10 FREG2—Flash Region 2 (Intel® ME) Register

(SPI Memory Mapped Configuration Registers) ...................................... 831

21.1.11 FREG3—Flash Region 3 (GbE) Register

(SPI Memory Mapped Configuration Registers) ...................................... 831

21.1.12 FREG4—Flash Region 4 (Platform Data) Register

(SPI Memory Mapped Configuration Registers) ...................................... 832

21.1.13 PR0—Protected Range 0 Register

(SPI Memory Mapped Configuration Registers) ...................................... 832

21.1.14 PR1—Protected Range 1 Register

(SPI Memory Mapped Configuration Registers) ...................................... 833

21.1.15 PR2—Protected Range 2 Register

(SPI Memory Mapped Configuration Registers) ...................................... 834

21.1.16 PR3—Protected Range 3 Register

(SPI Memory Mapped Configuration Registers) ...................................... 835

21.1.17 PR4—Protected Range 4 Register

(SPI Memory Mapped Configuration Registers) ...................................... 836

21.1.18 SSFS—Software Sequencing Flash Status Register

(SPI Memory Mapped Configuration Registers) ...................................... 837

21.1.19 SSFC—Software Sequencing Flash Control Register

(SPI Memory Mapped Configuration Registers) ...................................... 838

Datasheet 25

21.1.20 PREOP—Prefix Opcode Configuration Register

(SPI Memory Mapped Configuration Registers) ......................................839

21.1.21 OPTYPE—Opcode Type Configuration Register

(SPI Memory Mapped Configuration Registers) ......................................839

21.1.22 OPMENU—Opcode Menu Configuration Register

(SPI Memory Mapped Configuration Registers) ......................................840

21.1.23 BBAR—BIOS Base Address Configuration Register

(SPI Memory Mapped Configuration Registers) ......................................841

21.1.24 FDOC—Flash Descriptor Observability Control Register

(SPI Memory Mapped Configuration Registers) ......................................841

21.1.25 FDOD—Flash Descriptor Observability Data Register

(SPI Memory Mapped Configuration Registers) ......................................842

21.1.26 AFC—Additional Flash Control Register

(SPI Memory Mapped Configuration Registers) ......................................842

21.1.27 LVSCC—Host Lower Vendor Specific Component
Capabilities Register

(SPI Memory Mapped Configuration Registers) ......................................842

21.1.28 UVSCC—Host Upper Vendor Specific Component
Capabilities Register

(SPI Memory Mapped Configuration Registers) ......................................844

21.1.29 FPB—Flash Partition Boundary Register

(SPI Memory Mapped Configuration Registers) ......................................845

21.2 Flash Descriptor Records...................................................................................845

21.3 OEM Section ...................................................................................................846

21.4 GbE SPI Flash Program Registers .......................................................................846

21.4.1 GLFPR –Gigabit LAN Flash Primary Region Register

(GbE LAN Memory Mapped Configuration Registers) ...............................847

21.4.2 HSFS—Hardware Sequencing Flash Status Register

(GbE LAN Memory Mapped Configuration Registers) ...............................847

21.4.3 HSFC—Hardware Sequencing Flash Control Register

(GbE LAN Memory Mapped Configuration Registers) ...............................849

21.4.4 FADDR—Flash Address Register

(GbE LAN Memory Mapped Configuration Registers) ...............................850

21.4.5 FDATA0—Flash Data 0 Register

(GbE LAN Memory Mapped Configuration Registers) ...............................850

21.4.6 FRAP—Flash Regions Access Permissions Register

(GbE LAN Memory Mapped Configuration Registers) ...............................851

21.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register

(GbE LAN Memory Mapped Configuration Registers) ...............................852

21.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register

(GbE LAN Memory Mapped Configuration Registers) ...............................852

21.4.9 FREG2—Flash Region 2 (Intel® ME) Register

(GbE LAN Memory Mapped Configuration Registers) ...............................852

21.4.10 FREG3—Flash Region 3 (GbE) Register

(GbE LAN Memory Mapped Configuration Registers) ...............................853

21.4.11 PR0—Protected Range 0 Register

(GbE LAN Memory Mapped Configuration Registers) ...............................853

21.4.12 PR1—Protected Range 1 Register

(GbE LAN Memory Mapped Configuration Registers) ...............................854

21.4.13 SSFS—Software Sequencing Flash Status Register

(GbE LAN Memory Mapped Configuration Registers) ...............................855

21.4.14 SSFC—Software Sequencing Flash Control Register

(GbE LAN Memory Mapped Configuration Registers) ...............................856

21.4.15 PREOP—Prefix Opcode Configuration Register

(GbE LAN Memory Mapped Configuration Registers) ...............................857

21.4.16 OPTYPE—Opcode Type Configuration Register

(GbE LAN Memory Mapped Configuration Registers) ...............................857

21.4.17 OPMENU—Opcode Menu Configuration Register

(GbE LAN Memory Mapped Configuration Registers) ...............................858

22 Thermal Sensor Registers (D31:F6) .......................................................................859

22.1 PCI Bus Configuration Registers.........................................................................859

22.1.1 VID—Vendor Identification Register......................................................860

22.1.2 DID—Device Identification Register ......................................................860

22.1.3 CMD—Command Register ...................................................................860

22.1.4 STS—Status Register .........................................................................861

22.1.5 RID—Revision Identification Register ....................................................861

26 Datasheet

22.1.6 PI—Programming Interface Register .................................................... 861

22.1.7 SCC—Sub Class Code Register ............................................................ 862

22.1.8 BCC—Base Class Code Register........................................................... 862

22.1.9 CLS—Cache Line Size Register ............................................................ 862

22.1.10 LT—Latency Timer Register ................................................................ 862

22.1.11 HTYPE—Header Type Register............................................................. 862

22.1.12 TBAR—Thermal Base Register............................................................. 863

22.1.13 TBARH—Thermal Base High DWord Register ......................................... 863

22.1.14 SVID—Subsystem Vendor ID Register.................................................. 864

22.1.15 SID—Subsystem ID Register............................................................... 864

22.1.16 CAP_PTR—Capabilities Pointer Register ................................................ 864

22.1.17 Offset 3Ch – INTLN—Interrupt Line Register ......................................... 865

22.1.18 INTPN—Interrupt Pin Register ............................................................. 865

22.1.19 TBARB—BIOS Assigned Thermal Base Address Register.......................... 865

22.1.20 TBARBH—BIOS Assigned Thermal Base High DWord

Register ........................................................................................... 866

22.1.21 PID—PCI Power Management Capability ID Register............................... 866

22.1.22 PC—Power Management Capabilities Register........................................ 866

22.1.23 PCS—Power Management Control And Status Register ........................... 867

22.2 Thermal Memory Mapped Configuration Registers

(Thermal Sensor – D31:F26) ............................................................................ 868

22.2.1 TSIU—Thermal Sensor In Use Register................................................. 869

22.2.2 TSE—Thermal Sensor Enable Register.................................................. 869

22.2.3 TSS—Thermal Sensor Status Register .................................................. 870

22.2.4 TSTR—Thermal Sensor Thermometer Read Register............................... 870

22.2.5 TSTTP—Thermal Sensor Temperature Trip Point Register........................ 871

22.2.6 TSCO—Thermal Sensor Catastrophic Lock-Down Register ....................... 871

22.2.7 TSES—Thermal Sensor Error Status Register ........................................ 872

22.2.8 TSGPEN—Thermal Sensor General Purpose Event

Enable Register................................................................................. 873

22.2.9 TSPC—Thermal Sensor Policy Control Register ...................................... 874

22.2.10 PPEC—Processor Power Error Correction Register

(Mobile Only).................................................................................... 874

22.2.11 CTA—Processor Core Temperature Adjust Register................................. 875

22.2.12 PTA—PCH Temperature Adjust Register................................................ 875

22.2.13 MGTA—Memory Controller/Graphics Temperature

Adjust Register ................................................................................. 875

22.2.14 TRC—Thermal Reporting Control Register ............................................. 876

22.2.15 TES—Turbo Interrupt Status Register (Mobile Only) ............................... 877

22.2.16 TEN—Turbo Interrupt Enable Register (Mobile Only)............................... 877

22.2.17 PSC—Power Sharing Configuration Register (Mobile Only)....................... 877

22.2.18 CTV1—Core Temperature Value 1 Register ........................................... 878

22.2.19 CTV2—Core Temperature Value 2 Register ........................................... 878

22.2.20 CEV1—Core Energy Value Register ...................................................... 878

22.2.21 AE—Alert Enable Register................................................................... 879

22.2.22 HTS—Host Status Register (Mobile Only).............................................. 879

22.2.23 PTL—Processor Temperature Limit Register (Mobile Only) ....................... 880

22.2.24 MGTV—Memory Controller/Graphics Temperature

Value Register .................................................................................. 880

22.2.25 PTV—Processor Temperature Value Register ......................................... 880

22.2.26 MMGPC—Max Memory Controller/Graphics Power Clamp

Register (Mobile Only) ....................................................................... 880

22.2.27 MPPC—Max Processor Power Clamp Register (Mobile Only) ..................... 881

22.2.28 MPCPC—Max Processor Core Power Clamp Register

(Mobile Only).................................................................................... 881

22.2.29 TSPIEN—Thermal Sensor PCI Interrupt Enable Register.......................... 882

22.2.30 TSLOCK—Thermal Sensor Register Lock Control Register........................ 883

22.2.31 STS—Turbo Status (Mobile Only)......................................................... 883

22.2.32 SEC—Event Clear Register (Mobile Only) .............................................. 883

22.2.33 TC3—Thermal Compares 3 Register ..................................................... 883

22.2.34 TC1—Thermal Compares 1 Register ..................................................... 884

22.2.35 TC2—Thermal Compares 2 Register ..................................................... 885

22.2.36 DTV—DIMM Temperature Values Register............................................. 885

22.2.37 ITV—Internal Temperature Values Register........................................... 886

23 Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0).......... 887

Datasheet 27

23.1 First Intel® Management Engine Interface (Intel® MEI) Configuration Registers

(MEI—D22:F0) ................................................................................................887

23.1.1 VID—Vendor Identification Register

(MEI—D22:F0) .................................................................................. 888

23.1.2 DID—Device Identification Register

(MEI—D22:F0) .................................................................................. 888

23.1.3 PCICMD—PCI Command Register

(MEI—D22:F0) .................................................................................. 889

23.1.4 PCISTS—PCI Status Register

(MEI—D22:F0) .................................................................................. 889

23.1.5 RID—Revision Identification Register

(MEI—D22:F0) .................................................................................. 890

23.1.6 CC—Class Code Register

(MEI—D22:F0) .................................................................................. 890

23.1.7 HTYPE—Header Type Register

(MEI—D22:F0) .................................................................................. 890

23.1.8 MEI0_MBAR—MEI0 MMIO Base Address Register

(MEI—D22:F0) .................................................................................. 891

23.1.9 SVID—Subsystem Vendor ID Register

(MEI—D22:F0) .................................................................................. 891

23.1.10 SID—Subsystem ID Register

(MEI—D22:F0) .................................................................................. 891

23.1.11 CAPP—Capabilities List Pointer Register

(MEI—D22:F0) .................................................................................. 892

23.1.12 INTR—Interrupt Information Register

(MEI—D22:F0) .................................................................................. 892

23.1.13 HFS—Host Firmware Status Register

(MEI—D22:F0) .................................................................................. 892

23.1.14 ME_UMA—Management Engine UMA Register

(MEI—D22:F0) .................................................................................. 893

23.1.15 GMES—General ME Status Register

(MEI—D22:F0) .................................................................................. 893

23.1.16 H_GS—Host General Status Register

(MEI—D22:F0) .................................................................................. 893

23.1.17 PID—PCI Power Management Capability ID Register

(MEI—D22:F0) .................................................................................. 894

23.1.18 PC—PCI Power Management Capabilities Register

(MEI—D22:F0) .................................................................................. 894

23.1.19 PMCS—PCI Power Management Control and Status

Register (MEI—D22:F0)......................................................................895

23.1.20 MID—Message Signaled Interrupt Identifiers Register

(MEI—D22:F0) .................................................................................. 895

23.1.21 MC—Message Signaled Interrupt Message Control Register

(MEI—D22:F0) .................................................................................. 896

23.1.22 MA—Message Signaled Interrupt Message Address

Register (MEI—D22:F0)......................................................................896

23.1.23 MUA—Message Signaled Interrupt Upper Address Register

(MEI—D22:F0) .................................................................................. 896

23.1.24 MD—Message Signaled Interrupt Message Data Register

(MEI—D22:F0) .................................................................................. 896

23.1.25 HIDM—MEI Interrupt Delivery Mode Register

(MEI—D22:F0) .................................................................................. 897

23.1.26 HERES—MEI Extend Register Status

(MEI—D22:F0) .................................................................................. 897

23.1.27 HERX—MEI Extend Register DWX

(MEI—D22:F0) .................................................................................. 898

23.2 Second Management Engine Interface(MEI1) Configuration Registers

(MEI—D22:F1) ................................................................................................899

23.2.1 VID—Vendor Identification Register

(MEI—D22:F1) .................................................................................. 900

23.2.2 DID—Device Identification Register

(MEI—D22:F1) .................................................................................. 900

23.2.3 PCICMD—PCI Command Register

(MEI—D22:F1) .................................................................................. 900

23.2.4 PCISTS—PCI Status Register

(MEI—D22:F1) .................................................................................. 901

28 Datasheet

23.2.5 RID—Revision Identification Register

(MEI—D22:F1).................................................................................. 901

23.2.6 CC—Class Code Register

(MEI—D22:F1).................................................................................. 901

23.2.7 HTYPE—Header Type Register

(MEI—D22:F1).................................................................................. 902

23.2.8 MEI_MBAR—MEI MMIO Base Address Register

(MEI—D22:F1).................................................................................. 902

23.2.9 SVID—Subsystem Vendor ID Register

(MEI—D22:F1).................................................................................. 902

23.2.10 SID—Subsystem ID Register

(MEI—D22:F1).................................................................................. 903

23.2.11 CAPP—Capabilities List Pointer Register

(MEI—D22:F1).................................................................................. 903

23.2.12 INTR—Interrupt Information Register

(MEI—D22:F1).................................................................................. 903

23.2.13 HFS—Host Firmware Status Register

(MEI—D22:F1).................................................................................. 903

23.2.14 GMES—General ME Status Register

(MEI—D22:F1).................................................................................. 904

23.2.15 H_GS—Host General Status Register

(MEI—D22:F1).................................................................................. 904

23.2.16 PID—PCI Power Management Capability ID Register

(MEI—D22:F1).................................................................................. 904

23.2.17 PC—PCI Power Management Capabilities Register

(MEI—D22:F1).................................................................................. 905

23.2.18 PMCS—PCI Power Management Control and Status

Register (MEI—D22:F1) ..................................................................... 906

23.2.19 MID—Message Signaled Interrupt Identifiers Register

(MEI—D22:F1).................................................................................. 906

23.2.20 MC—Message Signaled Interrupt Message Control Register

(MEI—D22:F1).................................................................................. 907

23.2.21 MA—Message Signaled Interrupt Message Address

Register (MEI—D22:F1) ..................................................................... 907

23.2.22 MUA—Message Signaled Interrupt Upper Address Register

(MEI—D22:F1).................................................................................. 907

23.2.23 MD—Message Signaled Interrupt Message Data Register

(MEI—D22:F1).................................................................................. 907

23.2.24 HIDM—MEI Interrupt Delivery Mode Register

(MEI—D22:F1).................................................................................. 908

23.2.25 HERES—MEI Extend Register Status

(MEI—D22:F1).................................................................................. 908

23.2.26 HERX—MEI Extend Register DWX

(MEI—D22:F1).................................................................................. 909

23.3 MEI0_MBAR—MEI0 MMIO Registers ................................................................... 909

23.3.1 H_CB_WW—Host Circular Buffer Write Window Register

(MEI MMIO Register) ......................................................................... 910

23.3.2 H_CSR—Host Control Status Register

(MEI MMIO Register) ......................................................................... 910

23.3.3 ME_CB_RW—ME Circular Buffer Read Window Register

(MEI MMIO Register) ......................................................................... 911

23.3.4 ME CSR_HA—ME Control Status Host Access Register

(MEI MMIO Register) ......................................................................... 911

23.4 MEI1_MBAR—MEI0 MMIO Registers ................................................................... 912

23.4.1 H_CB_WW—Host Circular Buffer Write Window Register

(MEI MMIO Register) ......................................................................... 912

23.4.2 H_CSR—Host Control Status Register

(MEI MMIO Register) ......................................................................... 913

23.4.3 ME_CB_RW—ME Circular Buffer Read Window Register

(MEI MMIO Register) ......................................................................... 914

23.4.4 ME CSR_HA—ME Control Status Host Access Register

(MEI MMIO Register) ......................................................................... 914

23.5 IDE Function for Remote Boot and Installations

PT IDER Registers (IDER—D22:F2) .................................................................... 915

23.5.1 VID—Vendor Identification Register (IDER—D22:F2) .............................. 916

23.5.2 DID—Device Identification Register (IDER—D22:F2) .............................. 916

23.5.3 PCICMD—PCI Command Register (IDER—D22:F2) ................................. 916

Datasheet 29

23.5.4 PCISTS—PCI Device Status Register (IDER—D22:F2) ............................. 917

23.5.5 RID—Revision Identification Register (IDER—D22:F2)............................. 917

23.5.6 CC—Class Codes Register (IDER—D22:F2) ............................................917

23.5.7 CLS—Cache Line Size Register (IDER—D22:F2) .....................................918

23.5.8 PCMDBA—Primary Command Block IO Bar Register

(IDER—D22:F2) ................................................................................918

23.5.9 PCTLBA—Primary Control Block Base Address Register

(IDER—D22:F2) ................................................................................918

23.5.10 SCMDBA—Secondary Command Block Base Address

Register (IDER—D22:F2) ....................................................................919

23.5.11 SCTLBA—Secondary Control Block base Address

Register (IDER—D22:F2) ....................................................................919

23.5.12 LBAR—Legacy Bus Master Base Address Register

(IDER—D22:F2) ................................................................................919

23.5.13 SVID—Subsystem Vendor ID Register (IDER—D22:F2) ........................... 920

23.5.14 SID—Subsystem ID Register (IDER—D22:F2)........................................920

23.5.15 CAPP—Capabilities List Pointer Register

(IDER—D22:F2) ................................................................................920

23.5.16 INTR—Interrupt Information Register

(IDER—D22:F2) ................................................................................920

23.5.17 PID—PCI Power Management Capability ID Register

(IDER—D22:F2) ................................................................................921

23.5.18 PC—PCI Power Management Capabilities Register

(IDER—D22:F2) ................................................................................921

23.5.19 PMCS—PCI Power Management Control and Status

Register (IDER—D22:F2) ....................................................................922

23.5.20 MID—Message Signaled Interrupt Capability ID

Register (IDER—D22:F2) ....................................................................922

23.5.21 MC—Message Signaled Interrupt Message Control

Register (IDER—D22:F2) ....................................................................923

23.5.22 MA—Message Signaled Interrupt Message Address

Register (IDER—D22:F2) ....................................................................923

23.5.23 MAU—Message Signaled Interrupt Message Upper

Address Register (IDER—D22:F2) ........................................................923

23.5.24 MD—Message Signaled Interrupt Message Data

Register (IDER—D22:F2) ....................................................................924

23.6 IDE BAR0 .......................................................................................................924

23.6.1 IDEDATA—IDE Data Register (IDER—D22:F2) .......................................925

23.6.2 IDEERD1—IDE Error Register DEV1

(IDER—D22:F2) ................................................................................925

23.6.3 IDEERD0—IDE Error Register DEV0

(IDER—D22:F2) ................................................................................925

23.6.4 IDEFR—IDE Features Register

(IDER—D22:F2) ................................................................................926

23.6.5 IDESCIR—IDE Sector Count In Register

(IDER—D22:F2) ................................................................................926

23.6.6 IDESCOR1—IDE Sector Count Out Register Device 1

Register (IDER—D22:F2) ....................................................................926

23.6.7 IDESCOR0—IDE Sector Count Out Register Device

0 Register (IDER—D22:F2) .................................................................927

23.6.8 IDESNOR0—IDE Sector Number Out Register

Device 0 Register (IDER—D22:F2) .......................................................927

23.6.9 IDESNOR1—IDE Sector Number Out Register

Device 1 Register (IDER—D22:F2) .......................................................927

23.6.10 IDESNIR—IDE Sector Number In Register Register

(IDER—D22:F2) ................................................................................928

23.6.11 IDECLIR—IDE Cylinder Low In Register Register

(IDER—D22:F2) ................................................................................928

23.6.12 IDCLOR1—IDE Cylinder Low Out Register Device 1

Register (IDER—D22:F2) ....................................................................928

23.6.13 IDCLOR0—IDE Cylinder Low Out Register Device 0

Register (IDER—D22:F2) ....................................................................929

23.6.14 IDCHOR0—IDE Cylinder High Out Register Device 0

Register (IDER—D22:F2) ....................................................................929

23.6.15 IDCHOR1—IDE Cylinder High Out Register Device 1

Register (IDER—D22:F2) ....................................................................929

30 Datasheet

23.6.16 IDECHIR—IDE Cylinder High In Register

(IDER—D22:F2)................................................................................ 930

23.6.17 IDEDHIR—IDE Drive/Head In Register

(IDER—D22:F2)................................................................................ 930

23.6.18 IDDHOR1—IDE Drive Head Out Register Device 1

Register (IDER—D22:F2).................................................................... 931

23.6.19 IDDHOR0—IDE Drive Head Out Register Device 0

Register (IDER—D22:F2).................................................................... 931

23.6.20 IDESD0R—IDE Status Device 0 Register

(IDER—D22:F2)................................................................................ 932

23.6.21 IDESD1R—IDE Status Device 1 Register

(IDER—D22:F2)................................................................................ 933

23.6.22 IDECR—IDE Command Register (IDER—D22:F2) ................................... 933

23.7 IDE BAR1 ....................................................................................................... 934

23.7.1 IDDCR—IDE Device Control Register (IDER—D22:F2)............................. 934

23.7.2 IDASR—IDE Alternate status Register (IDER—D22:F2) ........................... 934

23.8 IDE BAR4 ....................................................................................................... 935

23.8.1 IDEPBMCR—IDE Primary Bus Master Command

Register (IDER—D22:F2).................................................................... 936

23.8.2 IDEPBMDS0R—IDE Primary Bus Master Device

Specific 0 Register (IDER—D22:F2) ..................................................... 936

23.8.3 IDEPBMSR—IDE Primary Bus Master Status

Register (IDER—D22:F2).................................................................... 937

23.8.4 IDEPBMDS1R—IDE Primary Bus Master Device

Specific 1 Register (IDER—D22:F2) ..................................................... 937

23.8.5 IDEPBMDTPR0—IDE Primary Bus Master Descriptor

Table Pointer Byte 0 Register (IDER—D22:F2)....................................... 938

23.8.6 IDEPBMDTPR1—IDE Primary Bus Master Descriptor

Table Pointer Byte 1 Register (IDER—D22:F2)....................................... 938

23.8.7 IDEPBMDTPR2—IDE Primary Bus Master Descriptor

Table Pointer Byte 2 Register (IDER—D22:F2)....................................... 938

23.8.8 IDEPBMDTPR3—IDE Primary Bus Master Descriptor

Table Pointer Byte 3 Register (IDER—D22:F2)....................................... 938

23.8.9 IDESBMCR—IDE Secondary Bus Master Command

Register (IDER—D22:F2).................................................................... 939

23.8.10 IDESBMDS0R—IDE Secondary Bus Master Device

Specific 0 Register (IDER—D22:F2) ..................................................... 939

23.8.11 IDESBMSR—IDE Secondary Bus Master Status

Register (IDER—D22:F2).................................................................... 940

23.8.12 IDESBMDS1R—IDE Secondary Bus Master Device

Specific 1 Register (IDER—D22:F2) ..................................................... 940

23.8.13 IDESBMDTPR0—IDE Secondary Bus Master Descriptor

Table Pointer Byte 0 Register (IDER—D22:F2)....................................... 940

23.8.14 IDESBMDTPR1—IDE Secondary Bus Master Descriptor

Table Pointer Byte 1 Register (IDER—D22:F2)....................................... 941

23.8.15 IDESBMDTPR2—IDE Secondary Bus Master Descriptor

Table Pointer Byte 2 Register (IDER—D22:F2)....................................... 941

23.8.16 IDESBMDTPR3—IDE Secondary Bus Master Descriptor

Table Pointer Byte 3 Register (IDER—D22:F2)....................................... 941

23.9 Serial Port for Remote Keyboard and Text (KT)

Redirection (KT—D22:F3)................................................................................. 942

23.9.1 VVID—Vendor Identification Register (KT—D22:F3) ............................... 943

23.9.2 DID—Device Identification Register (KT—D22:F3).................................. 943

23.9.3 CMD—Command Register Register (KT—D22:F3)................................... 943

23.9.4 STS—Device Status Register (KT—D22:F3)........................................... 944

23.9.5 RID—Revision ID Register (KT—D22:F3) .............................................. 944

23.9.6 CC—Class Codes Register (KT—D22:F3) ............................................... 944

23.9.7 CLS—Cache Line Size Register (KT—D22:F3) ........................................ 945

23.9.8 KTIBA—KT IO Block Base Address Register

(KT—D22:F3) ................................................................................... 945

23.9.9 KTMBA—KT Memory Block Base Address Register

(KT—D22:F3) ................................................................................... 945

23.9.10 SVID—Subsystem Vendor ID Register (KT—D22:F3) .............................. 946

23.9.11 SID—Subsystem ID Register (KT—D22:F3)........................................... 946

23.9.12 CAP—Capabilities Pointer Register (KT—D22:F3) ................................... 946

23.9.13 INTR—Interrupt Information Register (KT—D22:F3)............................... 946

Datasheet 31

23.9.14 PID—PCI Power Management Capability ID Register

23.9.15 PC—PCI Power Management Capabilities ID Register

23.9.16 MID—Message Signaled Interrupt Capability ID

23.9.17 MC—Message Signaled Interrupt Message Control

23.9.18 MA—Message Signaled Interrupt Message Address

23.9.19 MAU—Message Signaled Interrupt Message Upper

23.9.20 MD—Message Signaled Interrupt Message Data

23.10 KT IO/ Memory Mapped Device Registers ............................................................949

23.10.1 KTRxBR—KT Receive Buffer Register (KT—D23:F3) ................................950

23.10.2 KTTHR—KT Transmit Holding Register (KT—D23:F3) ..............................950

23.10.3 KTDLLR—KT Divisor Latch LSB Register (KT—D23:F3) ............................951

23.10.4 KTIER—KT Interrupt Enable Register (KT—D23:F3)................................951

23.10.5 KTDLMR—KT Divisor Latch MSB Register (KT—D23:F3)........................... 952

23.10.6 KTIIR—KT Interrupt Identification Register

23.10.7 KTFCR—KT FIFO Control Register (KT—D23:F3).....................................953

23.10.8 KTLCR—KT Line Control Register (KT—D23:F3)......................................953

23.10.9 KTMCR—KT Modem Control Register (KT—D23:F3) ................................954

23.10.10 KTLSR—KT Line Status Register (KT—D23:F3).......................................955

23.10.11 KTMSR—KT Modem Status Register (KT—D23:F3)..................................956

(KT—D22:F3)....................................................................................947

(KT—D22:F3)....................................................................................947

Register (KT—D22:F3) .......................................................................947

Register (KT—D22:F3) .......................................................................948

Register (KT—D22:F3) .......................................................................948

Address Register (KT—D22:F3) ...........................................................948

Register (KT—D22:F3) .......................................................................949

(KT—D23:F3)....................................................................................952

Figures

2-1 PCH Interface Signals Block Diagram ......................................................................60

2-2 Example External RTC Circuit.................................................................................97

4-1 PCH High-Level Clock Diagram.............................................................................121

5-1 Generation of SERR# to Platform .........................................................................130

5-2 LPC Interface Diagram ........................................................................................140

5-3 PCH DMA Controller............................................................................................144

5-4 DMA Request Assertion through LDRQ# ................................................................147

5-5 TCO Legacy/Compatible Mode SMBus Configuration................................................194

5-6 Advanced TCO Mode...........................................................................................196

5-7 Serial Post over GPIO Reference Circuit.................................................................198

5-8 Flow for Port Enable / Device Present Bits..............................................................206

5-9 Serial Data transmitted over the SGPIO Interface ...................................................210

5-10 EHCI with USB 2.0 with Rate Matching Hub ...........................................................226

5-11 PCH Intel® Management Engine High-Level Block Diagram ......................................256

5-12 Flash Partition Boundary ..................................................................................... 260

5-13 Flash Descriptor Sections ....................................................................................261

5-14 Analog Port Characteristics ..................................................................................270

5-15 LVDS Signals and Swing Voltage ..........................................................................272

5-16 LVDS Clock and Data Relationship ........................................................................272

5-17 Panel Power Sequencing .....................................................................................273

5-18 HDMI Overview..................................................................................................274

5-19 DP Overview......................................................................................................275

5-20 SDVO Conceptual Block Diagram.......................................................................... 277

6-1 PCH Ballout (top view—left side) (Desktop) ...........................................................284

6-2 PCH Ballout (top view—right side) (Desktop) ......................................................... 285

6-3 PCH ballout (top View—Leff side) (Mobile Only)......................................................295

6-4 PCH ballout (top View—right side) (Mobile Only).....................................................296

6-5 PCH ballout (top view—left side) (Mobile SFF Only).................................................307

6-6 PCH ballout (top view—right side) (Mobile SFF Only)...............................................308

7-1 PCH Desktop Package Drawing............................................................................. 320

7-2 PCH B-Step Mobile Package Drawing.....................................................................322

7-3 PCH Mobile SFF Package Drawing .........................................................................324

8-1 G3 w/RTC Loss to S4/S5 Timing Diagram ..............................................................363

8-2 S5 to S0 Timing Diagram ....................................................................................363

32 Datasheet

8-3 S3/M3 to S0 Timing Diagram............................................................................... 364

8-4 S5/Moff - S5/M3 Timing Diagram......................................................................... 364

8-5 S0 to S5 Timing Diagram.................................................................................... 365

8-6 DRAMPWRGD Timing Diagram ............................................................................. 365

8-7 Clock Cycle Time ............................................................................................... 366

8-8 Transmitting Position (Data to Strobe).................................................................. 366

8-9 Clock Timing ..................................................................................................... 366

8-11 Setup and Hold Times ........................................................................................ 367

8-12 Float Delay ....................................................................................................... 367

8-13 Pulse Width....................................................................................................... 367

8-10 Valid Delay from Rising Clock Edge ...................................................................... 367

8-14 Output Enable Delay .......................................................................................... 368

8-15 USB Rise and Fall Times ..................................................................................... 368

8-16 USB Jitter ......................................................................................................... 368

8-17 USB EOP Width ................................................................................................. 369

8-18 SMBus/SMLINK Transaction ................................................................................ 369

8-19 SMBus/SMLINK Timeout ..................................................................................... 369

8-20 SPI Timings ...................................................................................................... 370

8-21 Intel® High Definition Audio Input and Output Timings ........................................... 370

8-22 Dual Channel Interface Timings ........................................................................... 371

8-23 Dual Channel Interface Timings ........................................................................... 371

8-24 LVDS Load and Transition Times.......................................................................... 371

8-25 Transmitting Position (Data to Strobe).................................................................. 372

8-26 PCI Express Transmitter Eye ............................................................................... 372

8-27 PCI Express Receiver Eye.................................................................................... 373

8-28 Measurement Points for Differential Waveforms. .................................................... 374

8-29 PCH Test Load................................................................................................... 375

8-30 Controller Link Receive Timings ........................................................................... 375

8-31 Controller Link Receive Slew Rate ........................................................................ 375

Tables

1-1 Industry Specifications ......................................................................................... 44

1-2 PCI Devices and Functions .................................................................................... 48

1-3 Intel® 5 Series Chipset Desktop SKUs .................................................................... 55

1-4 Intel® 5 Series Chipset Mobile SKUs....................................................................... 56

1-5 Intel® 3400 Series Chipset Server SKUs ................................................................. 57

2-1 Direct Media Interface Signals ............................................................................... 61

2-2 PCI Express* Signals............................................................................................ 61

2-3 Firmware Hub Interface Signals ............................................................................. 62

2-4 PCI Interface Signals............................................................................................ 63

2-5 Serial ATA Interface Signals .................................................................................. 65

2-6 LPC Interface Signals ........................................................................................... 68

2-7 Interrupt Signals ................................................................................................. 68

2-8 USB Interface Signals........................................................................................... 69

2-9 Power Management Interface Signals ..................................................................... 71

2-10 Processor Interface Signals ................................................................................... 74

2-11 SM Bus Interface Signals ...................................................................................... 74

2-12 System Management Interface Signals ................................................................... 75

2-13 Real Time Clock Interface ..................................................................................... 75

2-14 Miscellaneous Signals ........................................................................................... 76

2-15 Intel® High Definition Audio Link Signals................................................................. 77

2-16 Controller Link Signals.......................................................................................... 78

2-17 Serial Peripheral Interface (SPI) Signals.................................................................. 78

2-18 Intel® Quiet System Technology Signals ................................................................. 79

2-19 JTAG Signals ....................................................................................................... 80

2-20 Clock Interface Signals ......................................................................................... 80

2-21 LVDS Interface Signals ......................................................................................... 82

2-22 Analog Display Interface Signals ............................................................................ 83

2-23 Intel® Flexible Display Interface Signals ................................................................. 84

2-24 Digital Display Interface Signals............................................................................. 84

2-25 General Purpose I/O Signals.................................................................................. 87

2-26 Manageability Signals ........................................................................................... 90

2-27 Power and Ground Signals .................................................................................... 91

2-28 Functional Strap Definitions................................................................................... 93

3-1 Integrated Pull-Up and Pull-Down Resistors ............................................................. 99

Datasheet 33

3-2 Power Plane and States for Output and I/O Signals for Desktop Configurations ........... 101

3-3 Power Plane and States for Output and I/O Signals for Mobile Configurations ............. 106

3-4 Power Plane for Input Signals for Desktop Configurations ........................................112

3-5 Power Plane for Input Signals for Mobile Configurations...........................................115

4-1 PCH System Clock Inputs ....................................................................................119

4-2 PCH System Clock Outputs ..................................................................................120

5-1 PCI Bridge Initiator Cycle Types ...........................................................................123

5-2 Type 1 Address Format ....................................................................................... 126

5-3 MSI versus PCI IRQ Actions .................................................................................128

5-4 LAN Mode Support..............................................................................................135

5-5 LPC Cycle Types Supported .................................................................................140

5-6 Start Field Bit Definitions.....................................................................................141

5-7 Cycle Type Bit Definitions....................................................................................141

5-8 Transfer Size Bit Definition ..................................................................................141

5-9 SYNC Bit Definition.............................................................................................142

5-10 DMA Transfer Size.............................................................................................. 145

5-11 Address Shifting in 16-Bit I/O DMA Transfers ......................................................... 146

5-12 Counter Operating Modes ....................................................................................151

5-13 Interrupt Controller Core Connections ...................................................................153

5-14 Interrupt Status Registers ...................................................................................154

5-15 Content of Interrupt Vector Byte ..........................................................................154

5-16 APIC Interrupt Mapping1.....................................................................................160

5-17 Stop Frame Explanation ......................................................................................163

5-18 Data Frame Format ............................................................................................ 164

5-19 Configuration Bits Reset by RTCRST# Assertion...................................................... 167

5-20 INIT# Going Active.............................................................................................169

5-21 NMI Sources......................................................................................................170

5-22 General Power States for Systems Using the PCH ...................................................171

5-23 State Transition Rules for the PCH ........................................................................172

5-24 System Power Plane ...........................................................................................173

5-25 Causes of SMI and SCI ....................................................................................... 174

5-26 Sleep Types.......................................................................................................178

5-27 GPI Wake Events ...............................................................................................180

5-28 Transitions Due to Power Failure .......................................................................... 181

5-29 Transitions Due to Power Button ..........................................................................182

5-30 Transitions Due to RI# Signal ..............................................................................183

5-31 Write Only Registers with Read Paths in ALT Access Mode........................................185

5-32 PIC Reserved Bits Return Values ..........................................................................187

5-33 Register Write Accesses in ALT Access Mode ..........................................................187

5-34 SLP_LAN# Pin Behavior ...................................................................................... 189

5-35 Causes of Host and Global Resets.........................................................................191

5-36 Event Transitions that Cause Messages .................................................................195

5-37 Multi-activity LED message type........................................................................... 209

5-38 Legacy Replacement Routing ...............................................................................212

5-39 Debug Port Behavior...........................................................................................220

5-40 I

2

C Block Read...................................................................................................230

5-41 Enable for SMBALERT# ....................................................................................... 232

5-42 Enables for SMBus Slave Write and SMBus Host Events...........................................233

5-43 Enables for the Host Notify Command ...................................................................233

5-44 Slave Write Registers..........................................................................................234

5-45 Command Types ................................................................................................235

5-46 Slave Read Cycle Format.....................................................................................236

5-47 Data Values for Slave Read Registers....................................................................236

5-48 Host Notify Format ............................................................................................. 239

5-49 I2C Write Commands to the ME............................................................................ 243

5-50 Block Read Command – Byte Definition.................................................................244

5-51 Processor Core Read Data Definition .....................................................................246

5-52 Region Size versus Erase Granularity of Flash Components ......................................259

5-53 Region Access Control Table ................................................................................262

5-54 Hardware Sequencing Commands and Opcode Requirements ...................................265

5-55 Flash Protection Mechanism Summary ..................................................................266

5-56 Recommended Pinout for 8-Pin Serial Flash Device .................................................267

5-57 Recommended Pinout for 16-Pin Serial Flash Device ...............................................268

5-58 PCH supported Audio formats over HDMI and DisplayPort* ......................................276

5-59 PCH Digital Display Port Pin Mapping.....................................................................278

5-60 Display Co-Existence Table.................................................................................. 279

6-1 PCH Ballout by Signal name (Desktop Only) ........................................................... 286

34 Datasheet

6-2 PCH Ballout by Signal name (Mobile Only)............................................................. 297

6-3 PCH Ballout by Signal name (Mobile SFF Only)....................................................... 309

8-1 Storage Conditions............................................................................................. 325

8-2 Mobile Thermal Design Power.............................................................................. 326

8-3 PCH Absolute Maximum Ratings........................................................................... 326

8-4 PCH Power Supply Range.................................................................................... 327

8-5 Measured ICC (Desktop Only) ............................................................................. 327

8-6 Measured ICC (Mobile Only)................................................................................ 328

8-7 Measured ICC (SFF Only)................................................................................... 329

8-8 DC Characteristic Input Signal Association............................................................. 330

8-9 DC Input Characteristics ..................................................................................... 332

8-10 DC Characteristic Output Signal Association .......................................................... 334

8-11 DC Output Characteristics ................................................................................... 337

8-12 Other DC Characteristics..................................................................................... 339

8-13 Signal Groups ................................................................................................... 340

8-14 CRT DAC Signal Group DC Characteristics: Functional Operating Range

(VccADAC = 3.3 V ±5%) .................................................................................... 340

8-15 LVDS Interface: Functional Operating Range (VccALVDS = 3.3 V ±5%) .................... 341

8-16 Display Port Auxiliary Signal Group DC Characteristics ............................................ 341

8-17 PCI Express* Interface Timings ........................................................................... 342

8-18 HDMI Interface Timings (DDP[D:B][3:0]).............................................................. 343

8-19 SDVO Interface Timings...................................................................................... 343

8-20 DisplayPort Interface Timings (DDP[D:B][3:0])...................................................... 344

8-21 DisplayPort Aux Interface ................................................................................... 345

8-22 DDC Characteristics

DDC Signals: CRT_DDC_CLK, CRT_DDC_DATA, L_DDC_CLK, L_DDC_DATA, SDVO_CTRLCLK, SDVO_CTRLDATA, DDP[D:C]_CTRLCLK,

DDP[D:C]_CTRLDATA ....................................................................................................... 345

8-23 LVDS Interface AC characteristics at Various Frequencies ........................................ 346

8-24 CRT DAC AC Characteristics ................................................................................ 348

8-25 Clock Timings.................................................................................................... 348

8-26 PCI Interface Timing .......................................................................................... 352

8-27 Universal Serial Bus Timing................................................................................. 353

8-28 SATA Interface Timings ...................................................................................... 354

8-29 SMBus Timing ................................................................................................... 354

8-30 Intel® High Definition Audio Timing...................................................................... 355

8-31 LPC Timing ....................................................................................................... 355

8-32 Miscellaneous Timings ........................................................................................ 356

8-33 SPI Timings (20 MHz)......................................................................................... 356

8-34 SPI Timings (33 MHz)......................................................................................... 357

8-35 SPI Timings (50 MHz)......................................................................................... 357

8-36 SST Timings...................................................................................................... 358

8-37 PECI Timings..................................................................................................... 359

8-38 Controller Link Receive Timings ........................................................................... 359

8-39 Power Sequencing and Reset Signal Timings.......................................................... 360

9-1 PCI Devices and Functions .................................................................................. 378

9-2 Fixed I/O Ranges Decoded by Intel

®

PCH.............................................................. 379

9-3 Variable I/O Decode Ranges................................................................................ 382

9-4 Memory Decode Ranges from Processor Perspective ............................................... 383

10-1 Chipset Configuration Register Memory Map (Memory Space) .................................. 387

11-1 PCI Bridge Register Address Map (PCI-PCI—D30:F0) .............................................. 435

12-1 Gigabit LAN Configuration Registers Address Map

(Gigabit LAN—D25:F0) ....................................................................................... 453

13-1 LPC Interface PCI Register Address Map (LPC I/F—D31:F0) ..................................... 467

13-2 DMA Registers................................................................................................... 492

13-3 PIC Registers .................................................................................................... 503

13-4 APIC Direct Registers ......................................................................................... 511

13-5 APIC Indirect Registers....................................................................................... 511

13-6 RTC I/O Registers .............................................................................................. 516

13-7 RTC (Standard) RAM Bank .................................................................................. 517

13-8 Processor Interface PCI Register Address Map ....................................................... 521

13-9 Power Management PCI Register Address Map (PM—D31:F0)................................... 524

13-10 APM Register Map .............................................................................................. 531

13-11 ACPI and Legacy I/O Register Map ....................................................................... 532

13-12 TCO I/O Register Address Map............................................................................. 551

13-13 Registers to Control GPIO Address Map................................................................. 558

14-1 SATA Controller PCI Register Address Map (SATA–D31:F2)...................................... 571

14-2 Bus Master IDE I/O Register Address Map ............................................................. 600

Datasheet 35

14-3 AHCI Register Address Map .................................................................................608

14-4 Generic Host Controller Register Address Map ........................................................609

14-5 Port [5:0] DMA Register Address Map ...................................................................619

15-1 SATA Controller PCI Register Address Map (SATA–D31:F5) ......................................637

15-2 Bus Master IDE I/O Register Address Map .............................................................655

16-1 USB EHCI PCI Register Address Map (USB EHCI—D29:F0, D26:F0) ........................... 663

16-2 Enhanced Host Controller Capability Registers........................................................685

16-3 Enhanced Host Controller Operational Register Address Map ....................................688

16-4 Debug Port Register Address Map.........................................................................701

17-1 Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0)................................................................... 705

17-2 Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0)................................................................... 728

18-1 SMBus Controller PCI Register Address Map (SMBus—D31:F3) .................................757

18-2 SMBus I/O and Memory Mapped I/O Register Address Map ......................................764

19-1 PCI Express* Configuration Registers Address Map

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/) ....................................................775

20-1 Memory-Mapped Registers ..................................................................................815

21-1 Serial Peripheral Interface (SPI) Register Address Map

(SPI Memory Mapped Configuration Registers) ....................................................... 823

21-2 Gigabit LAN SPI Flash Program Register Address Map

(GbE LAN Memory Mapped Configuration Registers)................................................846

22-1 Thermal Sensor Register Address Map...................................................................859

22-2 Thermal Memory Mapped Configuration Register Address Map..................................868

23-1 Intel® MEI Configuration Registers Address Map

(MEI—D22:F0)................................................................................................... 887

23-1 MEI1 Configuration Registers Address Map

(MEI—D22:F1)................................................................................................... 899

23-2 MEI MMIO Register Address Map (VE—D23:F0) ......................................................909

23-3 MEI MMIO Register Address Map (VE—D23:F0) ......................................................912

23-4 IDE Function for remote boot and Installations PT IDER Register Address Map ............ 915

23-5 IDE BAR0 Register Address Map...........................................................................924

23-6 IDE BAR4 Register Address Map...........................................................................935

23-7 Serial Port for Remote Keyboard and Text (KT) Redirection Register

Address Map...................................................................................................... 942

23-8 KT IO/ Memory Mapped Device Register Address Map .............................................949

36 Datasheet

Revision History

Revision
Number

001 • Initial release. September 2009

• SATA Port Multiplier Removal

• 1.5V On-Die PLL Voltage Regulator Support Removal

• Update on Note 9 for Table 2-25, “General Purpose I/O Signal”

• Updated GPIO15 and GPIO27 in Table 2-28, “Functional Strap Definition”

• Added Measure Icc for SFF Table

• Updated Measured Icc for Desktop and Mobile Tables

• Updated Table 2-20 CLKOUTFLEX0 type

• Updated PCIe Port Configurations

• Updated PME_B0_S5_DIS Bit Discription

• Updated Section 5.14.2.2 Advanced TCO Mode

002

003

• Updated Table 9-9 Other DC Characteristics

• Updated GCAP_ID Default Value

• Updated t240 and t218 Power Sequencing and Reset Signal Timings

• Added XTAL25 DC and AC Characteristics

• Added CEV1 Core Energy Value 1 Register to Section 22.2

• Updated Section 14.4.1.11 VSP - Vendor Specific Default Value

• Updated Desktop SKUs Definitions

• Added BCLK Input to AC Characteristics

• Updated MPC2- Miscellaneous Port Configuration Register 2

• Updated DMIC - DMI Control Register Description

• Updated NV_CLE Nomical pull-down in Table 3-1. Integrated Pull-ups and Pull-Downs

• Updated Section 10.1.62 BUC - Backed Up Control Register

®

• Addeed Intel

• Updated bit description for USBIRA—USB Initialization Register A

• Updated Table 2-29. Intel
and Revision ID Table.

• Updated bit description for GP_RST_SEL1 — GPIO Reset Select register

• Updated bit description for GP_RST_SEL2 — GPIO Reset Select register

• Updated bit description for GP_RST_SEL3 — GPIO Reset Select register

• Update Table 3-1 to include SPI_CS0#

• Updated Table 8-1, Storage Conditions

• Added Section 5.27.2.9 through Section 5.27.2.14

• Updated Table 8-14, PCI Express* Interface Timings

• Updated Section 21.1.2, HSFS—Hardware Sequencing Flash Status Register

B55 Express Chipset

®

Description Revision Date

January 2010

5 Series Chipset and Intel® 3400 Series Chipset Device

June 2010

Datasheet 37

Revision

Number

004

Description Revision Date

• Updated Table 1-1, Industry Standards

• Updated Section 1.2, Overview
— Updated the initial set of bullets
—Updated Intel

®

Active Management Technology Section
— Updated Serial Over Lan (SOL) Function Section
—Added KVM Section
— Updated IDE-R Function Section
— Added PCH Display Interface Section
—Added Intel

®

Flexible Display Interconnect (FDI) Section

• Updated Table 2-5, Serial ATA Interface Signals
— Added TEMP_ALERT# to the SATA5GP /GPIO49 / TEMP_ALERT# Signals

— SCLOCK/GPIO22 Signal

• Added note under Table 2-7, “Interrupt Signals”

• Updated Table 2-8, “USB Interface Signals” Overcurrent Indicators description.

• Updated Table 2-9, “Power Management Interface Signals” description for SLP_LAN#/

GPIO29.

• Update Table 2-15, “Intel High Definition Audio LInk Signals” description for

HDA_DOCK_RST#/GPIO13.

• Added Note 12 to Table 2-25, “General Purpose I/O SIgnals”.

• Updated Table 2-27, “Power and Ground Signals” description for DcpSusByp.

• Updated Table 2-28, “Functional Strap Definitions” Comment column for GNT3#/

GPIO55.

• Updated Table 2-29, “Intel 5 Series Chipset and Intel 3400 Series Chipset Device and

Revision ID Table”.

• Added Note to Section 5.2, “PCI Express* Root Ports (D28:F0, F1,F2,F3,F4,F5,F6,F7)”.

• Added note on wake up settings to Section 5.3.4.1.1, “Advanced Power Management

Wake Up” and Section 5.3.4.1.2, “ACPI Power Management Wake Up”.

• Updated Table 5-27, “Causes of Wake Events”.

• ”Added Section 5.13.10.5, “SLP_LAN# Pin Behavior” and Section 5.13.10.6, “RTCRST#

and SRTCRST#”.

• Updated Section 5.13.13, “Reset Behavior”.

• Updated Section 5.14.2.2, “Advanced TCO Mode”.

• Updated Section 5.16.11, “SGPIO Signals”.

• Added note to Block Read/Write command in Section 5.20.1.1, “Command Protocols”

for the SMBus Host Controller.

• Updated Section 5.27, “PCH Display Interfaces”.

• Updated Section 8.2, “Absolute Maximum and Minimum Ratings”.

• Updated VOL3 and VOH3 in Table 8-10, “DC Output Characteristics”.

• Updated VccVRM in Table 8-11, “Other DC Characteristics”. Also, Added Note 3 to the

table.

• Added notes to Table 8-16, “PCI Express* Interface Timings”, Table 8-17, “HDMI

Interface Timings”, and Table 8-18, “SDVO Interface Timings“.

• Added SMLink0 Clock timings to Table 8-24, “Clock Timings”.

• Updated Table 8-28, “SMBus Timing”.

• Updated Table 8-37, “Controller Link Receive Timings”.

• Added Note 18 to Table 8-18, “Power Sequencing and Reset Signal Timings” for

LAN_RST# timing.

• Added Figure 8-30, “Controller Link Receive Timings” and Figure 8-31, “Controller Link

Receive Slew Rate”.

January 2012

38 Datasheet

Revision
Number

004

Description Revision Date

• Chapter 9, “Register and Memory Mapping”
— Added R/WL register access attribute definition and updated the definition for

“Default”.
— Added notes to Table 9-1, “PCI Devices and Functions”.
— Updated Table 9-2, “Fixed I/O Ranges Decoded by Intel PCH”.
— Updated Table 9-3, “Variable I/O Decode Ranges”.
— Updated Table 9-4, “Memory Decode Ranges from Processor Perspective”.
— Updated Section 9.4.1, “Boot-Block Update Scheme”.

• Updated Section 10.1.9, “LCAP—Link Capabilities Register” Bits 17:15 L1 Exit Latency
(EL1).

• Updated Section 10.1.10, “LCTL—Link Control Register”.

• Updated Section 10.1.15, “RPFN—Root Port Function Number and Hide for PCI
Express* Root Ports” for bits 30:28 and 26:24.

• Updated Section 10.1.43, “OIC— Other Interrupt Control Register” note below table.

• Updated Section 10.1.62, “BUC—Backed Up control Register” bit 5 and bit 0.

• Updated Section 10.1.64, “CG—Clock Gating Register” bits 29:28.

• Updated Section 10.1.69, “USBOCM2—Overcurrent MAP Register 2”.

• Added Section 13.1.12, “CAPP—Capability List Pointer Register (LPC I/F—D31:Fo)

• Updated Section 14.1.22, “IDE_TIM—IDE Timing Register (SATA–D31:F2)”.

• Added Section 14.1.23, “SIDETIM—Slave IDE Timing Register”, Section 14.1.24,
“SDMA_CNT—Synchronous DMA Control Register”, Section 14.1.25,
“SDMA_TIM—Synchronous DMA Timing Register”, and Section 14.1.26,
“IDE_CONFIG—IDE I/O COnfiguration Register”.

• Updated Section 14.1.37, “SCLKGC—SATA Clock General Configuration Register”.

• Updated Section 14.3.2.3, “PxSERR—Serial ATA Error Register (B31:F2)” bit 23.

• Updated Section 14.4.1.10, “RSTF—RST Feature Capabilities Register” bit 7.

• Updated Section 14.4.1.12, “Intel

®

RST Feature Capabilities”.

• Updated Section 14.4.2.5, “PxIS—Port [5:0] Interrupt Status Register (D31:F2)” and
Section 14.4.2.6, “PxIE—Port [5:0] Interrupt Enable Register 9D31:F2)”

• Updated Section 15.1.21, “IDE_TIM—IDE Timing Register (SATA–D31:F5)”

• Added Section 15.1.22, “SDMA_CNT—Synchronous DMA Control Register”, Section

15.1.23, “SDMB_TIM—Synchronous DMA Timing Register”, and Section 15.1.24,
“IDE_CONFIG—IDE I/O COnfiguration Register”.

• Added note to Section 16.1, “USB EHCI Configuration Registers (USB EHCI—D29:F0,
D26:F0)”.

• Updated Section 16.1.20, “PWR_CNTL_STS—Power Managment Control/Status
Register” bits 1:0.

• Updated Section 16.1.31, “EHCIR1—EHCI Initialization Register 1”

• Added Section 16.1.32, “EHCIIR2—EHCI Initialization Register 2, Section 16.1.38,
“EHCIIR3—EHCI Initialization Register 3”, and Section 16.1.39, “EHCIIR4—EHCI
Initialization Register 4”.

• Added Section 17.1.20, “HDINIT1—Intel High Definition Audio Initialization Register
1”.

• Updated Section 17.2.15, “SSYNC—Stream Synchronization Register”.

• Added note to Section 19.1, “PCI Express Configuration Registers (PCI
Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)”.

• Updated Section 21.1.2, “HSFS—Hardware Sequencing Flash Status Register” bit 13
and Section 21.4.2, “HSFS—Hardware Sequencing Flash Status Register” bit 13

• Updated Section 22.1.3, “CMD—Command” bit 2.

• Updated Section 22.2.5, “TSTTP—Thermal Sensor Temperature Trip Point Register” bits
23:16.

• Updated Section 22.2.12, “PTA—P CH Tem peratur e Adju st”.

January 2012

Datasheet 39

Platform Controller Hub (PCH)
Features

 Direct Media Interface

— 10 Gb/s each direction, full duplex
— Transparent to software

 PCI Express*

— NEW: 8 PCI Express root ports
— NEW: PCI Express 2.0 specification running at

2.5 GT/s.

— NEW: Ports 1–4 or Ports 5–8 can independently

be configured to support four x1s, two x2s, one
x2 and 2 x1s, or one x4 port widths.

— Support for full 2.5 Gb/s bandwidth in each

direction per x1 lane

— Module based Hot-Plug supported (such as,

ExpressCard*)

 PCI Bus Interface

— Supports PCI Rev 2.3 Specification at 33 MHz
— Four available PCI REQ/GNT pairs
— Support for 64-bit addressing on PCI using DAC

protocol

 Integrated Serial ATA Host Controller

— Up to six SATA ports
— Data transfer rates up to 3.0 Gb/s

(300 MB/s).

— Integrated AHCI controller

 External SATA support

— NEW: Port Disable Capability

 Intel

®

Rapid Storage Technology

— Configures the PCH SATA controller as a RAID

controller supporting RAID 0/1/5/10

 Intel

®

High Definition Audio Interface

— PCI Express endpoint
— Independent Bus Master logic for eight general

purpose streams: four input and four output
— Support four external Codecs
— Supports variable length stream slots
— Supports multichannel, 32-bit sample depth,

192 kHz sample rate output
— Provides mic array support
— Allows for non-48 kHz sampling output
— Support for ACPI Device States
—Low Voltage Mode

 Intel

 Simple Serial Transport (SST) 1.0 Bus and Platform

®

Quiet System Technology

— Four TACH signals and Four PWM signals

Environmental Control Interface (PECI)

 USB 2.0

— Two EHCI Host Controllers, supporting up to

fourteen external ports
—Per-Port-Disable Capability
— Includes up to two USB 2.0 High-speed Debug

Ports
— Supports wake-up from sleeping states S1–S4
— Supports legacy Keyboard/Mouse software

 Integrated Gigabit LAN Controller

— NEW: PCI Express* connection
— Integrated ASF Management Controller
— Network security with System Defense
— Supports IEEE 802.3
— 10/100/1000 Mbps Ethernet Support
— Jumbo Frame Support

 Intel

 Intel
 Intel
 Power Management Logic

®

Active Management Technology with System

Defense

— NEW: Network Outbreak Containment Heuristics

®

I/O Virtualization (VT-d) Support

®

Trusted Execution Technology Support

— Supports ACPI 4.0a
— ACPI-defined power states (system level S0, S1,

S3, S4, and S5 states, various internal device

levels of Dx states, and processor driven C

states)
— ACPI Power Management Timer
—SMI# generation
— All registers readable/restorable for proper

resume from 0 V suspend states
— Support for A-based legacy power management

for non-ACPI implementations

 External Glue Integration

— Integrated Pull-up, Pull-down and Series

Termination resistors on processor interface
— Integrated Pull-down and Series resistors on USB

 Enhanced DMA Controller

— Two cascaded 8237 DMA controllers
— Supports LPC DMA

40 Datasheet

 SMBus

— Faster speed, up to 100 kbps
— Flexible SMBus/SMLink architecture to optimize

for ASF

— Provides independent manageability bus through

SMLink interface
— Supports SMBus 2.0 Specification
— Host interface allows processor to communicate

using SMBus
— Slave interface allows an internal or external

Microcontroller to access system resources
— Compatible with most two-wire components that

are also I

 High Precision Event Timers

— Advanced operating system interrupt scheduling

 Timers Based on 8254

— System timer, Refresh request, Speaker tone

2

C compatible

output

 Real-Time Clock

— 256-byte battery-backed CMOS RAM
— Integrated oscillator components
— Lower Power DC/DC Converter implementation

 System TCO Reduction Circuits

— Timers to generate SMI# and Reset upon

detection of system hang
— Timers to detect improper processor reset
— Integrated processor frequency strap logic
— Supports ability to disable external devices

 Serial Peripheral Interface (SPI)

— Supports up to two SPI devices
— Supports 20 MHz, 33 MHz, and 50 MHz SPI

devices
— Support up to two different erase granularities

 Interrupt Controller

— Supports up to eight PCI interrupt pins
— Supports PCI 2.3 Message Signaled Interrupts
— Two cascaded 8259 with 15 interrupts
— Integrated I/O APIC capability with 24 interrupts
— Supports Processor System Bus interrupt

delivery

 1.05 V operation with 1.5 V and 3.3 V I/O

— 5 V tolerant buffers on PCI, USB and selected

Legacy signals

 1.05 V Core Voltage
 Five Integrated Voltage Regulators for different

power rails

 Firmware Hub Interface supports BIOS Memory size

up to 8 MB

 Low Pin Count (LPC) I/F

— Supports two Master/DMA devices.
— Support for Security Device (Trusted Platform

Module) connected to LPC.

 GPIO

— TTL, Open-Drain, Inversion
—GPIO lock down

 Package

— 27 mm x 27 mm FCBGA (Desktop Only)
— 27 mm x 25 mm FCBGA (Mobile Only)
— 22 mm x 20 mm FCBGA (Mobile SFF Only)

 Analog Display Port
 Digital Display

— Three Digital Display ports capable of supporting

HDMI/DVI and Display port
— One Digital Display port supporting SDVO
—LDVS (Mobile Only)

 Intel
 JTAG

®

Anti-Theft Technology

— Boundary Scan for testing during board

manufacturing

Note: Not all features are available on all PCH SKUs. See Section 1.3 for more details.

§ §

Datasheet 41

42 Datasheet

Introduction

1 Introduction

1.1 About This Manual

This document is intended for Original Equipment Manufacturers and BIOS vendors
creating Intel

®

5 Series Chipset and Intel® 3400 Series Chipset based products. This

document is for the following components:

•Intel® 5 Series Chipset

—Intel® P55 Express Chipset

—Intel® H55 Express Chipset

—Intel® H57 Express Chipset

—Intel® Q57 Express Chipset

—Intel

®

B55 Express Chipset

—Intel® PM55 Express Chipset

—Intel® QM57 Express Chipset

—Intel® HM55 Express Chipset

—Intel® HM57 Express Chipset

—Intel® QS57 Express Chipset

•Intel® 3400 Series Chipset

—Intel® 3400 Chipset

—Intel® 3420 Chipset

—Intel® 3450 Chipset

Section 1.3 provides high-level feature differences for the Intel® 5 Series Chipset and

®

3400 Series Chipset.

Intel

Note: Throughout this document, PCH is used as a general term and refers to the Intel® 5

Series Chipset and Intel

Note: Throughout this document, the term “Desktop” refers to information that is for the

®

Intel

P55 Express Chipset, Intel® H55 Express Chipset, Intel® H57 Express Chipset,

®

Q57 Express Chipset, Intel

Intel
3420 Chipset, Intel

Throughout this document, the term “Mobile Only” refers to information that is for the

®

PM55 Express Chipset, Intel® QM57 Express Chipset, Intel® HM55 Express

Intel
Chipset, Intel

®

HM57 Express Chipset, and the Intel® QS57 Express Chipset, unless

®

3400 Series Chipset, unless specifically noted otherwise.

®

®

3450 Chipset, unless specifically noted otherwise.

B55 Express Chipset, Intel

®

3400 Chipset, Intel®

specifically noted otherwise.

This manual assumes a working knowledge of the vocabulary and principles of PCI
Express*, USB, AHCI, SATA, Intel

®

High Definition Audio (Intel® HD Audio), SMBus,
PCI, ACPI, and LPC. Although some details of these features are described within this
manual, see the individual industry specifications listed in Table 1-1 for the complete
details.

Datasheet 43

Table 1-1. Industry Specifications

Specification Location

PCI Express* Base Specification, Revision 1.1 http://www.pcisig.com/specifications

PCI Express* Base Specification, Revision 2.0 http://www.pcisig.com/specifications

Low Pin Count Interface Specification, Revision 1.1
(LPC)

System Management Bus Specification, Version 2.0
(SMBus)

PCI Local Bus Specification, Revision 2.3 (PCI) http://www.pcisig.com/specifications

PCI Power Management Specification, Revision 1.2 http://www.pcisig.com/specifications

SFF-8485 Specification for Serial GPIO (SGPIO) Bus,
Revision 0.7

Advanced Host Controller Interface specification for
Serial ATA, Revision 1.2

®

Intel

High Definition Audio Specification, Revision

1.0

Universal Serial Bus Specification (USB), Revision 2.0 http://www.usb.org/developers/docs

Advanced Configuration and Power Interface, Version

3.0b (ACPI)

Enhanced Host Controller Interface Specification for
Universal Serial Bus, Revision 1.0 (EHCI)

Serial ATA Specification, Revision 2.5 http://www.serialata.org/

Serial ATA II: Extensions to Serial ATA 1.0, Revision

1.0

Serial ATA II Cables and Connectors Volume 2 Gold http://www.serialata.org/

Alert Standard Format Specification, Version 1.03 http://www.dmtf.org/standards/asf

IEEE 802.3 Fast Ethernet http://standards.ieee.org/getieee802/

AT Attachment - 6 with Packet Interface (ATA/ATAPI -

6)

IA-PC HPET (High Precision Event Timers)
Specification, Revision 0.98a

TPM Specification 1.02, Level 2 Revision 103

®

Intel

Virtualization Technology

Introduction

http://developer.intel.com/design/
chipsets/industry/lpc.htm

http://www.smbus.org/specs/

ftp://ftp.seagate.com/sff/SFF-8485.PDF

http://www.intel.com/technology/
serialata/ahci.htm

http://www.intel.com/standards/
hdaudio/

http://www.acpi.info/spec.htm

http://developer.intel.com/technology/
usb/ehcispec.htm

http://www.serialata.org/

http://T13.org (T13 1410D)

http://www.intel.com/hardwaredesign/
hpetspec.htm

http://www.trustedcomputinggroup.org/
specs/TPM

http://www.intel.com/technology/
platform-technology/virtualization/
index.htm

44 Datasheet

Introduction

Chapter 1. Introduction

Chapter 1 introduces the PCH and provides information on manual organization and

gives a general overview of the PCH.

Chapter 2. Signal Description

Chapter 2 provides a block diagram of the PCH and a detailed description of each

signal. Signals are arranged according to interface and details are provided as to the
drive characteristics (Input/Output, Open Drain, etc.) of all signals.

Chapter 3. PCH Pin States

Chapter 3 provides a complete list of signals, their associated power well, their logic

level in each power state, and their logic level before and after reset.

Chapter 4. PCH and System Clock Domains

Chapter 4 provides a list of each clock domain associated with the PCH in an Intel

Series Chipset or Intel

®

3400 Series Chipset based system.

®

5

Chapter 5. Functional Description

Chapter 5 provides a detailed description of the functions in the PCH. All PCI buses,

devices and functions in this manual are abbreviated using the following nomenclature;
Bus:Device:Function. This manual abbreviates buses as B0 and B1, devices as D22,
D25, D25, D26, D27, D28, D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5,
F6 and F7. For example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8
Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and
can be considered to be Bus 0. Note that the PCH external PCI bus is typically Bus 1,
but may be assigned a different number depending upon system configuration.

Chapter 6. Ballout Definition

Chapter 6 provides a table of each signal and its ball assignment in the package.

Chapter 7. Package Information

Chapter 7 provides drawings of the physical dimensions and characteristics of the

package.

Chapter 8. Electrical Characteristics

Chapter 8 provides all AC and DC characteristics including detailed timing diagrams.

Chapter 9. Register and Memory Mappings

Chapter 9 provides an overview of the registers, fixed I/O ranges, variable I/O ranges

and memory ranges decoded by the PCH.

Chapter 10. Chipset Configuration Registers

Chapter 10 provides a detailed description of all registers and base functionality that is

related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI
Express*). It contains the root complex register block, which describes the behavior of
the upstream internal link.

Chapter 11. PCI-to-PCI Bridge Registers

Chapter 11 provides a detailed description of all registers that reside in the PCI-to-PCI

bridge. This bridge resides at Device 30, Function 0 (D30:F0).

Chapter 12. Integrated LAN Controller Registers

Chapter 12 provides a detailed description of all registers that reside in the PCH’s

integrated LAN controller. The integrated LAN Controller resides at Device 25, Function
0 (D25:F0).

Chapter 13. LPC Bridge Registers

Chapter 13 provides a detailed description of all registers that reside in the LPC bridge.

This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers
for many different units within the PCH including DMA, Timers, Interrupts, Processor
Interface, GPIO, Power Management, System Management and RTC.

Datasheet 45

Introduction

Chapter 14. SATA Controller Registers

Chapter 14 provides a detailed description of all registers that reside in the SATA

controller #1. This controller resides at Device 31, Function 2 (D31:F2).

Chapter 15. SATA Controller Registers

Chapter 15 provides a detailed description of all registers that reside in the SATA

controller #2. This controller resides at Device 31, Function 5 (D31:F5).

Chapter 16. EHCI Controller Registers

Chapter 16 provides a detailed description of all registers that reside in the two EHCI

host controllers. These controllers reside at Device 29, Function 0 (D29:F0) and Device
26, Function 0 (D26:F0).

Chapter 17. Intel

Chapter 17 provides a detailed description of all registers that reside in the Intel

®

High Definition Audio Controller Registers

®

High

Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0).

Chapter 18. SMBus Controller Registers

Chapter 18 provides a detailed description of all registers that reside in the SMBus

controller. This controller resides at Device 31, Function 3 (D31:F3).

Chapter 19. PCI Express* Port Controller Registers

Chapter 19 provides a detailed description of all registers that reside in the PCI Express

controller. This controller resides at Device 28, Functions 0 to 5 (D28:F0-F7).

Chapter 20. High Precision Event Timers Registers

Chapter 20 provides a detailed description of all registers that reside in the multimedia

timer memory mapped register space.

Chapter 21. Serial Peripheral Interface Registers

Chapter 21 provides a detailed description of all registers that reside in the SPI

memory mapped register space.

Chapter 22. Thermal Sensors

Chapter 22 provides a detailed description of all registers that reside in the thermal

sensors PCI configuration space. The registers reside at Device 31, Function 6
(D31:F6).

Chapter 23. Intel

®

Management Engine (Intel® ME)

Chapter 23 provides a detailed description of all registers that reside in the Intel ME

controller. The registers reside at Device 22, Function 0 (D22:F0).

46 Datasheet

Introduction

1.2 Overview

The PCH provides extensive I/O support. Functions and capabilities include:

• PCI Express* Base Specification, Revision 2.0 support for up to eight ports

• PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations
(supports up to four Req/Gnt pairs)

• ACPI Power Management Logic Support, Revision 3.0b

• Enhanced DMA controller, interrupt controller, and timer functions

• Integrated Serial ATA host controllers with independent DMA operation on up to six

ports

• USB host interface with support for up to fourteen USB ports; two EHCI high-speed

USB 2.0 Host controllers and 2 rate matching hubs

• Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense

• System Management Bus (SMBus) Specification, Version 2.0 with additional

support for I

• Supports Intel® High Definition Audio

• Supports Intel® Rapid Storage Technology

• Supports Intel® Active Management Technology

• Supports Intel® Virtualization Technology for Directed I/O

• Supports Intel® Trusted Execution Technology

• Supports Intel® Flexible Display Interconnect (Intel® FDI)

• Supports buffered mode generating extra clocks from a clock chip

• Analog and Digital Display ports

—Analog CRT
—HDMI
—DVI
—DisplayPort 1.1
—SDVO
— LVDS (Mobile Only)
— Embedded DisplayPort

• Low Pin Count (LPC) interface

• Firmware Hub (FWH) interface support

• Serial Peripheral Interface (SPI) support

•Intel® Quiet System Technology (Desktop only)

•Intel® Anti-Theft Technology

• JTAG Boundary Scan support

2

C devices

The PCH incorporates a variety of PCI devices and functions, as shown in Table 1-2.
They are divided into eight logical devices. The first is the DMI-To-PCI bridge (Device

30). The second device (Device 31) contains most of the standard PCI functions that
always existed in the PCI-to-ISA bridges (South Bridges), such as the Intel

®

PIIX4. The
third and fourth (Device 29 and Device 26) are the USB host controller devices. The
fifth (Device 28) is the PCI Express device. The sixth (Device 27) is the HD Audio
controller device, and the seventh (Device 25) is the Gigabit Ethernet controller device.
The eighth (Device 22) is the Intel® Management Engine Interface Controller.

Datasheet 47

Table 1-2. PCI Devices and Functions

Bus:Device:Function Function Description

Bus 0:Device 30:Function 0 DMI-to-PCI Bridge

Bus 0:Device 31:Function 0 LPC Controller

Bus 0:Device 31:Function 2 SATA Controller #1

Bus 0:Device 31:Function 5 SATA Controller #2

Bus 0:Device 31:Function 6 Thermal Subsystem

Bus 0:Device 31:Function 3 SMBus Controller

Bus 0:Device 29:Function 0 USB HS EHCI Controller #1

Bus 0:Device 26:Fucntion 0 USB HS EHCI Controller #2

Bus 0:Device 28:Function 0 PCI Express* Port 1

Bus 0:Device 28:Function 1 PCI Express Port 2

Bus 0:Device 28:Function 2 PCI Express Port 3

Bus 0:Device 28:Function 3 PCI Express Port 4

Bus 0:Device 28:Function 4 PCI Express Port 5

Bus 0:Device 28:Function 5 PCI Express Port 6

Bus 0:Device 28:Function 6 PCI Express Port 7

Bus 0:Device 28:Function 7 PCI Express Port 8

Bus 0:Device 27:Function 0 Intel

Bus 0:Device 25:Function 0 Gigabit Ethernet Controller

Bus 0:Device 22:Function 0 Intel

Bus 0:Device 22:Function 1 Intel

Bus 0:Device 22:Function 2 IDE-R

Bus 0:Device 22:Function 3 KT

1

3

®

High Definition Audio Controller

®

Management Engine Interface (Intel

®

Management Engine Interface (Intel

®

MEI) #1

®

MEI) #2

Introduction

NOTES:

1. The PCI-to-LPC bridge contains registers that control LPC, Power Management, System
Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA.

2. Device 26:Function 2 may be configured as Device 29:Function 3 during BIOS Post.

3. SATA Controller 2 is only visible when D31:F2 CC.SCC=01h.

48 Datasheet

Introduction

1.2.1 Capability Overview

The following sub-sections provide an overview of the PCH capabilities.

Direct Media Interface (DMI)

Direct Media Interface (DMI) is the chip-to-chip connection between the processor and
PCH. This high-speed interface integrates advanced priority-based servicing allowing
for concurrent traffic and true isochronous transfer capabilities. Base functionality is
completely software-transparent, permitting current and legacy software to operate
normally.

PCI Express* Interface

The PCH provides up to 8 PCI Express Root Ports, supporting the PCI Express Base
Specification, Revision 2.0. Each Root Port supports 2.5 Gb/s bandwidth in each

direction (5 Gb/s concurrent). PCI Express Root Ports 1-4 and Ports 5–8 can be
independently configured as four x1s, two x2s, one x2 and 2 x1s, or one x4 port
widths.

Serial ATA (SATA) Controller

The PCH has two integrated SATA host controllers that support independent DMA
operation on up to six ports and supports data transfer rates of up to 3.0 GB/s (300
MB/s). The SATA controller contains two modes of operation—a legacy mode using I/O
space, and an AHCI mode using memory space. Software that uses legacy mode will
not have AHCI capabilities.

The PCH supports the Serial ATA Specification, Revision 1.0a. The PCH also supports
several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0
Specification, Revision 1.0 (AHCI support is required for some elements).

AHCI

The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a
new programming interface for SATA host controllers. Platforms supporting AHCI may
take advantage of performance features such as no master/slave designation for SATA
devices—each device is treated as a master—and hardware-assisted native command
queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires
appropriate software support (such as an AHCI driver) and for some features, hardware
support in the SATA device or additional platform hardware. See Section 1.3 for details
on SKU feature availability.

Intel® Rapid Storage Technology

The PCH provides support for Intel® Rapid Storage Technology, providing both AHCI
(see above for details on AHCI) and integrated RAID functionality. The industry-leading
RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality on up to
6 SATA ports of the PCH. Matrix RAID support is provided to allow multiple RAID levels
to be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks.
Other RAID features include hot spare support, SMART alerting, and RAID 0 auto
replace. Software components include an Option ROM for pre-boot configuration and
boot functionality, a Microsoft Windows* compatible driver, and a user interface for
configuration and management of the RAID capability of the PCH. See Section 1.3 for
details on SKU feature availability.

Datasheet 49

Introduction

PCI Interface

The PCH PCI interface provides a 33 MHz, Revision 2.3 implementation. The PCH
integrates a PCI arbiter that supports up to four external PCI bus masters in addition to
the internal PCH requests. This allows for combinations of up to four PCI down devices
and PCI slots.

Low Pin Count (LPC) Interface

The PCH implements an LPC Interface as described in the LPC 1.1 Specification. The
Low Pin Count (LPC) bridge function of the PCH resides in PCI Device 31:Function 0. In
addition to the LPC bridge interface function, D31:F0 contains other functional units
including DMA, interrupt controllers, timers, power management, system management,
GPIO, and RTC.

Serial Peripheral Interface (SPI)

The PCH implements an SPI Interface as an alternative interface for the BIOS flash
device. An SPI flash device can be used as a replacement for the FWH, and is required
to support Gigabit Ethernet, Intel

®

Intel

Quiet System Technology. The PCH supports up to two SPI flash devices with

®

Active Management Technology and integrated

speeds of up to 50 MHz using two chip select pins.

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)

The DMA controller incorporates the logic of two 8237 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by­byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any
two of the seven DMA channels can be programmed to support fast Type-F transfers.
Channel 4 is reserved as a generic bus master request.

The PCH supports LPC DMA, which is similar to ISA DMA, through the PCH’s DMA
controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals
and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and
Increment modes are supported on the LPC interface.

The timer/counter block contains three counters that are equivalent in function to those
found in one 8254 programmable interval timer. These three counters are combined to
provide the system timer function, and speaker tone. The 14.31818 MHz oscillator
input provides the clock source for these three counters.

The PCH provides an ISA-Compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two 8259 interrupt controllers. The two interrupt
controllers are cascaded so that 14 external and two internal interrupts are possible. In
addition, the PCH supports a serial interrupt scheme.

All of the registers in these modules can be read and restored. This is required to save
and restore system state after power has been removed and restored to the platform.

Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA compatible Programmable Interrupt controller (PIC)
described in the previous section, the PCH incorporates the Advanced Programmable
Interrupt Controller (APIC).

50 Datasheet

Introduction

Universal Serial Bus (USB) Controllers

The PCH contains up to two Enhanced Host Controller Interface (EHCI) host controllers
that support USB high-speed signaling. High-speed USB 2.0 allows data transfers up to
480 Mb/s. The PCH also contains two Rate Matching Hubs (RMH) that support USB full­speed and low-speed signaling.

The PCH supports up to fourteen USB 2.0 ports. All fourteen ports are high-speed, full­speed, and low-speed capable.

Gigabit Ethernet Controller

The Gigabit Ethernet Controller provides a system interface using a PCI function. The
controller provides a full memory-mapped or IO mapped interface along with a 64 bit
address master support for systems using more than 4 GB of physical memory and
DMA (Direct Memory Addressing) mechanisms for high performance data transfers. Its
bus master capabilities enable the component to process high-level commands and
perform multiple operations; this lowers processor utilization by off-loading
communication tasks from the processor. Two large configurable transmit and receive
FIFOs (up to 20 KB each) help prevent data underruns and overruns while waiting for
bus accesses. This enables the integrated LAN controller to transmit data with
minimum interframe spacing (IFS).

The LAN controller can operate at multiple speeds (10/100/1000 MB/s) and in either
full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the
IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a
proprietary collision reduction mechanism. See Section 5.3 for details.

RTC

The PCH contains a Motorola* MC146818B-compatible real-time clock with 256 bytes
of battery-backed RAM. The real-time clock performs two key functions: keeping track
of the time of day and storing system data, even when the system is powered down.
The RTC operates on a 32.768 KHz crystal and a 3 V battery.

The RTC also supports two lockable memory ranges. By setting bits in the configuration
space, two 8-byte ranges can be locked to read and write accesses. This prevents
unauthorized reading of passwords or other system security information.

The RTC also supports a date alarm that allows for scheduling a wake up event up to 30
days in advance, rather than just 24 hours in advance.

GPIO

Various general purpose inputs and outputs are provided for custom system design.
The number of inputs and outputs varies depending on the PCH’s configuration.

Enhanced Power Management

The PCH power management functions include enhanced clock control and various low­power (suspend) states (such as, Suspend-to-RAM and Suspend-to-Disk). A hardware­based thermal management circuit permits software-independent entrance to low­power states. The the PCH contains full support for the Advanced Configuration and
Power Interface (ACPI) Specification, Revision 3.0a.

Datasheet 51

Introduction

Intel® Active Management Technology (Intel® AMT) (Not available on
all the I

Intel AMT is a fundamental component of Intel® vPro™ technology. Intel AMT is a set of
advanced manageability features developed as a direct result of IT customer feedback
gained through Intel market research. With the advent of powerful tools like the Intel®
System Defense Utility, the extensive feature set of Intel AMT easily integrates into any
network environment. See Section 1.3 for details on SKU feature availability.

ntel® 5 Series Chipset or Intel® 3400 Series Chipset SKUs)

Manageability

In addition to Intel® AMT, the PCH integrates several functions designed to manage the
system and lower the total cost of ownership (TCO) of the system. These system
management functions are designed to report errors, diagnose the system, and recover
from system lockups without the aid of an external microcontroller.

• TCO Timer. The PCH’s integrated programmable TCO timer is used to detect
system locks. The first expiration of the timer generates an SMI# that the system
can use to recover from a software lock. The second expiration of the timer causes
a system reset to recover from a hardware lock.

• Processor Present Indicator. The PCH looks for the processor to fetch the first
instruction after reset. If the processor does not fetch the first instruction, the PCH
will reboot the system.

• ECC Error Reporting. When detecting an ECC error, the host controller has the
ability to send one of several messages to the PCH. The host controller can instruct
the PCH to generate either an SMI#, NMI, SERR#, or TCO interrupt.

• Function Disable. The PCH provides the ability to disable the following integrated
functions: LAN, USB, LPC, Intel
disabled, these functions no longer decode I/O, memory, or PCI configuration
space. Also, no interrupts or power management events are generated from the
disabled functions.

• Intruder Detect. The PCH provides an input signal (INTRUDER#) that can be
attached to a switch that is activated by the system case being opened. The PCH
can be programmed to generate an SMI# or TCO interrupt due to an active
INTRUDER# signal.

®

HD Audio, SATA, PCI Express or SMBus. Once

System Management Bus (SMBus 2.0)

The PCH contains an SMBus Host interface that allows the processor to communicate
with SMBus slaves. This interface is compatible with most I
commands are implemented.

The PCH’s SMBus host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). Also, the PCH supports slave
functionality, including the Host Notify protocol. Hence, the host controller supports
eight command protocols of the SMBus interface (see System Management Bus
(SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write
Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.

The PCH SMBus also implements hardware-based Packet Error Checking for data
robustness and the Address Resolution Protocol (ARP) to dynamically provide address
to all SMBus devices.

52 Datasheet

2

C devices. Special I2C

Introduction

Intel® High Definition Audio Controller

The Intel® High Definition Audio Specification defines a digital interface that can be
used to attach different types of codecs, such as audio and modem codecs. The PCH’s

®

Intel

HD Audio controller supports up to 4 codecs. The link can operate at either 3.3 V

or 1.5 V.

With the support of multi-channel audio stream, 32-bit sample depth, and sample rate
up to 192 kHz, the Intel

®

HD Audio controller provides audio quality that can deliver CE
levels of audio experience. On the input side, the PCH adds support for an array of
microphones.

Intel® Quiet System Technology (Intel® QST)

The PCH integrates four fan speed sensors (four TACH signals) and four fan speed
controllers (three Pulse Width Modulator signals), which enables monitoring and
controlling up to four fans on the system. With the new implementation of the single­wire Simple Serial Transport (SST) 1.0 bus and Platform Environmental Control
Interface (PECI), the PCH provides an easy way to connect to SST-based thermal
sensors and access the processor thermal data. In addition, coupled with the new
sophisticated fan speed control algorithms, Intel
acoustic management for the platform.

Note: Intel® Quiet System Technology functionality requires a correctly configured system,

including an appropriate processor, Intel

®

BIOS support.

Intel® Anti-Theft Technology (Not available on all the Intel

Chipset or Intel® 3400 Series Chipset SKUs)

The PCH introduces a new hardware-based security technology which encrypts data
stored on any SATA compliant HDD in AHCI Mode. This feature gives the end-user the
ability to restrict access to HDD data by unknown parties. Intel® Anti-Theft Technology
can be used alone or can be combined with software encryption applications to add
protection against data theft.

®

QST provides effective thermal and

Management Engine firmware, and system

®

5 Series

Intel® Anti-Theft Technology functionality requires a correctly configured system,
including an appropriate processor, Intel® Management Engine firmware, and system
BIOS support.

Intel® Virtualization Technology for Directed I/O (Intel® VT-d)

The PCH provides hardware support for implementation of Intel® Virtualization
Technology with Directed I/O (Intel
technology components that support the virtualization of platforms based on Intel
Architecture Processors. Intel
and applications to run in independent partitions. A partition behaves like a virtual
machine (VM) and provides isolation and protection across partitions. Each partition is
allocated its own subset of host physical memory.

Datasheet 53

®

VT-d). Intel® VT-d Technology consists of

®

VT-d Technology enables multiple operating systems

®

Introduction

JTAG Boundary-Scan

The PCH adds the industry standard JTAG interface and enables Boundary-Scan in
place of the XOR chains used in previous generations. Boundary-Scan can be used to
ensure device connectivity during the board manufacturing process. The JTAG interface
allows system manufacturers to improve efficiency by using industry available tools to
test the PCH on an assembled board. Since JTAG is a serial interface, it eliminates the
need to create probe points for every pin in an XOR chain. This eases pin breakout and
trace routing and simplifies the interface between the system and a bed-of-nails tester.

Note: Contact your local Intel Field Sales Representative for additional information about

JTAG usage on the PCH.

Serial Over Lan (SOL) Function

This function supports redirection of keyboard and text screens to a terminal window
on a remote console. The keyboard and text redirection enables the control of the client
machine through the network without the need to be physically near that machine. Text
and keyboard redirection allows the remote machine to control and configure a client
system. The SOL function emulates a standard PCI device and redirects the data from
the serial port to the management console using the integrated LAN.

KVM

KVM provides enhanced capabilities to its predecessor – SOL. In addition to the
features set provided by SOL, KVM provides mouse and graphic redirection across the
integrated LAN. Unlike SOL, KVM does not appear as a host accessible PCI device but is
instead almost completely performed by Intel AMT Firmware with minimal BIOS
interaction as described in the Intel ME BIOS Writer’s Guide. The KVM feature is only
available with internal graphics.

IDE-R Function

The IDE-R function is an IDE Redirection interface that provides client connection to
management console ATA/ATAPI devices such as hard disk drives and optical disk
drives. A remote machine can setup a diagnostic SW or OS installation image and direct
the client to boot an IDE-R session. The IDE-R interface is the same as the IDE
interface although the device is not physically connected to the system and supports
the ATA/ATAPI-6 specification. IDE-R does not conflict with any other type of boot and
can instead be implemented as a boot device option. The Intel AMT solution will use
IDE-R when remote boot is required. The device attached through IDE-R is only visible
to software during a management boot session. During normal boot session, the IDE-R
controller does not appear as a PCI present device.

PCH Display Interface

The PCH integrates latest display technologies such as HDMI*, DisplayPort*, Embedded
DisplayPort (eDP*), SDVO, and DVI along with legacy display technologies: Analog Port
(VGA) and LVDS (mobile only). The Analog Port and LVDS Port are dedicated ports on
the PCH and the Digital Ports B, C and D can be configured to drive HDMI, DVI, or
DisplayPort. Digital Port B can also be configured as SDVO while Digital Port D can be
configured as eDP. The HDMI interface supports the HDMI* 1.3C specification while the
DisplayPort interface supports the DisplayPort* 1.1a specification. The PCH supports
High-bandwidth Digital Content Protection for high definition content playback over
digital interfaces. The PCH also integrates audio codecs for audio support over HDMI
and DisplayPort interfaces.

The PCH receives the display data over the Intel
the display technology protocol and sends the data through the display interface.

®

FDI and transcodes the data as per

54 Datasheet

Introduction

Intel® Flexible Display Interconnect (FDI)

The Intel® FDI connects the display engine in the processor with the display interfaces
on the PCH. The display data from the frame buffer is processed by the display engine
and sent to the PCH where it is transcoded and driven out on the panel. Intel FDI
involves two channels – A and B for display data transfer.

Intel FDI Channel A has 4 lanes and Channel B supports 4 lanes depending on the
display configuration. Each of the Intel FDI Channel lanes uses differential signal
supporting 2.7 Gb/s. For two display configurations Intel FDI CH A maps to display pipe
A while Intel CH B maps to the second display pipe B.

1.3 Intel® 5 Series Chipset and Intel® 3400 Series Chipset SKU Definition

Table 1-3. Intel® 5 Series Chipset Desktop SKUs

Feature Set

PCI Express* 2.0 Ports 886586

USB* 2.0 Ports 14 14 12

SATA Ports 6666 6

HDMI/DVI/VGA/SDVO/DisplayPort/eDP Yes Yes Yes No Yes

LVDS No No No No No

Integrated Graphics Support with PAVP 1.5 Yes Yes Yes No Yes

Intel® Quiet System Technology Yes Yes Yes No Yes

Intel® Rapid
Storage
Tec h n ol o g y

Intel® ME Ignition FW only No No No Yes No

Intel® AT Yes No No No No

Intel® AMT 6.0 Yes No No No No

Intel® Remote PC Assist Technology for
Business

Intel® Remote PC Assist Technology for
Consumer

Intel® Remote Wake Technology No Yes Yes No No

AHCI Yes Yes Yes Yes Yes

Raid 0/1/5/10 Support Yes Ye s N o Yes No

Q57 H57 H55 P55 B55

Yes No No No No

No Yes Yes No No

SKU Name(s)

4

14 12

5

4

NOTES:

1. Contact your local Intel Field Sales Representative for currently available PCH SKUs.

2. Table above shows feature difference between the PCH skus. If a feature is not listed in the

3. The PCH provides hardware support for AHCI functionality when enabled by appropriate

4. USB ports 6 and 7 are disabled.

5. PCIe* ports 7 and 8 are disabled.

Datasheet 55

table it is considered a Base feature that is included in all SKUs.

system configurations and software drivers.

Table 1-4. Intel® 5 Series Chipset Mobile SKUs

Introduction

Feature Set

SKU Name(s)

QM57 HM57 PM55 HM55 QS57

PCI Express* 2.0 Ports 888658

USB* 2.0 Ports 14 14 14 12

4

14

SATA Ports 666466

HDMI/DVI/VGA/SDVO/DisplayPort/eDP Yes Yes No Yes Yes

LVDS Yes Yes No Yes Yes

Graphics Support with PAVP 1.5 Yes Yes No Yes Yes

Intel® Quiet System Technology No No No No No

Intel® Rapid
Storage
Technology

AHCI Yes Ye s Yes Yes Ye s

Raid 0/1/5/10 Support Ye s Ye s Yes No Yes

Intel® ME Ignition FW only No No Yes No No

Intel® AT Yes Yes No Yes Yes

Intel® Active Managment Technology
(Intel AMT) 6.0

Intel® Remote PC Assist Technology for
Business

Intel® Remote PC Assist Technology for
Consumer

Yes No No N o Yes

Yes No No N o Yes

No Yes No No No

Intel® Remote Wake Technology No No No No No

NOTES:

1. Contact your local Intel Field Sales Representative for currently available PCH SKUs.

2. Table above shows feature difference between the PCH SKUs. If a feature is not listed in
the table it is considered a Base feature that is included in all skus.

3. The PCH provides hardware support for AHCI functionality when enabled by appropriate
system configurations and software drivers.

4. USB ports 6 and 7 are disabled.

5. PCIe* ports 7 and 8 are disabled.

6. SATA ports 2 and 3 are disabled.

56 Datasheet

Introduction

Table 1-5. Intel® 3400 Series Chipset Server SKUs

Feature Set

PCI Express* 2.0 Ports 6

USB* 2.0 Ports 8

SATA Ports 4

HDMI/DVI/VGA/SDVO/DisplayPort No No Yes

LVDS No No No

Graphics Support with PAVP 1.5 No No Yes

Intel® Quiet System Technology No No Yes

Intel® Rapid
Storage
Tec h n ol o g y

Intel® ME Ignition FW only Yes Yes No

Intel® AT No No Yes

Intel® AMT 6.0 No No Yes

Intel® Remote PC Assist Technology for Business No No Yes

Intel® Remote PC Assist Technology for Consumer No No No

Intel® Remote Wake Technology No No Yes

AHCI No

Raid 0/1/5/10 Support No Yes Yes

Intel

Chipset

®

3400

7

5

6

3

SKU Name(s)

®

Intel

3420

Chipset

88

4

12

66

Yes Yes

®

Intel

3450

Chipset

14

1. Contact your local Intel Field Sales Representative for currently available PCH skus.

2. Table above shows feature difference between the PCH skus. If a feature is not listed in the
table it is considered a Base feature that is included in all skus.

3. The PCH provides hardware support for AHCI functionality when enabled by appropriate
system configurations and software drivers.

4. USB ports 6 and 7 are disabled.

5. USB ports 8, 9, 10, 11, 12 and 13 are disabled.

6. SATA ports 2 and 3 are disabled.

7. PCIe* ports 7 and 8 are disabled.

1.4 Reference Documents

Document

®

Intel

5 Series Chipset and Intel® 3400 Series Chipset

Specification Update

®

Intel

5 Series Chipset and Intel® 3400 Series Chipset Thermal

Mechanical Specifications and Design Guidelines

Document Number /

Location

http://download.intel.com/
design/processor/
specupdt/322166.pdf

www.intel.com/Assets/
PDF/designguide/

322171.pdf

§ §

Datasheet 57

Introduction

58 Datasheet

Signal Description

2 Signal Description

This chapter provides a detailed description of each signal. The signals are arranged in
functional groups according to their associated interface.

The “#” symbol at the end of the signal name indicates that the active, or asserted
state occurs when the signal is at a low voltage level. When “#” is not present, the
signal is asserted when at the high voltage level.

The “†” symbol at the end of the signal name indicates that the signal is mobile only.

The following notations are used to describe the signal type:

I Input Pin
O Output Pin
OD O Open Drain Output Pin.
I/OD Bi-directional Input/Open Drain Output Pin.
I/O Bi-directional Input / Output Pin.

CMOS CMOS buffers. 1.5 V tolerant.
COD CMOS Open Drain buffers. 3.3 V tolerant.
HVCMOS High Voltage CMOS buffers. 3.3 V tolerant.
A Analog reference or output.

The “Type” for each signal is indicative of the functional operating mode of the signal.
Unless otherwise noted in Section 3.2 or Section 3.3, a signal is considered to be in the
functional operating mode after RTCRST# de-asserts for signals in the RTC well, after
RSMRST# de-asserts for signals in the suspend well, after PWROK asserts for signals in
the core well, and after LAN_RST# de-asserts for signals in the LAN well.

Datasheet 59

Figure 2-1. PCH Interface Signals Block Diagram

TBD

THRMTRIP#
SYS_RESET#
RSMRST#
SLP_S3#
SLP_S4#
SLP_S5#/GPIO63
SLP_M#
CLKRUN#

†

/GPIO32
PWROK
MEPWROK
PWRBTN#
RI#
WAKE#
SUS_STAT#/GPIO61
SUSCLK/GPIO62
LAN_RST#
BATLOW#

†

/GPIO72
PLTRST#
STP_PCI#/GPIO34
ACPRESENT

†

/GPIO31
DRAMPWROK
LAN_PHY_PWR_CT RL

SLP_LAN#/GPIO29

PMSYNCH

AD[31:0]

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY#
TRDY#
STOP#

PAR
PERR#
REQ0#

REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54

GNT0#

GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55

SERR#

PME#

CLKIN_PCILOOPBACK

PCIRST#

PLOCK#

PCI

Interface

Power
Mgnt.

Interrupt
Interface

INIT3_3V#

RCIN#

A20GATE

PROCPWRGD

Processor

Interface

USB

SERIRQ

PIRQ[D:A]#

PIRQ[H:E]#/GPIO[5:2]

USB[13:0]P; USB[13:0]N
OC0#/GPIO59; OC1#/GPIO40
OC2#/GPIO41; OC3#/GPIO42

OC4#/GPIO43; OC5#/GPIO9

OC6#/GPIO10; OC7#/GPIO14

USBRBIAS

USBRBIAS#

RTCX1
RTCX2

CLKIN_BCLK_P;CLKIN_ BCLK_N

CLKIN_DMI_P;CLKIN_DMI_N

CLKIN_SATA_[P:N]/CKSSCD_[P:N]

CLKIN_DOT96P;CLKIN_DOT96N

XTAL25_IN

REF14CLKIN

PCIECLKRQ0#/GPIO73;PCIECLKRQ1#/GPIO18
PCIECLKRQ2#/GPIO20;PCIECLKRQ3#/GPIO25
PCIECLKRQ4#/GPIO26;PCIECLKRQ5#/GPIO44
PCIECLKRQ6#/GPIO45;P CIECLKRQ7#/GPIO46

PEG_A_CLKRQ#/GPIO47;PEG_B_CLKRQ#/GPIO56

XCLK_RCOMP

RTC

Clock
Inputs

Misc.

Signals

INTVRMEN

SPKR

SRTCRST#

RTCRST#

General

Purpose

I/O

GPIO[72,57,35,32,28, 27,15,8,0]

PWM[3:0]/TP[12:9]

†

TACH0/GPIO17; TAC H1/GPIO1

TACH2/GPIO6; TACH3/GPIO7

SST

PECI

INTRUDER#;
SML[0:1]DATA;SML[0:1]CL K;
SML0ALERT#/GPIO60
SML1ALERT#/GPIO74

DMI[3:0]TXP, DMI[3:0]TXN
DMI[3:0]RXP, DMI[3:0]R XN
DMI_ZCOMP
DMI_IRCOMP

Direct

Media

Interface

LPC / FWH

Interface

SMBus

Interface

HDA_RST#
HDA_SYNC
HDA_BCLK
HDA_SDO
HDA_SDIN[3:0]
HDA_DOCK_EN#

†

;HDA_DOCK_RST#

†

Intel

®

High

Definition

Audio

System

Mgnt.

LAD[3:0]/FWH[3:0]
LFRAME#/FWH4
LDRQ0#; LDRQ1#/GPIO23

SMBDATA; SMBCLK
SMBALERT#/GPIO11

SATA[5:0]TXP, SATA[5:0]TXN
SATA[5:0]RXP, SATA[5:0]RX N
SATAICOMPO
SATAICOMPI
SATALED#
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA4GP/GPIO16
SATA5GP/GPIO49/TEMP _ALERT#
SCLOCK/GPIO22
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

Serial ATA

Interface

PCI Express*

Interface

PETp[8:1], PETn[8:1]
PERp[8:1], PERn[8:1]

SPI

SPI_CS0#; SPI_CS1#

SPI_MISO
SPI_MOSI

SPI_CLK

JTAG*

Fan Speed

Control

DDPB_[3:0]P;DDPB_[3:0] N;
DDPC_[3:0]P;DDPC_[3:0]N;
DDPD_[3:0]P;DDPD_[3:0]N;
DDP[B:D]_AUXP;DDP[B:D ]_AUXN;
DDP[B:D]_HPD
SDVO_CTRLCLK;SDVO_CTRLDA TA

DDPC_CTRLCLK;DDPC _CTRLDATA
DDPD_CTRLCLK;DDPD_CTRLDATA
SDVO_INTP;SDVO_I NTN
SDVO_TVCLKINP;SDVO _TVCLKINN
SDVO_STALLP;SDVO _STALLN

Digital

Display

Interface

Clock

Outputs

CLKOUT_DP_ [P:N]/CLKOUT_BCLK1_ [P:N]

CLKIN_DMI_P;CLKIN_DMI _N

XTAL25_OUT

CLKOUT_PEG_A_[P:N];CLKOUT_PEG_B_[P:N]

CLKOUT_PCIE[7:0]_P; CLK OUT_PCIE[7:0]_N

CLKOUT_PCI[4:0]

CLKOUTFLEX0/GPIO64;CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66;CLKOUTFLEX3/GPIO67

CRT_RED;CRT_GREEN;CRT_BLUE
DAC_IREF
CRT_HSYNC;CRT_VSYNC
CRT_DDC_CLK;CRT_DDC_DATA
CRT_IRTN

Analog
Display

LVDS

CLOCKOUT_BCLK0_[P :N]/CLKOUT_PCIE8_[P:N}

JTAGTCK
JTAGTMS
JTAGTDI
JTAGTDO

CL_CLK1

†

CL_DATA1

†

CL_RST1#

†

Controller

Link

LVDS[A:B]_DATA[3:0]

†

LVDS[A:B]_DATA#[3:0 ]

†

LVDS[A:B]_CLK†:LVDS[A:B]_CLK#

†

LVD_VREFH†;LVD_VREFL†;LFV_VBG

†

LVD_IBG

†

L_DDC_CLK†;L_DDC_DATA

†

L_VDDEN†;L_BLKTEN†;L_BKLTCTL

†

60 Datasheet

Signal Description

Signal Description

2.1 Direct Media Interface (DMI) to Host Controller

Table 2-1. Direct Media Interface Signals

Name Type Description

DMI0TXP,
DMI0TXN

DMI0RXP,
DMI0RXN

DMI1TXP,
DMI1TXN

DMI1RXP,
DMI1RXN

DMI2TXP,
DMI2TXN

DMI2RXP,
DMI2RXN

DMI3TXP,
DMI3TXN

DMI3RXP,
DMI3RXN

DMI_ZCOMP I

DMI_IRCOMP O

O Direct Media Interface Differential Transmit Pair 0

I Direct Media Interface Differential Receive Pair 0

O Direct Media Interface Differential Transmit Pair 1

I Direct Media Interface Differential Receive Pair 1

O Direct Media Interface Differential Transmit Pair 2

I Direct Media Interface Differential Receive Pair 2

O Direct Media Interface Differential Transmit Pair 3

I Direct Media Interface Differential Receive Pair 3

Impedance Compensation Input: Determines DMI input
impedance.

Impedance/Current Compensation Output: Determines DMI
output impedance and bias current.

2.2 PCI Express*

Table 2-2. PCI Express* Signals

Name Type Description

PETp1, PETn1 O PCI Express* Differential Transmit Pair 1

PERp1, PERn1 I PCI Express Differential Receive Pair 1

PETp2, PETn2 O PCI Express Differential Transmit Pair 2

PERp2, PERn2 I PCI Express Differential Receive Pair 2

PETp3, PETn3 O PCI Express Differential Transmit Pair 3

PERp3, PERn3 I PCI Express Differential Receive Pair 3

PETp4, PETn4 O PCI Express Differential Transmit Pair 4

PERp4, PERn4 I PCI Express Differential Receive Pair 4

PETp5, PETn5 O PCI Express Differential Transmit Pair 5

PERp5, PERn5 I PCI Express Differential Receive Pair 5

PETp6, PETn6 O PCI Express Differential Transmit Pair 6

PERp6, PERn6 I PCI Express Differential Receive Pair 6

PETp7, PETn7 O

PCI Express Differential Transmit Pair 7
NOTE: Port 7 may not be available in all PCH SKUs. Please see

Chapter 1.3 for more information.

Datasheet 61

Table 2-2. PCI Express* Signals

Name Type Description

PCI Express Differential Receive Pair 7

PERp7, PERn7 I

PETp8, PETn8 O

PERp8, PERn8 I

NOTE: Port 7 may not be available in all PCH SKUs. Please see

Chapter 1.3 for more information.

PCI Express Differential Transmit Pair 8
NOTE: Port 8 may not be available in all PCH SKUs. Please see

Chapter 1.3 for more information.

PCI Express Differential Receive Pair 8
NOTE: Port 8 may not be available in all PCH SKUs. Please see

Chapter 1.3 for more information.

2.3 Firmware Hub Interface

Table 2-3. Firmware Hub Interface Signals

Name Type Description

FWH[3:0] /

LAD[3:0]

FWH4 /

LFRAME#

INIT3_3V# O

Firmware Hub Signals. These signals are multiplexed with the LPC

I/O

address signals.

Firmware Hub Signals. This signal is multiplexed with the LPC

O

LFRAME# signal.

Initialization 3.3 V: INIT3_3V# is asserted by the PCH for 16 PCI
clocks to reset the processor. This signal is intended for Firmware Hub.

Signal Description

62 Datasheet

C/BE[3:0]# Command Type

0000b Interrupt Acknowledge
0001b Special Cycle
0010b I/O Read
0011b I/O Write
0110b Memory Read
0111b Memory Write
1010b Configuration Read
1011b Configuration Write
1100b Memory Read Multiple
1110b Memory Read Line
1111b Memory Write and Invalidate

Signal Description

2.4 PCI Interface

Table 2-4. PCI Interface Signals (Sheet 1 of 3)

Name Type Description

PCI Address/Data: AD[31:0] is a multiplexed address and data

bus. During the first clock of a transaction, AD[31:0] contain a

AD[31:0] I/O

C/BE[3:0]# I/O

physical address (32 bits). During subsequent clocks, AD[31:0]
contain data. The PCH will drive all 0s on AD[31:0] during the
address phase of all PCI Special Cycles.

Bus Command and Byte Enables: The command and byte enable
signals are multiplexed on the same PCI pins. During the address
phase of a transaction, C/BE[3:0]# define the bus command.
During the data phase C/BE[3:0]# define the Byte Enables.

Datasheet 63

DEVSEL# I/O

FRAME# I/O

IRDY# I/O

All command encodings not shown are reserved. The PCH does not
decode reserved values, and therefore will not respond if a PCI
master generates a cycle using one of the reserved values.

Device Select: The PCH asserts DEVSEL# to claim a PCI
transaction. As an output, the PCH asserts DEVSEL# when a PCI
master peripheral attempts an access to an internal PCH address or
an address destined for DMI (main memory or graphics). As an
input, DEVSEL# indicates the response to a PCH-initiated
transaction on the PCI bus. DEVSEL# is tri-stated from the leading
edge of PLTRST#. DEVSEL# remains tri-stated by the PCH until
driven by a target device.

Cycle Frame: The current initiator drives FRAME# to indicate the
beginning and duration of a PCI transaction. While the initiator
asserts FRAME#, data transfers continue. When the initiator
negates FRAME#, the transaction is in the final data phase.
FRAME# is an input to the PCH when the PCH is the target, and
FRAME# is an output from the PCH when the PCH is the initiator.
FRAME# remains tri-stated by the PCH until driven by an initiator.

Initiator Ready: IRDY# indicates the PCH ability, as an initiator, to
complete the current data phase of the transaction. It is used in
conjunction with TRDY#. A data phase is completed on any clock
both IRDY# and TRDY# are sampled asserted. During a write,
IRDY# indicates the PCH has valid data present on AD[31:0].
During a read, it indicates the PCH is prepared to latch data. IRDY#
is an input to the PCH when the PCH is the target and an output
from the PCH when the PCH is an initiator. IRDY# remains tri-stated
by the PCH until driven by an initiator.

Table 2-4. PCI Interface Signals (Sheet 2 of 3)

Name Type Description

Target Ready: TRDY# indicates the PCH ability, as a target, to

complete the current data phase of the transaction. TRDY# is used
in conjunction with IRDY#. A data phase is completed when both
TRDY# and IRDY# are sampled asserted. During a read, TRDY#

TRDY# I/O

STOP# I/O

PAR I/O

PERR# I/O

REQ0#
REQ1#/ GPIO50
REQ2#/ GPIO52

REQ3#/GPIO54

GNT0#
GNT1#/ GPIO51

GNT2#/ GPIO53

GNT3#/GPIO55

CLKIN_PCILOO

PBACK

indicates that the PCH, as a target, has placed valid data on
AD[31:0]. During a write, TRDY# indicates the PCH, as a target is
prepared to latch data. TRDY# is an input to the PCH when the PCH
is the initiator and an output from the PCH when the PCH is a
target. TRDY# is tri-stated from the leading edge of PLTRST#.
TRDY# remains tri-stated by the PCH until driven by a target.

Stop: STOP# indicates that the PCH, as a target, is requesting the
initiator to stop the current transaction. STOP# causes the PCH, as
an initiator, to stop the current transaction. STOP# is an output
when the PCH is a target and an input when the PCH is an initiator.

Calculated/Checked Parity: PAR uses “even” parity calculated on
36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the
PCH counts the number of ones within the 36 bits plus PAR and the
sum is always even. The PCH always calculates PAR on 36 bits
regardless of the valid byte enables. The PCH generates PAR for
address and data phases and only ensures PAR to be valid one PCI
clock after the corresponding address or data phase. The PCH
drives and tri-states PAR identically to the AD[31:0] lines except
that the PCH delays PAR by exactly one PCI clock. PAR is an output
during the address phase (delayed one clock) for all PCH initiated
transactions. PAR is an output during the data phase (delayed one
clock) when the PCH is the initiator of a PCI write transaction, and
when it is the target of a read transaction. The PCH checks parity
when it is the target of a PCI write transaction. If a parity error is
detected, the PCH will set the appropriate internal status bits, and
has the option to generate an NMI# or SMI#.

Parity Error: An external PCI device drives PERR# when it receives
data that has a parity error. The PCH drives PERR# when it detects
a parity error. The PCH can either generate an NMI# or SMI# upon
detecting a parity error (either detected internally or reported using
the PERR# signal).

PCI Requests: The PCH supports up to 4 masters on the PCI bus.

I

REQ[3:1]# pins can instead be used as GPIO.

PCI Grants: The PCH supports up to 4 masters on the PCI bus.
GNT[3:1]# pins can instead be used as GPIO.

Pull-up resistors are not required on these signals. If pull-ups are

O

used, they should be tied to the Vcc3_3 power rail.

NOTE: GNT[3:0]# are sampled as a functional strap. See

Section 2.28.1 for details.

PCI Clock: This is a 33 MHz clock feedback input to reduce skew
between PCH PCI clock and clock observed by connected PCI

I

devices. This signal must be connected to one of the pins in the
group CLKOUT_PCI[4:0]

Signal Description

64 Datasheet

Signal Description

Table 2-4. PCI Interface Signals (Sheet 3 of 3)

Name Type Description

PCI Reset: This is the Secondary PCI Bus reset signal. It is a

PCIRST# O

PLOCK# I/O

SERR# I/OD

PME# I/OD

logical OR of the primary interface PLTRST# signal and the state of
the Secondary Bus Reset bit of the Bridge Control register
(D30:F0:3Eh, bit 6).

PCI Lock: This signal indicates an exclusive bus operation and may
require multiple transactions to complete. The PCH asserts PLOCK#
when it performs non-exclusive transactions on the PCI bus.
PLOCK# is ignored when PCI masters are granted the bus.

System Error: SERR# can be pulsed active by any PCI device that
detects a system error condition. Upon sampling SERR# active, the
PCH has the ability to generate an NMI, SMI#, or interrupt.

PCI Power Management Event: PCI peripherals drive PME# to
wake the system from low-power states S1–S5. PME# assertion can
also be enabled to generate an SCI from the S0 state. In some
cases the PCH may drive PME# active due to an internal wake
event. The PCH will not drive PME# high, but it will be pulled up to
VccSus3_3 by an internal pull-up resistor.

2.5 Serial ATA Interface

Table 2-5. Serial ATA Interface Signals (Sheet 1 of 3)

Name Type Description

Serial ATA 0 Differential Transmit Pairs: These are outbound

SATA0TXP

SATA0TXN

SATA0RXP

SATA0RXN

SATA1TXP

SATA1TXN

SATA1RXP

SATA1RXN

—SATA2TXP

SATA2TXN

high-speed differential signals to Port 0.

O

In compatible mode, SATA Port 0 is the primary master of SATA
Controller 1.

Serial ATA 0 Differential Receive Pair: These are inbound high­speed differential signals from Port 0.

I

In compatible mode, SATA Port 0 is the primary master of SATA
Controller 1.

Serial ATA 1 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 1.

O

In compatible mode, SATA Port 1 is the secondary master of SATA
Controller 1.

Serial ATA 1 Differential Receive Pair: These are inbound high­speed differential signals from Port 1.

I

In compatible mode, SATA Port 1 is the secondary master of SATA
Controller 1.

Serial ATA 2 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 2.

In compatible mode, SATA Port 2 is the primary slave of SATA

O

Controller 1.

NOTE: SATA Port 2 may not be available in all PCH SKUs.

Datasheet 65

Table 2-5. Serial ATA Interface Signals (Sheet 2 of 3)

Name Type Description

Serial ATA 2 Differential Receive Pair: These are inbound high-

speed differential signals from Port 2.

SATA2RXP

SATA2RXN

SATA3TXP
SATA3TXN

SATA3RXP

SATA3RXN

SATA4TXP
SATA4TXN

SATA4RXP

SATA4RXN

SATA5TXP
SATA5TXN

SATA5RXP

SATA5RXN

SATAICOMPO O

SATAICOMPI I

SATA0GP /

GPIO21

SATA1GP /

GPIO19

In compatible mode, SATA Port 2 is the primary slave of SATA

I

Controller 1.

NOTE: SATA Port 2 may not be available in all PCH SKUs.

Serial ATA 3 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 3
In compatible mode, SATA Port 3 is the secondary slave of SATA

O

Controller 1.

NOTE: SATA Port 3 may not be available in all PCH SKUs.

Serial ATA 3 Differential Receive Pair: These are inbound high-

speed differential signals from Port 3
In compatible mode, SATA Port 3 is the secondary slave of SATA

I

Controller 1.

NOTE: SATA Port 3 may not be available in all PCH SKUs.

Serial ATA 4 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 4.

O

In compatible mode, SATA Port 4 is the primary master of SATA
Controller 2.

Serial ATA 4 Differential Receive Pair: These are inbound high­speed differential signals from Port 4.

I

In compatible mode, SATA Port 4 is the primary master of SATA
Controller 2.

Serial ATA 5 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 5.

O

In compatible mode, SATA Port 5 is the secondary master of SATA
Controller 2.

Serial ATA 5 Differential Receive Pair: These are inbound high­speed differential signals from Port 5.

I

In compatible mode, SATA Port 5 is the secondary master of SATA
Controller 2.

Serial ATA Compensation Output: Connected to the external
precision resistor to VccCore. Must be connected to SATAICOMPI on
the board.

Serial ATA Compensation Input: Connected to SATAICOMPO on
the board.

Serial ATA 0 General Purpose: This is an input pin which can be
configured as an interlock switch corresponding to SATA Port 0.
When used as an interlock switch status indication, this signal

I

should be driven to ‘0’ to indicate that the switch is closed and to ‘1’
to indicate that the switch is open.

This signal can instead be used as GPIO21.

Serial ATA 1 General Purpose: This is an input pin which can be
configured as an interlock switch corresponding to SATA Port 1.
When used as an interlock switch status indication, this signal

I

should be driven to ‘0’ to indicate that the switch is closed and to ‘1’
to indicate that the switch is open.

This signal can instead be used as GPIO19.

Signal Description

66 Datasheet

Signal Description

Table 2-5. Serial ATA Interface Signals (Sheet 3 of 3)

Name Type Description

Serial ATA 2 General Purpose: This is an input pin which can be

configured as an interlock switch corresponding to SATA Port 2.

SATA2GP /

GPIO36

SATA3GP /

GPIO37

SATA4GP /

GPIO16

SATA5GP /

GPIO49 /

TEMP_ALERT#

SATALED# OD O

SCLOCK/

GPIO22

OD O

SLOAD/GPIO38 OD O

SDATAOUT0/

GPIO39

SDATAOUT1/

OD O

GPIO48

When used as an interlock switch status indication, this signal

I

should be driven to ‘0’ to indicate that the switch is closed and to ‘1’
to indicate that the switch is open.

This signal can instead be used as GPIO36.

Serial ATA 3 General Purpose: This is an input pin which can be
configured as an interlock switch corresponding to SATA Port 3.
When used as an interlock switch status indication, this signal

I

should be driven to ‘0’ to indicate that the switch is closed and to ‘1’
to indicate that the switch is open.

This signal can instead be used as GPIO37.

Serial ATA 4 General Purpose: This is an input pin which can be
configured as an interlock switch corresponding to SATA Port 4.
When used as an interlock switch status indication, this signal

I

should be driven to ‘0’ to indicate that the switch is closed and to ‘1’
to indicate that the switch is open.

This signal can instead be used as GPIO16.

Serial ATA 5 General Purpose: This is an input pin which can be
configured as an interlock switch corresponding to SATA Port 5.
When used as an interlock switch status indication, this signal

I

should be driven to ‘0’ to indicate that the switch is closed and to ‘1’
to indicate that the switch is open.

This signal can instead be used as GPIO49.

Serial ATA LED: This signal is an open-drain output pin driven
during SATA command activity. It is to be connected to external
circuitry that can provide the current to drive a platform LED. When
active, the LED is on. When tri-stated, the LED is off. An external
pull-up resistor to Vcc3_3 is required.

SGPIO Reference Clock: The SATA controller uses rising edges of
this clock to transmit serial data, and the target uses the falling
edge of this clock to latch data. The SCLOCK frequency supported is
32 kHz.

This signal can instead be used as a GPIO22.

SGPIO Load: The controller drives a ‘1’ at the rising edge of
SCLOCK to indicate either the start or end of a bit stream. A 4-bit
vendor specific pattern will be transmitted right after the signal
assertion.

This signal can instead be used as a GPIO38.

SGPIO Dataout: Driven by the controller to indicate the drive
status in the following sequence: drive 0, 1, 2, 3, 4, 5, 0, 1, 2...

These signals can instead be used as GPIOs.

Datasheet 67

2.6 LPC Interface

Table 2-6. LPC Interface Signals

Name Type Description

LAD[3:0] /

FWH[3:0]

LFRAME# /

FWH4

LDRQ0#,

LDRQ1# /

GPIO23

LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull-

I/O

ups are provided.

O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.

LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to
request DMA or bus master access. These signals are typically connected
to an external Super I/O device. An internal pull-up resistor is provided on

I

these signal.
This signal can instead be used as GPIO23.

2.7 Interrupt Interface

Table 2-7. Interrupt Signals

Name Type Description

SERIRQ I/OD

PIRQ[D:A]# I/OD

PIRQ[H:E]# /

GPIO[5:2]

I/OD

Serial Interrupt Request: This pin implements the serial interrupt
protocol.

PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can
be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in Section 5.8.6. Each PIRQx# line has a separate Route
Control register.

In APIC mode, these signals are connected to the internal I/O APIC in
the following fashion: PIRQA# is connected to IRQ16, PIRQB# to
IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the
legacy interrupts.

PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can
be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in Section 5.8.6. Each PIRQx# line has a separate Route
Control register.

In APIC mode, these signals are connected to the internal I/O APIC in
the following fashion: PIRQE# is connected to IRQ20, PIRQF# to
IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the
legacy interrupts.

These signals can instead be used as GPIOs.

Signal Description

NOTE: PIRQ Interrupts can only be shared if it is configured as level sensitive. They cannot be

68 Datasheet

shared if configured as edge triggered.

Signal Description

2.8 USB Interface

Table 2-8. USB Interface Signals (Sheet 1 of 2)

Name Type Description

Universal Serial Bus Port [1:0] Differential: These differential

USBP0P,

USBP0N

USBP1P,

USBP1N

USBP2P,

USBP2N

USBP3P,

USBP3N

USBP4P,

USBP4N

USBP5P,

USBP5N

USBP6P,

USBP6N

USBP7P,

USBP7N

pairs are used to transmit Data/Address/Command signals for port 0.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [1:0] Differential: These differential
pairs are used to transmit Data/Address/Command signals for port 1.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [3:2] Differential: These differential
pairs are used to transmit Data/Address/Command signals for port 2.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [3:2] Differential: These differential
pairs are used to transmit Data/Address/Command signals for port 3.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [5:4] Differential: These differential
pairs are used to transmit Data/Address/Command signals for port 4.

I/O

NOTE: No external resistors are required on these signals. The PCH

Universal Serial Bus Port [5:4] Differential: These differential

pairs are used to transmit Data/Address/Command signals for port 5.

I/O

NOTE: No external resistors are required on these signals. The PCH

Universal Serial Bus Port [7:6] Differential: These differential

pairs are used to transmit Data/Address/Command signals for port 6.

I/O

NOTE: No external resistors are required on these signals. The PCH

Universal Serial Bus Port [7:6] Differential: These differential

pairs are used to transmit Data/Address/Command signals for port 7.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Datasheet 69

Table 2-8. USB Interface Signals (Sheet 2 of 2)

Name Type Description

Universal Serial Bus Port [9:8] Differential: These differential

USBP8P,

USBP8N

USBP9P,

USBP9N

USBP10P,

USBP10N

USBP11P,

USBP11N

USBP12P,

USBP12N

USBP13P,

USBP13N

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

USBRBIAS O

USBRBIAS# I

pairs are used to transmit Data/Address/Command signals for port 8.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [9:8] Differential: These differential
pairs are used to transmit Data/Address/Command signals for port 9.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [11:10] Differential: These differential
pairs are used to transmit Data/Address/Command signals for port 10.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [11:10] Differential: These differential
pairs are used to transmit Data/Address/Command signals for port 11.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [13:12] Differential: These differential
pairs are used to transmit Data/Address/Command signals for port 12.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [13:12] Differential: These differential
pairs are used to transmit Data/Address/Command signals for port 13.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Overcurrent Indicators: These signals set corresponding bits in the
USB controllers to indicate that an overcurrent condition has occurred.

These signals can instead be used as GPIOs.

NOTES:

I

1. OC# pins are not 5 V tolerant.

2. Depending on platform configuration, sharing of OC# pins may
be required.

3. OC#[3:0] can only be used for EHCI controller #1

4. OC#[4:7] can only be used for EHCI controller #2

USB Resistor Bias: Analog connection point for an external resistor.
Used to set transmit currents and internal load resistors.

USB Resistor Bias Complement: Analog connection point for an
external resistor. Used to set transmit currents and internal load
resistors.

Signal Description

70 Datasheet

Signal Description

2.9 Power Management Interface

Table 2-9. Power Management Interface Signals (Sheet 1 of 3)

Name Type Description

Platform Reset: The PCH asserts PLTRST# to reset devices on the

platform (such as, SIO, FWH, LAN, processor, etc.). The PCH asserts
PLTRST# during power-up and when software initiates a hard reset
sequence through the Reset Control register (I/O Register CF9h). The

PLTRST# O

THRMTRIP# I

SLP_S3# O

SLP_S4# O

SLP_S5# /

GPIO63

SLP_M# O

SLP_LAN# /

GPIO29

PCH drives PLTRST# inactive a minimum of 1 ms after both PWROK
and SYS_PWROK are driven high. The PCH drives PLTRST# active a
minimum of 1 ms when initiated through the Reset Control register
(I/O Register CF9h).

NOTE: PLTRST# is in the VccSus3_3 well.

Thermal Trip: When low, this signal indicates that a thermal trip from

the processor occurred, and the PCH will immediately transition to a
S5 state. The PCH will not wait for the processor stop grant cycle since
the processor has overheated.

S3 Sleep Control: SLP_S3# is for power plane control. This signal
shuts off power to all non-critical systems when in S3 (Suspend To
RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.

S4 Sleep Control: SLP_S4# is for power plane control. This signal
shuts power to all non-critical systems when in the S4 (Suspend to
Disk) or S5 (Soft Off) state.

NOTE: This pin must be used to control the DRAM power to use the

PCH’s DRAM power-cycling feature. See Chapter 5.13.10.2 for
details

S5 Sleep Control: SLP_S5# is for power plane control. This signal is
used to shut power off to all non-critical systems when in the S5 (Soft

O

Off) states.
This signal can instead be used as GPIO63

Manageability Sleep State Control: SLP_M# is for power plane
control. If no Management Engine firmware is present, SLP_M# will
have the same timings as SLP_S3#.

LAN Sub-System Sleep Control: When SLP_LAN# is deasserted it
indicates that the PHY device must be powered. When SLP_LAN# is
asserted, power can be shut off to the PHY device. SLP_LAN# will
always be deasserted in S0 and anytime SLP_A# is deasserted.

A SLP_LAN#/GPIO Select Soft-Strap can be used for systems NOT

O

using SLP_LAN# functionality to revert to GPIO29 usage. When soft­strap is 0 (default), pin function will be SLP_LAN#. When soft-strap is
set to 1, the pin returns to its regular GPIO mode.

The pin behavior is summarized in Section 5.13.10.5.

Power OK: When asserted, PWROK is an indication to the PCH that all
of its core power rails are powered and stable. PWROK can be driven
asynchronously. When PWROK is negated, the PCH asserts PLTRST#.

PWROK I

Datasheet 71

NOTE: It is required that the power rails associated with PCI/PCIe

typically the 3.3 V, 5 V, and 12 V core well rails) have been
valid for 99 ms prior to PCH PWROK assertion to comply with
the 100 ms PCI 2.3/PCIe 2.0 specification on PLTRST# de­assertion. PWROK must not glitch, even if RSMRST# is low.

Table 2-9. Power Management Interface Signals (Sheet 2 of 3)

Name Type Description

MEPWROK I

PWRBTN# I

RI# I

SYS_RESET# I

RSMRST# I

LAN_RST# I

LAN_PHY_PW

R_CTRL /

GPIO12

WAKE# I

SUS_STAT# /

GPIO61

SUSCLK /

GPIO62

Management Engine Power OK: When asserted, this signal
indicates that power to the ME subsystem is stable.

Power Button: The Power Button will cause SMI# or SCI to indicate a
system request to go to a sleep state. If the system is already in a
sleep state, this signal will cause a wake event. If PWRBTN# is pressed
for more than 4 seconds, this will cause an unconditional transition
(power button override) to the S5 state. Override will occur even if the
system is in the S1–S4 states. This signal has an internal pull-up
resistor and has an internal 16 ms de-bounce on the input.

Ring Indicate: This signal is an input from a modem. It can be
enabled as a wake event, and this is preserved across power failures.

System Reset: This pin forces an internal reset after being
debounced. The PCH will reset immediately if the SMBus is idle;
otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before
forcing a reset on the system.

Resume Well Reset: This signal is used for resetting the resume
power plane logic. This signal must be asserted for at least 10 ms after
the suspend power wells are valid. When de-asserted, this signal is an
indication that the suspend power wells are stable.

LAN Reset: When asserted, the internal LAN controller is in reset.
This signal must remain asserted until at least 1 ms after the LAN
power well (VccLAN) and ME power well (VccME3_3) are valid. Also,
LAN_RST# must assert a minimum of 40 ns before the LAN power rails
become inactive. When de-asserted, this signal is an indication that
LAN power wells are stable.

NOTES:

1. If Intel LAN is enabled, LAN_RST# must be connected to the
same source as MEPWROK.

2. If Intel LAN is not used or disabled, LAN_RST# must be
grounded through an external pull-down resistor.

LAN PHY Power Control: LAN_PHY_PWR_CTRL should be connected
to LAN_DISABLE_N on the Intel 82567 GbE PHY. The PCH will drive
LAN_PHY_PWR_CTRL low to put the PHY into a low power state when
functionality is not needed.

O

NOTES:

LAN_PHY_PWR_CTRL can only be driven low if SLP_LAN# is de­asserted.

This signal can instead be used as GPIO12.

PCI Express* Wake Event: Sideband wake signal on PCI Express
asserted by components requesting wake up.

Suspend Status: This signal is asserted by the PCH to indicate that
the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal
refresh to suspend refresh mode. It can also be used by other

O

peripherals as an indication that they should isolate their outputs that
may be going to powered-off planes.

This signal can instead be used as GPIO61.

Suspend Clock: This clock is an output of the RTC generator circuit to
use by other chips for refresh clock.

O

This signal can instead be used as GPIO62.

Signal Description

72 Datasheet

Signal Description

Table 2-9. Power Management Interface Signals (Sheet 3 of 3)

Name Type Description

DRAM Power OK: This signal should connect to the Processor’s

SM_DRAMPWROK pin. The PCH asserts this pin to indicate when DRAM

DRAMPWROK O

PMSYNCH O

CLKRUN#

(Mobile Only) /

GPIO32

(Desktop Only)

BATLOW#

(Mobile Only) /

GPIO72

(Desktop Only)

SYS_PWROK I

STP_PCI# /

GPIO34

power is on.

NOTE:

1. This pin should have External pull-up to the an always on
Voltage level of 1.05 V / 1.1 V

Power Management Sync: Provides state information from the PCH
to the processor relevant to C-state transitions.

PCI Clock Run: Mobile only signal used to support PCI CLKRUN
protocol. Connects to peripherals that need to request clock restart or
prevention of clock stopping.

I/O

Mobile: Can be configured as CLKRUN#
Desktop: GPIO mode only.

Battery Low: Mobile only signal is an input from the battery to

indicate that there is insufficient power to boot the system. Assertion
will prevent wake from S3–S5 state. This signal can also be enabled to
cause an SMI# when asserted.

I

Mobile: Can be configured as BATLOW#
Desktop: GPIO mode only.

NOTE: Desktop requires a weak external pull-up

System Power OK: This generic power good input to the PCH is

driven and used in a platform-specific manner. While PWROK always
indicates that the CORE well of the PCH is stable, SYS_PWROK is used
to inform the PCH that power is stable to some other system
component(s) and the system is ready to start the exit from reset. The
particular component(s) associated with SYS_PWROK can vary across
platform types supported by the same generation of the PCH.
Depending on the platform, the PCH may expect (and wait) for
SYS_PWROK at different stages of the boot flow before continuing.

Stop PCI Clock: This signal is an output to the external clock
generator for it to turn off the PCI clock.

O

This signal can instead be used as GPIO34.

Datasheet 73

2.10 Processor Interface

Table 2-10. Processor Interface Signals

Name Type Description

Keyboard Controller Reset Processor: The keyboard controller

can generate INIT# to the processor. This saves the external OR gate
with the PCH’s other sources of INIT#. When the PCH detects the

RCIN# I

A20GATE I

PROCPWRGD O

assertion of this signal, INIT# is generated for
16 PCI clocks.

NOTE: The PCH will ignore RCIN# assertion during transitions to the

S1, S3, S4, and S5 states.

A20 Gate: A20GATE is from the keyboard controller. The signal acts
as an alternative method to force the A20M# signal active. It saves
the external OR gate needed with various other chipsets.

Processor Power Good: This signal should be connected to the
processor’s VCCPWRGOOD_1 and VCCPWRGOOD_0 input to indicate
when the processor power is valid.

2.11 SMBus Interface

Signal Description

Table 2-11. SM Bus Interface Signals

Name Type Description

SMBDATA I/OD SMBus Data: External pull-up resistor is required.

SMBCLK I/OD SMBus Clock: External pull-up resistor is required.

SMBALERT# /

GPIO11

SMBus Alert: This signal is used to wake the system or generate
SMI#.

I

This signal can instead be used as GPIO11.

74 Datasheet

Signal Description

2.12 System Management Interface

Table 2-12. System Management Interface Signals

Name Type Description

Intruder Detect: This signal can be set to disable system if box

INTRUDER# I

SML0DATA I/OD

SML0CLK I/OD

SML0ALERT# /

GPIO60 /

SML1ALERT# /

GPIO74

SML1CLK /

GPIO58

SML1DATA /

GPIO75

detected open. This signal’s status is readable, so it can be used like a
GPI if the Intruder Detection is not needed.

System Management Link 0 Data: SMBus link to external PHY.
External pull-up is required.

System Management Link 0 Clock: SMBus link to external PHY.
External pull-up is required.

SMLink Alert 0: Output of the integrated LAN controller to external
PHY. External pull-up resistor is required.

O OD

This signal can instead be used as GPIO60.

SMLink Alert 1: Alert for the Intel ME SMBus controller to optional
Embedded Controller or BMC. External pull-up resistor is required.

O OD

This signal can instead be used as GPIO74.

System Management Link 1 Clock: SMBus link to optional
Embedded Controller or BMC. External pull-up resistor is required.

I/OD

This signal can instead be used as GPIO58.

System Management Link 1 Data: SMBus link to optional
Embedded Controller or BMC. External pull-up resistor is required.

I/OD

This signal can instead be used as GPIO75.

2.13 Real Time Clock Interface

Table 2-13. Real Time Clock Interface

Name Type Description

RTCX1 Special

RTCX2 Special

Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If

no external crystal is used, then RTCX1 can be driven with the desired
clock rate.

Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If
no external crystal is used, then RTCX2 should be left floating.

Datasheet 75

2.14 Miscellaneous Signals

Table 2-14. Miscellaneous Signals

Name Type Description

Internal Voltage Regulator Enable: This signal enables the

INTVRMEN I

SPKR O

RTCRST# I

internal 1.05 V regulators.
This signal must be always pulled-up to VccRTC.

Speaker: The SPKR signal is the output of counter 2 and is internally
“ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This
signal drives an external speaker driver device, which in turn drives
the system speaker. Upon PLTRST#, its output state is 0.

NOTE: SPKR is sampled as a functional strap. See Section 2.28.1 for

more details. There is a weak integrated pull-down resistor on
SPKR pin.

RTC Reset: When asserted, this signal resets register bits in the RTC
well.

NOTES:

1. Unless CMOS is being cleared (only to be done in the G3
power state), the RTCRST# input must always be high when
all other RTC power planes are on.

2. In the case where the RTC battery is dead or missing on the
platform, the RTCRST# pin must rise before the RSMRST#
pin.

Secondary RTC Reset: This signal resets the manageability register
bits in the RTC well when the RTC battery is removed.

Signal Description

SRTCRST# I

NOTES:

1. The SRTCRST# input must always be high when all other RTC
power planes are on.

2. In the case where the RTC battery is dead or missing on the
platform, the SRTCRST# pin must rise before the RSMRST#
pin.

76 Datasheet

Signal Description

2.15 Intel® High Definition Audio Link

Table 2-15. Intel® High Definition Audio Link Signals

Name Type Description

®

Intel

HDA_RST# O

HDA_SYNC O

HDA_BCLK O

HDA_SDO O

HDA_SDIN[3:0] I

High Definition Audio Reset: Master hardware reset to

external codec(s).

®

Intel

High Definition Audio Sync: 48 kHz fixed rate sample

sync to the codec(s). Also used to encode the stream number.

NOTE: This signal is sampled as a functional strap. See

Section 2.28.1 for more details. There is a weak

integrated pull-down resistor on this pin.

®

Intel

High Definition Audio Bit Clock Output: 24.000 MHz
serial data clock generated by the Intel
controller (the PCH). This signal has a weak internal pull-down
resistor.

®

Intel

High Definition Audio Serial Data Out: Serial TDM
data output to the codec(s). This serial output is double-pumped
for a bit rate of 48 Mb/s for Intel

NOTE: This signal is sampled as a functional strap. See

Section 2.28.1 for more details. There is a weak

integrated pull-down resistor on this pin.

®

Intel

High Definition Audio Serial Data In [3:0]: Serial
TDM data inputs from the codecs. The serial input is single­pumped for a bit rate of 24 Mb/s for Intel
These signals have integrated pull-down resistors, which are
always enabled.

®

High Definition Audio

®

High Definition Audio.

®

High Definition Audio.

HDA_DOCK_EN#

(Mobile Only) /

GPIO33

HDA_DOCK_RST#

/ GPIO13

NOTE: During enumeration, the PCH will drive this signal. During

normal operation, the CODEC will drive it.

High Definition Audio Dock Enable: This mobile signal
controls the external Intel

®

HD Audio docking isolation logic. This
is an active low signal. When de-asserted the external docking
switch is in isolate mode. When asserted the external docking
switch electrically connects the Intel
the corresponding PCH signals.

O

®

HD Audio dock signals to

Mobile: Can be configured as HDA_DOCK_EN#
Desktop: GPIO mode only.

NOTE: This signal is sampled as a functional strap. See

Section 2.28.1 for more details.

Intel High Definition Audio Dock Reset: This signal is a
dedicated HDA_RST# signal for the codec(s) in the docking
station. Aside from operating independently from the normal
HDA_RST# signal, it otherwise works similarly to the HDA_RST#

O

signal.
This signal is shared with GPIO13. This signal defaults to GPIO13

mode after PLTRST#. BIOS is responsible for configuring GPIO13
to HDA_DOCK_RST# mode.

Datasheet 77

2.16 Controller Link

Table 2-16. Controller Link Signals

Signal Name Type Description

CL_RST1# /

TP20

(Desktop Only)

CL_CLK1 / TP18

(Desktop Only)

CL_DATA1 /

TP19

(Desktop Only)

Controller Link Reset 1: Controller Link reset that connects to a

O

Wireless LAN Device supporting Intel
Tec h n ol o g y.

Controller Link Clock 1: Bi-directional clock that connects to a

I/O

Wireless LAN Device supporting Intel
Tec h n ol o g y.

Controller Link Data 1: Bi-directional data that connects to a

I/O

Wireless LAN Device supporting Intel
Tec h n ol o g y.

2.17 Serial Peripheral Interface (SPI)

Table 2-17. Serial Peripheral Interface (SPI) Signals

Name Type Description

SPI_CS0# O SPI Chip Select 0: Used as the SPI bus request signal.

SPI_CS1# OSPI Chip Select 1: Used as the SPI bus request signal.

SPI_MISO I SPI Master IN Slave OUT: Data input pin for the PCH.

SPI Master OUT Slave IN: Data output pin for the PCH.

Signal Description

®

Active Management

®

Active Management

®

Active Management

SPI_MOSI O

SPI_CLK O

NOTE: This signal is sampled as a functional strap. See

Section 2.28.1 for more details. There is a weak integrated

pull-down resistor on this pin.

SPI Clock: SPI clock signal, during idle the bus owner will drive the
clock signal low. 17.86 MHz and 31.25 MHz.

78 Datasheet

Signal Description

2.18 Intel® Quiet System Technology and Thermal Reporting

Table 2-18. Intel® Quiet System Technology Signals

Signal Name Type Description

PWM[3:0]

(Desktop Only) /

TP[12:9]

(Mobile Only)

TACH0

(Desktop Only) /

GPIO17

TACH1

(Desktop Only) /

GPIO1

TACH2

(Desktop Only) /

GPIO6

TACH3

(Desktop Only) /

GPIO7

SST I/O

PECI I/O

OD O

I

Fan Pulse Width Modulation Outputs: Pulse Width Modulated
duty cycle output signal that is used for Intel
Tec h no lo g y.

When controlling a 3-wire fan, this signal controls a power
transistor that, in turn, controls power to the fan. When controlling
a 4-wire fan, this signal is connected to the “Control” signal on the
fan. The polarity of this signal is programmable. The output default
is low.

These signals are 5 V tolerant.

Fan Tachometer Inputs: Tachometer pulse input signal that is
used to measure fan speed. This signal is connected to the “Sense”
signal on the fan.

These signals can instead be used as a GPIOs.

Simple Serial Transport: Single-wire, serial bus. Connect to SST
compliant devices such as SST thermal sensors or voltage sensors.

Platform Environment Control Interface: Single-wire, serial
bus. Connect to corresponding pin of the processor for accessing
processor digital thermometer.

®

Quiet System

Datasheet 79

2.19 JTAG Signals

Table 2-19. JTAG Signals

Name Type Description

JTAG_TCK I

JTAG_TMS I

JTAG_TDI I

JTAG_TDO OD

TRST# I

NOTE: JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary-Scan

Architecture (IEEE Std. 1149.1-2001).

Signal Description

Test Clock Input (TCK): The test clock input provides the clock
for the JTAG test logic.

Test Mode Select (TMS): The signal is decoded by the Test
Access Port (TAP) controller to control test operations.

Test Data Input (TDI): Serial test instructions and data are
received by the test logic at TDI.

Test Data Output (TDO): TDO is the serial output for test
instructions and data from the test logic defined in this standard.

Test Reset (RST): RST is an active low asynchronous signal that
can reset the Test Access Port (TAP) controller.

NOTE: The RST signal is optional per the IEEE 1149.1

specification, and is not functional for Boundary Scan
Tes t in g.

2.20 Clock Signals

Table 2-20. Clock Interface Signals (Sheet 1 of 3)

Name Type Description

CLKIN_BCLK_P,

CLKIN_BCLK_N

CLKOUT_BCLK0_P /

CLKOUT_PCIE8_P,

CLKOUT_BCLK0_N /

CLKOUT_PCIE8_N

CLKOUT_DP_P /

CLKOUT_BCLK1_P,

CLKOUT_DP_N /

CLKOUT_BCLK1_N

CLKIN_DMI_P,

CLKIN_DMI_N

CLKOUT_DMI_P,

CLKOUT_DMI_N

CLKIN_SATA_P /

CKSSCD_P,

CLKIN_SATA_N /

CKSSCD_N

CLKIN_DOT96P,

CLKIN_DOT96N

133 MHz differential reference clock from a clock chip in

I

Buffer-Through Mode.

133 MHz Differential output to Processor or 100 MHz

O

PCIe* Gen 1.1 specification differential output to PCI
Express devices.

120 MHz Differential output for DisplayPort reference or

O

133 MHz Differential output to processor

100 MHz differential reference clock from a clock chip in
Buffer-Through Mode.

I

NOTE: This input clock is required to be PCIe 2.0 jitter

100 MHz Gen2 specification jitter tolerant differential

O

output to processor.

100 MHz differential reference clock from a clock chip,

I

provided separately from CLKIN_DMI, for use only as a
100 MHz source for SATA.

I 96 MHz differential reference clock from a clock chip.

spec compliant from a clock chip, for PCIe 2.0
discrete Graphics platforms.

80 Datasheet

Signal Description

Table 2-20. Clock Interface Signals (Sheet 2 of 3)

Name Type Description

XTAL25_IN I

XTAL25_OUT O

REFCLK14IN I

CLKOUT_PEG_A_P,

CLKOUT_PEG_A_N

CLKOUT_PEG_B_P,

CLKOUT_PEG_B_N

PEG_A_CLKRQ# / GPIO47,

PEG_B_CLKRQ# / GPIO56

CLKOUT_PCIE[7:0]P,

CLKOUT_PCIE[7:0]N

PCIECLKRQ0# / GPIO73,
PCIECLKRQ1# / GPIO18,
PCIECLKRQ2# / GPIO20,
PCIECLKRQ3# / GPIO25,
PCIECLKRQ4# / GPIO26,
PCIECLKRQ5# / GPIO44,
PCIECLKRQ6# / GPIO45,

PCIECLKRQ7# / GPIO46

CLKOUT_PCI[4:0] O

CLKOUTFLEX0 / GPIO64 O

Connection for 25 MHz crystal to the PCH oscillator
circuit.

Connection for 25 MHz crystal to the PCH oscillator
circuit.

Single-ended 14.31818 MHz reference clock driven by a
clock chip.

100 MHz Gen2 specification differential output to PCI-

O

Express Graphics device

100 MHz Gen2 specification differential output to a

O

second PCI-Express Graphics device

Clock Request Signals for PEG SLOTS

I

These signals can instead be used as GPIOs

100 MHz PCIe* Gen1.1 specification differential output

O

to PCI Express* devices

Clock Request Signals for PCI Express 100 MHz Clocks
These signals can instead be used as GPIOs

I

NOTE: External Pull-up Resistor required if used for

Single Ended 33.3 MHz outputs to PCI connectors/
devices. One of these signals must be connected to
CLKIN_PCILOOPBACK to function as a PCI clock
loopback. This allows skew control for variable lengths of
CLKOUT_PCI[4:0].

Configurable as a GPIO or as an Intel
Firmware programmable output clock, which can be
configured as one of the following:

•33 MHz

• 14.31818 MHz

• DC Output logic ‘0’ (Default)

CLKREQ# functionality

®

Management

NOTE: Default clock setting requires no Intel ME FW

configuration.

®

Configurable as a GPIO or as an Intel

Management
Firmware programmable output clock, which can be
configured as one of the following:

Non functional and unsupported clock output value
(Default)

CLKOUTFLEX1 / GPIO65 O

•33 MHz

• 14.31818 MHz output to SIO

• DC Output logic ‘0’

NOTE: Default clock setting requires no Intel ME FW

configuration.

Datasheet 81

Table 2-20. Clock Interface Signals (Sheet 3 of 3)

Name Type Description

Configurable as a GPIO or as an Intel
Firmware programmable output clock which can be
configured as one of the following:

• 33 MHz

CLKOUTFLEX2 / GPIO66 O

CLKOUTFLEX3 / GPIO67 O

XCLK_RCOMP I/O

• 14.31818 MHz (Default)

• DC Output logic ‘0’

NOTE: Default clock setting requires no Intel ME FW

Configurable as a GPIO or as an Intel
Firmware programmable output clock which can be
configured as one of the following:

• 48 MHz (Default)

• 33 MHz

• 14.31818 MHz output to SIO

• DC Output logic ‘0’

NOTE: Default clock setting requires no Intel ME FW

Differential clock buffer Impedance Compensation:

Connected to an external precision resistor (90.9 ohms
± 1%) to VccIO.

configuration.

configuration.

Signal Description

®

Management

®

Management

2.21 LVDS Signals (Mobile only)

Table 2-21. LVDS Interface Signals (Sheet 1 of 2)

Name Type Description

LVDSA_DATA[3:0] O LVDS Channel A differential data output – positive

LVDSA_DATA#[3:0] O LVDS Channel A differential data output – negative

LVDSA_CLK O LVDS Channel A differential clock output – positive

LVDSA_CLK# O LVDS Channel A differential clock output – negative

LVDSB_DATA[3:0] O LVDS Channel B differential data output – positive

LVDSB_DATA#[3:0] O LVDS Channel B differential data output – negative

LVDSB_CLK O LVDS Channel B differential clock output – positive

LVDSB_CLK# O LVDS Channel B differential clock output – negative

L_DDC_CLK I/O EDID support for flat panel display

L_DDC_DATA I/O EDID support for flat panel display

L_CTRL_CLK I/O

L_CTRL_DATA I/O

L_VDD_EN O

Control signal (clock) for external SSC clock chip control –
optional

Control signal (data) for external SSC clock chip control –
optional

LVDS Panel Power Enable:

Panel power control enable control for LVDS.
This signal is also called VDD_DBL in the CPIS specification
and is used to control the VDC source to the panel logic.

82 Datasheet

Signal Description

Table 2-21. LVDS Interface Signals (Sheet 2 of 2)

Name Type Description

LVDS Backlight Enable:

L_BKLTEN O

L_BKLTCTL O

LVDS_VREFH O Test mode voltage reference.

LVDS_VREFL O Test mode voltage reference.

LVD_IBG I LVDS reference current.

LVD_VBG O Test mode voltage reference.

Panel backlight enable control for LVDS.
This signal is also called ENA_BL in the CPIS specification

and is used to gate power into the backlight circuitry.

Panel Backlight Brightness Control:

Panel brightness control for LVDS.
This signal is also called VARY_BL in the CPIS specification

and is used as the PWM Clock input signal.

2.22 Analog Display /CRT DAC Signals

Table 2-22. Analog Display Interface Signals

Name Type Description

O

CRT_RED

CRT_GREEN

CRT_BLUE

DAC_IREF

CRT_HSYNC

CRT_VSYNC

CRT_DDC_CLK

CRT_DDC_DATA

CRT_IRTN

I/O

HVCMOS

HVCMOS

I/O

COD

I/O

COD

I/O

COD

RED Analog Video Output: This signal is a CRT Analog video
output from the internal color palette DAC.

A

O

GREEN Analog Video Output: This signal is a CRT Analog
video output from the internal color palette DAC.

A

O

BLUE Analog Video Output: This signal is a CRT Analog video
output from the internal color palette DAC.

A

Resistor Set: Set point resistor for the internal color palette
DAC. A 1 KOhm 1% resistor is required between DAC_IREF and

A

motherboard ground.

CRT Horizontal Synchronization: This signal is used as the

O

horizontal sync (polarity is programmable) or “sync interval”.

2.5 V output

O

CRT Vertical Synchronization: This signal is used as the
vertical sync (polarity is programmable). 2.5V output.

Monitor Control Clock

Monitor Control Data

Monitor Interrupt Return

Datasheet 83

2.23 Intel® Flexible Display Interface (FDI)

Table 2-23. Intel® Flexible Display Interface Signals

Signal Name Type Description

FDI_RXP[3:0] I Display Link 1 positive data in

FDI_RXN[3:0] I Display Link 1 negative data in

FDI_FSYNC[0] O Display link 1 Frame sync

FDI_LSYNC[0] O Display link 1 Line sync

FDI_RXP[7:4] I Display Link 2 positive data in

FDI_RXN[7:4] I Display Link 2 negative data in

FDI_FSYNC[1] O Display link 2 Frame sync

FDI_LSYNC[1] O Display link 2 Line sync

FDI_INT O Used for Display interrupts from the PCH to processor.

2.24 Digital Display Signals

Table 2-24. Digital Display Interface Signals (Sheet 1 of 3)

Signal Description

Name Type Description

Port B: Capable of SDVO / HDMI / DVI / DisplayPort

SDVO

DDPB_[0]P: red
DDPB_[1]P: green
DDPB_[2]P: blue
DDPB_[3]P: clock

DDPB_[3:0]P O

HDMI / DVI Port B Data and Clock Lines

DDPB_[0]P: TMDSB_DATA2
DDPB_[1]P: TMDSB_DATA1
DDPB_[2]P: TMDSB_DATA0
DDPB_[3]P: TMDSB_CLK

DisplayPort Port B

DDPB_[0]P: Display Port Lane 0
DDPB_[1]P: Display Port Lane 1
DDPB_[2]P: Display Port Lane 2
DDPB_[3]P: Display Port Lane 3

84 Datasheet

Signal Description

Table 2-24. Digital Display Interface Signals (Sheet 2 of 3)

Name Type Description

Port B: Capable of SDVO / HDMI / DVI / DisplayPort

SDVO

DDPB_[0]N: red complement
DDPB_[1]N: green complement
DDPB_[2]N: blue complement
DDPB_[3]N: clock complement

HDMI / DVI Port B Data and Clock Line Complements

DDPB_[3:0]N O

DDPB_AUXP I/O Port B: Display Port Aux

DDPB_AUXN I/O Port B: Display Port Aux Complement

DDPB_HPD I Port B: TMDSB_HPD Hot Plug Detect

SDVO_CRTLCLK I/O Port B: HDMI Control Clock. Shared with port B SDVO

SDVO_CTRLDATA I/O Port B: HDMI Control Data. Shared with port B SDVO

SDVO_INTP I SDVO_INTP: Serial Digital Video Input Interrupt

SDVO_INTN I SDVO_INTN: Serial Digital Video Input Interrupt Complement.

SDVO_TVCLKINP I

SDVO_TVCLKINN I

SDVO_STALLP I SDVO_STALLP: Serial Digital Video Field Stall.

SDVO_STALLN I SDVO_STALLN: Serial Digital Video Field Stall Complement.

DDPC_[3:0]P O

DDPB_[0]N: TMDSB_DATA2B
DDPB_[1]N: TMDSB_DATA1B
DDPB_[2]N: TMDSB_DATA0B
DDPB_[3]N: TMDSB_CLKB

DisplayPort Port B

DDPB_[0]N: Display Port Lane 0 complement
DDPB_[1]N: Display Port Lane 1 complement
DDPB_[2]N: Display Port Lane 2 complement
DDPB_[3]N: Display Port Lane 3 complement

SDVO_TVCLKINP: Serial Digital Video TVOUT Synchronization
Clock.

SDVO_TVCLKINN: Serial Digital Video TVOUT Synchronization
Clock Complement.

Port C: Capable of HDMI / DVI / DP

HDMI / DVI Port C Data and Clock Lines

DDPC_[0]P: TMDSC_DATA2
DDPC_[1]P: TMDSC_DATA1
DDPC_[2]P: TMDSC_DATA0
DDPC_[3]P: TMDSC_CLK

DisplayPort Port C

DDPC_[0]P: Display Port Lane 0
DDPC_[1]P: Display Port Lane 1
DDPC_[2]P: Display Port Lane 2
DDPC_[3]P: Display Port Lane 3

Datasheet 85

Table 2-24. Digital Display Interface Signals (Sheet 3 of 3)

Name Type Description

Port C: Capable of HDMI / DVI / DisplayPort

HDMI / DVI Port C Data and Clock Line Complements

DDPC_[0]N: TMDSC_DATA2B
DDPC_[1]N: TMDSC_DATA1B
DDPC_[2]N: TMDSC_DATA0B

DDPC_[3:0]N O

DDPC_AUXP I/O Port C: Display Port Aux

DDPC_AUXN I/O Port C: Display Port Aux Complement

DDPC_HPD I Port C: TMDSC_HPD Hot Plug Detect

DDPC_CTRLCLK I/O HDMI port C Control Clock

DDPC_CTRLDATA I/O HDMI port C Control Data

DDPC_[3]N: TMDSC_CLKB

DisplayPort Port C Complements

DDPC_[0]N: Lane 0 complement
DDPC_[1]N: Lane 1 complement
DDPC_[2]N: Lane 2 complement
DDPC_[3]N: Lane 3 complement

Port D: Capable of HDMI / DVI / DP

Signal Description

HDMI / DVI Port D Data and Clock Lines

DDPD_[0]P: TMDSC_DATA2
DDPD_[1]P: TMDSC_DATA1
DDPD_[2]P: TMDSC_DATA0

DDPD_[3:0]P O

DDPD_[3]P: TMDSC_CLK

DisplayPort Port D

DDPD_[0]P: Display Port Lane 0
DDPD_[1]P: Display Port Lane 1
DDPD_[2]P: Display Port Lane 2
DDPD_[3]P: Display Port Lane 3

Port D: Capable of HDMI / DVI / DisplayPort

HDMI / DVI Port D Data and Clock Line Complements

DDPD_[0]N: TMDSC_DATA2B
DDPD_[1]N: TMDSC_DATA1B
DDPD_[2]N: TMDSC_DATA0B

DDPD_[3:0]N O

DDPD_[3]N: TMDSC_CLKB

DisplayPort Port D Complements

DDPD_[0]N: Lane 0 complement
DDPD_[1]N: Lane 1 complement
DDPD_[2]N: Lane 2 complement
DDPD_[3]N: Lane 3 complement

DDPD_AUXP I/O Port D: Display Port Aux

DDPD_AUXN I/O Port D: Display Port Aux Complement

DDPD_HPD I Port D: TMDSD_HPD Hot Plug Detect

DDPD_CTRLCLK I/O HDMI port D Control Clock

DDPD_CTRLDATA I/O HDMI port D Control Data

86 Datasheet

Signal Description

2.25 General Purpose I/O Signals

NOTES:

1. GPIO Configuration registers within the Core Well are reset whenever PWROK is de­asserted.

2. GPIO Configuration registers within the Suspend Well are reset when RSMRST# is
asserted, CF9h reset (06h or 0Eh) event occurs, or SYS_RST# is asserted.

3. GPIO24 is an exception to the other GPIO Signals in the Suspend Well and is not
reset by CF9h reset (06h or 0Eh).

Table 2-25. General Purpose I/O Signals (Sheet 1 of 3)

Name Type Tolerance

GPIO75 I/O 3.3 V Suspend Native No Multiplexed with SML1DATA. (Note 10)

GPIO74 I/O 3.3 V Suspend Native No

GPIO73 I/O 3.3 V Suspend Native No Multiplexed with PCIECLKRQ0#

GPIO72 I/O 3.3 V Suspend

GPIO67 I/O 3.3 V Core Native No Multiplexed with CLKOUTFLEX3

GPIO66 I/O 3.3 V Core Native No Multiplexed with CLKOUTFLEX2

GPIO65 I/O 3.3 V Core Native No Multiplexed with CLKOUTFLEX1

GPIO64 I/O 3.3 V Core Native No Multiplexed with CLKOUTFLEX0

GPIO63 I/O 3.3 V Suspend Native No Multiplexed with SLP_S5#

GPIO62 I/O 3.3 V Suspend Native No Multiplexed with SUSCLK

GPIO61 I/O 3.3 V Suspend Native No Multiplexed with SUS_STAT#

GPIO60 I/O 3.3 V Suspend Native No Multiplexed with SML0ALERT#

GPIO59 I/O 3.3 V Suspend Native No Multiplexed with OC[0]#. (Note 10)

GPIO58 I/O 3.3 V Suspend Native No Multiplexed with SML1CLK

GPIO57 I/O 3.3 V Suspend GPI No Unmultiplexed

GPIO56 I/O 3.3 V Suspend Native No Multiplexed with PEG_B_CLKRQ#

GPIO55 I/O 3.3 V Core Native No Multiplexed with GNT3#

GPIO54 I/O 5.0 V Core Native No Multiplexed with REQ3#. (Note 10)

GPIO53 I/O 3.3 V Core Native No Multiplexed with GNT2#

GPIO52 I/O 5.0 V Core Native No Multiplexed with REQ2#.(Note 10)

GPIO51 I/O 3.3 V Core Native No Multiplexed with GNT1#

GPIO50 I/O 5.0 V Core Native No Multiplexed with REQ1#.(Note 10)

GPIO49 I/O 3.3V Core GPI No Multiplexed with SATA5GP.

GPIO48 I/O 3.3 V Core GPI No Multiplexed with SDATAOUT1.

GPIO47 I/O 3.3V Suspend Native No Multiplexed with PEG_A_CLKRQ#

GPIO46 I/O 3.3V Suspend Native No Multiplexed with PCIECLKRQ7#

GPIO45 I/O 3.3V Suspend Native No Multiplexed with PCIECLKRQ6#

Power

Well

Default

Native

(Mobile

Only)

Blink

Capability

No

Description

Multiplexed with SML1ALERT#. (Note

10)

Mobile: Multiplexed with BATLOW#.
Desktop: Unmultiplexed (Note 4)

Datasheet 87

Table 2-25. General Purpose I/O Signals (Sheet 2 of 3)

Signal Description

Name Type Tolerance

Power

Well

Default

Blink

Capability

Description

GPIO44 I/O 3.3V Suspend Native No Multiplexed with PCIECLKRQ5#

GPIO[43:40] I/O 3.3 V Suspend Native No Multiplexed with OC[4:1]#. (Note 10)

GPIO39 I/O 3.3 V Core GPI No Multiplexed with SDATAOUT0.

GPIO38 I/O 3.3 V Core GPI No Multiplexed with SLOAD.

GPIO37 I/O 3.3 V Core GPI No Multiplexed with SATA3GP.

GPIO36 I/O 3.3 V Core GPI No Multiplexed with SATA2GP.

GPIO35 I/O 3.3 V Core GPO No Unmultiplexed.

GPIO34 I/O 3.3 V Core GPI No Multiplexed with STP_PCI#

GPIO33 I/O 3.3 V Core GPO No

GPO,

GPIO32 I/O 3.3 V Core

Native

(Mobile

No

only)

Multiplexed with HDA_DOCK_EN#
(Mobile Only) (Note 4)

Desktop Only: Unmultiplexed
Mobile Only: Used as CLKRUN#,

unavailable as GPIO. (Note 4)

GPIO31 I/O 3.3 V Suspend GPI Yes Multiplexed with ACPRESENT (Note 6)

Multiplexed with SUS_PWR_DN_ACK
Desktop: Cannot be used for native

GPIO30 I/O 3.3 V Suspend GPI Yes

function. Used as GPIO30 only.
Mobile: Used as SUS_PWR_DN_ACK or

GPIO30

GPIO29 I/O 3.3 V Suspend GPI No Multiplexed with SLP_LAN# (Note 9)

GPIO28 I/O 3.3 V Suspend GPI Yes Unmultiplexed

GPIO27 I/O 3.3 V Suspend GPO Yes Unmultiplexed

GPIO26 I/O 3.3 V Suspend Native Yes Multiplexed with PCIECLKRQ4#

GPIO25 I/O 3.3 V Suspend Native Yes Multiplexed with PCIECLKRQ3#

Unmultiplexed

GPIO24 I/O 3.3 V Suspend GPO Yes

NOTE: GPIO24 configuration register

bits are not cleared by CF9h
reset event.

GPIO23 I/O 3.3 V Core Native Yes Multiplexed with LDRQ1#.

GPIO22 I/O 3.3 V Core GPI Yes Multiplexed with SCLOCK

GPIO21 I/O 3.3 V Core GPI Yes Multiplexed with SATA0GP

GPIO20 I/O 3.3 V Core Native Yes Multiplexed with PCIECLKRQ2#

GPIO19 I/O 3.3 V Core GPI Yes Multiplexed with SATA1GP

GPIO18 I/O 3.3 V Core Native Yes (Note 7) Multiplexed with PCIECLKRQ1#

GPIO17 I/O 3.3 V Core GPI Yes

Multiplexed with TACH0.
Mobile: Used as GPIO17 only.

GPIO16 I/O 3.3 V Core GPI Yes Multiplexed with SATA4GP.

GPIO15 I/O 3.3 V Suspend GPO Yes Unmultiplexed

GPIO14 I/O 3.3 V Suspend Native Yes Multiplexed with OC7#

88 Datasheet

Signal Description

Table 2-25. General Purpose I/O Signals (Sheet 3 of 3)

Name Type Tolerance

3.3 V or

GPIO13 I/O

1.5 V

(Note 11)

Power

Well

HDA

Suspend

Default

GPI Yes

Blink

Capability

Description

Multiplexed with HDA_DOCK_RST#
(Mobile Only) (Note 4)

Multiplexed with LAN_PHY_PWR_CTRL.

GPIO12 I/O 3.3 V Suspend Native Yes

GPIO / Native functionality controlled
using soft strap.

GPIO11 I/O 3.3 V Suspend Native Yes Multiplexed with SMBALERT#. (Note 10)

GPIO10 I/O 3.3 V Suspend Native Yes Multiplexed with OC6#. (Note 10)

GPIO9 I/O 3.3 V Suspend Native Yes Multiplexed with OC5#. (Note 10)

GPIO8 I/O 3.3 V Suspend GPO Yes Unmultiplexed

GPIO[7:6] I/O 3.3 V Core GPI Yes

Multiplexed with TACH[3:2].
Mobile: Used as GPIO[7:6] only.

GPIO[5:2] I/OD 5 V Core GPI Yes Multiplexed with PIRQ[H:E]# (Note 5).

GPIO1 I/O 3.3 V Core GPI Yes

Multiplexed with TACH1.
Mobile: Used as GPIO1 only.

GPIO0 I/O 3.3 V Core GPI Yes Unmultiplexed

NOTES:

1. All GPIOs can be configured as either input or output.

2. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to
either an SMI# or an SCI, but not both.

3. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO
signals are not driven high into powered-down planes. Also, external devices should not be
driving powered down GPIOs high. Some GPIOs may be connected to pins on devices that
exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core
power (PWROK low) or a Power Button Override event will result in the PCH driving a pin to
a logic 1 to another device that is powered down.

4. The functionality that is multiplexed with the GPIO may not be used in desktop
configuration.

5. When this signal is configured as GPO, the output stage is an open drain.

6. In a ME disabled system, GPIO31 may be used as ACPRESENT from the EC.

7. GPIO18 will toggle at a frequency of approximately 1 Hz when the signal is programmed as
a GPIO (when configured as an output) by BIOS.

8. This pins are used as Functional straps. See Section 2.28.1 for more detail.

9. For functional purposes of SLP_LAN# (the native functionality of the pin), this pin always
behaves as an output even if the GPIO defaults to an input. Therefore, this pin cannot be
used as a true GPIO29 by system designers. If Host BIOS does not control SLP_LAN#
control, SLP_LAN# behavior will be based on the setting of the RTC backed SLP_LAN#
Default Bit (D31:F0:A4h:Bit 8).

10. When the multiplexed GPIO is used as GPIO functionality, care should be taken to ensure
the signal is stable in its inactive state of the native functionality, immediately after reset
until it is initialized to GPIO functionality.

11. GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Voltage tolerance on the signal
is the same as VccSusHDA.

Datasheet 89

2.26 Manageability Signals

The following signals can be optionally used by the PCH Management engine supported
applications and appropriately configured by Management Engine firmware. When
configured and used as a Manageability function, the associated host GPIO functionality
is no longer available. If the Manageability function is not used in a platform, the signal
can be used as a host General Purpose I/O or a native function.

Table 2-26. Manageability Signals

Name Type Description

Signal Description

GPIO30/

PROC_MISSING

(Desktop Only)

SATA5GP / GPIO49 /

TEMP_ALERT#

ACPRESENT

(Mobile Only)/ GPIO31

SUS_PWR_DN_ACK

(Mobile Only)/ GPIO30

NOTE: SLP_LAN#/GPIO29 may also be configured by ME FW in Sx/Moff. See SLP_LAN#/GPIO29 signal

description for details.

Used to indicate Processor Missing to the PCH Management

I

Engine.

Used as an alert (active low) to indicate to the external
controller (such as, EC or SIO) that temperatures are out of

O

range for the PCH or Graphics/Memory Controller or the
processor core.

Used in Mobile systems. Input signal from the Embedded
Controller to indicate AC power source or the system battery.
Active High indicates AC power.

I

NOTE: This Signal is required unless using Intel Management

Engine Ignition firmware.

Active High output signal asserted by the Intel
Embedded Controller, when it does not require the PCH
Suspend well to be powered.

O

NOTE: This signal is required by Management Engine in all

platforms.

®

ME to the

90 Datasheet

Signal Description

2.27 Power and Ground Signals

Table 2-27. Power and Ground Signals (Sheet 1 of 2)

Name Description

DcpRTC

DcpSST

DcpSus

DcpSusByp

V5REF

V5REF_Sus

VccCore

Vcc3_3

VccME

VccME3_3

VccDMI

VccLAN

VccRTC

VccIO

VccSus3_3

VccSusHDA

VccVRM 1.8 V supply for internal PLL and VRMs

VccpNAND This pin should be pulled up to 1.8V or 3.3V.

Decoupling: This signal is for RTC decoupling only. This signal requires

decoupling.

Decoupling: Internally generated 1.5V powered off of Suspend Well. This
signal requires decoupling. Decoupling is required even if this feature is not
used.

Decoupling: 1.05 V Suspend well supply that is supplied internally by
Internal VRs. This signal requires decoupling.

Decoupling: 1.05 V Suspend well supply that is supplied internally by
Internal VRs. This signal requires decoupling.

Reference for 5 V tolerance on core well inputs. This power may be shut off in
S3, S4, S5 or G3 states.

Reference for 5 V tolerance on suspend well inputs. This power is not
expected to be shut off unless the system is unplugged.

1.05 V supply for core well logic. This power may be shut off in S3, S4, S5 or
G3 states.

3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4,
S5 or G3 states.

1.05 V supply for the Intel
S0 and other times the Intel

3.3 V supply for the Intel

®

Management Engine. This plane must be on in

®

Management Engine is used.

®

Management Engine I/O and SPI I/O. This is a
separate power plane that may or may not be powered in S3–S5 states. This
plane must be on in S0 and other times the Intel
used.

Power supply for DMI.

1.1 V or 1.05 V based on the processor used. See the respective processor
documentation to find the appropriate voltage level.

1.05 V supply for LAN controller logic. This is a separate power plane that
may or may not be powered in S3–S5 states.

NOTE: VccLAN may be grounded if Intel LAN is disabled.

3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power
is not expected to be shut off unless the RTC battery is removed or
completely drained.

NOTE: Implementations should not attempt to clear CMOS by using a jumper

to pull VccRTC low. Clearing CMOS in a PCH-based platform can be
done by using a jumper on RTCRST# or GPI.

1.05 V supply for core well I/O buffers. This power may be shut off in S3, S4,
S5 or G3 states.

3.3 V supply for suspend well I/O buffers. This power is not expected to be
shut off unless the system is unplugged.

®

Suspend supply for Intel

High Definition Audio. This pin can be either 1.5 or

3.3 V.

®

Management Engine is

Datasheet 91

Table 2-27. Power and Ground Signals (Sheet 2 of 2)

Name Description

VccADPLLA

VccADPLLB

VccADAC

Vss Grounds.

VSS_NCTF

Vcc3_3_NCTF

VccRTC_NCTF

VccSUS3_3_N

CTF

V_CPU_IO_NCTFNon-Critical To Function. These pins are for package mechanical reliability.

TP22_NCTF

VccAClk

VccSATAPLL

VccAPLLEXP

VccFDIPLL

VccALVDS 3.3 V Analog power supply for LVDS (Mobile Only)

VccTX_LVDS

V_CPU_IO

1.05 V supply for Display PLL A Analog Power. This power is supplied by the
core well.

1.05 V supply for Display PLL B Analog Power. This power is supplied by the
core well.

3.3 V supply for Display DAC Analog Power. This power is supplied by the core
well.

Non-Critical To Function. These pins are for package mechanical reliability.
NOTE: These pins should be connected to Ground.

Non-Critical To Function. These pins are for package mechanical reliability.
NOTE: These pins should be connected the same as the Vcc3_3 pins.

Non-Critical To Function. These pins are for package mechanical reliability.
NOTE: These pins should be connected to DcpRTC or left as No Connect.

Non-Critical To Function. These pins are for package mechanical reliability.
NOTE: These pins should be connected the same as the VccSUS3_3 pins.

NOTE: These pins should be connected the same as the V_CPU_IO pins.

Non-Critical To Function. These pins are for package mechanical reliability.
NOTE: These pins should be connected to Ground.

1.05 V Analog power supply for internal clock PLL. This requires a filter and
power is supplied by the core well.
NOTE: This pin can be left as no connect in On-Die VR enabled mode

(default).

1.05 V Analog power supply for SATA. This signal is used for the analog
power for SATA. This requires an LC filter and is supplied by the core well.
Must be powered even if SATA is not used.
NOTE: This pin can be left as no connect in On-Die VR enabled mode

(default).

1.05 V Analog Power for DMI. This power is supplied by the core well. This
requires an LC filter.
NOTE: This pin can be left as no connect in On-Die VR enabled mode

(default).

1.05 V analog power supply for the FDI PLL. This power is supplied with core
well. This requires an LC filter.
NOTE: This pin can be left as no connect in On-Die VR enabled mode

(default).

1.8 V I/O power supply for LVDS. (Mobile Only) This power is supplied by
core well.

Powered by the same supply as the processor I/O voltage. This supply is used
to drive the processor interface signals. See the respective processor
documentation to find the appropriate voltage level.

Signal Description

92 Datasheet

Signal Description

2.28 Pin Straps

2.28.1 Functional Straps

The following signals are used for static configuration. They are sampled at the rising
edge of PWROK to select configurations (except as noted), and then revert later to their
normal usage. To invoke the associated mode, the signal should be driven at least four
PCI clocks prior to the time it is sampled.

The PCH has implemented Soft Straps. Soft Straps are used to configure specific
functions within the PCH and processor very early in the boot process before BIOS or
SW intervention. When Descriptor Mode is enabled, the PCH will read Soft Strap data
out of the SPI device prior to the de-assertion of reset to both the Management Engine
and the Host system. See Section 5.24.2 for information on Descriptor Mode.

Table 2-28. Functional Strap Definitions (Sheet 1 of 4)

Signal Usage

SPKR No Reboot

INIT3_3V# Reserved

GNT[3]#/

GPIO[55]

INTVRMEN

Top - B lo c k

Swap Override

Integrated 1.05
V VRM Enable /

Disable

When

Sampled

Rising edge of

PWROK

Rising edge of

PWROK

Rising edge of

PWROK

Always

Comment

The signal has a weak internal pull-down.

NOTE: The internal pull-down is disabled after PLTRST# de-

asserts. If the signal is sampled high, this indicates
that the system is strapped to the “No Reboot”
mode (the PCH will disable the TCO Timer system
reboot feature). The status of this strap is readable
using the NO REBOOT bit (Chipset Config Registers:
Offset 3410h:bit 5).

This signal has a weak internal pull up. Note that the
internal pull-up is disabled after PLTRST# de-asserts.

NOTE: This signal should not be pulled low.

The signal has a weak internal pull-up. If the signal is
sampled low, this indicates that the system is strapped to
the “topblock swap” mode.

The status of this strap is readable using the Top Swap bit
(Chipset Config Registers:Offset 3414h:bit 0).

NOTES:

1. The internal pull-up is disabled after PLTRST#
deasserts.

2. Software will not be able to clear the Top-Swap bit
until the system is rebooted without GNT3#/GPIO55
being pulled down.

Integrated 1.05 V VRMs is enabled when high

NOTE: This signal should always be pulled high

Datasheet 93

Table 2-28. Functional Strap Definitions (Sheet 2 of 4)

Bit11 Bit 10

Boot BIOS

Destination

01 Reserved
10 PCI
11 SPI
00 LPC

Bit11 Bit 10

Boot BIOS

Destination

01 Reserved
10 PCI
11 SPI
00 LPC

Signal Description

Signal Usage

GNT1# /

GPIO51

Boot BIOS Strap

bit [1]

BBS[1]

When

Sampled

Rising edge of

PWROK

Comment

This signal has a weak internal pull-up.
Note that the internal pull-up is disabled after PCIRST# de-

asserts.
This field determines the destination of accesses to the

BIOS memory range. Also, controllable using Boot BIOS
Destination bit (Chipset Config Registers:Offset 3410h:bit

11). This strap is used in conjunction with Boot BIOS
Destination Selection 0 strap.

NOTE: If option 00 LPC is selected, BIOS may still be

placed on LPC; however, all platforms with the PCH
require SPI flash connected directly to the PCH SPI
bus with a valid descriptor to boot.

NOTE: Booting to PCI is intended for debut/testing only.

Boot BIOS Destination Select to LPC/PCI by
functional strap or using Boot BIOS Destination Bit
will not affect SPI accesses initiated by Intel

®

Management Engine or Integrated GbE LAN.

This Signal has a weak internal pull-up.
Note that the internal pull-up is disabled after PCIRST# de-

asserts.
This field determines the destination of accesses to the

BIOS memory range. Also, controllable using Boot BIOS
Destination bit (Chipset Config Registers:Offset 3410h:bit

10). This strap is used in conjunction with Boot BIOS
Destination Selection 1 strap.

GNT[0]#

94 Datasheet

Boot BIOS Strap

bit[0]

BBS[0]

Rising edge of

PWROK

NOTE: If option 00 LPC is selected, BIOS may still be

placed on LPC; however, all platforms with the PCH
require SPI flash connected directly to the PCH's SPI
bus with a valid descriptor to boot.

NOTE: Booting to PCI is intended for debut/testing only.

Boot BIOS Destination Select to LPC/PCI by
functional strap or using Boot BIOS Destination Bit
will not affect SPI accesses initiated by Management
Engine or Integrated GbE LAN.

Signal Description

Table 2-28. Functional Strap Definitions (Sheet 3 of 4)

Signal Usage

GNT2#/
GPIO53

ESI Strap

(Server Only)

NV_ALE Reserved

Flash Descriptor

HDA_DOCK_E

N#/GPIO[33]

Security

Override/ ME

Debug Mode

SPI_MOSI Reserved

NV_CLE

DMI Termination

Voltage

HDA_SDO Reserved

GPIO8 Reserved

GPIO27 Reserved

On-Die PLL

HDA_SYNC

Voltage

Regulator

Voltage Select

When

Sampled

Rising edge of

PWROK

Rising edge of

PWROK

Rising edge of

PWROK

Rising edge of

MEPWROK

Rising edge

of PWROK

Rising edge of

RSMRST#

Rising edge of

RSMRST#

Rising edge of

RSMRST#

Rising edge of
RSMRST# pin

Comment

This Signal has a weak internal pull-up.
Note that the internal pull-up is disabled after PCIRST# de-

asserts.
Tying this strap low configures DMI for ESI compatible

operation.
NOTE: ESI compatible mode is for server platforms only.

This signal should not be pulled low for desktop and
mobile.

This signal has a weak internal pull down.
NOTE: This signal should not be pulled high

Signal has a weak internal pull-up.
If strap is sampled high, the security measures defined in

the Flash Descriptor will be in effect (default).
If sampled low, the Flash Descriptor Security will be

overridden.
This strap should only be asserted low using external pull

down in manufacturing/debug environments ONLY.
NOTE: Asserting the GPIO33 low on the rising edge of

PWROK will also halt Intel
after chipset bringup and disable runtime Intel

®

Management Engine

®

Management Engine features. This is a debug mode
and must not be asserted after manufacturing/
debug.

This signal has a weak internal pull-down resistor. This
signal must be sampled low.

This signal has a weak internal pull-down.

This signal has a weak internal pull down.
NOTE: This signal should not be pulled high

This signal has a weak internal pull up. Note that the weak
internal pull-up is disabled after RSMRST# de-asserts.
NOTE: This signal should not be pulled low

This signal has a weak internal pull-up. note that the weak
internal pull-up is disabled after RSMRST# de-asserts.
NOTE: This signal should not be pulled low and can be left

as a No Connect.

This signal has a weak internal pull down.
On-Die PLL VR is supplied by 1.8 V when sampled low.

NOTE: This signal should not be pulled high.

Datasheet 95

Table 2-28. Functional Strap Definitions (Sheet 4 of 4)

Signal Description

Signal Usage

GPIO15 Reserved

L_DDC_DATA LVDS

SDVO_CTRLDATADigital Display

Port (Port B)

DDPC_CTRLDATADigital Display

Port (Port C)

DDPD_CTRLDATADigital Display

Port (Port D)

When

Sampled

Rising edge of

RSMRST# pin

Rising Edge of

PWROK

Rising Edge of

PWROK

Rising Edge of

PWROK

Rising Edge of

PWROK

Comment

Low = Intel

®

Management Engine Crypto Transport Layer

Security (TLS) cipher suite with no confidentiality

®

High = Intel

Management Engine Crypto TLS cipher suite

with confidentiality
This signal has a weak internal pull down.

NOTE: A strong pull up may be needed for GPIO

functionality

NOTE: This signa l i s r equired to be pulled up to enable TLS.

If this signal is pulled down or left floating Intel®
RPAT and Intel® AMT with TLS will not be
functional.

This signal has a weak internal pull-down.
Note that the weak internal pull-down is disabled after

PLTRST# de-asserts.
LVDS is enabled when sampled high. When sampled low

LVDS is Disabled.

This signal has a weak internal pull-down.
Note that the weak internal pull-down is disabled after

PLTRST# de-asserts.
Port B is enabled when sampled high. When sampled low

Port B is Disabled.

This signal has a weak internal pull-down.
Note that the weak internal pull-down is disabled after

PLTRST# de-asserts.
Port C is enabled when sampled high. When sampled low

Port C is Disabled.

This signal has a weak internal pull-down.
Note that the weak internal pull-down is disabled after

PLTRST# de-asserts.
Port D is enabled when sampled high. When sampled low

Port D is Disabled.

NOTE: See Section 3.1 for full details on pull-up/pull-down resistors.

96 Datasheet

32.768 KHz
Xtal

10MΩ

VCCRTC

RTCX2

RTCX1

Vbatt

1uF

1 K Ω

3.3V Sus

C1 C2

R1

RTCRST#

1.0 uF

20 KΩ

0.1uF

SRTCRST#

20 KΩ

1.0 uF

Schottky Diodes

Signal Description

2.28.2 External RTC Circuitry

The PCH implements an internal oscillator circuit that is sensitive to step voltage
changes in VccRTC. Figure 2-2 shows an example schematic recommended to ensure
correct operation of the PCH RTC.

Figure 2-2. Example External RTC Circuit

Notes:

1. The exact capacitor values for C1 and C2 must be based on the crystal maker recommendations.

2. Vbatt is voltage provided by the battery.

3. VccRTC, RTCX1, and RTCX2 are PCH pins.

4. VccRTC powers PCH RTC well.

5. RTCX1 is the input to the internal oscillator.

6. RTCX2 is the amplified feedback for the external crystal.

§ §

Datasheet 97

Signal Description

98 Datasheet

PCH Pin States

3 PCH Pin States

3.1 Integrated Pull-Ups and Pull-Downs

Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 1 of 2)

Signal Resistor Nominal Notes

CL_CLK1

CL_DATA1

CLKOUTFLEX[3:0]/GPIO[67:64] Pull-down 20K 1, 16

HDA_RST# Pull-down 20K 2, 16

GPIO15 Pull-down 20K 3, 21

HDA_BCLK Pull-down 20K 1, 16

HDA_DOCK_EN#/GPIO33 Pull-up 20K 3, 7

HDA_SDIN[3:0] Pull-down 20K 2

HDA_DOCK_RST# /GPIO13 Pull-down 20K 19, 20

HDA_SYNC, HDA_SDO Pull-down 20K 2, 7

GNT[3:1]#/GPIO[55,53,51], GNT0# Pull-up 20K 3, 11, 12

GPIO8 Pull-up 20K 3, 21

LAD[3:0]# / FHW[3:0]# Pull-up 20K 3

LDRQ0#, LDRQ1# / GPIO23 Pull-up 20K 3

NV_ALE, NV_CLE Pull-down 20K 13

PME# Pull-up 20K 3

INIT3_3V# Pull-up 20K 3

PWRBTN# Pull-up 20K 3

SPI_MOSI Pull-down 20K 3,7

SPI_CS0#, SPI_CS1#, SPI_MISO Pull-up 20K 3

SPKR Pull-down 20K 3,15

TACH[3:0]/GPIO[7,6,1,17] Pull-up 20K 3;only on TACH[3:0]

USB[13:0] [P,N] Pull-down 20K 5

DDP[D:C]_CTRLCLK Pull-down 10K

DDP[D:C]_CRTLDATA Pull down 20K 3, 15

SDVO_CTRLDATA,L_DDC_DATA Pull down 20K 3, 15

SDVO_CTRLCLK Pull down 20K 3

BATLOW#/GPIO72 Pull-up 20K 3

CLKOUT_PCI[4:0] Pull-down 20K 1, 16

GPIO27 Pull-up 20K 3, 21

PCIECLKRQ0#/GPIO73 Pull-up 20K 3, 21

JTAG_TDI, JTAG_TMS, TRST# Pull-up 20K 1, 17

Pull-up/Pull-

down

Pull-up/Pull-

down

32/100 13, 22

32/100 13, 22

Datasheet 99

Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 2 of 2)

Signal Resistor Nominal Notes

JTAG_TCK Pull-down 20K 1, 18

GPIO28 Pull-up 20K 3

PCIECLKRQ6#/GPIO45 Pull-up 20K 3

NOTES:

1. Simulation data shows that these resistor values can range from 10 kΩ to 40 kΩ.

2. Simulation data shows that these resistor values can range from 9 kΩ to 50 kΩ.

3. Simulation data shows that these resistor values can range from 15 kΩ to 40 kΩ.

4. Simulation data shows that these resistor values can range from 7.5kΩ to 16kΩ.

5. Simulation data shows that these resistor values can range from 14.25 kΩ to 24.8 kΩ.

6. Simulation data shows that these resistor values can range from 10 kΩ to 30 kΩ.

7. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function.

8. Simulation data shows that these resistor values can range from 10 kΩ to 20 kΩ.
The internal pull-up is only enabled during PLTRST# assertion.

9. The pull-down on this signal is only enabled when in S3.

10. The pull-up or pull-down on this signal is only enabled during reset.

11. The pull-up on this signal is not enabled when PCIRST# is high.

12. The pull-up on this signal is not enabled when PWROK is low.

13. Simulation data shows that these resistor values can range from 15 kΩ to 31 kΩ.

14. The pull-down is disabled after pins are driven strongly to logic zero when PWROK
is asserted.

15. The Pull-up or pull down is not active when PLTRST# is NOT asserted.

16. The pull-down is enabled when PWROK is low.

17. External termination is also required on these signals for JTAG enabling. Internal pull-up
is added in B-step Silicon.

18. External termination is also required on these signals for JTAG enabling. Internal pull-down
is added in B-step Silicon.

19. Simulation data shows that these resistor values can range from 20 kΩ to 27 kΩ.

20. Pull-down is enabled only when PCIRST# pin is driven low.

21. Pull-up is disabled after RSMRST# is de-asserted.

22. The Controller Link Clock and Data buffers use internal pull-up or pull-down resistors
to drive a logical 1 or 0.

PCH Pin States

100 Datasheet