Intel 324632-003 User Manual

Intel® 82575EB Gigabit Ethernet Controller Software Developer’s Manual and EEPROM Guide

LAN Access Division

324632-003

Revision: 2.1

January 2011

Intel® 82575EB Gigabit Ethernet Controller — Legal

Legal

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Pentium® 4 processor supporting HT Technology and a

Intel® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 2 January 2011

Revisions — Intel® 82575EB Gigabit Ethernet Controller

Revisions

Revision Date Description

.25 2/2006 Initial release (Intel Secret).

1.1 1/2008 • Updated Section 13.4.8.15 (bit 15 description).

• Updated Table 61 (bit 13 bit description).

.5 6/2006 Major revisions all sections.

1.0 6/2007 Final release (Intel Confidential).

1.2 6/2008 • Updated Section 5.6.1.5 (changed default device ID to 10A7h.

• Updated Section 5.6.1.1 (removed note concerning MAC addresses).

• Removed table note from Sections 13.7.4 through 13.7.6.

• Updated Sections 13.4.65 and 14.7 concerning COLD field values.

• Updated Section 13.4.8.15 (revised bit 15 description).

• Updated Section 13.4.8.19 (removed statement that D0LPLU can be loaded from the EEPROM.

• Updated Section 5.6.9 (added new PHY values).

.75 6/2006 Initial release (Intel Confidential).

1.3 9/2008 • Updated Section 13.4.2 (updated SPEED field description; bits

2.0 12/14/2010 • Section 4.1, EEPROM Device - EEPROM size data updated.

2.1 1/28/2011 • Updated brand strings. Updated title.

7:6).

• Replaced device ID table with note to refer to the spec update for supported device IDs.

• Section 4.5.1.29, PXE Words (Words 30h:3Eh) - Section updated. Specific field information exposed.

• Section 4.6.4, NC-SI Configuration Structure - Hardware default values added.

• Section 4.7.2, PBA Number (Words 08h, 09h) - Section updated to address new methodology.

• Section 5.4.1.3, Association through VLAN tag ID - Added.

• Section 5.4.1.4, Association through VLAN tag ID +RSS - Added.

• Section 10.2.1, Adding 802.1q Tags on Transmits - Section updated.

• Section 14.3.34, Interrupt Cause Read Register - ICR (000C0H; R)

- Note located in OUTSYNC description updated.

• ASF references removed.

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82575EB Gigabit Ethernet Controller

Intel® 82575EB Gigabit Ethernet Controller — Content

Content

1.0 Introduction ...........................................................................................................................19

1.1 Register and Bit References ........................................................................................................ 19

1.2 Byte and Bit Designations ........................................................................................................... 19

1.3 References ............................................................................................................................... 19

1.4 Memory Alignment Terminology .................................................................................................. 20

2.0 Architectural Overview ...........................................................................................................21

2.1 External Architecture ................................................................................................................. 21

2.1.1 Integrated 10/100/1000 Mb/s PHY......................................................................................... 22

2.1.2 System Interface................................................................................................................. 22

2.1.3 EEPROM Interface ............................................................................................................... 22

2.1.4 Flash Memory Interface........................................................................................................ 23

2.1.5 Management Interfaces........................................................................................................ 23

2.1.5.1 Software Watchdog ....................................................................................................... 23

2.1.6 General-Purpose I/O (Software-Definable Pins) ....................................................................... 23

2.1.7 LEDs.................................................................................................................................. 24

2.1.8 Network Interfaces .............................................................................................................. 24

2.2 DMA Addressing ........................................................................................................................ 24

2.3 Ethernet Addressing................................................................................................................... 25

2.4 Interrupt Control and Tuning....................................................................................................... 26

2.5 Hardware Acceleration Capability ................................................................................................. 26

2.5.1 Jumbo Frame Support.......................................................................................................... 27

2.5.2 Receive and Transmit Checksum Offloading ............................................................................ 27

2.5.3 TCP Segmentation ............................................................................................................... 27

2.5.4 Receive Fragmented UDP Checksum Offloading ....................................................................... 27

2.6 Buffer and Descriptor Structure ...................................................................................................27

2.7 Multiple Transmit Queues ........................................................................................................... 28

2.8 iSCSI Boot................................................................................................................................ 28

3.0 General Initialization and Reset Operation..............................................................................29

3.1 Power Up State ......................................................................................................................... 29

3.2 Initialization Sequence ............................................................................................................... 29

3.3 Interrupts During Initialization..................................................................................................... 29

3.4 Global Reset and General Configuration ........................................................................................ 30

3.5 Receive Initialization .................................................................................................................. 30

3.5.1 Initialize the Receive Control Register ....................................................................................31

3.5.2 Dynamic Queue Enabling and Disabling .................................................................................. 31

3.6 Transmit Initialization ................................................................................................................ 31

3.6.1 Dynamic Queue Enabling and Disabling .................................................................................. 32

3.7 Link Setup Mechanisms and Control/Status Bit Summary ................................................................ 32

3.7.1 PHY Initialization ................................................................................................................. 32

3.7.2 MAC/PHY Link Setup (CTRL_EXT.LINK_MODE = 00b) ............................................................... 32

3.7.3 MAC/SerDes Link Setup (CTRL_EXT.LINK_MODE = 11b)........................................................... 34

3.7.4 MAC/SGMII Link Setup (CTRL_EXT.LINK_MODE = 10b) ............................................................ 35

3.8 Reset Operation ........................................................................................................................ 37

3.8.1 PHY Behavior During a Manageability Session: ........................................................................ 41

3.9 Initialization of Statistics ............................................................................................................ 42

4.0 EEPROM and Flash Interface................................................................................................... 43

4.1 EEPROM Device ......................................................................................................................... 43

4.1.1 Software Accesses............................................................................................................... 43

4.1.2 Signature and CRC Fields ..................................................................................................... 44

4.1.3 EEPROM Recovery ............................................................................................................... 44

4.1.4 Protected EEPROM Space...................................................................................................... 45

4.1.5 Initial EEPROM Programming ................................................................................................ 45

4.1.6 Activating the Protection Mechanism ...................................................................................... 46

4.1.7 Non Permitted Accesses to Protected Areas in the EEPROM ....................................................... 46

4.1.8 EEPROM-Less Support.......................................................................................................... 46

Intel® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 4 January 2011

Content — Intel® 82575EB Gigabit Ethernet Controller

4.2 Flash Interface Operation ........................................................................................................... 49

4.2.1 Flash Write Control .............................................................................................................. 50

4.2.2 Flash Erase Control.............................................................................................................. 50

4.3 Shared EEPROM ........................................................................................................................ 50

4.3.1 EEPROM Deadlock Avoidance ................................................................................................ 50

4.3.2 EEPROM Map Shared Words.................................................................................................. 51

4.4 Shared FLASH........................................................................................................................... 51

4.4.1 Flash Access Contention ....................................................................................................... 52

4.4.2 Flash Deadlock Avoidance..................................................................................................... 52

4.5 EEPROM Map ............................................................................................................................ 52

4.5.1 Hardware Accessed Words....................................................................................................54

4.5.1.1 Ethernet Address (Words 00h – 02h) ............................................................................... 56

4.5.1.2 Initialization Control 1 (Word 0Ah) .................................................................................. 56

4.5.1.3 Subsystem ID (Word 0Bh) ............................................................................................. 57

4.5.1.4 Subsystem Vendor ID (Word 0Ch)................................................................................... 57

4.5.1.5 Device ID (Word 0Dh, 11h) ............................................................................................ 57

4.5.1.6 Dummy Device ID (Word 1Dh) ....................................................................................... 57

4.5.1.7 Initialization Control 2 (Word 0Fh)................................................................................... 57

4.5.1.8 Software Defined Pins Control (Word 10h)........................................................................ 59

4.5.1.9 EEPROM Sizing & Protected Fields (Word 12h) .................................................................. 60

4.5.1.10 Initialization Control 3 (Word 14h, 24h) ........................................................................... 61

4.5.1.11 NC-SI and PCIe* Completion Timeout Configuration (Word 15h) ......................................... 63

4.5.1.12 MSI-X Configuration (Word 16h) ..................................................................................... 64

4.5.1.13 PLL/Lane/PHY Initialization Pointer (Word 17h) ................................................................. 64

4.5.1.14 PCIe* Initialization Configuration 1 (Word 18h)................................................................. 64

4.5.1.15 PCIe* Initialization Configuration 2 (Word 19h)................................................................. 64

4.5.1.16 Software Defined Pins Control (Word 20h)........................................................................ 65

4.5.1.17 PCIe* Initialization Configuration 3 (Word 1Ah)................................................................. 66

4.5.1.18 PCIe* Control (Word 1Bh) .............................................................................................. 68

4.5.1.19 LED 1, 3 Configuration Defaults (Word 1Ch) ..................................................................... 69

4.5.1.20 Device Revision ID (Word 1Eh) ....................................................................................... 70

4.5.1.21 LED 0, 2 Configuration Defaults (Word 1Fh)...................................................................... 70

4.5.1.22 Functions Control (Word 21h) ......................................................................................... 72

4.5.1.23 LAN Power Consumption (Word 22h) ............................................................................... 72

4.5.1.24 Management Hardware Configuration Control (Word 23h) .................................................. 72

4.5.1.25 End of RO Area (Word 2Ch ............................................................................................. 74

4.5.1.26 Start of RO Area (Word 2Dh) .......................................................................................... 74

4.5.1.27 Watchdog Configuration (Word 2Eh) ................................................................................ 74

4.5.1.28 VPD Pointer (Word 2Fh) ................................................................................................. 74

4.5.1.29 PXE Words (Words 30h:3Eh) .......................................................................................... 74

4.5.1.29.1 Main Setup Options PCI Function 0 (Word 30h) .............................................................. 74

4.5.1.29.2 Configuration Customization Options PCI Function 0 (Word 31h) ...................................... 76

4.5.1.29.3 PXE Version (Word 32h)............................................................................................ 77

4.5.1.29.4 IBA Capabilities (Word 33h) ........................................................................................ 77

4.5.1.29.5 Setup Options PCI Function 1 (Word 34h) ..................................................................... 77

4.5.1.29.6 Configuration Customization Options PCI Function 1 (Word 35h) ...................................... 78

4.5.1.29.7 iSCSI Option ROM Version (Word 36h).......................................................................... 78

4.5.1.29.8 Alternate MAC Address Pointer (Word 37h).................................................................... 78

4.5.1.29.9 Setup Options PCI Function 2 (Word 38h) ..................................................................... 78

4.5.1.29.10 Configuration Customization Options PCI Function 2 (Word 39h) ...................................... 78

4.5.1.29.11 Setup Options PCI Function 3 (Word 3Ah) ..................................................................... 78

4.5.1.29.12 Configuration Customization Options PCI Function 3 (Word 3Bh) ...................................... 78

4.5.1.29.13 iSCSI Boot Configuration Offset (Word 3Dh) .................................................................. 78

4.5.1.29.13.1 iSCSI Module Structure ........................................................................................ 78

4.5.1.29.14 Checksum Word (Word 3Fh)........................................................................................ 80

4.6 Manageability Control Sections .................................................................................................... 81

4.6.1 Sideband Configuration Structure .......................................................................................... 81

4.6.1.1 Section Header - (0ffset 0h) ........................................................................................... 81

4.6.1.2 SMBus Max Fragment Size - (0ffset 01h).......................................................................... 81

4.6.1.3 SMBus Notification Timeout and Flags - (0ffset 02h) .......................................................... 81

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Intel® 82575EB Gigabit Ethernet Controller — Content

4.6.1.4 SMBus Slave Addresses - (0ffset 03h).............................................................................. 81

4.6.1.5 SMBus Fail-Over Register (Low Word) - (0ffset 04h) .......................................................... 83

4.6.1.6 SMBus Fail-Over Register (High Word) - (0ffset 05h) ......................................................... 83

4.6.1.7 NC-SI Configuration (0ffset 06h)..................................................................................... 83

4.6.2 Flex TCO Filter Configuration Structure................................................................................... 83

4.6.2.1 Section Header - (0ffset 0h) ........................................................................................... 83

4.6.2.2 Flex Filter Length and Control - (0ffset 01h) ..................................................................... 85

4.6.2.3 Flex Filter Enable Mask - (0ffset 02 - 09h) ........................................................................ 85

4.6.2.4 Flex Filter Data - (0ffset 0Ah - Block Length) .................................................................... 85

4.6.3 NC-SI Microcode Download Structure ..................................................................................... 85

4.6.3.1 Data Patch Size (Offset 0h) ............................................................................................ 85

4.6.3.2 Rx and Tx Code Size (Offset 1h) ..................................................................................... 85

4.6.3.3 Download Data (Offset 2h - Data Size)............................................................................. 85

4.6.4 NC-SI Configuration Structure............................................................................................... 86

4.6.4.1 Section Header - (0ffset 0h) ........................................................................................... 86

4.6.4.2 Rx Mode Control1 (RR_CTRL[15:0]) (Offset 01h)............................................................... 86

4.6.4.3 Rx Mode Control2 (RR_CTRL[31:16]) (Offset 02h)............................................................. 86

4.6.4.4 Tx Mode Control1 (RT_CTRL[15:0]) (Offset 03h) .............................................................. 86

4.6.4.5 Tx Mode Control2 (RT_CTRL[31:16]) (Offset 04h) ............................................................. 87

4.6.4.6 MAC Tx Control Reg1 (TxCntrlReg1 (15:0]) (Offset 05h) .................................................... 87

4.6.4.7 MAC Tx Control Reg2 (TxCntrlReg1 (31:16]) (Offset 06h) .................................................. 87

4.6.5 Common Firmware Pointer ................................................................................................... 87

4.6.5.1 Manageability Capability/Manageability Enable (Word 54h) ................................................. 88

4.6.6 Pass Through Pointers.......................................................................................................... 88

4.6.6.1 PT LAN0 Configuration Pointer (Word 56h) ....................................................................... 88

4.6.6.2 SMBus Configuration Pointer (Word 57h).......................................................................... 88

4.6.6.3 Flex TCO Filter Configuration Pointer (Word 58h)............................................................... 88

4.6.6.4 PT LAN1 Configuration Pointer (Word 59h) ....................................................................... 90

4.6.6.5 NC-SI Microcode Download Pointer (Word 5Ah)................................................................. 90

4.6.6.6 NC-SI Configuration Pointer (Word 5Bh)........................................................................... 90

4.6.7 PT LAN Configuration Structure .............................................................................................90

4.6.7.1 Section Header (Offset 0h) ............................................................................................. 90

4.6.7.2 LAN0 IPv4 Address 0 LSB, MIPAF0 (Offset 01h)................................................................. 90

4.6.7.3 LAN0 IPv4 Address 0 LSB, MIPAF0 (Offset 02h)................................................................. 90

4.6.7.4 LAN0 IPv4 Address 1; MIPAF1 (Offset 03h:04h) ................................................................ 90

4.6.7.5 LAN0 IPv4 Address 2; MIPAF2 (Offset 05h:06h) ................................................................ 91

4.6.7.6 LAN0 IPv4 Address 3; MIPAF3 (Offset 07h:08h) ................................................................ 91

4.6.7.7 LAN0 MAC Address 0 LSB, MMAL0 (Offset 09h) ................................................................. 91

4.6.7.8 LAN0 MAC Address 0 LSB, MMAL0 (Offset 0Ah) ................................................................. 91

4.6.7.9 LAN0 MAC Address 0 MSB, MMAH0 (Offset 0Bh)................................................................ 91

4.6.7.10 LAN0 MAC Address 1; MMAL/H1 (Offset 0Ch:0Eh) ............................................................. 91

4.6.7.11 LAN0 MAC Address 2; MMAL/H2 (Offset 0Fh:11h).............................................................. 91

4.6.7.12 LAN0 MAC Address 3; MMAL/H3 (Offset 12h:14h) ............................................................. 91

4.6.7.13 LAN0 UDP Flex Filter Ports 0:15; MFUTP Registers (Offset 15h:24h)..................................... 92

4.6.7.14 LAN0 VLAN Filter 0:7; MAVTV Registers (Offset 25h:2Ch)................................................... 92

4.6.7.15 LAN0 Manageability Filters Valid; MFVAL LSB (Offset 2Dh) .................................................. 92

4.6.7.16 LAN0 Manageability Filters Valid; MFVAL MSB (Offset 2Eh) ................................................. 92

4.6.7.17 LAN0 MAC Value MSB (Offset 2Fh) .................................................................................. 93

4.6.7.18 LAN0 MANC Value LSB (Offset 30h) ................................................................................. 93

4.6.7.19 LAN0 Receive Enable 1(Offset 31h) ................................................................................. 93

4.6.7.20 LAN0 Receive Enable 2 (Offset 32h) ................................................................................ 93

4.6.7.21 LAN0 MANC2H Value LSB (Offset 33h) ............................................................................. 95

4.6.7.22 LAN0 MANC2H Value MSB (Offset 34h) ............................................................................ 95

4.6.7.23 Manageability Decision Filters; MDEF0,1 (Offset 35h)......................................................... 95

4.6.7.24 Manageability Decision Filters; MDEF0, 2 (Offset 36h) ........................................................ 96

4.6.7.25 Manageability Decision Filters; MDEF1:6, 1:2 (Offset 37h:42h) ........................................... 96

4.6.7.26 ARP Response IPv4 Address 0 LSB (Offset 43h) ................................................................ 97

4.6.7.27 ARP Response IPv4 Address 0 MSB (Offset 44h)................................................................ 97

4.6.7.28 LAN0 IPv6 Address 0 LSB; MIPAF (Offset 45h) .................................................................. 97

4.6.7.29 LAN0 IPv6 Address 0 MSB; MIPAF (Offset 46h) ................................................................. 97

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Content — Intel® 82575EB Gigabit Ethernet Controller

4.6.7.30 LAN0 IPv6 Address 0 LSB; MIPAF (Offset 47h) .................................................................. 97

4.6.7.31 LAN0 IPv6 Address 0 MSB; MIPAF (Offset 48h) ................................................................. 97

4.6.7.32 LAN0 IPv6 Address 0 LSB; MIPAF (Offset 49h) .................................................................. 98

4.6.7.33 LAN0 IPv6 Address 0 MSB; MIPAF (Offset 4Ah) ................................................................. 98

4.6.7.34 LAN0 IPv6 Address 0 LSB; MIPAF (Offset 4B).................................................................... 98

4.6.7.35 LAN0 IPv6 Address 0 MSB; MIPAF (Offset 4Ch) ................................................................. 98

4.6.7.36 LAN0 IPv6 Address 1; MIPAF (Offset 4Dh) ........................................................................ 98

4.6.7.37 LAN0 IPv6 Address 2; MIPAF (Offset 55h:5Ch).................................................................. 98

4.7 Software Owned EEPROM Words..................................................................................................98

4.7.1 Compatibility Fields (Word 03h:07h) ...................................................................................... 99

4.7.2 PBA Number (Words 08h, 09h) ............................................................................................. 99

5.0 Receive and Transmit Description......................................................................................... 101

5.1 82575 Data Flows.................................................................................................................... 101

5.1.1 Transmit Data Flow ............................................................................................................101

5.2 Receive Data Flow ................................................................................................................... 102

5.3 Receive Functionality ............................................................................................................... 102

5.3.1 Packet Address Filtering ......................................................................................................103

5.3.2 Receive Data Storage .........................................................................................................103

5.3.3 Legacy Receive Descriptor Format ........................................................................................104

5.3.3.1 Length Field ................................................................................................................104

5.3.3.2 Packet Checksum.........................................................................................................104

5.3.3.3 Receive Descriptor Status Field ...................................................................................... 105

5.3.3.4 Receive Descriptor Errors Field ......................................................................................107

5.3.3.5 VLAN Tag Field ............................................................................................................109

5.3.4 Advanced Receive Descriptors..............................................................................................109

5.3.4.1 Packet Buffer Address................................................................................................... 109

5.3.4.2 Header Buffer Address .................................................................................................. 109

5.3.4.3 Packet Type ................................................................................................................111

5.3.4.4 RSS Type.................................................................................................................... 111

5.3.4.5 Split Header ................................................................................................................ 111

5.3.4.6 Packet Checksum.........................................................................................................112

5.3.4.7 RSS Hash Value ...........................................................................................................113

5.3.4.8 Extended Status ..........................................................................................................113

5.3.4.9 Extended Errors...........................................................................................................114

5.3.4.10 Packet Buffer (Number of Bytes Exists in the Host Packet Buffer) .......................................115

5.3.4.11 VLAN Tag Field ............................................................................................................116

5.3.5 Receive UDP Fragmentation Checksum..................................................................................116

5.3.6 Receive Descriptor Fetching .................................................................................................116

5.3.7 Receive Descriptor Write-Back .............................................................................................117

5.3.7.1 Receive Descriptor Packing............................................................................................ 117

5.3.8 Receive Descriptor Ring Structure.........................................................................................117

5.4 Multiple Receive Queues ........................................................................................................... 119

5.4.1 Queuing for Virtual Machine Devices (VMDq)..........................................................................120

5.4.1.1 Association Through MAC Address ..................................................................................120

5.4.1.2 Association Through MAC Address + RSS ........................................................................121

5.4.1.3 Association through VLAN tag ID.................................................................................... 121

5.4.1.4 Association through VLAN tag ID +RSS ...........................................................................121

5.4.2 Multiple Receive Queues & Receive-Side Scaling (RSS) ............................................................122

5.4.2.1 RSS Hash Function.......................................................................................................122

5.4.2.1.1 Hash for IPv4 with TCP ..............................................................................................124

5.4.2.1.2 Hash for IPv4 with UDP.............................................................................................. 125

5.4.2.1.3 Hash for IPv4 without TCP.......................................................................................... 125

5.4.2.1.4 Hash for IPv6 with TCP ..............................................................................................125

5.4.2.1.5 Hash for IPv6 with UDP.............................................................................................. 125

5.4.2.1.6 Hash for IPv6 without TCP.......................................................................................... 125

5.4.2.2 Indirection Table.......................................................................................................... 125

5.4.2.3 Support for Multiple Processors ...................................................................................... 126

5.4.3 RSS Verification Suite .........................................................................................................126

5.4.3.1 IPv4...........................................................................................................................126

5.4.3.2 IPv6...........................................................................................................................126

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Intel® 82575EB Gigabit Ethernet Controller — Content

5.5 Header Splitting and Replication ................................................................................................ 127

5.5.1 Receive Packet Checksum Offloading ................................................................................... 130

5.5.1.1 MAC Address Filter .......................................................................................................131

5.5.1.2 SNAP/VLAN Filter .........................................................................................................131

5.5.1.3 IPv4 Filter ...................................................................................................................131

5.5.1.4 IPv6 Filter ...................................................................................................................131

5.5.1.5 IPv6 Extension Headers ................................................................................................132

5.5.1.6 UDP/TCP Filter.............................................................................................................133

5.6 Packet Transmission ................................................................................................................ 133

5.6.1 Transmit Data Storage ....................................................................................................... 134

5.6.2 Transmit Contexts ............................................................................................................. 134

5.6.3 Transmit Descriptors.......................................................................................................... 135

5.6.4 Legacy Transmit Descriptor Format...................................................................................... 135

5.6.5 Transmit Descriptor Write Back Format ................................................................................ 136

5.6.5.1 Length........................................................................................................................136

5.6.5.2 Checksum Offset and Start (CSO and CSS)...................................................................... 136

5.6.5.3 Command Byte (CMD) .................................................................................................. 137

5.6.5.4 Transmit Descriptor Status Field Format.......................................................................... 139

5.6.6 Transmit Descriptor Special Field Format .............................................................................. 139

5.6.7 Advanced Transmit Context Descriptor ................................................................................. 140

5.6.7.1 Maximum Segment Size (MSS) Control ...........................................................................141

5.6.8 Advanced Transmit Data Descriptor ..................................................................................... 142

5.6.8.1 Address ......................................................................................................................142

5.6.8.2 DTALEN ......................................................................................................................142

5.6.8.3 DTYP ..........................................................................................................................142

5.6.8.4 DCMD.........................................................................................................................143

5.6.8.5 STA............................................................................................................................144

5.6.8.6 IDX ............................................................................................................................144

5.6.8.7 POPTS ........................................................................................................................ 144

5.6.8.8 PAYLEN.......................................................................................................................144

5.7 Transmit Descriptor Ring Structure ............................................................................................ 144

5.7.1 Transmit Descriptor Fetching .............................................................................................. 146

5.7.2 Transmit Descriptor Write-Back ........................................................................................... 146

5.8 TCP Segmentation ................................................................................................................... 147

5.8.1 Assumptions..................................................................................................................... 148

5.8.2 Transmission Process......................................................................................................... 148

5.8.2.1 TCP Segmentation Data Fetch Control............................................................................. 148

5.8.3 TCP Segmentation Performance .......................................................................................... 148

5.8.4 Packet Format .................................................................................................................. 149

5.8.5 TCP Segmentation Indication .............................................................................................. 149

5.8.6 IP and TCP/UDP Headers .................................................................................................... 151

5.8.7 IP/TCP/UDP Header Updating.............................................................................................. 156

5.8.7.1 TCP/IP/UDP Header for the First Frame ........................................................................... 157

5.8.7.2 TCP/IP/UDP Header for the Subsequent Frames ...............................................................157

5.8.7.3 TCP/IP/UDP Header for the Last Frame ...........................................................................158

5.9 IP/TCP/UDP Transmit Checksum Offloading ................................................................................. 158

5.10 IP/TCP/UDP Transmit Checksum Offloading in Non-Segmentation Mode .......................................... 159

5.10.1 IP Checksum .................................................................................................................... 159

5.10.2 TCP Checksum .................................................................................................................. 160

5.11 Multiple Transmit Queues ......................................................................................................... 160

5.12 Tx Completions Head Write-Back ............................................................................................... 161

5.13 Interrupts............................................................................................................................... 162

5.13.1 Interrupt Cause Register (ICR)............................................................................................ 162

5.13.2 Interrupt Cause Set Register (ICS) ...................................................................................... 163

5.13.3 Interrupt Mask Set/Read Register (IMS) ............................................................................... 163

5.13.4 Interrupt Mask Clear Register (IMC)..................................................................................... 163

5.13.5 Interrupt Acknowledge Auto-mask register (IAM)................................................................... 163

5.13.6 Extended Interrupt Cause Registers (EICR)........................................................................... 163

5.13.7 Extended Interrupt Cause Set Register (EICS)....................................................................... 164

Intel® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 8 January 2011

Content — Intel® 82575EB Gigabit Ethernet Controller

5.13.8 Extended Interrupt Mask Set and Read Register (EIMS)/Extended Interrupt Mask Clear Register (EIMC) 164

5.13.9 Extended Interrupt Auto Clear Enable Register (EIAC).............................................................164

5.13.10 Extended Interrupt Auto Mask Enable Register (EIAM).............................................................164

5.13.11 Interrupt Modes Setting Bits ................................................................................................165

5.14 Interrupt Moderation................................................................................................................ 165

5.15 Clearing Interrupt Causes ......................................................................................................... 168

5.15.1 Auto-Clear.........................................................................................................................168

5.15.2 Write to Clear ....................................................................................................................169

5.15.3 Read to Clear.....................................................................................................................169

5.16 Dynamic Interrupt Moderation................................................................................................... 169

5.16.1 TCP Timer Interrupt............................................................................................................170

5.17 Memory Error Correction and Detection ...................................................................................... 170

6.0 PCIe* Local Bus Interface..................................................................................................... 173

6.1 General Functionality ............................................................................................................... 173

6.1.1 Message Handling (Receive Side) .........................................................................................173

6.1.2 Message Handling (Transmit Side)........................................................................................173

6.1.3 Data Alignment ..................................................................................................................174

6.1.3.1 4 KB Boundary ............................................................................................................174

6.1.4 Transaction Attributes.........................................................................................................174

6.1.4.1 Traffic Class and Virtual Channels................................................................................... 174

6.1.4.2 Relaxed Ordering ......................................................................................................... 175

6.1.4.3 Snoop Not Required .....................................................................................................175

6.1.4.3.1 No Snoop and Relaxed Ordering for LAN Traffic.............................................................175

6.1.4.3.2 No Snoop Option for Payload ......................................................................................175

6.2 Flow Control ........................................................................................................................... 176

6.2.1 Flow Control Rules..............................................................................................................176

6.2.2 Upstream Flow Control Tracking ...........................................................................................176

6.2.3 Flow Control Update Frequency ............................................................................................177

6.2.4 Flow Control Timeout Mechanism..........................................................................................177

6.2.5 Error Forwarding ................................................................................................................177

6.3 Host Interface......................................................................................................................... 177

6.3.1 Tag IDs.............................................................................................................................177

6.3.2 Completion Timeout Mechanism ...........................................................................................181

6.4 Error Events and Error Reporting ............................................................................................... 182

6.4.1 Error Events ......................................................................................................................182

6.4.2 Error Pollution....................................................................................................................184

6.4.3 Unsuccessful Completion Status ..........................................................................................184

6.4.4 Error Reporting Changes .....................................................................................................184

6.5 Link Layer .............................................................................................................................. 185

6.5.1 ACK/NAK Scheme...............................................................................................................185

6.5.2 Supported DLLPs................................................................................................................185

6.5.3 Transmit EDB Nullifying.......................................................................................................186

6.6 Physical Layer ......................................................................................................................... 186

6.6.1 Link Width.........................................................................................................................186

6.6.1.1 Polarity Inversion.........................................................................................................187

6.6.1.2 L0s Exit latency ...........................................................................................................187

6.6.1.3 Lane-to-Lane De-Skew .................................................................................................187

6.6.1.4 Lane Reversal.............................................................................................................. 187

6.6.1.5 Reset .........................................................................................................................188

6.6.1.6 Scrambler Disable ........................................................................................................188

6.6.2 Performance Monitoring ......................................................................................................188

6.6.3 Configuration Registers .......................................................................................................188

6.6.3.1 PCI Compatibility .........................................................................................................188

6.6.4 Mandatory PCI Configuration Registers.................................................................................. 189

6.6.5 PCI Power Management Registers.........................................................................................195

6.6.5.1 Message Signaled Interrupt (MSI) Configuration Registers .................................................197

6.6.5.2 MSI-X Configuration ..................................................................................................... 198

6.6.5.3 PCIe* Configuration Registers........................................................................................ 201

6.6.5.3.1 PCIe* Extended Configuration Space ...........................................................................210

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6.6.5.3.2 Advanced Error Reporting Capability............................................................................211

6.6.5.3.3 Device Serial Number ................................................................................................211

7.0 Power Management .............................................................................................................. 215

7.1 Power States .......................................................................................................................... 215

7.2 Auxiliary Power ....................................................................................................................... 216

7.3 Form Factor Power Limits ......................................................................................................... 216

7.4 Power Management Interconnects ............................................................................................. 217

7.4.0.1 PCIe* Link Power Management ......................................................................................217

7.4.0.2 NC-SI Clock Control .....................................................................................................219

7.4.0.3 PHY Power Management ...............................................................................................219

7.4.0.3.1 Link Speed Control ....................................................................................................219

7.4.0.3.2 D0a State ................................................................................................................220

7.4.0.3.3 Non-D0a State..........................................................................................................221

7.4.0.3.4 Link Energy Detect ....................................................................................................221

7.4.0.3.5 PHY Power-Down State .............................................................................................. 221

7.4.0.3.6 SerDes/SGMII Power-Down State................................................................................222

7.4.1 Power States .................................................................................................................... 222

7.4.1.1 Dr State .....................................................................................................................222

7.4.1.1.1 Dr Disable Mode .......................................................................................................222

7.4.1.1.2 Entry to Dr State ......................................................................................................223

7.4.1.2 D0 Uninitialized State ...................................................................................................223

7.4.1.2.1 Entry to D0u State ....................................................................................................223

7.4.1.3 D0 Active State............................................................................................................224

7.4.1.3.1 Entry to D0a State ....................................................................................................224

7.4.1.4 D3 State .....................................................................................................................224

7.4.1.4.1 Entry to D3 State......................................................................................................224

7.4.1.4.2 Master Disable.......................................................................................................... 225

7.4.1.5 Link-Disconnect ...........................................................................................................225

7.4.2 Power-State Transitions Timing ........................................................................................... 226

7.4.2.1 Power Up (Off to Dup to D0u to D0a).............................................................................. 226

7.4.2.2 Transition from D0a to D3 and Back without PE_RST_N.....................................................227

7.4.2.3 Transition from D0a to D3 and Back with PE_RST_N .........................................................228

7.4.2.4 D0a to Dr and Back without Transition to D3 ...................................................................229

7.4.2.5 Timing Requirements.................................................................................................... 229

7.4.2.6 Timing Guarantees .......................................................................................................230

7.4.3 82575 and SerDes Power-Down State .................................................................................. 230

7.4.3.1 SerDes Power-Down State.............................................................................................230

7.4.3.2 82575 Power-Down State.............................................................................................. 231

7.5 Wake Up ................................................................................................................................ 231

7.5.1 Advanced Power Management Wakeup................................................................................. 231

7.5.2 PCIe Power Management Wakeup........................................................................................ 232

7.5.3 Wake-Up Packets .............................................................................................................. 233

7.5.3.1 Pre-Defined Filters .......................................................................................................233

7.5.3.1.1 Directed Exact Packet ................................................................................................ 233

7.5.3.1.2 Directed Multicast Packet ...........................................................................................233

7.5.3.1.3 Broadcast ................................................................................................................234

7.5.3.1.4 Magic Packet* ..........................................................................................................234

7.5.3.1.5 ARP/IPv4 Request Packet ........................................................................................... 235

7.5.3.1.6 Directed IPv4 Packet .................................................................................................235

7.5.3.1.7 Directed IPv6 Packet .................................................................................................236

7.5.3.2 Flexible Filter...............................................................................................................236

7.5.3.2.1 IPX Diagnostic Responder Request Packet ....................................................................237

7.5.3.2.2 Directed IPX Packet...................................................................................................237

7.5.3.2.3 IPv6 Neighbor Discovery Filter ....................................................................................238

7.5.3.3 Wake Up Packet Storage ............................................................................................... 238

8.0 DCA ...................................................................................................................................... 239

8.1 Implementation Details ............................................................................................................ 239

8.1.1 PCIe* Message Format for DCA (MWr Mode) ......................................................................... 239

Intel® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 10 January 2011

Content — Intel® 82575EB Gigabit Ethernet Controller

9.0 Ethernet Interface ................................................................................................................ 241

9.1 Internal MAC/PHY 10/100/1000Base-T Interface.......................................................................... 242

9.1.1 MDIO/MDC ........................................................................................................................242

9.2 Duplex Operation for Copper PHY Operation ................................................................................ 243

9.2.1 Full Duplex ........................................................................................................................243

9.2.2 Half Duplex .......................................................................................................................244

9.2.3 Gigabit Physical Coding Sub-Layer (PCS) for SerDes ...............................................................244

9.2.3.1 8B10B Encoding/Decoding ............................................................................................244

9.2.3.2 Code Groups and Ordered Sets ...................................................................................... 245

9.2.4 SGMII Encoding in 10/100 Mb/s ...........................................................................................245

9.3 Auto-Negotiation and Link Setup ............................................................................................... 246

9.3.1 SerDes Link Configuration ...................................................................................................246

9.3.1.1 SerDes Mode Auto-Negotiation ......................................................................................246

9.3.1.2 PCS Hardware Auto-Negotiation ..................................................................................... 247

9.3.1.3 Forcing Link ................................................................................................................ 247

9.3.1.4 Hardware Detection of Non-Auto-Negotiation Partner........................................................248

9.3.1.5 SGMII Auto-Negotiation ................................................................................................ 248

9.3.2 Copper PHY Link Configuration .............................................................................................249

9.3.2.1 PHY Auto-Negotiation (Speed, Duplex, and Flow Control) ..................................................249

9.3.2.2 MAC Speed Resolution .................................................................................................. 249

9.3.2.2.1 Forcing MAC Speed ...................................................................................................249

9.3.2.2.2 Using Internal PHY Direct Link-Speed Indication............................................................250

9.3.2.3 MAC Full/Half Duplex Resolution ....................................................................................250

9.3.2.4 Using PHY Registers .....................................................................................................250

9.3.2.5 Comments Regarding Forcing Link.................................................................................. 251

9.3.3 Loss of Signal/Link Status Indication.....................................................................................251

9.3.4 Flow Control ......................................................................................................................251

9.3.4.1 MAC Control Frames and Reception of Flow Control Packets ............................................... 252

9.3.5 Discard PAUSE Frames and Pass MAC Control Frames .............................................................254

9.3.6 Transmission of PAUSE Frames ............................................................................................254

9.3.7 Software Initiated PAUSE Frame Transmission........................................................................255

9.4 Loopback Support.................................................................................................................... 255

9.4.1 MAC Loopback ...................................................................................................................256

9.4.1.1 Setting the 82575 to MAC Loopback Mode ....................................................................... 256

9.4.2 Internal PHY Loopback ........................................................................................................256

9.4.2.1 Setting the 82575 to Internal PHY Loopback Mode............................................................256

9.4.3 Internal SerDes Loopback....................................................................................................257

9.4.3.1 Setting Internal SerDes Loopback Mode ..........................................................................257

9.4.4 External PHY Loopback........................................................................................................257

9.4.4.1 Setting External PHY Loopback Mode ..............................................................................258

10.0 802.1q VLAN Support............................................................................................................ 259

10.1 802.1q VLAN Packet Format...................................................................................................... 259

10.1.1 802.1q Tagged Frames .......................................................................................................259

10.2 Transmitting and Receiving 802.1q Packets................................................................................. 260

10.2.1 Adding 802.1q Tags on Transmits.........................................................................................260

10.2.2 Stripping 802.1q Tags on Receives .......................................................................................261

10.3 802.1q VLAN Packet Filtering .................................................................................................... 261

10.4 Double VLAN Support............................................................................................................... 262

11.0 PHY Functionality and Features ............................................................................................ 263

11.1 Auto MDIO Register Initialization ............................................................................................... 263

11.1.1 General Register Initialization ..............................................................................................263

11.1.2 Visible Mirror Bit Initialization...............................................................................................263

11.2 Determining Link State............................................................................................................. 264

11.2.1 False Link..........................................................................................................................264

11.2.2 Forced Operation................................................................................................................265

11.2.3 Auto Negotiation ................................................................................................................265

11.2.4 Parallel Detection ...............................................................................................................266

11.2.5 Auto Cross-Over ................................................................................................................266

11.2.5.1 Support for Different Board Layouts ...............................................................................266

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11.3 Link Criteria............................................................................................................................ 267

11.3.1 1000BASE-T ..................................................................................................................... 267

11.3.2 100BASE-TX..................................................................................................................... 267

11.3.3 10BASE-T......................................................................................................................... 267

11.4 Link Enhancements.................................................................................................................. 267

11.4.1 SmartSpeed ..................................................................................................................... 267

11.4.1.1 Using SmartSpeed .......................................................................................................268

11.4.2 Flow Control ..................................................................................................................... 268

11.5 Management Data Interface ...................................................................................................... 269

11.6 Low Power Operation ............................................................................................................... 269

11.7 Power Down via the PHY Register .............................................................................................. 269

11.8 1000 Mb/s Operation ............................................................................................................... 269

11.8.1 Transmit Functions ............................................................................................................ 270

11.8.1.1 Scrambler ................................................................................................................... 270

11.8.2 Transmit FIFO................................................................................................................... 271

11.8.2.1 Transmit Phase-Locked Loop PLL.................................................................................... 271

11.8.2.2 Trellis Encoder.............................................................................................................271

11.8.2.3 4DPAM5 Encoder..........................................................................................................271

11.8.2.4 Spectral Shaper ........................................................................................................... 271

11.8.2.5 Low-Pass Filter ............................................................................................................272

11.8.2.6 Line Driver ..................................................................................................................272

11.8.2.7 Transmit/Receive Flow..................................................................................................272

11.8.3 Receive Functions.............................................................................................................. 273

11.8.3.1 Hybrid ........................................................................................................................ 273

11.8.3.2 Automatic Gain Control .................................................................................................273

11.8.3.3 Timing Recovery ..........................................................................................................273

11.8.3.4 Analog-to-Digital Converter ........................................................................................... 273

11.8.3.5 Digital Signal Processor.................................................................................................273

11.8.3.6 Descrambler................................................................................................................ 273

11.8.3.7 Viterbi Decoder/Decision Feedback Equalizer (DFE)...........................................................274

11.8.3.8 4DPAM5 Decoder .........................................................................................................274

11.9 100 Mb/s Operation ................................................................................................................. 274

11.10 10 Mb/s Operation ................................................................................................................... 274

11.10.1 Link Test.......................................................................................................................... 274

11.10.2 10Base-T Link Failure Criteria and Override .......................................................................... 275

11.10.3 Jabber ............................................................................................................................. 275

11.10.4 Polarity Correction............................................................................................................. 275

11.10.5 Dribble Bits ...................................................................................................................... 275

12.0 Configurable LED Outputs..................................................................................................... 277

13.0 Dual Port Characteristics ...................................................................................................... 279

13.1 Features of Each MAC .............................................................................................................. 279

13.1.1 PCIe* Interface................................................................................................................. 279

13.1.2 MAC Configuration Register Space ....................................................................................... 281

13.1.3 SDP, LED, INT# Output...................................................................................................... 281

13.2 Shared EEPROM ...................................................................................................................... 281

13.3 Shared FLASH ......................................................................................................................... 281

13.3.1 FLASH Access Contention ................................................................................................... 281

13.4 Link Mode/Configuration........................................................................................................... 282

13.5 LAN Disable ............................................................................................................................ 282

13.5.1 Overview ......................................................................................................................... 282

13.5.2 Multi-Function Advertisement.............................................................................................. 283

13.5.3 Legacy Interrupt Use ......................................................................................................... 283

13.5.4 Power Reporting................................................................................................................ 283

13.6 Device Disable ........................................................................................................................ 283

13.6.1 BIOS Handling of Device Disable ......................................................................................... 284

13.7 Copper/Fiber Switch................................................................................................................. 284

14.0 Register Descriptions............................................................................................................ 287

14.1 Register Conventions ............................................................................................................... 287

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Content — Intel® 82575EB Gigabit Ethernet Controller

14.1.1 Memory and I/O Address Decoding .......................................................................................289

14.1.1.1 Memory-Mapped Access to Internal Registers and Memories ..............................................289

14.1.1.2 Memory-Mapped Access to FLASH ..................................................................................289

14.1.1.3 Memory-Mapped Access to MSI-X Tables......................................................................... 289

14.1.1.4 Memory-Mapped Access to Expansion ROM...................................................................... 290

14.1.2 I/O-Mapped Internal Register, Internal Memory, and Flash ......................................................290

14.1.2.1 IOADDR...................................................................................................................... 290

14.1.2.2 IODATA ......................................................................................................................291

14.1.2.3 Undefined I/O Offsets ................................................................................................... 292

14.2 Register Summary................................................................................................................... 292

14.3 Main Register Descriptions ........................................................................................................ 298

14.3.1 Device Control Register - CTRL (00000h; R/W).......................................................................299

14.3.2 Device Status Register - STATUS (00008h; R)........................................................................302

14.3.3 EEPROM/Flash Control Register - EEC (00010h; R/W)..............................................................303

14.3.4 EEPROM Read Register - EERD (00014h; RW) ........................................................................305

14.3.5 Extended Device Control Register - CTRL_EXT (00018h, R/W)..................................................306

14.3.6 Flash Access - FLA (0001Ch; R/W)........................................................................................309

14.3.7 MDI Control Register - MDIC (00020h; R/W)..........................................................................310

14.3.8 PHY Registers ....................................................................................................................311

14.3.8.1 PHY Control Register - PCTRL (00d; R/W)........................................................................ 312

14.3.8.2 PHY Status Register - PSTATUS (01d; R).........................................................................313

14.3.8.3 PHY Identifier Register 1 (LSB) - PHY ID 1 (02d; R) .......................................................... 314

14.3.8.4 PHY Identifier Register 2 (MSB) - PHY ID 2 (03d; R) .........................................................314

14.3.8.5 Auto-Negotiation Advertisement Register - ANA (04d; R/W) ..............................................314

14.3.8.6 Auto-Negotiation Base Page Ability Register - (05d; R)...................................................... 315

14.3.8.7 Auto-Negotiation Expansion Register - ANE (06d; R)......................................................... 316

14.3.8.8 Auto-Negotiation Next Page Transmit Register - NPT (07d; R/W)........................................316

14.3.8.9 Auto-Negotiation Next Page Ability Register - LPN (08d; R)................................................317

14.3.8.10 1000BASE-T/100BASE-T2 Control Register - GCON (09d; R/W) .......................................... 317

14.3.8.11 1000BASE-T/100BASE-T2 Status Register - GSTATUS (10d; R) ..........................................318

14.3.8.12 Extended Status Register - ESTATUS (15d; R) .................................................................319

14.3.8.13 Port Configuration Register - PCONF (16d; R/W) ..............................................................319

14.3.8.14 Port Status 1 Register - PSTAT (17d; RO) ........................................................................320

14.3.8.15 Port Control Register - PCONT (18d; R/W) ....................................................................... 321

14.3.8.16 Link Health Register - LINK (19d; RO) ............................................................................ 322

14.3.8.17 1000Base-T FIFO Register - PFIFO (20d; R/W) ................................................................. 323

14.3.8.18 Channel Quality Register - CHAN (21d; RO) ..................................................................... 324

14.3.8.19 PHY Power Management - (25d; R/W) ............................................................................ 324

14.3.8.20 Special Gigabit Disable Register - (26d; R/W) ..................................................................324

14.3.8.21 Misc Cntrl Register 1 - (27d; R/W) ................................................................................. 325

14.3.8.22 Misc Cntrl Register 2 - (28d; RO) ...................................................................................325

14.3.8.23 Page Select Core Register - (31d; WO) ........................................................................... 326

14.3.9 SERDES ANA - SERDESCTL (00024h; R/W)............................................................................326

14.3.10 Copper/Fiber Switch Control - CONNSW (00034h; R/W) ..........................................................326

14.3.11 VLAN Ether Type - VET (00038h; R/W) .................................................................................327

14.3.12 Fuse Register - UFUSE (5B78h; RO)......................................................................................327

14.3.13 Flow Control Address Low - FCAL (00028h; R/W)....................................................................328

14.3.14 Flow Control Address High - FCAH (0002Ch; R/W) ..................................................................328

14.3.15 Flow Control Type - FCT (00030h; R/W) ................................................................................329

14.3.16 Flow Control Transmit Timer Value - FCTTV (00170h; R/W) .....................................................329

14.3.17 LED Control - LEDCTL (00E00h; RW) ....................................................................................329

14.3.17.1 MODE Encodings for LED Outputs ................................................................................... 330

14.3.18 Packet Buffer Allocation - PBA (01000h; R/W)........................................................................331

14.3.19 Packet Buffer Size - PBS (01008h; R/W)................................................................................332

14.3.20 SFP 12C Command - I2CCMD (01028h; R/W) ........................................................................332

14.3.21 SFP 12C Parameters - I2CPARAMS (0102Ch; R/W) .................................................................333

14.3.22 Flash Opcode - FLASHOP (0103Ch; R/W)...............................................................................334

14.3.23 EEPROM Diagnostic - EEDIAG (01038h; RO) ..........................................................................334

14.3.24 Manageability EEPROM Control Register - EEMNGCTL (01010h; RO) ..........................................335

14.3.25 Manageability EEPROM Read/Write Data - EEMNGDATA (1014h; RO).........................................336

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14.3.26 Manageability Flash Control Register - FLMNGCTL (1018h; R/W).............................................. 336

14.3.27 Manageability Flash Read Data - FLMNGDATA (101Ch; R/W) ................................................... 336

14.3.28 Manageability Flash Read Counter - FLMNGCNT (1020h; R/W)................................................. 337

14.3.29 EEPROM Auto Read Bus Control - EEARBC (01024h; R/W) ...................................................... 337

14.3.30 Watchdog Setup - WDSTP (01040h; R/W) ............................................................................ 338

14.3.31 Watchdog SW Device Status - WDSWSTS (01044h; R/W) ....................................................... 338

14.3.32 Free Running Timer - FRTIMER (01048h; RWS) ..................................................................... 339

14.3.33 TCP Timer - TCPTIMER (0104Ch; R/W)................................................................................. 339

14.3.34 Interrupt Cause Read Register - ICR (000C0H; R).................................................................. 340

14.3.35 Interrupt Cause Set Register - ICS (000C8h; WO) ................................................................. 341

14.3.36 Interrupt Mask Set/Read Register - IMS (000D0h; R/W) ......................................................... 342

14.3.37 Interrupt Mask Clear Register - IMC (000D8h; W).................................................................. 343

14.3.38 Interrupt Acknowledge Auto Mask Register - IAM (000E0h; R/W)............................................. 344

14.3.39 Extended Interrupt Cause - EICR (01580h; RC/W1C) ............................................................. 345

14.3.40 Extended Interrupt Cause Set - EICS (01520h; WO) .............................................................. 345

14.3.41 Extended Interrupt Mask Set/Read - EIMS (01524h; RWS) ..................................................... 346

14.3.42 Extended Interrupt Mask Clear - EIMC (01528h; WO)............................................................. 346

14.3.43 Extended Interrupt Auto Clear - EIAC (0152Ch; R/W)............................................................. 347

14.3.44 Extended Interrupt Auto Mask Enable - EIAM (01530h; R/W) .................................................. 347

14.3.45 Interrupt Throttle - EITR (01680h + 4*n [n = 0..9]; R/W) ...................................................... 348

14.3.46 Immediate Interrupt Rx - IMIR (05A80h + 4*n [n = 0..7]; R/W) ............................................. 349

14.3.47 Immediate Interrupt Rx Extended - IMIREXT (05AA0h + 4*n [n = 0..7]; R/W) .......................... 350

14.3.48 Immediate Interrupt Rx VLAN Priority - IMIRVP (05AC0h; R/W)............................................... 350

14.3.49 MSI-X Allocation - MSIXBM (01600h + 4*n [n = 0..9]; R/W)................................................... 351

14.3.50 Receive Control Register - RCTL (00100h; R/W) .................................................................... 351

14.3.51 Split and Replication Receive Control - SRRCTL (0280Ch + 100*n [n=0..3]; R/W) ..................... 354

14.3.52 Packet Split Receive Type - PSRTYPE (05480h + 4*n [n=0..3]; R/W) ....................................... 355

14.3.53 Flow Control Receive Threshold Low - FCRTL (02160h; R/W)................................................... 356

14.3.54 Flow Control Receive Threshold High - FCRTH (02168h; R/W) ................................................. 357

14.3.55 Flow Control Refresh Threshold Value - FCRTV (02460h; R/W) ................................................ 357

14.3.55.1 Receive Descriptor Base Address Low - RDBAL (02800h + 100*n [n=0..3]; R/W) .................358

14.3.56 Receive Descriptor Base Address High - RDBAH (02804h + 100*n [n=0..3]; R/W) ..................... 358

14.3.57 Receive Descriptor Length - RDLEN (02808h + 100*n [n=0..3]; R/W)...................................... 358

14.3.58 Receive Descriptor Head - RDH (02810h + 100*n [n=0..3]; R/W) ........................................... 359

14.3.59 Receive Descriptor Tail - RDT (02818h + 100*n [n=0..3]; R/W) .............................................. 359

14.3.60 Receive Descriptor Control - RXDCTL (02828h + 100*n [n=0..3]; R/W).................................... 360

14.3.61 Receive Checksum Control - RXCSUM (05000h; R/W) ............................................................ 361

14.3.62 Receive Long Packet Maximum Length - RLPML (05004; R/W)................................................. 362

14.3.63 Receive Filter Control Register - RFCTL (05008h; R/W)........................................................... 362

14.3.64 Transmit Control Register - TCTL (00400h; R/W)................................................................... 363

14.3.65 Transmit Control Extended - TCTL_EXT (00404;R/W) ............................................................. 364

14.3.66 Transmit IPG Register - TIPG (00410;R/W)........................................................................... 365

14.3.67 DMA Tx Control - DTXCTL (03590h; R/W)............................................................................. 365

14.3.68 Transmit Descriptor Base Address Low - TDBAL (03800h + 100*n [n=0..3]; R/W) ..................... 366

14.3.69 Transmit Descriptor Base Address High - TDBAH (03804h + 100*n [n=0..3]; R/W).................... 366

14.3.70 Transmit Descriptor Length - TDLEN (03808h + 100*n [n=0..3]; R/W) .................................... 367

14.3.71 Transmit Descriptor Head - TDH (03810h + 100*n [n=0..3]; R/W) .......................................... 367

14.3.72 Transmit Descriptor Tail - TDT (03818h + 100*n [n=0..3]; R/W)............................................. 367

14.3.73 Transmit Descriptor Control - TXDCTL (03828h + 100*n [n=0..3]; R/W) .................................. 368

14.3.74 Tx Descriptor Completion Write-Back Address Low - TDWBAL (03838h + 100*n [n=0..3]; R/W) .. 369

14.3.75 Tx Descriptor Completion Write-Back Address High - TDWBAH (0383Ch + 100*n [n=0..3]; R/W) 370

14.3.76 PCS Configuration 0 - PCS_CFG (04200h; R/W)..................................................................... 370

14.3.77 PCS Link Control - PCS_LCTL (04208h; R/W) ........................................................................ 371

14.3.78 PCS Link Status - PCS_LSTS (0420Ch; R/W)......................................................................... 372

14.3.79 AN Advertisement - PCS_ANADV (04218h; R/W) ................................................................... 373

14.3.80 Link Partner Ability - PCS_LPAB (0421Ch; RO) ...................................................................... 374

14.3.81 Next Page Transmit - PCS_NPTX (04220h; RO) ..................................................................... 375

14.3.82 Link Partner Ability Next Page - PCS_LPABNP (04224h; RO).................................................... 376

14.4 DCA Registers ......................................................................................................................... 376

14.4.1 Rx DCA Control Registers - RXCTL (02814h 100h *n [n=0..3]; R/W)........................................ 376

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Content — Intel® 82575EB Gigabit Ethernet Controller

14.4.2 Tx DCA Control Registers - TXCTL (03814h + 100h *n [n=0..3]; R/W) ......................................378

14.5 Filter Registers........................................................................................................................ 378

14.5.1 Multicast Table Array - MTA (05200h + 4*n [n..127]; R/W) .....................................................379

14.5.2 Receive Address Low - RAL (05400h + 8*n [n=0..15]; R/W)....................................................380

14.5.3 Receive Address High - RAH (05404h + 8*n [n=0..15]; R/W) ..................................................380

14.5.4 VLAN Filter Table Array - VFTA (05600h + 4*n [n=0..127]; R/W) .............................................381

14.5.5 Multiple Receive Queues Command Register - MRQC (05818h; R/W).........................................382

14.5.6 Redirection Table - RETA (05C00h + 4*n [n=0..31]; R/W).......................................................383

14.5.7 RSS Random Key Register - RSSRK (05C80h + 4*n [n=0..9]; R/W)..........................................384

14.5.8 VMDq Control - VMD_CTRL (0581Ch; R/W)............................................................................384

14.5.9 VLAN Filter Queue Array 0 - VFQA0 (0B100h + 4*n [n=0…127]; R/W) ......................................385

14.5.10 VLAN Filter Queue Array 1 - VFQA1 (0B200h + 4*n [n=0…127]; R/W) ......................................385

14.6 Wakeup Registers.................................................................................................................... 385

14.6.1 Wakeup Control Register - WUC (05800h; R/W) .....................................................................385

14.6.2 Wakeup Filter Control Register - WUFC (05808h; R/W)............................................................386

14.6.3 Wakeup Status Register - WUS (05810h; R/W1C)...................................................................387

14.6.4 IP Address Valid - IPAV (5838h; R/W)...................................................................................387

14.6.5 IPv4 Address Table - IP4AT (05840h + 8*n [n=0..3]; R/W) .....................................................388

14.6.6 IPv6 Address Table - IP6AT (05880h + 4*n[n=0..3]; R/W) ......................................................388

14.6.7 Wakeup Packet Length - WUPL (05900h; RC).........................................................................389

14.6.8 Wakeup Packet Memory (128 Bytes) - WUPM (05A00h + 4*n [n=0..31]; RC).............................389

14.6.9 Flexible Filter Mask Table - FFMT (09000h + 8*n [n=0..127]; R/W) ..........................................389

14.6.10 Flexible Filter Value Table - FFVT (09800h + 8*n [n=0..127]; R/W) ..........................................390

14.6.11 Flexible Filter Length Table - FFLT (05F00h + 8*n [n=0..3]; R/W) ............................................390

14.7 Manageability Registers............................................................................................................ 391

14.7.1 Management VLAN TAG Value - MAVTV (5010h +4*n [n=0..7]; R/W) .......................................391

14.7.2 Management Flex UDP/TCP Ports - MFUTP (5030h + 4*n [n=0..7]; R/W)...................................392

14.7.3 Management Control Register - MANC (05820h; R/W).............................................................392

14.7.4 Manageability Filters Valid - MFVAL (5824h; R/W)...................................................................393

14.7.5 Management Control to Host Register - MANC2H (5860h; R/W)................................................394

14.7.6 Manageability Decision Filters- MDEF (5890h + 4*n [n=0..7]; R/W)..........................................394

14.7.7 Manageability IP Address Filter - MIPAF (0x58B0-0x58EC; RW) ................................................395

14.7.8 Manageability MAC Address Low - MMAL (5910h + 8*n[n=0..3]; RW) .......................................398

14.7.9 Manageability MAC Address High - MMAH (0x5914 + 8*n[n=0..3]; RW) ....................................398

14.7.10 Flexible TCO Filter Table Registers - FTFT (09400h-097FCh; RW)..............................................398

14.7.11 Legacy Sensor Polling Mask 1...8 Register (F8h:FFh)...............................................................400

14.8 PCIe* Registers....................................................................................................................... 400

14.8.1 PCIe* Control - GCR (05B00h; R).........................................................................................400

14.8.2 Function Tag - FUNCTAG (05B08h; R/W) ...............................................................................403

14.8.3 PCIe* Statistics Control #1 - GSCL_1 (05B10h; R) .................................................................403

14.8.4 PCIe* Statistics Control #2 - GSCL_2 (05B14h; R) .................................................................403

14.8.5 PCIe* Statistics Control #3 - GSCL_3 (05B18h; R/W) .............................................................407

14.8.6 PCIe* Statistics Control #4 - GSCL_4 (05B1Ch; R/W) .............................................................407

14.8.7 PCIe* Counter #0 - GSCN_0 (05B20h; R/W) .........................................................................407

14.8.8 PCIe* Counter #1 - GSCN_1 (05B24h; R/W) .........................................................................407

14.8.9 PCIe* Counter #2 - GSCN_2 (05B28h; R/W) .........................................................................408

14.8.10 PCIe* Counter #3 - GSCN_3 (05B2Ch; R/W) .........................................................................408

14.8.11 Function Active and Power State to MNG - FACTPS (05B30h; R) ...............................................408

14.8.12 SerDes/CCM/PCIe* CSR - GIOANACTL0 (05B34h; R/W) ..........................................................409

14.8.13 SerDes/CCM/PCIe* CSR - GIOANACTL1 (05B38h; R/W) ..........................................................409

14.8.14 GIOANACTL2 (05B3Ch; R/W)............................................................................................... 409

14.8.15 GIOANACTL3 (05B40h; R/W) ...............................................................................................410

14.8.16 SerDes/CCM/PCIe* CSR - GIOANACTLALL (05B44h; R/W) .......................................................410

14.8.17 SerDes/CCM/PCIe* CSR - CCMCTL (05B48h; R/W) .................................................................410

14.8.18 SerDes/CCM/PCIe* CSR - SCCTL (05B4Ch; R/W)....................................................................410

14.8.19 Software Semaphore - SWSM (05B50h; R/W) ........................................................................411

14.8.20 Firmware Semaphore - FWSM (05B58h; R/WS) ......................................................................411

14.8.21 Software-Firmware Synchronization - SW_FW_SYNC (05B5Ch; R/WS) ......................................413

14.8.21.1 Using the Software-Firmware Synchronization Register .....................................................413

14.8.22 Mirrored Revision ID - MREVID (05B64h; R/W).......................................................................415

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14.8.23 MSI-X PBA Clear - PBACL (05B68h; R/W1C).......................................................................... 415

14.8.24 DCA Requester ID Information - DCA_ID (05B70h; R/W)........................................................ 415

14.8.25 DCA Control - DCA_CTRL (05B74h; R/W) ............................................................................. 416

14.9 Statistics Registers .................................................................................................................. 416

14.9.1 CRC Error Count - CRCERRS (04000h; RC) ........................................................................... 416

14.9.2 Alignment Error Count - ALGNERRC (04004h; RC) ................................................................. 417

14.9.3 Symbol Error Count - SYMERRS (04008h; RC)....................................................................... 417

14.9.4 RX Error Count - RXERRC (0400Ch; RC) ............................................................................... 417

14.9.5 Missed Packets Count - MPC (04010h; RC) ........................................................................... 417

14.9.6 Single Collision Count - SCC (04014h; RC) ........................................................................... 418

14.9.7 Excessive Collisions Count - ECOL (04018h; RC).................................................................... 418

14.9.8 Multiple Collision Count - MCC (0401Ch; RC)......................................................................... 418

14.9.9 Late Collisions Count - LATECOL (04020h; RC)...................................................................... 418

14.9.10 Collision Count - COLC (04028h; RC) ................................................................................... 418

14.9.11 Defer Count - DC (04030h; RC)........................................................................................... 419

14.9.12 Transmit with No CRS - TNCRS (04034h; RC) ....................................................................... 419

14.9.13 Receive Length Error Count - RLEC (04040h; RC) .................................................................. 419

14.9.14 XON Received Count - XONRXC (04048h; RC)....................................................................... 419

14.9.15 XON Transmitted Count - XONTXC (0404Ch; RC)................................................................... 420

14.9.16 XOFF Received Count - XOFFRXC (04050h; RC)..................................................................... 420

14.9.17 XOFF Transmitted Count - XOFFTXC (04054h; RC)................................................................. 420

14.9.18 FC Received Unsupported Count - FCRUC (04058h; RC) ......................................................... 420

14.9.19 Packets Received (64 Bytes) Count - PRC64 (0405Ch; RC)...................................................... 421

14.9.20 Packets Received (65-127 Bytes) Count - PRC127 (04060h; RC) ............................................. 421

14.9.21 Packets Received (128-255 Bytes) Count - PRC255 (04064h; RC)............................................ 421

14.9.22 Packets Received (256-511 Bytes) Count - PRC511 (04068h; RC)............................................ 421

14.9.23 Packets Received (512-1023 Bytes) Count - PRC1023 (0406Ch; RC) ........................................ 422

14.9.24 Packets Received (1024 to Max Bytes) Count - PRC1522 (04070h; RC) .................................... 422

14.9.25 Good Packets Received Count - GPRC (04074h; RC)............................................................... 422

14.9.26 Broadcast Packets Received Count - BPRC (04078h; RC) ........................................................ 423

14.9.27 Multicast Packets Received Count - MPRC (0407Ch; RC) ......................................................... 423

14.9.28 Good Packets Transmitted Count - GPTC (04080h; RC) .......................................................... 423

14.9.29 Good Octets Received Count - GORCL (04088h; RC)/GORCH (0408Ch; RC)............................... 424

14.9.30 Good Octets Transmitted Count - GOTCL (04090h; RC)/ GOTCH (04094; RC)............................ 424

14.9.31 Receive No Buffers Count - RNBC (040A0h; RC) .................................................................... 424

14.9.32 Receive Undersize Count - RUC (040A4h; RC) ....................................................................... 425

14.9.33 Receive Fragment Count - RFC (040A8h; RC)........................................................................ 425

14.9.34 Receive Oversize Count - ROC (040ACh; RC) ........................................................................ 425

14.9.35 Receive Jabber Count - RJC (040B0h; R) .............................................................................. 425

14.9.36 Management Packets Received Count - MNGPRC (040B4h; RC) ............................................... 426

14.9.37 Management Packets Dropped Count - MPDC (040B8h; RC) .................................................... 426

14.9.38 Management Packets Transmitted Count - MNGPTC (040BCh; RC) ........................................... 426

14.9.39 Total Octets Received - TORL (040C0h; RC) / TORH (040C4h; RC)........................................... 427

14.9.40 Total Octets Transmitted - TOTL (040C8h; RC / TOTH (040CCh; RC)........................................ 427

14.9.41 Total Packets Received - TPR (040D0h; RC) .......................................................................... 427

14.9.42 Total Packets Transmitted - TPT (040D4h; RC)...................................................................... 428

14.9.43 Packets Transmitted (64 Bytes) Count - PTC64 (040D8h; RC) ................................................. 428

14.9.44 Packets Transmitted (65-127 Bytes) Count - PTC127 (040DCh; RC)......................................... 428

14.9.45 Packets Transmitted (128-255 Bytes) Count - PTC255 (040E0h; RC)........................................ 429

14.9.46 Packets Transmitted (256-511 Bytes) Count - PTC511 (040E4h; RC)........................................ 429

14.9.47 Packets Transmitted (512-1023 Bytes) Count - PTC1023 (040E8h; RC) .................................... 429

14.9.48 Packets Transmitted (1024 Bytes or Greater) Count - PTC1522 (040ECh; RC) ........................... 429

14.9.49 Multicast Packets Transmitted Count - MPTC (040F0h; RC) ..................................................... 430

14.9.50 Broadcast Packets Transmitted Count - BPTC (040F4h; RC) .................................................... 430

14.9.51 TCP Segmentation Context Transmitted Count - TSCTC (040F8h; RC) ...................................... 430

14.9.52 Interrupt Assertion Count - IAC (04100h; RC)....................................................................... 431

14.9.53 Rx Packets to Host Count - RPTHC (04104h; RC)................................................................... 431

14.9.54 Transmit Queue Empty Count - TXQEC (04118h; RC)............................................................. 431

14.9.55 Receive Descriptor Minimum Threshold Count - RXDMTC (04120h; RC) .................................... 431

14.9.56 Interrupt Cause Receiver Overrun Count - ICRXOC (04124h; RC) ............................................ 431

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Content — Intel® 82575EB Gigabit Ethernet Controller

14.9.57 SerDes/SGMII Code Violation Packet Count - SCVPC (04228h; R/WS) .......................................432

14.10 Diagnostics Registers ............................................................................................................... 432

14.10.1 Receive Data FIFO Head Register - RDFH (02410h; RO) ..........................................................432

14.10.2 Receive Data FIFO Tail Register - RDFT (02418h; RO) .............................................................432

14.10.3 Receive Data FIFO Head Saved Register - RDFHS (02420h; RO) ...............................................433

14.10.4 Receive Data FIFO Tail Saved Register - RDFTS (02428h; RO)..................................................433

14.10.5 Receive Data FIFO Packet Count - RDFPCQ (02430h + 4 *n [n=0..3]; RO).................................433

14.10.6 PB Descriptor Read Pointers - PBDESCRP (02454h; RO) ..........................................................434

14.10.7 Packet Buffer Diagnostic - PBDIAG (02458h; R/W)..................................................................434

14.10.8 Transmit Data FIFO Head Register - TDFH (03410h; RO) .........................................................434

14.10.9 Transmit Data FIFO Tail Register - TDFT (03418h; R/WS)........................................................435

14.10.10 Transmit Data FIFO Head Saved Register - TDFHS (03420h; R/WS) ..........................................435

14.10.11 Transmit Data FIFO Tail Saved Register - TDFTS (03428h; R/WS).............................................435

14.10.12 Transmit Data FIFO Packet Count - TDFPC (03430h; RO).........................................................436

14.10.13 Packet Buffer ECC Error Inject - PBEEI (03438h; RO) ..............................................................436

14.10.14 Tx Descriptor Handler ECC Error Inject - TDHEEI (035F8h; R/W) ..............................................437

14.10.15 Rx Descriptor Handler ECC Error Inject - RDHEEI (025F8h; R/W)..............................................437

14.10.16 Packet Buffer Memory - PBM (10000h - 10FFCh; R/W) ............................................................438

14.10.17 Packet Buffer Memory Page NPBMPN Register Bit Description ...................................................438

14.10.18 Rx Descriptor Handler Memory Page Number - RDHMP (025FCh; R/W) ......................................438

14.10.19 Tx Descriptor Handler Memory Page Number - TDHMP (035FCh; R/W) ......................................439

14.10.20 Packet Buffer ECC Status - PBECCSTS (0245Ch; R/W).............................................................440

14.10.21 Rx Descriptor Handler ECC Status - RDHESTS (02468h; R/W) ..................................................440

14.10.22 Tx Descriptor Handler ECC Status - TDHESTS (0246Ch; R/W) ..................................................441

14.11 Packet Generator Registers ....................................................................................................... 441

14.11.1 Packet Generator Destination Address Low - PGDAL (04280h; R/W)..........................................441

14.11.2 Packet Generator Destination Address High - PGDAH (04284h; R/W) ........................................441

14.11.3 Packet Generator Source Address Low - PGSAL (04288h; R/W) ................................................442

14.11.4 Packet Generator Source Address High - PGSAH (0428Ch; R/W)...............................................442

14.11.5 Packet Generator Inter Packet Gap - PGIPG (04290h; R/W) .....................................................442

14.11.6 Packet Generator Packet Length - PGPL (04294h; R/W)...........................................................443

14.11.7 Packet Generator Number of Packets - PGNP (04298h; R/W)....................................................443

14.11.8 Packet Generator StaPGSTS Bit Description ...........................................................................444

14.11.9 Packet Generator ContPGCTL Bit Description..........................................................................444

14.12 MSI-X Registers ...................................................................................................................... 445

14.12.1 MSI-X Table Entry Lower Address - MSIXTADD (00000h - 00090h; R/W) ...................................446

14.12.2 MSI-X Table Entry Upper Address - MSIXTUADD (BAR3: 0004h + n*10h [n=0..9]; RW) ..............446

14.12.3 MSI-X Table Entry Message - MSIXTMSG (BAR3: 0008h + n*10h [n=0..9]; RW) ........................446

14.12.4 MSI-X Table Entry Vector Control - MSIXVCTRL (BAR3: 000Ch + n*10h [n=0..9]; RW) ...............446

14.12.5 MSI-X Pending Bit Array - MSIXPBA Bit Description.................................................................447

15.0 Diagnostics and Testability................................................................................................... 449

15.1 Diagnostics............................................................................................................................. 449

15.1.1 FIFO Pointer Accessibility ....................................................................................................449

15.1.2 FIFO Data Accessibility........................................................................................................449

15.1.3 Loopback Operations ..........................................................................................................449

15.2 Testability .............................................................................................................................. 450

15.2.1 EXTEST Instruction.............................................................................................................450

15.2.2 SAMPLE/PRELOAD Instruction ..............................................................................................450

15.2.3 IDCODE Instruction ............................................................................................................450

15.2.4 BYPASS Instruction ............................................................................................................451

16.0 Statistics .............................................................................................................................. 453

16.1 IEEE 802.3 Clause 30 Management ............................................................................................ 453

16.2 OID_GEN_STATISTICS ............................................................................................................. 454

16.3 RMON .................................................................................................................................... 455

16.4 Linux net_device_stats............................................................................................................. 455

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Intel® 82575EB Gigabit Ethernet Controller — Content

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Intel® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 18 January 2011

Introduction — Intel® 82575EB Gigabit Ethernet Controller

1.0 Introduction

This document describes the external architecture (including device operation, register definitions, etc.) for the 82575, a Gigabit Ethernet (GbE) network interface controller.

For introduction to the 82575EB and for an overview, see the Intel® 82575EB GbE Controller Datasheet.

1.1 Register and Bit References

This document refers to device register names with all capital letters. To refer to a specific bit in a

in the Device Control Register (CTRL).

1.2 Byte and Bit Designations

This document uses “B” to abbreviate quantities of bytes. For example, a 4 KB represents 4096 bytes. Similarly, “b” is used to represent quantities of bits. For example, 100 Mb/s represents 100 Megabits per second.

1.3 References

Intel references include the following manuals:

• Intel® 82575EB Gigabit Ethernet Controller Datasheet

• Intel® 82575EB Gigabit Ethernet Controller Design Guide

• Intel® 82575EB Gigabit Ethernet Controller Manageability

• Intel® 82575EB Gigabit Ethernet Controller Software Developer's Manual and EEPROM Guide

• Intel® 82575EB Gigabit Ethernet Controller Thermal Design Considerations

• Intel® 82575EB Gigabit Ethernet Controller Specification Update

Industry references include:

• IEEE standard 802.3, 2002 Edition (Ethernet). Incorporates various IEEE Standards previously published separately. Institute of Electrical and Electronic Engineers (IEEE).

• IEEE standard 1149.1, 2001 Edition (JTAG). Institute of Electrical and Electronics Engineers (IEEE)

• PCI Express* Base Specification, Rev.1.1RD, November 2004

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Intel® 82575EB Gigabit Ethernet Controller — Memory Alignment Terminology

• PCI Express* Card Electromechanical Specification, Rev 1.1RD, November 2004

• PICMG3.1 Ethernet/Fiber Channel Over PICMG 3.0 Draft Specification, September 4, 2002, Version

0.90.

• Advanced Configuration and Power Interface Specification, Rev 2.0b, October 2002

• PCI Bus Power Management Interface Specification, Rev. 1.2, March 2004

• PCI Local Bus Specification Revision 2.3 MSI-X ECN

1.4 Memory Alignment Terminology

Some 82575 data structures have special memory alignment requirements. This implies that the starting physical address of a data structure must be aligned as specified in this manual. The following terms are used for this purpose:

• BYTE alignment: Implies that the physical addresses can be odd or even. Examples: 0FECBD9A1h, 02345ADC6h.

• WORD alignment: Implies that physical addresses must be aligned on even boundaries. For example, the last nibble of the address can only end in 0, 2, 4, 6, 8, Ah, Ch, or Eh (0FECBD9A2h).

• DWORD (Double-Word) alignment: Implies that the physical addresses can only be aligned on 4byte boundaries. For example, the last nibble of the address can only end in 0, 4, 8, or Ch (0FECBD9A8h).

• QWORD (Quad-Word) alignment: Implies that the physical addresses can only be aligned on 8byte boundaries. For example, the last nibble of the address can only end in 0 or 8 (0FECBD9A8h).

• PARAGRAPH alignment: Implies that the physical addresses can only be aligned on 16-byte boundaries. For example, the last nibble must be a 0 (02345ADC0h).

§ §

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Architectural Overview — Intel® 82575EB Gigabit Ethernet Controller

2.0 Architectural Overview

This section provides an overview of the 82575. The following sections give detailed information about the 82575’s functionality, register description, and initialization sequence. All major interfaces of the 82575 is described in detail.

The following principles shaped the design of the 82575:

1. Provide an Ethernet interface containing a 10/100/1000Mb/s PHY that also supports 1000 Base-X implementations.

2. Provide the highest performance solution possible, based on the following:

— Provide direct access to all memory without using mapping registers

— Minimize the PIO accesses required to manage the 82575

— Minimize the interrupts required to manage the 82575

— Off-load the host processor from simple tasks such as TCP checksum calculations

— Maximize PCIe* efficiency and performance

3. Provide a simple software interface for basic operations.

4. Provide a highly configurable design that can be used effectively in different environments.

2.1 External Architecture

Figure 1 shows the external interfaces to the 82575.

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Intel® 82575EB Gigabit Ethernet Controller — Integrated 10/100/1000 Mb/s PHY

Figure 1. 82575 External Interfaces

2.1.1 Integrated 10/100/1000 Mb/s PHY

The 82575 contains integrated 10/100/1000 Mb/s-capable Copper PHY's. Each of these PHY's communicate with its MAC controllers using a standard 10/100/1000Base-T interface internal to the component to transfer transmit and receive data. A standard MDIO interface, accessible to software via MAC control registers, is also used to configure and monitor each PHY operation.

2.1.2 System Interface

The 82575 provides 4 lanes of PCIe* bus interface working at 2.5 GHz each, this should provide sufficient bandwidth to support sustained dual port of 1000 Mb/s transfer rates. 48 KB of on-chip buffering mitigates instantaneous receive bandwidth demands and eliminates transmit under-runs by buffering the entire outgoing packet prior to transmission.

2.1.3 EEPROM Interface

The 82575 provides a four-wire direct interface to a serial EEPROM device such as the 93C46 or compatible for storing product configuration information. Several words of the data stored in the EEPROM are automatically accessed by the 82575, after reset, to provide pre-boot configuration data to the 82575 before it is accessible by the host software. The remainder of the stored information is accessed by various software modules to report product configuration, serial number and other parameters.

Note: An EEPROM is required for normal operation.

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Flash Memory Interface — Intel® 82575EB Gigabit Ethernet Controller

2.1.4 Flash Memory Interface

The 82575 provides an external serial interface to a FLASH device. Accesses to the FLASH are controlled by the 82575 and are accessible to software as normal PCIe* reads or writes to the FLASH memory mapping area. The 82575 supports FLASH devices with up to 512 KB of memory

2.1.5 Management Interfaces

The 82575 contains two possible interfaces to an external BMC.

• SMBus

•NC-SI

Since the manageability sideband throughput is lower than the network link throughput, the 82575 allocates an 8 KB internal buffer for incoming network packets prior to being send over the sideband

interface. Refer to the 82575 System Management Bus Interface Application Note for detailed

information about the management interface.

2.1.5.1 Software Watchdog

In some situations it might be useful to give an indication to the manageability firmware or to external devices that the 82575 hardware or the driver is not functional. In order to provide this functionality, a watchdog mechanism is used. This mechanism can be enabled by default, according to the EEPROM configuration. Once the host driver is up and it determines hardware is functional, it might reset the watchdog timer to indicate the device is functional. The software device driver then should re-arm the timer periodically. If the timer is not re-armed after a pre-programmed timeout, an interrupt is given to firmware and a pre-programmed SDP is raised. The SDP indication is shared between the ports.

The register controlling this feature is WDSETUP. This register enables setting the timeout period and the activation of this mode. Both get their default from the EEPROM.

The re-arming of the timer is done by setting the WDSWSTS.Dev_functional.

If software needs to trigger the watchdog immediately because it suspects hardware is stuck, it can set the WDSWSTS.Force_WD bit. It can also give firmware an indication if the watchdog reason using the WDSWSTS.stuck_reason field.

The SDP that provides the watchdog indication is set using the CTRL.SDP0_WDE. In this mode the CTRL.SDP0_IODIR should be set to output. The CTRL.SDP0_DATA bit indicates the polarity of the indication. Setting this bit in one of the cores causes the watchdog indications of both cores to be indicated on this SDP.

2.1.6 General-Purpose I/O (Software-Definable Pins)

The 82575 has four software-defined pins (SDP pins) per port that can be used for miscellaneous hardware or software-controllable purposes. These pins and their function are bound to a specific LAN device (for example, eight SDP pins might not be associated with a single LAN device). These pins can each be individually configurable to act as either input or output pins. The default direction of each of

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Intel® 82575EB Gigabit Ethernet Controller — LEDs

the four pins is configurable via EEPROM as well as the default value of any pins configured as outputs. To avoid signal contention, all four pins are set as input pins until after the EEPROM configuration is loaded.

The use, direction, and values of SDP pins are controlled and accessed using fields in the Device Control register (CTRL) and Extended Device Control register (CTRL_EXT).

2.1.7 LEDs

The 82575 provides four LEDs per port that can be used to indicate different traffic status. The default setup of the LEDs is done via the EEPROM words 1Ch and 1Fh. The default setup for both ports is the same. This setup is reflected in the LEDCTL register of each port. Each software device driver can change its setup individually. For each of the LEDs the following parameters can be defined:

• Mode: Defines which information is reflected by this LED. The encoding is described in the LEDCTL register.

• Polarity: Defines the polarity of the LED.

• Blink mode: should the LED blink or be stable.

In addition, the blink rate of all LEDs can be defined. The possible rates are 200 ms or 83 ms for each phase. There is one rate for all LEDs.

2.1.8 Network Interfaces

The 82575 MAC provides a complete CSMA/CD function that supports IEEE 802.3 (10 Mb/s), 802.3u (100 Mb/s), 802.3z and 802.3ab (1000 Mb/s) implementations. The 82575 performs all of the functions required for transmission, reception, and collision handling called out in the standards.

Each 82575 MAC can be configured to be used as a different media interface. While the most likely application is expected to be based on use of the internal copper PHY, the 82575 supports the following potential configurations:

• Internal copper PHY

• External SerDes device such as an optical SerDes (SFP or onboard) or backplane connections.

• External SGMII device. This mode is used for SFP connections or external SGMII PHYs.

Selection between the various configurations is programmable via each MAC's Extended Device Control register (CTRL_EXT.LINK_MODE bits) and defaulted via EEPROM settings.

2.2 DMA Addressing

In appropriate systems, all addresses mastered by the 82575 are 64 bits in order to support systems that have larger than 32-bit physical addressing. Providing 64-bit addresses eliminates the need for special segment registers.

Note: Descriptor accesses are not byte swapped.

The following example illustrates data-byte ordering. Bytes for a receive packet arrive in the order shown from left to right.

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Ethernet Addressing — Intel® 82575EB Gigabit Ethernet Controller

01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e

Example 1. Byte Ordering

There are no alignment restrictions on packet-buffer addresses. The byte address for the major words is shown on the left. The byte numbers and bit numbers for the PCIe* bus are shown across the top.

Table 1. Little Endian Data Ordering

Byte

Address

00807060504030201

8100f 0e0d0c0b0a09

10 18 17 16 15 14 13 12 11

18 20 1f 1e 1d 1c 1b 1a 19

63 0

76543210

2.3 Ethernet Addressing

Several registers store Ethernet addresses in the 82575. Two 32-bit registers make up the address: one is called “high”, and the other is called “low”. For example, the Receive Address Register is comprised of Receive Address High (RAH) and Receive Address Low (RAL). The least significant bit of the least significant byte of the address stored in the register (for example, bit 0 of RAL) is the multicast bit. The LS byte is the first byte to appear on the wire. This notation applies to all address registers, including the flow control registers.

Figure 2 shows the bit/byte addressing order comparison between what is on the wire and the values in

the unique receive address registers.

Preamble & SFD Destination Address Source Address

...55 D5 00 11 22 33 ...XXX00 AA

Bit 0 of this byte is first on the wire

dest_addr[0]

2233 00AA0011

Destination address stored internally as shown here

...

001122

00AA

Multicast bit

Figure 2. Example of Address Byte Ordering

The address byte order numbering shown in Figure 2 maps to Table 2. Byte #1 is first on the wire.

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Intel® 82575EB Gigabit Ethernet Controller — Interrupt Control and Tuning

Table 2. Intel® Architecture Byte Ordering

IA Byte # 1 (LSB) 2 3 4 5 6 (MSB)

Byte Value (Hex) 00 AA 00 11 22 33

Note: The notation in this manual follows the convention shown in Table 2. For example, the

address in Table 2 indicates 00_AA_00_11_22_33h, where the first byte (00h_) is the first byte on the wire, with bit 0 of that byte transmitted first.

2.4 Interrupt Control and Tuning

The 82575 provides a complete set of interrupts that allow for efficient software management. The interrupt structure is designed to accomplish the following:

• Make accesses “thread-safe” by using ‘set’ and ‘clear-on-read’ rather than ‘read-modify-write’ operations.

• Correlate between related bits in different registers (for example, ICR)

• Minimize the number of interrupts needed relative to work accomplished.

• Minimize the processing overhead associated with each interrupt.

The interrupt logic consists of the interrupt registers that are described in sections 14.3.34 through

14.3.37.

Two actions minimize the number of interrupts:

1. Reducing the frequency of all interrupts

2. Accepting multiple receive packets before signaling an interrupt.

One interrupt register consolidates all interrupt information eliminating the need for multiple accesses.

Note: The 82575 supports Message Signaled Interrupts per the PCI 2.2, 2.3, and PCIe*

specifications. See Section 4.7.5.1 for details.

2.5 Hardware Acceleration Capability

The 82575 provides the ability to offload IP, TCP, and UDP checksum for transmit. The functionality provided by these features can significantly reduce processor utilization by shifting the burden of the functions from the driver to the hardware. Features include:

• Jumbo frame support

• Receive and transmit checksum offloading

• TCP segmentation

• Receive fragmented UDP checksum offload

• These features are briefly outlined in the following sections.

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Jumbo Frame Support — Intel® 82575EB Gigabit Ethernet Controller

2.5.1 Jumbo Frame Support

The 82575 supports jumbo frames to increase performance and decrease CPU utilization. By default, the 82575 might receive packets with a maximum size of 1522 bytes. If large frame reception is enabled by the RCTL register, the 82575 supports jumbo packet reception of up to 9018 bytes (including CRC and headers). On the transmit size, jumbo packets are always supported by the 82575. It is the responsibility of the software device driver to initiate jumbo packets only when it is configured to do so.

2.5.2 Receive and Transmit Checksum Offloading

The 82575 provides the ability to offload the IP, TCP, and UDP checksum requirements from the software device driver. For common frame types, the hardware automatically calculates, inserts, and checks the appropriate checksum values normally handled by software.

For transmits where the 82575 is doing non-TCP segmentation, every transmitted Ethernet packet can have two checksums calculated and inserted by the 82575. Typically these would be the IPv4 and either TCP or UDP checksums. The software device driver specifies which portions of the packet are included in the checksum calculations, and where the calculated values are inserted, via descriptor(s).

For receives, the hardware recognizes the packet type and performs the checksum calculations as well as error checking automatically. Checksum and error information is provided to software via the receive descriptor(s). Refer to Section 5.5.1 for details.

2.5.3 TCP Segmentation

The 82575 implements a TCP segmentation capability for transmits that enables the software device driver to offload packet segmentation and encapsulation to the hardware. The software device driver can send the 82575 the entire IP (IPv6 or IPv6), TCP or UDP message sent down by the Network Operating System (NOS) for transmission. The 82575 segments the packet into legal Ethernet frames and transmit them on the wire. By handling the segmentation tasks, the hardware alleviates the software from handling some of the framing responsibilities. This reduces the overhead on the CPU for the transmission process thus reducing overall CPU utilization.

2.5.4 Receive Fragmented UDP Checksum Offloading

The 82575 provides the ability to offload inbound fragmented UDP packet reassembly. The 82575 provides the partial checksum calculation for each incoming UDP fragment so that the software device driver is required to sum the partial checksum words for each fragment to produce the complete checksum. The fragmented UDP checksum offload is provided to IPv4 packets.

2.6 Buffer and Descriptor Structure

Software allocates the transmit and receive buffers, and also forms the descriptors that contain pointers to, and the status of, those buffers. A conceptual ownership boundary exists between the driver software and the hardware of the buffers and descriptors.

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Intel® 82575EB Gigabit Ethernet Controller — Multiple Transmit Queues

The software gives the hardware ownership of a queue of buffers for receives. These receive buffers store data that the software then owns once a valid packet arrives.

For transmits, the software maintains a queue of buffers. The driver software owns a buffer until it is ready to transmit. The software then commits the buffer to the hardware; the hardware then owns the buffer until the data is loaded or transmitted in the transmit FIFO.

Descriptors store the following information about the buffers:

• The physical address

• The length

• Status and command information about the referenced buffer

Descriptors contain an end-of-packet field that indicates the last buffer for a packet. Descriptors also contain packet-specific information indicating the type of packet, and specific operations to perform in the context of transmitting a packet, such as those for VLAN or checksum offload.

2.7 Multiple Transmit Queues

The 82575 supports four transmit descriptor rings (this matches the expected number of processors on most server platforms).

The priority between the queues can be set and specified in the memory space. Multiple transmit queues are intended for the following usage models.

Note: If there are more processors than queues, then one queue can be used to service more

than one processor.

2.8 iSCSI Boot

This feature consists of adding an iSCSI class code to potentially replace the LAN class code of the ports. When the system is booting, the BIOS detects this class code and runs SCSI software.

The 82575 reads two control bits out of EEPROM. Each bit affects its respective LAN class code value. If the bit is 0b (this is the current value of the unused bits) the LAN class code remains as it is (value = 020000 = LAN). If the bit is set to 1b, the LAN class code becomes a SCSI class code (value = 010000 = SCSI). Having this functionality enables programmers to change one port (or two in specific applications) to a SCSI device type and loads an iSCSI miniport driver for that port. This port also functions as iSCSI HBA. Default values for these fields in the EEPROM for both ports remain as a network class type.

In this case, the MAC address and the IP address of the port are used by the iSCSI function.

§ §

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General Initialization and Reset Operation — Intel® 82575EB Gigabit Ethernet Controller

3.0 General Initialization and Reset Operation

This section lists all necessary initializations and describes the reset commands for the 82575.

3.1 Power Up State

When the 82575 powers up, it reads the EEPROM. The EEPROM contains sufficient information to bring the link up and configure the 82575 for manageability and/or APM wakeup. However, software initialization is required for normal operation.

3.2 Initialization Sequence

The following sequence of commands is typically issued to the 82575 by the software device driver in order to initialize the 82575 to normal operation. The major initialization steps are:

• Disable Interrupts - see Interrupts during initialization.

• Issue Global Reset and perform General Configuration - see Global Reset and General Configuration.

• Setup the PHY and the link - see Link Setup Mechanisms and Control/Status Bit Summary.

• Initialize all statistical counters - see Initialization of Statistics.

• Initialize Receive - see Receive Initialization.

• Initialize Transmit - see Transmit Initialization.

• Enable Interrupts - see Interrupts During Initialization.

3.3 Interrupts During Initialization

Most drivers disable interrupts during initialization to prevent re-entrancy. Interrupts are disabled by writing to the IMC and EIMC registers. Note that the interrupts also need to be disabled after issuing a global reset, so a typical driver initialization flow might be:

• Disable interrupts

• Issue a Global Reset

• Disable interrupts (again)

•…

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Intel® 82575EB Gigabit Ethernet Controller — Global Reset and General Configuration

After the initialization completes, a typical driver enables the desired interrupts by writing to the IMS and EIMS registers.

3.4 Global Reset and General Configuration

The 82575 initialization typically starts with a global reset that puts it into a known state and enables the software device driver to continue the initialization sequence.

Several values in the Device Control Register (CTRL) need to be set upon power up or after an 82575 reset for normal operation.

• FD should be set per interface negotiation (if done in software), or is set by the hardware if the interface is Auto-Negotiating. This is reflected in the Device Status Register in the Auto-Negotiating case.

• Speed is determined via Auto-Negotiation or forced by software if the link is forced. Status information for speed is also readable in STATUS.

• In SerDes mode, CTRL.ILOS should be set to according to the polarity of the Sig_DET signal.

Set the packet buffer allocation for transmit receive flows in the PBA register. This should be done before RCTL.RXEN & TCTL.TXEN are set. An ordered disabling of all queues and of the Rx and Tx flows is required before any change in the packet buffer allocation is done.

If flow control is enabled, program the FCRTL, FCRTH, FCTTV and FCRTV registers.

3.5 Receive Initialization

Program the Receive address register(s) per the station address. This can come from the EEPROM or from any other means (for example, on some systems, this comes from the system PROM not the EEPROM on the adapter card)

Set up the MTA (Multicast Table Array) per software by zeroing all entries initially and adding in entries as requested.

Program RCTL with appropriate values. If initializing it at this stage, it is best to leave the receive logic disabled (EN = 0b) until after the receive descriptor ring has been initialized. If VLANs are not used, software should clear VFE. Then there is no need to initialize the VFTA. Select the receive descriptor type.

The following should be done once per receive queue:

• Allocate a region of memory for the receive descriptor list.

• Receive buffers of appropriate size should be allocated and pointers to these buffers should be stored in the descriptor ring.

• Program the descriptor base address with the address of the region.

• Set the length register to the size of the descriptor ring.

• Program PSRCTL of the queue according to the size of the buffers and the required header handling

• If header split or header replication is required for this queue, program the PSRTYPE register according to the required headers.

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