ICST AV9250F-32-T, ICS9250F-32-T Datasheet
ICS9250-32
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
Block Diagram
9250-32 Rev B 9/7/00
Recommended Application:
Timna Style Chipset
Output Features:
• 3 - CPUs @ 2.5V
• 8 - PCI @ 3.3V
• 2 - IOAPIC @ 2.5V
• 1 - MREF @ 2.5V, DRCG memory reference clock
• 9 - SDRAM @ 3.3V including one free running
• 1 - 2V48M @ 2.5V fixed (DOT)
• 1 - 3V48M @ 3.3V fixed (USB)
• 2 - REF @ 3.3V, 14.318MHz.
Features:
• Support power management: CPU, PCI, SDRAM stop
from I
2
C programming.
• Spread spectrum for EMI control (0 to -0.5%)
• Uses external 14.318MHz crystal
Key Specifications:
• CPU Output Jitter
(Cyc-Cyc)
: <175ps
• IOAPIC Output Jitter
(Cyc-Cyc)
: <500ps
• MREF Output Jitter
(Cyc-Cyc)
: <250ps
• 2V48M Output Jitter
(Cyc-Cyc)
: <250ps
• 3V48M Output Jitter
(Cyc-Cyc)
: <500ps
• CPU - CPU: < 175ps
• SDRAM - SDRAM < 250ps
• PCI - PCI: < 500ps
• IOAPIC - IOAPIC: < 250ps
• BUFFER_IN to SDRAM prop delay: 5.5 to 7.5ns
Functionality
Pin Configuration
56-Pin 300mil SSOP
* These inputs have a 50K pull up to VDD.
Frequency Generator & Integrated Buffers for PII/III™
2V48M
3V48M
VDD48
GND48
X1
X2
GND
*(CPU2_EN#)REF0
REF1
VDD
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
VDDPCI
GNDPCI
PCICLK6
PCICLK7
SCLK
VDDA
GNDA
S DATA
BUF_IN
*FS0
VDDLIOAPIC
IOAPIC0
IOAPIC1
GNDLIOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
VDDLCPU
GNDLCPU
CPUCLK2
MREF66
VDD
SDRAM_F
SDRAM0
VDDSDR
GNDSDR
SDRAM1
SDRAM2
SDRAM3
GNDSDR
VDDSDR
SDRAM4
SDRAM5
VDDSDR
GNDSDR
SDRAM6
SDRAM7
FS1*
ICS9250-32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PLL2
PLL1
Spread
Spectrum
3V48M
2V48M
CPUCLK (2:0)
SDRAM (7:0)
IOAPIC (1:0)
PCICLK (7:0)
8
8
3
2
2
SDRAM_F
MREF66
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
REF (1:0)
CPU_EN#
BUF_IN
S DATA
SCLK
FS (1:0)
Control
Logic
Config.
Reg.
1SF0SF
dehctaLpurewoP
#NE_2UPC/1FER
0UPC
,1UPC
FERM
2UPC
11 1 zHM66etatsirT
11 0 zHM66zHM66
10 X 2/KLCT2/KLCT
01 X devreseRdevreseR
00 X etatsirTetatsirT
Power Groups
VDD = REF, X1, X2
VDDPCI = PCICLK
VDDSDR = SDRAM
VDD48 = 3V48M
VDDLCPU = CPU
VDDLIOAPIC = IOAPIC, 2V48M
VDDA = PLL Core
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9250-32
Third party brands and names are the property of their respective owners.
Functionality
The ICS9250-32 is the single chip clock solution for Desktop designs. It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-32 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
General Description
Pin Configuration
PIN NUMBER PIN NAME TYPE DESCRIPTION
1
2V48M OUT 48MHz output clock 2.5V (DOT) clock
2 3V48M OUT 48MHz output clock 3.3V (USB) clock
3, 10, 14, 19, 24,
33, 36, 42, 45
VDD PWR
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference out
p
ut buffers and 3V48 outpu
t
4, 7, 13, 20, 25,
32, 37, 41, 48, 53
GND PWR Ground pins
5 X1 IN Crystal input,nominally 14.318MHz.
6 X2 OUT Crystal output, nominally 14.318MHz.
CPU2_EN# IN
Disables CPU2 when pulled high (default)
Enables CPU2 when
p
ulled Low
REF0 OUT 14.318 MHz reference clock.
9 REF1 OUT 14.318 MHz reference clock.
22, 21, 18, 17, 16,
15, 12, 11
PCICLK (7:0) OUT PCI clock outputs.
23 SCLK IN
Clock
p
in of I2C circuitry 5V tolerant
26 SDATA I/O
Data
p
in for I2C circuitry 5V tolerant
27 BUF_IN IN Input to fan out buffer for SDRAM
28 FS0 IN Frequency select pin.
29 FS1 IN Frequency select pin.
30, 31, 34, 35, 38,
39, 40, 43
SDRAM (7:0) OUT SDRAM clock outputs
44 SDRAM_F OUT
SDRAM clock out
p
ut free running not affected by I2C
46 MREF66 OUT DRCG reference memory 2.5V 66MHz
49, 52, 56 VDDL PWR Power pins for CPUCLKs, and IOAPIC clocks. 2.5V
47, 50, 51 CPUCLK (2:0) OUT 2.5V CPU clock outputs.
54, 55 IOAPIC (1:0) OUT 2.5V IOAPIC clock outputs
8
1SF0SF
dehctaLpurewoP
#NE_2UPC/1FER
0UPC
FERM,1UPC
2UPC
MARDS
]7:0[
:84V2
84V3
ICPFERCIPAOI
11 1 zHM66etatsirTNI_FUBzHM84zHM33zHM813.41zHM33
11 0 zHM66zHM66NI_FUBzHM84zHM33zHM813.41zHM33
10 X 2/KLCT2/KLCTNI_FUB2/KLCT4/KLCTKLCT4/KLCT
01 X devreseRdevreseRdevreseRdevreseRdevreseRdevreseRdevreseR
00 X etatsirTetatsirTetatsirTetatsirTetatsirTetatsirTetatsirT
3
ICS92 50-32
Third party brands and names are the property of their respective owners.
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
AC
K
Byte Count
ACK
Byte
0
ACK
Byte 1
ACK
Byte
2
ACK
Byte
3
ACK
Byte 4
ACK
Byte
5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
AC
K
Dummy Command Code
AC
K
Dummy Byte Count
AC
K
Byte 0
AC
K
Byte 1
ACK
Byte 2
AC
K
Byte 3
AC
K
Byte 4
AC
K
Byte 5
AC
K
Stop Bit
How to Write:
4
ICS9250-32
Third party brands and names are the property of their respective owners.
Byte 0: Active/Inactive Control Register
(1= enable, 0 = disable)
Byte 1: Active/Inactive Control Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB031 7MARDS
6tiB131 6MARDS
5tiB431 5MARDS
4tiB531 4MARDS
3tiB831 3MARDS
2tiB931 2MARDS
1tiB041 1MARDS
0tiB341 0MARDS
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
TIB#NIPDWPNOITPIRCSED
7tiB-0 devreseR
6tiB-><devreseR
5tiB-><devreseR
4tiB-><devreseR
3tiB-0 devreseR
2tiB-0 devreseR
1tiB-0 devreseR
0tiB-0 devreseR
Byte 3: Active/Inactive Control Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-0 devreseR
6tiB-0 devreseR
5tiB-0 devreseR
4tiB-0 devreseR
3tiB-0 devreseR
2tiB-0 devreseR
1tiB-0 devreseR
0tiB-0 devreseR
Byte 4: Active/Inactive Control Register
(1= enable, 0 = disable)
Byte 2: Active/Inactive Control Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB221 7KLCICP
6tiB121 6KLCICP
5tiB811 5KLCICP
4tiB711 4KLCICP
3tiB611 3KLCICP
2tiB511 2KLCICP
1tiB211 1KLCICP
0tiB111 0KLCICP
TIB#NIPDWPNOITPIRCSED
7tiB-0 devreseR
6tiB-0 devreseR
5tiB-0 devreseR
4tiB-0 devreseR
3tiB-0
murtcepSdaerpS
ffO=1/nO=0(
2tiB11 )TOD(M84V2
1tiB21 )BSU(M84V3
0tiB-1 devreseR
Note:
<>, with these 3 bits, the registers will store the written
values. The read back, however, will be the invert of the
written value.
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