ICOM IC-R2 User Guide
SERVICE
MANUAL
COMMUNICATIONS RECEIVER
INTRODUCTION
DANGER
ORDERING PARTS
REPAIR NOTES
This service manual describes the latest service information
for the
IC-R2 at the time of publication.
NEVER connect the receiver to an AC outlet or to a DC
power supply that uses more than 3.5 V. Such a connection
could cause a fire hazard and/or electric.
DO NOT expose the receiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when
connecting the receiver.
DO NOT apply an RF signal of more than 20 dBm (100mW)
to the antenna connector. This could damage the receiver's front end.
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<
SAMPLE ORDER>
8930046581 LCD Contact IC-R2 LOGIC UNIT 5 pieces
8810009560 Screw PH BO M2x6 ZK IC-R2 Chassis 10 pieces
Addresses are provided on the inside back cover for your
convenience.
1. Make sure a problem is internal before disassembling the receiver.
2.
DO NOT open the receiver until the receiver is disconnected from its power source.
3.
DO NOT force any of the variable components. Turn them slowly and smoothly.
4.
DO NOT short any circuits or electronic parts. An insulated turning tool MUST be used for all adjustments.
5.
DO NOT keep power ON for a long time when the receiver is defective.
6.
READ the instructions of test equipment thoroughly before connecting equipment to the receiver.
To upgrade quality, all electrical or mechanical parts and
internal circuits are subject to change without notice or obligation.
MODEL
IC-R2
VERSION
Europe
Italy
Taiwan
U.S.A.
Canada
Other
SYMBOL
EUR
ITA
TPE
USA
CAN
OTH
OTH-1
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASSEMBLY INSTRUCTIONS
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4-2 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4-3 POWER SUPPLY CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4-4 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
SECTION 5 ADJUSTMENT PROCEDURES
5-1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5-2 PLL ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
5-3 RECEIVER ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS AND DISASSEMBLY
SECTION 8 SEMI-CONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
9-1 LOGIC UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
9-2 RF UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
SECTION 10 BLOCK DIAGRAM
SECTION 11 VOLTAGE DIAGRAM
11-1 LOGIC UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
11-2 RF UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2
TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
1 - 1
M GENERAL
• Frequency range :
• Mode : FM, WFM, AM
• No. of memory channel : 450 channel
• Frequency stability : ±6 ppm max.
(–10˚C to +60˚)
• Tuning steps : 5, 6.25, 10, 12.5, 15, 20,
25, 30, 50, and 100 kHz
• Anntena Impedance : 50 Ω
• Power supply requirement : 2
× AA(R6) Ni-Cd or alka-
line cell
• Polarity : Negative ground
• Frequency resolution : 5 kHz, 6.25 kHz
• Current drain (at 3.0 V) :
Rated audio 170 mA typical
Standby 100 mA typical
Power saved 41 mAtypical
• Usable temperature range : –10˚C to +60˚C
( –14˚F to +140˚F)
• Dimensions :
58(W) × 86(H) × 27(D) mm;
(projections not included)
29⁄32 (W) × 33⁄8 (H) × 11⁄16(D) in
• Weight
(with antenna and battely)
: 170 (g); 6 (oz)
• External SP connector : 3-conductor 3.5(d) mm
(
1
⁄8”) / 8Ω
M RECEIVER
• Receiver system : Tripple super heterodyne
• Intermediate frequency : 1st 266.7 MHz
2nd 19.65 MHz
3rd 450 kHz
• Sensitivity* :
(except spurious points)
*
FM and WFM are measured at 12 dB SINAD; AM is measured
at 10 dB S/N.
• Squelch Sensitivity :
• Selectivity :
AM / FM more than 15 kHz / –6 dB
less than 30 kHz / –60 dB
WFM more than 150 kHz / –6 dB
• Audio output power : 100 mW typical at 10 %
distortion with an 8 Ω load
All stated specifications are subject to change without notice or obligation.
Version
EUR, U.K.,
CAN, OTH,
OTH-1
U.S.A.
Receive Frequencies (MHz)
0.495 – 1309.995
0.495 – 823.995
849.000 – 868.995
894.000 – 1309.995
Frequency (MHz)
0.495 – 1.625
1.625 – 5.0
5.0 – 30.0
30.0 – 76.0
76.0 – 108.0
108.0 – 118.0
118.0 – 136.0
136.0 – 175.0
175.0 – 222.0
222.0 – 247.0
247.0 – 330.0
330.0 – 470.0
470.0 – 770.0
770.0 – 833.0
833.0 – 1309.995
FM
—
0.56 µV
0.4 µV
0.56 µV
0.79 µV
WFM
—
1.8 µV
—
1.8 µV
—
2.5 µV
—
AM
2.5 µV
1.8 µV
—
1.8 µV
—
1.8 µV
—
Frequency (MHz)
0.495 – 1.625
1.625 – 5.0
5.0 – 30.0
30.0 – 76.0
76.0 – 108.0
108.0 – 118.0
118.0 – 136.0
136.0 – 175.0
175.0 – 222.0
222.0 – 247.0
247.0 – 330.0
330.0 – 470.0
470.0 – 770.0
770.0 – 833.0
833.0 – 1309.995
FM
—
0.56 µV
0.4 µV
0.56 µV
0.79 µV
WFM
—
5.6 µV
—
5.6 µV
—
5.6 µV
—
AM
2.5 µV
1.8 µV
—
1.8 µV
—
1.8 µV
—
SECTION 2 INSIDE VIEWS
•
LOGIC UNIT
2 - 1
•
RF UNIT
AF power amplifier
(IC15: TA31056F)
AF mute switch
(Q37: 2SJ144)
AF filter
(Q30: XP6501)
+3.2 regurater
(IC4: S-81332H)
2nd mixer
(IC10: µPC2757T)
IF amplifer
(Q5: 2SC5231)
FM IF IC
(IC2: TA31136FN)
PLL circuit
PLL IC
(IC3: µPD3140GS)
PLL reference
oscillator
(X1: CR593 19.200MHz)
VCO circuit
1st mixer
(IC1: µPC2757T)
BOTTOM VIEWTOP VIEW
SECTION 3 DISASSEMBLY INSTRUCTIONS
3 - 1
•
REMOVING THE REAR PANEL
1 Unscrew 2 screws, A
.
2 Remove the rear panel in the direction of the arrow.
•
REMOVING THE RF UNIT
1 Unscrew 1 screw, B
.
2 Remove 1 knob, c.
Unscrew 2 nuts,
D and E.
3 Unsolder 5 points, F, and then remove the RF unit.
•
REMOVING THE LOGIC UNIT
1 Unscrew 2 screws, G
.
2 Unsolder 2 points, H, and then remove the LOGIC unit.
A
Rear panel
B
E
D
C
RF unit
F
H
G
LOGIC unit
SECTION 4 CIRCUIT DESCRIPTION
4 - 1
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT (RF UNIT)
The RF signals from the antenna connector pass through
the limitter (D68) and an attenuator (D69). The signals are
then applied to the RF circuit the antenna switching circuit
(D13, D73, D75) which suppress out-of-band signals.
4-1-2 RF CIRCUIT (RF UNIT)
The RF circuit amplifies the received signals within the
range of frequency coverage and filters out-of-band signals.
(1) 0.495 MHz–29.999 MHz
RF signals (0.495–29.999MHz) from an antenna switching
circuit (D73) pass through a low-pass filter (C511–C515,
L81, L82). The filtered signals are amplified at an RF amplifier (Q505) passing through each band-pass filter depending
on the receiving frequency. The amplified signals are then
applied to the 1st mixer circuit (IC1) after being amplified at
another RF amplifier (IC11) via the band switching
diode(D71).
The signals below 1.9 MHz pass through a low-pass filter
(C534, C535, C657, C658, L88, L89) via the band switching
diode (D66), and are then applied to the RF amplifier circuit
(Q505) via the band switching diode (D67).
The 1.9 MHz–14.995 MHz signals pass through the band
switching diode (D65) and band-pass filter (C522–C531,
L85–L87, L91), and are then applied to the RF amplifier circuit (Q505) via the band switching diode (D70).
The 15 MHz–29.995 MHz signals pass through the band
switching diode (D63) and high-pass filter (C516–C520,
L83, L84) and are then applied to the RF amplifier circuit
(Q505) via the band switching diode (D64).
(2) 118 MHz–174.995 MHz, 330 MHz–832.995 MHz
RF signals (118 MHz–174.995 MHz, 330 MHz–832.995
MHz) from an antenna switching diode (D75) are passed
through each bandpass filter and RF amplifier, and are then
applied to the 1st mixer circuit (IC1) via the band switching
diode (D71) and RF amplifier (IC11).
The 118 MHz–174.995 MHz signals pass through the band
switching diode (D74) and low-pass filter (C8–C13, C67,
C416, L14, L57–L59, L70), and are then amplified at RF
amplifier (Q14). The amplified signal passes through the
tunable band-pass filters (D1, D2) and band switching diode
(D25).
The 330 MHz–469.995 MHz signals are amplified at RF
amplifier (Q35) via the band switching diode (D3) and bandpass filter (C19–C23, C216, L2–L5). The amplified signal
passes through the tunable band-pass filters (D3, D4) and
band switching diode (D29).
The 470 MHz–832.995 MHz signals are amplified at RF
amplifier (Q24) via the band-pass filter (C32, C33,
C35–C37, C39, C144, C145), between the band switching
diode (D11, D32).
(3) 30–117.995 MHz, 175–329.995 MHz
The 30 MHz–117.95 MHz, 175 MHz–329.995 MHz signals
pass through the low-pass filter (C40–C43, C665, C666, L9,
L10, L92), and are then applied to the RF amplifier (Q36).
The amplified signals are amplified at the RF amplifier (IC11)
via band switching diodes (D34, D71). The amplified signals
are applied to the 1st mixer circuit (IC1).
(4) 833 MHz–1309.995 MHz
The 833 MHz–1309.995 MHz signals pass through the
bandpass filter (C5, C45–51, L11–L13, L43), and are then
applied to the RF amplifier (Q26). The amplified signals are
amplified at the RF amplifier (IC11) via band switching
diodes (D36). The amplified signals are applied to 1st mixer
circuit (IC1).
4-1-3 1ST MIXER CIRCUIT (RF UNIT)
The 1st mixer circuit converts the received RF signals to a
fixed frequency of the 1st IF signal with a PLL output frequency. By changing the PLL frequency, only the desired
frequency will pass through the bandpass filters at the next
stage of the 1st mixer.
The filtered RF signals are mixed with 1st LO signals at the
1st mixer circuit (IC1) to produce a 266.7 MHz 1st IF signal.
The 1st IF signal is output from pin 6, and passed through
the bandpass filter (FI1) to suppress unwanted harmonic
components. The filtered 1st IF signal is applied to the 2nd
mixer circuit.
The 1st LO signals are generated at the 1st VCO (Q28, Q30,
D45) and are applied to the 1st mixer (IC1, pin 3) directly or
passing through the doubler circuit (Q31) after being amplified at the buffer amplifiers (IC4, Q40).
4-1-4 1ST IF AND 2ND MIXER CIRCUITS (RF UNIT)
The 2nd mixer circuit converts the 1st IF signal to a 2nd IF
signal.
The filtered 266.7 MHz 1st IF signal from the bandpass filter
is mixed with the 2nd LO signal at the 2nd mixer circuit
(IC10, pin 1) to produce a 19.65 MHz 2nd IF signal. The 2nd
IF signal pass through (except WFM mode) or bypass (WFM
mode) the bandpass filter (FI3), and is then amplified at the
2nd IF amplifier (Q5). The amplified signal is applied to the
demodulator circuit.
4-1-5 DEMODULATOR CIRCUITS (RF UNIT)
The demodulator circuit converts the 2nd IF signal into AF
signals.
The 19.65 MHz 2nd IF signal from the 2nd IF amplifier (Q5)
is applied to the 3rd mixer section of the FM IF IC (IC2, pin
16) and is then mixed with the 3rd LO signal for conversion
into a 450 kHz 3rd IF signal.
4 - 2
IC2 contains the 3rd mixer, limiter amplifier, quadrature
detector and S-meter detector, etc. A frequency from the
PLL reference oscillator is used for the 3rd LO signal (19.20
MHz).
(1) FM mode
The 3rd IF signal is output from FM IF IC (IC2, pin 3) and
passes through the ceramic bandpass filter (FI2). The filtered signal is fed back and amplified at the limiter amplifier
section (pin 5), then demodulated AF signals at the quadrature detector section (pins 10, 11) and detector coil (L21).
The demodulated AF signals are output from pin 9 and are
applied to the AF circuit (LOGIC unit).
(2) WFM mode
The 3rd IF signal from the 3rd mixer bypasses the ceramic
filter (FI2) and fed back to the limiter amplifier section (pin 5).
The amplified signal is demodulated at the quadrature
detector section (pins 10, 11) and detector coil (L21). The AF
signals are output from pin 9 and are applied to the AF circuit (LOGIC unit).
By connecting R55 to R54 in parallel, the output characteristics of pin 12, “RSSI”, change gradually. Therefore, the FM
IF IC can detect WFM components.
(3) AM mode
The filtered 3rd IF signal from the bandpass filter (FI2) is
amplified at the 3rd IF amplifier (Q1). The amplified IF signal
is applied to the AM detector circuit (Q4) to converted into
AF signals, and the signals are applied to the AF circuit
(LOGIC unit).
4-1-6 AF AMPLIFIER CIRCUIT (LOGIC UNIT)
The AF amplifier circuit amplifies the demodulated AF signals to drive a speaker.
While in FM mode, AF signals from the demodulator circuit
(RF unit) are passed through the de-emphasis circuit (R1 18,
C66, C68) with frequency characteristics of –6 dB/octave,
and are then applied to the pre-amplifier (Q31) via the bandpass filter (Q30).
While in AM mode, AF signals are pass through the bandpass filter and are then applied to the pre-amplifier (Q31).
While in WFM mode, AF signals are applied to the preamplifier (Q31) directly.
The pre-amplified AF signals pass through the AF mute circuit (Q37) and are then applied to the electronic volume control circuit (IC14, pin 6). The level controlled AF signals are
output from pin 7 and applied to the AF power amplifier
(IC15, pin 1) via the buffer amplifier (Q36). The power amplified AF signals are applied to the internal speaker via the
[EXT SP] jack.
The electronic volume control circuit controls AF gain, therefore, the AF output level is according to the [VOL] setting
and also the squelch conditions.
4-1-7 SQUELCH CIRCUIT (LOGIC AND RF UNITS)
• NOISE SQUELCH
The noise squelch circuit cuts out AF signals when no RF
signals are received. By detecting noise components in the
AF signals, the squelch circuit switches the AF mute switch.
A portion of the AF signals from the FM IF IC (RF unit; IC2,
pin 9) are applied to the active filter section (IC2, pin 8). The
active filter section amplifies and filters noise components.
The filtered signals are applied to the noise detector section
and output from IC2 (pin 13) as the “SDET” signal.
The “SDET” signal from IC2 (pin 13) passes through the
noise detector (LOGIC unit; IC1), and is then applied to the
CPU (LOGIC unit; IC11, pin 12) via the “SQL” line. The CPU
analyzes the noise condition and outputs the “AMUTE” signal to the AF mute switch (Q37).
Even when the squelch id closed, the AF mute switch (Q37)
opens at the moment of emitting beep tones.
• 2nd IF AND DEMODULATOR CIRCUITS
Mixer
16
Limiter
amp.
3rd IF filter
450 kHz
PLL IC
IC3
X1
19.2 MHz
RSSI
IC2 TA31136F
13
2nd IF (19.65 MHz)
from Q5
"RSSI" signal to the CPU
pin 7 (Logic unit)
11
10
9
87 5 3
2
17
16
Active
filter
FI2
Noise
detector
FM
detector
LPF
Noise
comp.
"SDET" signal to the IC11 (Logic unit)
12
R54
R55
C101
C94
R56
C95
C98
C99
C96
R57
R58
R60
WFM
L21
C93
C242
AF signal "WFMS"
3rd
Q41
4 - 3
• TONE SQUELCH
The tone squelch circuit detects AF signals and opens the
squelch only when receiving a signal containing a matching
subaudible tone (CTCSS). When tone squelch is in use, and
a signal with a mismatched or no subaudible tone is
received, the tone squelch circuit mutes the AF signals even
when noise squelch is open.
A portion of the AF signals from the FM IF IC (IC2, pin 9)
passes through the low-pass filter (LOGIC unit; IC9) via the
“WFMS” line to remove AF (voice) signals and is applied to
the CTCSS decoder inside the CPU (LOGIC unit; IC11, pin
8) via the “RTONE” line to control the AF mute switch.
4-2 PLL CIRCUITS
4-2-1 PLL CIRCUIT (RF UNIT)
A PLL circuit provides stable oscillation of the receive
1st/2nd LO frequencies. The PLL circuit compares the
phase of the divided VCO frequency to the reference frequency. The PLL output frequency is controlled by the divided ratio (N-data) of a programmable divider.
An oscillated signal from the 1st VCO passes thorough the
buffer amplifiers (IC4, Q43) is applied to the PLLIC (IC3, pin
19) and is prescaled in the PLL IC based on the divided ratio
(N-data). The PLLIC detects the out-of-step phase using the
reference frequency and outputs it from pin 13. The output
signal is passed through the loop filter (Q2, Q45) and is then
applied to the 1ST VCO circuit as the lock voltage.
4-2-2 REFERENCE OSCILLATOR CIRCUIT
(RF UNIT)
The reference oscillator circuit (X1, IC3) generates a 19.2
MHz reference frequency which is stabilized within the temperature range –10˚C (+14˚F) to +60˚C (+140˚F). The reference frequency is applied to the PLL IC (IC3, pin 16) and the
signal is output from the pin 17, and is then applied to the
FM IF IC (IC2, pin 2) via the low-pass fileter.
4-2-3 1ST VCO CIRCUIT (RF UNIT)
The oscillated signal is applied to the buffer amplifiers (IC4,
Q40). The amplified signal is applied to the 1st mixer circuit
(IC1) via the RX LO swtich circuit (D42–D44) and doubler
circuit (Q31).
The 1st VCO circuit (Q28, Q30, D54) oscillates 267.2
MHz–380 MHz and 380 MHz–550 MHz by switching the
SHIFT switch (Q29) “High” and “Low” respectively.
A portion of the signal from IC4 is amplified at the buffer
amplifier (Q43) and is then fed back to the PLL IC (IC3, pin
2) as the comparison signal.
4-2-4 2nd VCO CIRCUIT (RF UNIT)
The 2nd LO circuit generates the 2nd LO frequencies, and
the signals are applied to the 2nd mixer circuit.
The 2nd VCO circuit (Q6, L45, C80, C207, C208) oscillates
260 MHz. The oscillated signal is applied to the 2nd mixer
(IC10, pin 3), and is then mixed with the 1st IF signal.
An oscillated signal from the 2nd VCO passes through the
low-pass filter (C154, C250–C252, L69), and is applied to
the PLL IC (IC3, pin 2), and is then output from pin 8.
• PLL circuit
Shift register
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
X1
19.2 MHz
to the FM IF IC
1st VCO
Buffer
Buffer
Buffer
Q40
Q43
IC4
3
4
5
PSTB
IC3 (PLL IC)
CLK
DATA
to 1st mixer circuit
17
16
13
19
Q28, Q30, D54
Q2, Q45
• 2nd LO VCO circuit
Q6, D17
VCO
2nd LO
VCO
Loop
filter
Ripple
filter
LPF
Q37, D53
R3V
to the 2nd mixer (IC10)
PLL IC
IC3
8
2
4 - 4
LINE
BATT
VP
R3V
+3S
+3V
DESCRIPTION
The voltage from the attached battery.
Common 13 V converted from BATT line by the
DC-DC convertors (IC10 and D3, D5, D15). The
output voltage is applied to the PLL circuit (RF
unit).
Receive 3V controlled by the R3V regulator circuit (Q4) using the “RX” signal from CPU (IC11).
Common 3V converted by the +3S regulator circuit (Q3, Q39) using the “+3SC” signal from CPU
(IC11).
Common 3V converted by the +3V regulator circuit (Q6) using the “POWERC” signal from CPU
(IC11).
4-3 POWER SUPPLY CIRCUITS
VOLTAGE LINE
4-4 PORT ALLOCATIONS
4-4-1 CPU (LOGIC UNIT IC11)
Pin Port
Description
number name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
21
22
23
24
25
ADJ
ATT
K2
K1
AMUTE
BATT
RSSI
RTONE
TRC
FSET
CTON
SQL
KFUNC
KTS
VRC
DCK
AM
WFM
BEEP
DUD
POWER
AFON
DBL1
Output control signal for the adjustment mode.
Outputs RF attenuator control signal
to attenuator switch.
Input port for [LOCK], [BAND], [V/M]
switches.
Input port for [UP], [DOWN] switches.
Output AF mute switch (LOGIC unit;
Q37) control signal.
LOW : While squelched.
Input port for the Low battery detection.
Input port for the RSSI signal from the
FM IF IC (RF unit; IC2, pin12) to
detect receiving signal strength.
Input port for the receiving tone signal.
Outputs control signal for the tunable
band-pass filter.
Outputs control signal for the RIT fre-
quency.
Outputs control signal for the CTCSS
requlator circuit.
Pulse signal input port for the squelch.
Input port for the [FUNC] switch.
Low : While [FUNC] switch is
pushed.
Input port for the [TS] switch.
Low : While [TS] switch is pushed.
Outputs level control signal for AF volume.
Input port for the DOWN signal from
the [DIAL].
Outputs AM mode select signals.
Low : When AM is selected.
Outputs WFM mode select signals.
Low : When WFM is selected.
Outputs beep audio signals.
Input port for the UP signal from the
[DIAL].
Input for the [POWER] switch.
Low : While [POWER] switch is
pushed
Outputs control signal for the AF
amplifier requlator circuit.
High : Activates the AF amplifier circuit.
Outputs control signal for the 1st doubler circuit.
Low : Activates the 1st doubler cir-
cuit.
Pin Port
Description
number name
Pin Port
Description
number name
4 - 5
26
27
28
29
30
31
32
33
39
42
43
44, 45
46
47
48
50
51
52
53
54
LIGHT
+3SC
POWERC
B3
B2
B1
KSQL
RESET
EDA
PCK/IS
ECK/I3
I2, I1
PSTB
PDA
DBL2
300MC
GC
800MC
UHFC
VHFC
Output LCD backlight control signal.
High : Lights ON
Outputs +3S requlator control singal
for the receiver circuit.
Low : Receiving.
Outputs +3V requlator control singals.
Outputs high-pass filter select signal.
Low : When frequency 15 to 30
MHz are displayed.
Outputs band-pass filter select signal.
Low : When frequency 1.9 to 15
MHz are displayed.
Outputs low-pass filter select signal.
Low : When frequency 0.5 to 1.5
MHz are displayed.
Input port for the [SQL] switch.
High : While [SQL] switch is pushed.
Input port for the RESET signal.
Outputs data signals to the EEPROM
IC (LOGIC unit; IC2).
Outputs clock signal to both PLL IC
(RF unit; IC3) and EEPROM IC
(LOGIC unit; IC2).
Outputs clock signal to EEPROM IC.
Input ports for Initial matrix.
Outputs strobe signals for the PLL IC.
Outputs data signals to the PLL IC.
Input port for PLL unlock signal from
PLL IC (RF unit; IC3).
Output control signal for the doubler
circuit.
Low : Activates the 2nd doubler cir-
cuit.
Outputs low-pass filter select signal.
Low : When frequencies 30 to 118
MHz or 175 to 330 MHz are
displayed.
Outputs band-pass filter select signal.
Low :When frequencies 833 to
1309.995 MHz are displayed.
Outputs band-pass filter select signal.
Low : When frequencies 470 to
1027 MHz are displayed.
Outputs band-pass filter select signal.
Low : When frequencies 330 to 470
MHz are displayed.
Outputs band-pass filter select signal.
Low : When frequencies 118 to 175
MHz are displayed.
55
56
SHIFT
HFC
Output port for 1st VCO SHIFT signals
to the shift switch (RF unit; Q29).
High : Shift ON (380 – 550 MHz).
Low : Shift OFF (267.2 – 380 MHz).
Output control signal for the 0.5–30
MHz band RF amplifier.
Low : Receiving 0.5–30 MHz bands.
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