HP AT-31033-TR1, AT-31033-BLK, AT-31011-TR1, AT-31011-BLK Datasheet

Low Current, High Performance NPN Silicon Bipolar Transistor

Technical Data

AT-31011 AT-31033

Features

• High Performance Bipolar Transistor Optimized for Low Current, Low Voltage Operation

• 900 MHz Performance:

AT-31011: 0.9 dB NF, 13 dB G AT-31033: 0.9 dB NF, 11 dB G

• Characterized for End-OfLife Battery Use (2.7 V)

• SOT-143 SMT Plastic Package

• Tape-And-Reel Packaging Option Available

[1]

Outline Drawing

EMITTER COLLECTOR

310

BASE EMITTER

SOT-143 (AT-31011)

COLLECTOR

310

BASE EMITTER

SOT-23 (AT-31033)

Description

Hewlett-Packard’s AT-31011 and AT-31033 are high performance NPN bipolar transistors that have been optimized for operation at low voltages, making them ideal

for use in battery powered applications in wireless markets. The AT-31033 uses the 3 lead SOT-23, while the AT-31011 places the same die in the higher performance 4 lead SOT-143. Both packages are industry standards compatible with high volume surface mount assembly techniques.

battery operated systems as an LNA, gain stage, buffer, oscillator, or active mixer. Applications include cellular and PCS handsets as well as Industrial-ScientificMedical systems. Typical amplifier designs at 900 MHz yield 1.3 dB noise figures with 11 dB or more associated gain at a 2.7 V, 1 mA bias. Moderate output power capability (+9 dBm P

) coupled

1dB

with an excellent noise figure yields high dynamic range for a microcurrent device. High gain capability at 1 V, 1 mA makes these devices a good fit for 900 MHz pager applications.

The 3.2 micron emitter-to-emitter pitch and reduced parasitic design of these transistors yields extremely high performance products that can perform a multiplicity of tasks. The 10 emitter finger interdigitated geometry yields an extremely fast transistor with low operating currents and reasonable impedances.

The AT-3 series bipolar transistors are fabricated using an optimized version of Hewlett-Packard’s 10 GHz fT, 30 GHz f

max

SelfAligned-Transistor (SAT) process. The die are nitride passivated for surface protection. Excellent device uniformity, performance and reliability are produced by the use of ion-implantation, self-

Optimized performance at 2.7 V makes these devices ideal for use in 900 MHz, 1.9 GHz, and 2.4 GHz

alignment techniques, and gold metalization in the fabrication of these devices.

Note:

1. Refer to “Tape-and-Reel Packaging for Semiconductor Devices”

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5965-8919E

AT-31011, AT-31033 Absolute Maximum Ratings

Symbol Parameter Units Absolute Maximum

EBO

CBO

CEO

STG

Notes:

1. Operation of this device above any one of these parameters may cause permanent damage.

2. T

Mounting Surface

3. Derate at 1.82 mW/°C for TC > 67.5°C.

Emitter-Base Voltage V 1.5

Collector-Base Voltage V 11

Collector-Emitter Voltage V 5.5

Collector Current mA 16

Power Dissipation

Junction Temperature °C 150

[2,3]

mW 150

Storage Temperature °C -65 to 150

= 25°C.

[1]

Thermal Resistance

θjc = 550°C/W

[2]

Electrical Specifications, T

= 25°C

AT-31011 AT-31033

Symbol Parameters and Test Conditions Units Min Typ Max Min Typ Max

NF Noise Figure

VCE = 2.7 V, IC = 1 mA f = 0.9 GHz dB 0.9

Associated Gain

VCE = 2.7 V, IC = 1 mA f = 0.9 GHz dB 11

Forward Current VCE = 2.7 V - 70 300 70 300

[1]

1.2

[1]

[2]

0.9

1.2

[2]

Transfer Ratio IC = 1 mA

CBO

EBO

Notes:

1. Test circuit B, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.4 dB; output loss = 0.4 dB.

2. Test circuit A, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.4 dB; output loss = 0.4 dB.

1000 pF

W = 10 L = 1000

TEST CIRCUIT BOARD MATL = 0.062" FR-4 (ε = 4.8)

DIMENSIONS IN MILS

Collector Cutoff Current V

Emitter Cutoff Current V

W = 10 L = 1860

W = 30 L = 100

TEST CIRCUIT A: W = 20 L = 100 TEST CIRCUIT B: W = 20 L = 200 x 2

NOT TO SCALE

= 3 V µA 0.05 0.2 0.05 0.2

= 1 V µA 0.1 1.5 0.1 1.5

25 Ω

W = 10 L = 1860

1000 pF

W = 10 L = 1025

[2]

Figure 1. Test Circuit for Noise Figure and Associated Gain. This Circuit is a Compromise Match Between Best Noise Figure, Best Gain, Stability, a Practical, Synthesizable Match, and a Circuit Capable of Matching Both the AT-305 and AT-310 Geometries.

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Characterization Information, T

= 25°

AT-31011 AT-31033

Symbol Parameters and Test Conditions Units Typ Typ

1dB

Power at 1 dB Gain Compression (opt tuning) VCE = 2.7 V, IC = 10 mA f = 0.9 GHz dBm 9 9

Gain at 1 dB Gain Compression (opt tuning)

1dB

VCE = 2.7 V, IC = 10 mA f = 0.9 GHz d B 15 13

Output Third Order Intercept Point,

VCE = 2.7 V, IC = 10 mA (opt tuning) f = 0.9 GHz dBm 20 20

|S21|

2.5

1.5

NOISE FIGURE (dB)

0.5

Figure 2. AT-31011 and AT-31033 Minimum Noise Figure and Amplifier

[1]

vs. Frequency and Current at

VCE␣ = 2.7 V.

Gain in 50 Ω System; V

Collector-Base Capacitance VCB = 3V, f = 1 M Hz pF 0.04 0.04

AMPLIFIER NF

NF MIN.

1 mA 10 mA

0.5 2.5

1 1.5

FREQUENCY (GHz)

= 2.7 V, IC = 1 mA f = 0.9 GHz dB 10 9

Ga (dB)

0.5 2.5

10 mA

1 mA

1.0 1.5

FREQUENCY (GHz)

2.0

Figure 3. AT-31011 Associated Gain at Optimum Noise Match vs. Frequency and Current at VCE␣ = 2.7 V.

Ga (dB)

0.5 2.5

10 mA

1 mA

1.0 1.5

FREQUENCY (GHz)

Figure 4. AT-31033 Associated Gain at Optimum Noise Match vs. Frequency and Current at VCE␣ = 2.7 V.

2.0

P 1dB (dBm)

10 mA

5 mA

2 mA

0.5 2.5

FREQUENCY (GHz)

1.0 1.5

2 mA 5 mA 10 mA

2.0

Figure 5. AT-31011 and AT-31033 Power at 1 dB Gain Compression vs. Frequency and Current at VCE␣ = 2.7 V.

G 1dB (dB)

0.5 2.5

1.0 1.5

FREQUENCY (GHz)

2 mA 5 mA 10 mA

2.0

Figure 6. AT-31011 1 dB Compressed Gain vs. Frequency and Current at VCE␣ = 2.7 V.

G 1dB (dB)

1.0 1.5

0.5 2.5 FREQUENCY (GHz)

2 mA 5 mA 10 mA

2.0

Figure 7. AT-31033 1 dB Compressed Gain vs. Frequency and Current at VCE␣ = 2.7 V.

Note:

1. Amplifier NF represents the noise figure which can be expected in a real circuit representing reasonable reflection coefficients and including circuit losses.

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