HP AT-30533-TR1, AT-30533-BLK, AT-30511-TR1, AT-30511-BLK Datasheet

Low Current, High Performance

NPN Silicon Bipolar Transistor

Technical Data

AT-30511 AT-30533

Features

• High Performance Bipolar Transistor Optimized for Low Current, Low Voltage Operation

• 900 MHz Performance:

AT-30511: 1.1 dB NF, 16 dB G AT-30533: 1.1 dB NF, 13 dB G

• Characterized for End-OfLife Battery Use (2.7 V)

• SOT-23 and SOT-143 SMT Plastic Packages

• Tape-And-Reel Packaging Option Available

[1]

Outline Drawing

EMITTER COLLECTO

305

BASE EMITTER

SOT-143 (AT-30511)

COLLECTOR

305

Description

Hewlett-Packard’s AT-30511 and AT-30533 are high performance NPN bipolar transistors that have been optimized for maximum fT at low voltage operation, making

them ideal for use in battery powered applications in wireless markets. The AT-30533 uses the 3 lead SOT-23, while the AT-30511 places the same die in the higher performance 4 lead SOT-143. Both packages are industry standard, and compatible with high volume

Optimized performance at 2.7 V makes these devices ideal for use in 900 MHz, 1.8 GHz, and 2.4 GHz battery operated systems as an LNA, gain stage, buffer, oscillator, or active mixer. Typical amplifier designs at 900 MHz yield 1.3 dB noise figures with 13 dB or more associated gain at a 2.7 V, 1 mA bias. Voltage breakdowns are high enough for use at 5 volts. High gain capability at 1 V, 1 mA makes these devices a good fit for 900␣ MHz pager applications.

surface mount assembly techniques.

The AT-3 series bipolar transistors are fabricated using an optimized

The 3.2 micron emitter-to-emitter pitch and reduced parasitic design of these transistors yields extremely high performance products that can perform a multiplicity of tasks. The 5 emitter finger interdigitated geometry yields an extremely fast transistor with high gain and low operating currents.

version of Hewlett- Packard’s 10␣ GHz fT, 30 GHz f

MAX

SelfAligned-Transistor (SAT) process. The die are nitride passivated for surface protection. Excellent device uniformity, performance and reliability are produced by the use of ion-implantation, selfalignment techniques, and gold metalization in the fabrication of these devices.

Note:

1. Refer to “Tape-and-Reel Packaging for

BASE EMITTER

SOT-23 (AT-30533)

Semiconductor Devices”.

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5965-8918E

AT-30511, AT-30533 Absolute Maximum Ratings

Symbol Parameter Units Absolute Maximum

EBO

CBO

CEO

STG

Notes:

1. Operation of this device above any one of these parameters may cause permanent damage.

2. T

Mounting Surface

3. Derate at 1.82 mW/°C for TC > 95°C.

Emitter-Base Voltage V 1.5 Collector-Base Voltage V 11 Collector-Emitter Voltage V 5.5 Collector Current mA 8

Power Dissipation

Junction Temperature °C 150

[2] [3]

mW 100

Storage Temperature °C -65 to 150

= 25°C.

[1]

Thermal Resistance

θjc = 550°C/W

[2]

Electrical Specifications, T

= 25°C

AT-30511 AT-30533

Symbol Parameters and Test Conditions Units Min Typ Max Min Typ Max

NF Noise Figure

VCE = 2.7 V, IC = 1 mA f = 0.9 GHz dB 1.1

Associated Gain

VCE = 2.7 V, IC = 1 mA f = 0.9 GHz dB 14

Forward Current VCE = 2.7 V - 70 300 70 300

[1]

1.4

[1]

[2]

1.1

1.4

[2]

Transfer Ratio IC = 1 mA

CBO

EBO

Notes:

1. Test circuit B, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.4 dB; output loss = 0.4 dB.

2. Test circuit A, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.4 dB; output loss = 0.4 dB.

1000 pF

W = 10 L = 1000

TEST CIRCUIT BOARD MATL = 0.062" FR-4 (ε = 4.8)

DIMENSIONS IN MILS

Collector Cutoff Current V

Emitter Cutoff Current V

W = 10 L = 1860

W = 30 L = 100

TEST CIRCUIT A: W = 20 L = 100 TEST CIRCUIT B: W = 20 L = 200 x 2

NOT TO SCALE

= 3 V µA 0.03 0.2 0.03 0.2

= 1 V µA 0.1 1.5 0.1 1.5

25 Ω

W = 10 L = 1860

1000 pF

W = 10 L = 1025

[2]

Figure 1. Test Circuit for Noise Figure and Associated Gain. This Circuit is a Compromise Match Between Best Noise Figure, Best Gain, Stability, a Practical, Synthesizable Match, and a Circuit Capable of Matching Both the AT-305 and AT-310 Geometries.

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AT-30511, AT-30533 Characterization Information, T

= 25° C

AT-30511 AT-30533

Symbol Parameters and Test Conditions Units Typ Typ

1dB

Power at 1 dB Gain Compression (opt tuning) VCE = 2.7 V, IC = 5 mA f = 0.9 GHz dBm 7 7

Gain at 1 dB Gain Compression (opt tuning)

1dB

VCE = 2.7 V, IC = 5 mA f = 0.9 GHz dB 16.5 15

Output Third Order Intercept Point,

VCE = 2.7 V, IC = 5 mA (opt tuning) f = 0.9 GHz dBm 17 17

|S21|

Gain in 50 Ω System; V

Collector-Base Capacitance VCB = 3V, f = 1 M Hz p F 0.04 0.04

Typical Performance

2.5

2.0

1.5

1.0 NF MIN.

NOISE FIGURE (dB)

0.5

AMPLIFIER NF

0.5 2.5

1.0 1.5

FREQUENCY (GHz)

1 mA 5 mA

2.0

= 2.7 V, IC = 1 mA f = 0.9 GHz dB 10 9

Ga (dB)

5 mA

1 mA

0.5 2.5

1.0 1.5

FREQUENCY (GHz)

2.0

Ga (dB)

5 mA

1 mA

0.5 2.5

1.0 1.5

FREQUENCY (GHz)

Figure 2. AT-30511 and AT-30533 Minimum Noise Figure and Amplifier

[1]

vs. Frequency and Current at

Figure 3. AT-30511 Associated Gain at Optimum Noise Match vs. Frequency and Current at VCE␣ = 2 .7 V.

Figure 4. AT-30533 Associated Gain at Optimum Noise Match vs. Frequency and Current at VCE␣ = 2 .7 V.

VCE␣= 2.7V.

P 1dB (dBm)

5 mA

2 mA

0.5 2.5

1.0 1.5

FREQUENCY (GHz)

2.0

Figure 5. AT-30511 and AT-30533 Power at 1 dB Gain Compression vs. Frequency and Current at VCE␣ = 2.7 V.

5 mA

G 1dB (dBm)

0.5 2.5 FREQUENCY (GHz)

2 mA

1.0 1.5

2.0

Figure 6. AT-30511 1 dB Compressed Gain vs. Frequency and Current at VCE␣ = 2.7 V.

G 1dB (dBm)

5 mA

2 mA

0.5 2.5

1.0 1.5

FREQUENCY (GHz)

2.0

Figure 7. AT-30533 1 dB Compressed Gain vs. Frequency and Current at VCE␣ = 2.7 V.

Note:

1. Amplifier NF represents the noise figure which can be expected in a real circuit representing reasonable reflection coefficients and including circuit losses.

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