PACKAGE AND PACKAGE PARTS11WIRING DIAGRAM................ 113
DISASSEMBLY12SCHEMATIC DIAGRAMS....... 114
UNIT EXPLODED VIEW AND PARTS13
harman/kardon, Inc.
250 Crossways Park Dr.
Woodbury, New York, 11797
Released 2007
Discontinued XXXXRev 0, 8/2007
Page 2
harman/kardon
Service manual DVD37EU
Page 2 of 117
ESD PRECAUTIONS
Electrostatically Sensitive Devices (ESD)
Some semiconductor (solid state) devices can be damaged easily by static electricity. Such components commonly are called Electrostatically Sensitive Devices (ESD). Examples of typical ESD devices are integrated circuits and some field-effect transistors and semiconductor chip components. The following techniques should
be used to help reduce the incidence of component damage caused by static electricity.
1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain off
any electrostatic charge on your body by touching a known earth ground. Alternatively, obtain and wear a
commercially available discharging wrist strap device, which should be removed for potential shock reasons
prior to applying power to the unit under test.
2. After removing an electrical assembly equipped with ESD devices, place the assembly on a conductive surface such as aluminum foil, to prevent electrostatic charge buildup or exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ESD devices.
4. Use only an anti-static solder removal device. Some solder removal devices not classified as "anti-static"
can generate electrical charges sufficient to damage ESD devices.
5. Do not use freon-propelled chemicals. These can generate electrical charges sufficient to damage ESD
devices.
6. Do not remove a replacement ESD device from its protective package until immediately before you are
ready to install it. (Most replacement ESD devices are packaged with leads electrically shorted together by
conductive foam, aluminum foil or comparable conductive materials).
7. Immediately before removing the protective material from the leads of a replacement ESD device, touch the
protective material to the chassis or circuit assembly into which the device will by installed.
CAUTION : BE SURE NO POWER IS APPLIED TO THE CHASSIS OR CIRCUIT, AND OBSERVE ALL
OTHER SAFETY PRECAUTIONS.
8. Minimize bodily motions when handing unpackaged replacement ESD devices. (Otherwise harmless motion
such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted floor can generate static electricity sufficient to damage an ESD device).
Page 3
SERVICING PRECAUTIONS
NOTES REGARDING HANDLING OF THE PICK-UP
1. Notes for transport and storage
1) The pick-up should always be left in its conductive bag until immediately prior to use.
2) The pick-up should never be subjected to external pressure or impact.
2. Repair notes
1) The pick-up incorporates a strong magnet, and so should never be brought close to magnetic materials.
2) The pick-up should always be handled correctly and carefully, taking care to avoid external pressure and
impact. If it is subjected to strong pressure or impact, the result may be an operational malfunction
and/or damage to the printed-circuit board.
3) Each and every pick-up is already individually adjusted to a high degree of precision, and for that reason
the adjustment point and installation
screws should absolutely never be touched.
4) Laser beams may damage the eyes!
Absolutely never permit laser beams to enter the eyes!
Also NEVER switch ON the power to the laser output part (lens, etc.) of the pick-up if it is damaged.
5) Cleaning the lens surface
If there is dust on the lens surface, the dust should be cleaned away by using an air bush (such as used
for camera lens). The lens is held by a delicate spring. When cleaning the lens surface, therefore, a cotton swab should be used, taking care not to distort this.
6) Never attempt to disassemble the pick-up.
Spring by excess pressure. If the lens is extremely dirty, apply isopropyl alcohol to the cotton swab. (Do
not use any other liquid cleaners, because they will damage the lens.) Take care not to use too much of
this alcohol on the swab, and do not allow the alcohol to get inside the pick-up.
Storage in conductive bag
NEVER look directly at the laser beam, and don’t let contact
fingers or other exposed skin.
Magnet
How to hold the pick-up
Conductive Sheet
Cotton swab
Pressure
Pressure
Drop impact
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Service manual DVD37EU
Page 3 of 117
Page 4
NOTES REGARDING COMPACT DISC PLAYER REPAIRS
1. Preparations
1) Compact disc players incorporate a great many ICs as well as the pick-up (laser diode). These components are sensitive to, and easily affected by, static electricity. If such static electricity is high voltage,
components can be damaged, and for that reason components should be handled with care.
2) The pick-up is composed of many optical components and other high-precision components. Care must
be taken, therefore, to avoid repair or storage where the temperature of humidity is high, where strong
magnetism is present, or where there is excessive dust.
2. Notes for repair
1) Before replacing a component part, first disconnect the power supply lead wire from the unit
2) All equipment, measuring instruments and tools must be grounded.
3) The workbench should be covered with a conductive sheet and grounded.
When removing the laser pick-up from its conductive bag, do not place the pick-up on the bag. (This is
because there is the possibility of damage by static electricity.)
4) To prevent AC leakage, the metal part of the soldering iron should be grounded.
5) Workers should be grounded by an armband (1MΩ)
6) Care should be taken not to permit the laser pick-up to come in contact with clothing, in order to prevent
static electricity changes in the clothing to escape from the armband.
7) The laser beam from the pick-up should NEVER be directly facing the eyes or bare skin.
VCD, CD, CD-R, CD-RW or MP3 discs
Region code: DVD video disc with Code 1 or 0 only
DVD layers: Single side/single layer, single side/dual layer, dual side/dual layer
Audio formats: DVD Audio MLP lossless, linear PCM, MPEG, Windows Media
Still-image format: JPEG
Video Signal System:NTSC
HDMI™Output:Video: 480p, 720p, 1080i
HDMI Version 1.0-compliant
HDCP Version 1.1-compliant
Signal/Noise Ratio (SNR):105dB (A-weighted)
Dynamic Range:DVD: 100dB (18-bit)/105dB (20-bit)
CD/DVD: 96dB (16-bit)
THD/1kHz:DVD/CD: 0.0025%
Wow & Flutter:Below measurable limits
AC Power:110–240V AC/50–60Hz
Power Consumption:1 Watt (on/standby)/13 watts (max)
Dimensions (H x W x D):2" x 17-3/10" x 11-1/4" (50mm x 440mm x 285mm)
Weight:6 lb (2.7kg)
Shipping Dimensions (H x W x D):5" x 14-3/8" x 20" (127mm x 365mmx 508mm)
Shipping Weight:8.8 lb (4kg)
®
9, Dolby®Digital or DTS®audio discs
Depth measurement includes knobs and connectors.
Height measurement includes feet and chassis.
All specifications subject to change without notice.
Harman Kardon and Harman International are trademarks of Harman International Industries, Incorporated, registered in the United States and/or other countries.
Dolby, Pro Logic and the double-D symbol are registered trademarks of Dolby Laboratories. Confidential Unpublished Works.
1992-1997 Dolby Laboratories, Inc.All rights reserved. Manufactured under license from Dolby Laboratories.
DTS and DTS-ES are registered trademarks of DTS, Inc.
Kodak and Photo CD are trademarks of Eastman Kodak Company.
Microsoft, Windows Media, HDCD and High Definition Compatible Digital are registered trademarks of Microsoft Corporation in the United States and/or other countries.
Blu-ray Disc is a trademark of the Blu-ray Disc Association.
HDMI, the HDMI logo and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC.
HD-DVD is a trademark of the DVD Format/Logo Licensing Corporation (DVD FLLC).
SACD is a trademark of Sony Corporation.
This product incorporates copyright protection technology that is protected by method claims of certain U.S. patents and other intellectual property rights owned by
Macrovision Corporation and other rights owners. Use of this copyright protection technology must be authorized by Macrovision Corporation and is intended for home
and other limited viewing uses only unless otherwise authorized by Macrovision Corporation. Reverse engineering or disassembly is prohibited.
38TECHNICAL SPECIFICATIONS
Page 6
MODEL NAME : DVD 37 & DVD 37/230
D
ifi
f
Audi
o
TDV-540A (ABEX)
,
TDV-540A (ABEX)
harman/kardon
Service manual DVD37EU
Page 6 of 117
escription : Characteristics Spec
cation o
o
Test Disc : YEDS7 (SONY), TDV-540A (ABEX)
Test Conditions : 10kΩ Load Terminated, AC100V 50/60Hz
Test Measuerment : VP-7722A (Audio Analyzer) ,CASCADE SYS-2522(AP)
1.ANALOG AUDIO OUTPUT
Measurement Item
Output Level[Vrms]L
R
LimitResult
2.0 ± 0.2
YEDS7 (SONY)
Level difference [Vrms] < 0.2
F/ response [dB]L
Ref.1kHz 0dBL
z
2 0 H
100 Hz
10 KHz
20 KHz
R
R
L
R
L
R
L
44 KHz
R
Emphasis L
Characteristic[dB]R
Ref.1kHz 0dBL
5 KHz
16 KHz
R
S/N [dB]L
R
Channel Separation [dB]L→R
R→L
Linearity [dB]L
-90dB playbackR
T.H.D [%]L
R
Dynamic Range [dB]L
-60dB playbackR
全高調波歪率 [%]L
DVD 96kR
Dynamic Range [dB]L
DVD 96kR
全高調波歪率 [%]L
DVD 48kR
Dynamic Range [dB]L
DVD 48kR
0± 1.0
0± 1.0
0± 1.0
0± 1.5
0± 1.5
-4.53±1.0
-9.04 ± 1.0
>105
> 95
89.5±3
< 0.01
>93
< 0.01
>95
< 0.01
>95
YEDS7 (SONY)
YEDS7 (SONY)
YEDS7 (SONY)
YEDS7 (SONY)
TDV-540A (ABEX)
TITLE 4,CHAPTER
AUDIO STREAM 3
YEDS7 (SONY)
YEDS7 (SONY)
YEDS7 (SONY)
YEDS7 (SONY)
YEDS7 (SONY)
YEDS7 (SONY)
YEDS7 (SONY)
TDV-540A (ABEX)
TITLE 3, CHAPTER 1
TDV-540A (ABEX)
TITLE 3, CHAPTER 2
TITLE 2, CHAPTER 1
TITLE 2, CHAPTER 2
TEST DISC
TRACK 1
TRACK 2
TRACK 4
TRACK 10
TRACK 13
16
TRACK 40
TRACK 41
TRACK 23
TRACK 30
TRACK 22
TRACK 1
TRACK 20
34
2. DIGITAL OUTPUT
1) OPTICAL OUT
JITTER 44.1kHzNormal 44.1kHz
JITTER 96kHzNormal 96kHz
2) COAXIAL OUT
OUTPUT Level [mV]Normal CD or DVD
Peak to Peak Level at 75ohm L
(mUI)CD Playback
(mUI)DVD Playback
< 50mUI
< 50mUI
500±50 (mV)
Playback
Page 7
MODEL NAME : DVD 37& DVD 37/230
harman/kardon
Service manual DVD37EU
Page 7 of 117
Description : Characteristics Specification of Video
Test Disc : TDV-540A (ABEX) , MDVD-111 (TEAC) Serial NO.:
Test Conditions : 75Ω Load Terminated
AC Input : For USA (120V/60Hz) , For Europe (230V/50Hz)
Test Measuerment : VM-700T
Description : Characteristics Specification of Video
Test Disc : TDV-540A (ABEX) , MDVD-111 (TEAC) Serial NO.:
Test Conditions : 75Ω Load Terminated
AC Input : For USA (120V/60Hz) , For Europe (230V/50Hz)
Test Measuerment : VM-700T
Unit does not turn on • No AC power• Check AC power plug and make certain any switched
outlet is turned on.
Disc does not play• Disc loaded improperly• Load disc label-side up; align the disc with the guides and place
it in its proper position.
• Incorrect disc type• Check to see that disc is SACD, CD, CD-R, CD-RW, VCD, MP3, WMA, JPEG,
DVD-R, DVD-RW, DVD+R, DVD+RW (standard-conforming), DVD-Audio or
DVD-Video; other types will not play.
• Invalid Region Code• Use Region 1 or Open Region (0) disc only.
• Rating is above parental preset• Enter password to override or change rating settings (see page 20).
No picture• Intermittent connections• Check all video connections.
• Wrong input• Check input selection of TV or receiver.
• Progressive Scan output selected• Use Progressive Scan mode only with compatible TV. Press
Interlaced Button
• Video Off feature active• Press
•
HDMI Output 2 is connected to a • The HDMI Output 2 may not be used with video displays that are not
video display that is not HDCP-compliant.HDCP-compliant. Unplug the cable and select another audio and video
Video Off ButtonFto reactivate video circuitry.
connection (see pages 14 through 16).
I to toggle to the correct mode (see page 23).
Progressive Scan/
No sound• Intermittent connections• Check all audio connections.
• Incorrect digital audio selection• Check digital audio settings on DVD 47 and on receiver.
• DVD disc is in fast or slow mode• There is no audio playback on DVD discs during fast or slow modes.
• Surround receiver not compatible • Use analog audio outputs.
with 96kHz PCM audio
• DVD Audio or SACD disc is loaded • Use
without using analog audio connection
Picture is distorted or jumps during• MPEG-2 decoding• It is a normal artifact of DVD playback for pictures to jump or show
fast forward or reverse playsome distortion during rapid play.
Some remote buttons do not operate• Function not permitted at this time• With most discs, some functions are not permitted at certain
during DVD play; prohibited symbol times (e.g., Track Skip) or at all (e.g., direct audio track selection).
appears (see below)
The OSD menu is in a foreign language• Incorrect OSD language• Change the display language selection (see page 23).
The symbol appears• Requested function not available at • Certain functions may be disabled by the DVD itself during
this timepassages of a disc.
Picture is displayed in the• Incorrect match of aspect ratio settings• Change aspect ratio settings (see page 23).
wrong aspect ratioto disc
Remote control inoperative• Weak batteries• Change both batteries.
• Sensor is blocked• Clear path to sensor or use optional outboard remote sensor.
Disc will not copy to VCR• Copy protection• Many DVDs are encoded with copy protection to prevent
6-Channel Audio Outputs 9 or Analog Audio Outputs 8.
copying to VCR.
Password not accepted.• Incorrect password being used or• Stop play of disc. Press and hold
Clear Button 3 until the display blinks.
password has been forgotten.This resets the password and all settings to their defaults.
0.1UF ZF 1608
390PF JA 1608
390PF JA 1608
390PF JA 1608
390PF JA 1608
390PF JA 1608
390PF JA 1608
390PF JA 1608
390PF JA 1608
390PF JA 1608
390PF JA 1608
390PF JA 1608
0.1UF ZF 1608
0.1UF ZF 1608
0.1UF ZF 1608
0.1UF ZF 1608
0.1UF ZF 1608
0.1UF ZF 1608
0.1UF ZF 1608
0.1UF ZF 1608
0.1UF ZF 1608
0.1UF ZF 1608
56PF JA 1608
100PF JA 1608
0.1UF ZF 1608
100PF JA 1608
100PF JA 1608
C822 CCUS1H560JACAP , CHIP56PF JA 1608
C823 CCUS1H104KCCAP , CHIP
0.1UF ZF 1608
C828 CCUS1H220JACAP , CHIP22PF JA 1608
C830 CCUS1H150JACHIP, CAP 15PF/50V/1608
C831 CCUS1H150JACHIP, CAP 15PF/50V/1608
C834 CCUS1H104KCCAP , CHIP
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by
16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2003
Revision: 1.7 1/44
Page 73
ESMT M12L64164A
A
A
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Service manual DVD37EU
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FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
ddress
CS
RAS
CAS
WE
Clock
Generator
Row
ddress
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Row Decoder
Sense Amplifier
Column Decoder
Data Control Circuit
Command Decoder
Mode
Register
Control Logic
Bank B
Bank A
Bank D
Bank C
L(U)DQM
DQ
Buffer
Latch Circuit
Input & Output
PIN FUNCTION DESCRIPTION
PIN NAME INPUT FUNCTION
CLK System Clock Active on the positive going edge to sample all inputs
CS
CKE Clock Enable
A0 ~ A11 Address
A12 , A13 Bank Select Address
RAS
CAS
WE
L(U)DQM Data Input / Output Mask
DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins.
VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic.
VDDQ / VSSQ Data Output Power / Ground
NC No Connection This pin is recommended to be left No Connection on the device.
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
CAS , WE active.
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2003
Revision: 1.7 2/44
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ESMT M12L64164A
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DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between V
high all inputs are assumed to be in valid state (low or high)
for the duration of setup and hold time around positive edge
of the clock for proper functionality and Icc specifications.
CLOCK ENABLE(CKE)
The clock enable (CKE) gates the clock onto SDRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock suspended
from the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When all banks are in the idle state and CKE goes low
synchronously with clock, the SDRAM enters the power
down mode from the next clock cycle. The SDRAM remains
in the power down mode ignoring the other inputs as long as
CKE remains low. The power down exit is synchronous as
the internal clock is suspended. When CKE goes high at
least “1CLK + tSS” before the high going edge of the clock,
then the SDRAM becomes active from the same clock edge
accepting all the input commands.
BANK ADDRESSES (A13~A12)
This SDRAM is organized as four independent banks of
1,048,576 words x 16 bits memory arrays. The A13~A12
inputs are latched at the time of assertion of
CAS to select the bank to be used for the operation. The
banks addressed A13~A12 are latched at bank active, read,
write, mode register set and precharge operations.
ADDRESS INPUTS (A0~A11)
The 20 address bits are required to decode the 1,048,576
word locations are multiplexed into 12 address input pins
(A0~A11). The 12 row addresses are latched along with
RAS and A13~A12 during bank active command. The 8 bit
column addresses are latched along with
A13~A12 during read or with command.
NOP and DEVICE DESELECT
IL and VIH. During operation with CKE
RAS and
CAS , WE and
POWER-UP
1.Apply power and start clock, Attempt to maintain CKE
= “H”, DQM = “H” and the other pins are NOP
condition at the inputs.
2.Maintain stable power, stable clock and NOP input
condition for minimum of 200us.
3.Issue precharge commands for both banks of the
devices.
4.Issue 2 or more auto-refresh commands.
5.Issue a mode register set command to initialize the
mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the
various operating modes of SDRAM. It programs the
CAS latency, burst type, burst length, test mode and
various vendor specific options to make SDRAM useful
for variety of different applications. The default value of
the mode register is not defined, therefore the mode
register must be written after power up to operate the
SDRAM. The mode register is written by asserting low
CS , RAS , CAS and WE (The SDRAM should
on
be in active mode with CKE already high prior to writing
the mode register). The state of address pins A0~A11
and A13~A12 in the same cycle as
WE going low is the data written in the mode
and
register. Two clock cycles is required to complete the
write in the mode register. The mode register contents
can be changed using the same command and clock
cycle requirements during operation as long as all banks
are in the idle state. The mode register is divided into
various fields into depending on functionality. The burst
length field uses A0~A2, burst type uses A3, CAS
latency (read latency from column address) use A4~A6,
vendor specific options or test mode use A7~A8,
A10/AP~A11 and A13~A12. The write burst length is
programmed using A9. A7~A8, A10/AP~A11 and
A13~A12 must be set to low for normal SDRAM
operation. Refer to the table for specific codes for
various burst length, burst type and CAS latencies.
CS , RAS , CAS
When
performs no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which
require more than single clock cycle like bank activate, burst
read, auto refresh, etc. The device deselect is also a NOP
and is entered by asserting
the command decoder so that
the address inputs are ignored.
RAS , CAS and WE are high, The SDRAM
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2003
Revision: 1.7 11/44
CS high. CS high disables
RAS , CAS , WE and all
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Page 75 of 117
DEVICE OPERATIONS (Continued)
BANK ACTIVATE
The bank activate command is used to select a random row
in an idle bank. By asserting low on RAS and CS with
desired row and bank address, a row access is initiated. The
read or write operation can occur after a time delay of t
(min) from the time of bank activation. tRCD is the internal
RCD
timing parameter of SDRAM, therefore it is dependent on
operating clock frequency. The minimum number of clock
cycles required between bank activate and read or write
command should be calculated by dividing tRCD(min) with
cycle time of the clock and then rounding of the result to the
next higher integer. The SDRAM has four internal banks in
the same chip and shares part of the internal circuitry to
reduce chip area, therefore it restricts the activation of four
banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high requiring some time
for power supplies to recover before another bank can be
sensed reliably. tRRD (min) specifies the minimum time required
between activating different bank. The number of clock
cycles required between different bank activation must be
calculated similar to t
RCD specification. The minimum time
required for the bank to be active to initiate sensing and
restoring the complete row of dynamic cells is determined by
RAS (min). Every SDRAM bank activate command must satisfy
t
t
RAS (min) specification before a precharge command to that
active bank can be asserted. The maximum time any bank
can be in the active state is determined by tRAS (max) and tRAS
(max) can be calculated similar to tRCD specification.
BURST READ
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low on
CS and RAS with WE being high on the positive edge
of the clock. The bank must be active for at least tRCD (min)
before the burst read command is issued. The first output
appears in CAS latency number of clock cycles after the
issue of burst read command. The burst length, burst
sequence and latency from the burst read command is
determined by the mode register which is already
programmed. The burst read can be initiated on any column
address of the active row. The address wraps around if the
initial address does not start from a boundary such that
number of outputs from each I/O are equal to the burst
length programmed in the mode register. The output goes
into high-impedance at the end of burst, unless a new burst
read was initiated to keep the data output gapless. The burst
read can be terminated by issuing another burst read or
burst write in the same bank or the other active bank or a
precharge command to the same bank. The burst stop
command is valid at every page burst length.
BURST WRITE
The burst write command is similar to burst read command
and is used to write data into the SDRAM on consecutive
clock cycles in adjacent addresses depending on burst
length
and burst sequence. By asserting low on
WE with valid column address, a write burst is
and
initiated. The data inputs are provided for the initial
address in the same clock cycle as the burst write
command. The input buffer is deselected at the end of
the burst length, even though the internal writing can be
completed yet. The writing can be complete by issuing a
burst read and DQM for blocking data inputs or burst
write in the same or another active bank. The burst stop
command is valid at every burst length. The write burst
can also be terminated by using DQM for blocking data
and procreating the bank t
RDL after the last data input to
be written into the active row. See DQM OPERATION
also.
DQM OPERATION
The DQM is used mask input and output operations. It
works similar to
OE during operation and inhibits
writing during write operation. The read latency is two
cycles from DQM and zero cycle for write, which means
DQM masking occurs two cycles later in read cycle and
occurs in the same cycle during write cycle. DQM
operation is synchronous with the clock. The DQM
signal is important during burst interrupts of write with
read or precharge in the SDRAM. Due to asynchronous
nature of the internal write, the DQM operation is critical
to avoid unwanted or incomplete writes when the
complete burst write is required. Please refer to DQM
timing diagram also.
PRECHARGE
The precharge is performed on an active bank by
asserting low on clock cycles required between bank
activate and clock cycles required between bank
activate and
CS , RAS , WE and A10/AP with valid
A13~A12 of the bank to be procharged. The precharge
command can be asserted anytime after t
satisfy from the bank active command in the desired
bank. t
RP is defined as the minimum number of clock
cycles required to complete row precharge is calculated
by dividing tRP with clock cycle time and rounding up to
the next higher integer. Care should be taken to make
sure that burst write is completed or DQM is used to
inhibit writing before precharge command is asserted.
The maximum time any bank can be active is specified
RAS (max). Therefore, each bank activate command. At
by t
the end of precharge, the bank enters the idle state and
is ready to be activated again. Entry to power-down,
Auto refresh, Self refresh and Mode register set etc. is
possible only when all banks are in idle state.
CS , CAS
RAS (min) is
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2003
Revision: 1.7 12/44
Page 76
ESMT M12L64164A
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DEVICE OPERATIONS (Continued)
AUTO PRECHARGE
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy t
and CAS latency. The auto precharge command is issued at
the same time as burst write by asserting high on A10/AP,
the bank is precharge command is asserted. Once auto
precharge command is given, no new commands are
possible to that particular bank until the bank achieves idle
state.
BOTH BANKS PRECHARGE
Both banks can be precharged at the same time by using
Precharge all command. Asserting low on CS , RAS , and
WE with high on A10/AP after all banks have satisfied tRAS
(min) requirement, performs precharge on all banks. At the
end of t
state.
AUTO REFRESH
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asserting low on
and
with both banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The
time required to complete the auto refresh operation is
specified by t
required can be calculated by driving t
time and them rounding up to the next higher integer. The
auto refresh command must be followed by NOP’s until the
auto refresh operation is completed. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us or the burst of 4096 auto refresh
cycles in 64ms.
RAS (min) and “tRP” for the programmed burst length
RP after performing precharge all, all banks are in idle
CS , RAS and CAS with high on CKE
WE . The auto refresh command can only be asserted
RFC (min). The minimum number of clock cycles
RFC with clock cycle
SELF REFRESH
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode
for data retention and low power operation of SDRAM.
In self refresh mode, the SDRAM disables the internal
clock and all the input buffers except CKE. The refresh
addressing and timing is internally generated to reduce
power consumption. The self refresh mode is entered
from all banks idle state by asserting low on
RAS , CAS and CKE with high on WE . Once the self
refresh mode is entered, only CKE state being low
matters, all the other inputs including clock are ignored
to remain in the refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed
by NOP’s for a minimum time of t
reaches idle state to begin normal operation. If the
system uses burst auto refresh during normal operation,
it is recommended to use burst 4096 auto refresh cycles
immediately after exiting self refresh.
RFC before the SDRAM
CS ,
Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2003
Revision: 1.7 13/44
Page 77
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Page 78
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SN74LVC157A
QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER
SCAS292G – JANUARY 1993 – REVISED OCTOBER 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Typical V
< 0.8 V at V
D
Typical V
> 2 V at V
D
Inputs Accept Voltages to 5.5 V
D
ESD Protection Exceeds 2000 V Per
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
(Output VOH Undershoot)
OHV
= 3.3 V, TA = 25°C
CC
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
D, DB, OR PW PACKAGE
(TOP VIEW)
A/B
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
V
CC
G
4A
4B
4Y
3A
3B
9
3Y
JESD 17
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
description
This quadruple 2-line to 1-line data selector/multiplexer is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC157A features a common strobe (G
the strobe is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. The device
provides true data.
) input. When the strobe is high, all outputs are low. When
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN74LVC157A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
GA/BAB
HXXXL
LLLX L
LLHX H
LHXL L
LHXH H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
INPUTS
OUTPUT
Y
Copyright 1998, Texas Instruments Incorporated
Page 79
SN74LVC157A
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QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER
SCAS292G – JANUARY 1993 – REVISED OCTOBER 1998
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
15
A/B
1A
1B
2A
2B
3A
3B
4A
4B
G
1
2
3
5
6
11
10
14
13
EN
G1
1
1
MUX
logic diagram (positive logic)
2
1A
3
1B
12
4
1Y
7
2Y
9
3Y
4Y
4
1Y
2A
2B
3A
3B
4A
4B
A/B
5
7
12
2Y
9
3Y
4Y
6
11
10
14
13
15
G
1
Page 80
74VHC04
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Page 80 of 117
Hex Inverte r
74VHC04 Hex Inverter
November 1992
Revised February 2005
General Description
The VHC04 is an advanced high speed CMOS Inverter
fabricated with silicon gate CMOS technology. It achieves
the high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissipation.
The internal circuit is composed of 3 stages including buffer
output, which provide high noise immunity and stabl e output. An input protection circuit ensures that 0V to 7V can be
applied to the input pins witho ut regard to the supply vol tage. This device can be used to interface 5V to 3V systems
and two supply systems such as bat tery back up. This circuit prevents device destruction du e to mismatch ed suppl y
and input voltages.
Surface mount packag es are also available on Tape and Reel. Specify by appen ding the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free pac k age (per JEDEC J-STD-020B). Device available in Tape and Reel only.
The AM5888S is a five-channel BTL driver IC for driving the motors and actuators such as used in DVD player and
consists of two independent precision voltage regulators with adjustable range from 1.5V to 4 V. It supports a
variety of applications. Also, Pb free package is selectable (Please refer to Marking Identification).
Applications
BTL driver for CD, CD-ROM and DVD.
Features
1) Two channels are voltage-type BTL drivers for
actuators of tracking and focus. Two channels are
voltage-type BTL driver for sled and spindle
motors. It is also built-in one channel bi-direction
DC motor driver for tray.
2) Wide dynamic range [9.0V (typ.) when Vcc1=
Vcc2= 12V, at R
3) Separating power of Vcc1 and Vcc2 is to
improve power efficiency by a low supply
voltage for tracking, focus, and spindle.
4) Level shift circuit built-in.
5) Thermal shut down circuit built-in.
6) Mute mode built-in.
7) Dual actuator drivers:
A general purpose input OP provides differential
input for signal addition. The output structure is
two power OPAMPS in bridge configuration.
= 20Ω load].
L
8) Sled motor driver:
A general purpose input OP provides differential
input for signal addition. The output structure is
one power OPAMP in bridge configuration.
9) Spindle driver:
Single input linear BTL driver. The output
structure are two power OPAMPS in bridge
configuration.
10) Tray in-out driver:
The DC motor driver supports forward/reverse
control for tray motor.
11) 2 Built-in regulator controllers
Adjustable range 1.5V ~ 4V
AAMMtteekk SSEEMMIICCOONNDDUUCCTTOORRSS
- 1 -
FFeebb 22000055 VV11..22
Page 82
AM5888S
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Absolute maximum ratings (Ta=25°C)
Motor Driver ICs
Parameter Symbol Limits Unit
Supply voltage
Vcc1
Vcc2
Power dissipation Pd *1.7 W
T
Operate T emp range
Storage Temp range
-35 ~ +85
opr
T
**-55 ~ +150
stg
*When mounted on a 70mm×70mm×1.6mm glass epoxy board.
*Reduced by 13.6mW for each increase in T
**Should not exceed Pd or ASO and T
of 1℃ over 25℃.
a
=150°C values
j
13.5 V
℃
℃
Guaranteed operating conditions (Ta=25°C)
Parameter Symbol Limits Unit
Power supply voltage
Block diagram
MUTEBIASVINTKVINLDGNDVCC2
2827262524232221201918171615
MUTE
+
Thermal
Shut down
25K
-
+
-
10K
Vcc1 4.3 ~ 13.2 V
Vcc2 4.3 ~ Vcc1 V
TRB_2NCNC
10K
-
PGND
+
25K
PGND
GND
10K
-
25K
+
10K
-
+
VCTL
Pre-DRV
Vcc1
15K
-
+
TRAY
DRIVER
VOLD- VOLD+ VOTK- VOTK+
Vcc2
Spindle
Driver(4X)
Sled
Driver(4X)
Actuator
Driver(6x)
Vcc2
Vcc2
Vcc1
Actuator
Driver(6x)
AAMMtteekk SSEEMMIICCOONNDDUUCCTTOORRSS
8910111213141234567
VINSL+VINFC
REGO2TRB_1
REGO1
FWDREV
VCC1
VOTR- VOTR+ VOSL+VOSL- VOFC-VOFC+
- 2 -
FFeebb 22000055 VV11..22
Page 83
AM5888S
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Pin description
PIN No Pin Name Function
1 VINFC Input for focus driver
2 TRB_1 Connect to external transistor base
3 REGO2 Regulator voltage output, connect to external transistor collector
4 VINSL+ Input for the sled driver
5 REGO1 Regulator voltage output, connect to external transistor collector
6 FWD Tray driver forward input
7 REV Tray driver reverse input
8 Vcc1 Vcc for pre-drive block and power block of sled and tray
9 VOTR- Tray driver output (-)
Motor Driver ICs
10 VOTR+ Tray driver output (+)
11 VOSL+ Sled driver output (+)
12 VOSL- Sled driver output (-)
13 VOFC- Focus driver output (-)
14 VOFC+ Focus driver output (+)
15 VOTK+ Tracking driver output (+)
16 VOTK- Tracking driver output (-)
17 VOLD+ Spindle driver output (+)
18 VOLD- Spindle driver output (-)
19 Vcc2 Vcc for power block of spindle, tracking and focus
20 NC No Connection
21 VCTL Speed control input of tray driver
22 GND Ground
23 VINLD Input for spindle driver
24 NC No Connection
25 TRB_2 Connect to external transistor base
26 VINTK Input for tracking driver
27 BIAS Input for reference voltage
28 MUTE Input for mute control
Notes) Symbol of + and – (output of drivers) means polarity to input pin.
(For example, if voltage of pin1 is high, pin14 is high.)
AAMMtteekk SSEEMMIICCOONNDDUUCCTTOORRSS
- 5 -
FFeebb 22000055 VV11..22
Page 84
Features
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• Medium-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (V
• Automotive Temperature Range –40°C to 125°C
• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
= 2.7V to 5.5V)
CC
Two-wire
Automotive
Temperature
Serial EEPROM
1K (128 x 8)
Description
The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial
electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
automotive applications where low-power and low-voltage operation are essential.
The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP, 8-lead
JEDEC SOIC, and 8-lead TSSOP packages and is accessed via a two-wire serial
interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) versions.
8-lead PDIP
Table 1. Pin Configurations
Pin NameFunction
A0 − A2Address Inputs
SDASerial Data
SCLSerial Clock Input
WPWrite Protect
NCNo Connect
GND
A0
A1
A2
GND
1
A0
2
A1
3
A2
4
8-lead SOIC
1
2
3
4
8
VCC
7
WP
6
SCL
5
SDA
VCC
8
WP
7
SCL
6
SDA
5
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
16K (2048 x 8)
AT24C01A
AT24C02
AT24C04
AT24C08A
AT24C16A
A0
A1
A2
GND
8-lead TSSOP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
5092B–SEEPR–9/05
1
Page 85
Absolute Maximum Ratings
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Operating Temperature ......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
*NOTICE:Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
2
AT24C01A/02/04/08A/16A
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or opencollector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device
address inputs that are hard wired for the AT24C01A and the AT24C02. As many as
eight 1K/2K devices may be addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section).
The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K
devices may be addressed on a single bus system. The A0 pin is a no connect.
5092B–SEEPR–9/05
Page 86
AT24C01A/02/04/08A/16A
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The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K
devices may be addressed on a single bus system. The A0 and A1 pins are no
connects.
The AT24C16A does not use the device address pins, which limits the number of
devices on a single bus to one. The A0, A1 and A2 pins are no connects.
WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that
provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to
, the write protection feature is enabled and operates as shown in the following
Memory Organization AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,
the 1K requires a 7-bit data word address for random word addressing.
AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,
the 2K requires an 8-bit data word address for random word addressing.
AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,
the 4K requires a 9-bit data word address for random word addressing.
AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each,
the 8K requires a 10-bit data word address for random word addressing.
AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes
each, the 16K requires an 11-bit data word address for random word addressing.
Page 87
Table 5. AC Characteristics
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Applicable over recommended operating range from T
100 pF (unless otherwise noted)
AT24C01A/02/04/08A/16A
= −40°C to +125°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and
A
AT24C01A/02/04/08A/16A
SymbolParameter
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(2)
Clock Frequency, SCL400kHz
Clock Pulse Width Low1.2µs
Clock Pulse Width High0.6µs
Noise Suppression Time
Clock Low to Data Out Valid0.10.9µs
Time the bus must be free before
a new transmission can start
Start Hold Time0.6µs
Start Set-up Time0.6µs
Data In Hold Time0µs
Data In Set-up Time100ns
Inputs Rise Time
Inputs Fall Time
Stop Set-up Time0.6µs
Data Out Hold Time50ns
Write Cycle Time5ms
5.0V, 25°C, Page Mode1MWrite Cycles
UnitsMinMax
(1)
(2)
(2)
(2)
1.2µs
50ns
300ns
300ns
Note:1. This parameter is characterized and is not 100% tested (TA = 25°C).
2. This parameter is characterized.
Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see to
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see to Figure 5 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has received
each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode
which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the
completion of any internal operations.
Page 88
BH7862FS
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Multimedia ICs
High-performance 6-channel video driver
IC for progressive DVD
BH7862FS
BH7862FS is a 6-channel video driver IC developed for progressive DVD player/recorder. Special filters adjusted to each
band of various video signals are incorporated into a single chip. Extended definition, size reduction, and high cost
performance can be achieved in DVD players.
!!!!Application
DVD players, DVD recorders
!!!!Features
1) Each high-performance filter, 6dB amplifier, and 75Ω driver for DVD are incorporated into a single chip.
2) Driver 6ch (Y, C, MIX, and PY, Pb, Pr for progressive)
3) Group delay difference between chroma signal and luminance signal is a small number of nsec.
4) Drive 2 lines of each signal
5) Operating by 5V single power supply
6) Built-in mute circuit
!!!!Absolute maximum ratings (Ta = 25°C)
ParameterSymbolLimitsUnit
Impressed voltage
Power dissipation
Operating temperature range
Storage temperature range
∗ Reduced by −7.6mW for each increase in Ta of 1°C over 25°C.
PCB (70mm×70mm, t=1.6mm) glass epoxy mounting.
!!!!Recommended operating conditions (Ta = 25°C)
Parameter
Power supply voltage
Radiation resistance is not included in the design.
VCC max
Pd
Topr
Tstg
SymbolUnitMax.Typ.Min.
CC
V
4.5−5.5
6.0V
∗
0.95
−10~+70
−55~+150
W
°C
°C
V
1/9
Page 89
Multimedia ICs
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Page 89 of 117
!!!!Block diagram
BH7862FS
MUTE1
CIN
GND
YIN
V
GND
PYIN
GND
PYTRAP
V
PbIN
GND
1
75Ω6dB
2
3
MUTE1TEST
20k
1.5-6M
BPF
75Ω6dB
4
5
6
CC
7
8
6M
LPF
CLAMP
CLAMP
12M
LPF
75Ω6dB
9
10
CC
11
12
20k
6M
LPF
75Ω6dB
13
32
31
30
29
28
27
26
25
24
23
22
21
20
COUTCTRAP
TEST
MIXOUT
MIXFB
GND
YTRAP
GND
YOUT
YFB
GND
PYOUT
PYFB
GND
PrIN
MUTE2
PrTRAP
14
15
16
20k
MUTE2
6M
LPF
75Ω6dB
75Ω6dB
19
18
17
PbOUT
N.C.
PrOUT
Page 90
SEMICONDUCTOR
TECHNICAL DATA
THREE TERMINAL POSITIVE VOLTAGE REGULATORS
5V, 6V, 8V, 9V, 10V, 12V, 15V, 18V, 20V, 24V.
FEATURES
Suitable for C-MOS, TTL, the Other Digital IC's Power Supply.
Internal Thermal Overload Protection.
Internal Short Circuit Current Limiting.
Output Current in Excess of 1A.
Satisfies IEC-65 Specification. (International Electronical Commission)
MAXIMUM RATINGS (Ta=25 )
KIA7805API~
KIA7824API
BIPOLAR LINEAR INTEGRATED CIRCUIT
CHARACTERISTICSYMBOLRATINGUNIT
Input Voltage
KIA7805API
KIA7815API
V
IN
35
V
KIA7818API
KIA7824API
40
Power Dissipation (Tc=25 )
P
D
20.8W
Power Dissipation
(Without Heatsink)
KIA7805API
KIA7824API
P
D
2.0W
Operating Junction Temperature
T
j
-30 150
Storage Temperature
T
stg
-55 150
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A
U
E
L
K
D
N
T
O
1
F
B
G
L
M
J
D
N
T
3
2
Q
TO-220IS
P
S
T
1. INPUT
2. COMMON
3. OUTPUT
C
DIM MILLIMETERS
A
B
C
D
E
F
G12.30 MAX
R
J
K
L
M
V
N
O
P
Q
R
H
S
T
U
10.30 MAX
15.30 MAX
2.70Ź0.30
0.85 MAX
Φ3.20Ź0.20
3.00Ź0.30
0.75 MAXH
13.60Ź0.50
3.90 MAX
1.20
1.30
2.54
4.50Ź0.20
6.80
2.60Ź0.20
10Ɓ
25Ş
5Ş
0.5
2.60Ź0.15V
Page 91
THREE TERMINAL POSITIVE VOLTAGE REGULATORS
5V, 6V, 8V, 9V, 10V, 12V, 15V, 18V, 20V, 24V.
FEATURES
Best Suited to a Power Supply for TTL and CMOS.
Built-in Overcurrent Protective Circuit.
Built-in Thermal Protective Circuit.
Max. Output Current 150mA (Tj=25 ).
Packaged in TO-92L.
MAXIMUM RATINGS (Ta=25 )
KIA79L05BP~
KIA79L24BP
BIPOLAR LINEAR INTEGRATED CIRCUIT
EQUIVALENT CIRCUIT
CHARACTERISTICSYMBOLRATINGUNIT
Input Voltage
KIA79L05BP
KIA79L15BP
V
IN
-35
V
KIA79L18BP
KIA79L24BP
-40
Power Dissipation (Tc=25 )
P
D
800mW
Operating Junction Temperature
T
j
-30 150
Operating Temperature
T
opr
-30 75
Storage temperature
T
stg
-55 150
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B
D
P
DEPTH:0.2
C
Q
FF
HH
E
M
123
O
A
G
K
J
M
H
NN
1. COMMON
2. INPUT
3. OUTPUT
R
D
L
DIM MILLIMETERS
A
B
C
S
D
E
F
G
H
J
K
H
L
M
N
O
P
Q
7.20 MAX
5.20 MAX
0.60 MAX
2.50 MAX
1.15 MAX
1.27
1.70 MAX
0.55 MAX
_
+
14.00 0.50
0.35 MIN
_
+
0.75 0.10
4
25
1.25
Φ1.50
0.10 MAX
_
12.50 0.50R
+
1.00S
TO-92L
R
1
R
10
Q
19
Q
1
R
Z
1
2
R
3
GND
(1)
R
9
R
5
Q
2
R
6
Q
4
Q
3
R
4
R
Q
5
7
R
8
R
11
Q
6
R
10
Q
Q
9
R
12
Q
8
R
17
7
Q
10
Q
11
Q
12
R
18
OUTPUT
(3)
R
20
C
Q
1
13
Q
14
R
R
13
14
Q
16
Q
15
Q
17
Q
18
R
15
R
16
INPUT
(2)
Page 92
Optic receiver modules
harman/kardon
Service manual DVD37EU
Page 92 of 117
KSM-60 T H 2·KSM-70 T H 2
K O D E N S H I
The KSM-60TH2 consist of a PIN Photodiode of
high speed and a preamplifier IC in the package as an
receiver for Infrared remote control systems
F E A T U R E S
•One mold small package
•5 Volt supply voltage, low power consumption
•Shielded against electrical field disturbance
•High immunity against ambient light
•Easy interface with the main board
•TTL and CMOS compatibility
A P P L I C A T I O N S
•TV, VTR, Acoustic Devices, Air Conditioners, Car
Stereo Units, Computers, Interior controlling
appliances, and all appliances that require remote
c o n t r o l l i n g
R a t i n gS y m b o lP a r a m e t e r
5 . 5
- 1 0 ~ + 6 0
- 2 0 ~ + 7 5
( T a = 2 5℃U n l e s s
otherwise noted)
U n i t
MAXIMUM RATINGS
Supply Voltage
Operating Temperature
Storage Temperature
Soldering Temperature
C C
V
T o p r .
T s t g .
T s o l .
260(Max 5 sec)
D I M E N S I O N S
B.P.F CENTER FREQUENCY
V
℃
℃
℃
K S M -◯◯1 TH2
K S M -◯◯2 TH2
K S M -◯◯3 TH2
K S M -◯◯4 TH2
K S M -◯◯5 TH2
(Unit : mm)
N O T E
PIN configuration
6 0T H 2 7 0T H 2
① V o u tV o u t
② G N DV c c
③ V c cG N D
B.P.F Center Frequency(kHz)Model NO.
4 0 . 0
3 6 . 7
3 7 . 9
3 2 . 7
5 6 . 9
ELECTRO-OPTICAL CHARACTERISTICS
P a r a m e t e rT y p .
Supply Voltage
Current Consumption
Peak Wavelength *1
B.P.F Center Frequency
Transmission Distance *1
H Level Output Voltage *1
L Level Output Voltage *1
H Level Output Pulse Width *1
L Level Output Pulse Width *1
Output Form
Note : *1. It specifies the maximum distance between emitter and detector that the output waveform satisfies the standard under the conditions below against the standard
t r a n s m i t t e r
1) Measuring place : Indoor without extreme reflection of light
2) Ambient light source : Detecting surface illumination shall be irradiate 200±50lx under ordinary white fluorescence lamp without high frequency lightning
3) Standard transmitter : Burst wave of standard transmitter shall be arranged to 50mVp-p under the measuring circuit
( T a = 2 5℃), Vcc=5.0V
S y m b o lC o n d i t i o n sM i n .M a x .U n i t .
V
I
λp
f o
V
V
T
T
C C
C C
L
O H
O L
W H
W L
Input Signal=0
2 0 0±50l x
30cm over the ray
Burst Wave=600μs
P e r i o d = 1 . 2㎳
0°
±3 0°
a x i s
4 . 5
-
-
-
1 0
7
4 . 5
5 0 0
5 0 0
Active Low Output
5 . 0
1 . 2
9 4 0
3 7 . 9
-
5 . 0
0 . 1
6 0 0
6 0 0
5 . 5
2 . 5
-
-
-
-
-
0 . 5
7 0 0
7 0 0
V
m A
n m
k H z
m
m
V
V
μs
μs
Page 93
harman/kardon
Service manual DVD37EU
Page 93 of 117
Page 94
LM1117/LM1117I
harman/kardon
Service manual DVD37EU
Page 94 of 117
800mA Low-Dropout Linear Regulator
LM1117/LM1117I 800mA Low-Dropout Linear Regulator
October 2002
General Description
The LM1117 is a series of low dropout voltage regulators
with a dropout of 1.2V at 800mA of load current. It has the
same pin-out as National Semiconductor’s industry standard
LM317.
The LM1117 is available in an adjustable version, which can
set the output voltage from 1.25V to 13.8V with only two
external resistors. In addition, it is also available in five fixed
voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V.
The LM1117 offers current limiting and thermal shutdown. Its
circuit includes a zener trimmed bandgap reference to assure output voltage accuracy to within
The LM1117 series is available in LLP, TO-263, SOT-223,
TO-220, and TO-252 D-PAK packages. A minimum of 10µF
tantalum capacitor is required at the output to improve the
transient response and stability.
±
1%.
Typical Application
Active Terminator for SCSI-2 Bus
Features
n Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable
Versions
n Space Saving SOT-223 and LLP Packages
n Current Limiting and Thermal Protection
n Output Current800mA
n Line Regulation0.2% (Max)
n Load Regulation0.4% (Max)
n Temperature Range
— LM11170˚C to 125˚C
— LM1117I−40˚C to 125˚C
Applications
n 2.85V Model for SCSI-2 Active Termination
n Post Regulator for Switching DC/DC Converter
n High Efficiency Linear Regulators
n Battery Charger
n Battery Powered Instrumentation
10091905
Fixed Output Regulator
10091928
Page 95
Block Diagram
harman/kardon
Service manual DVD37EU
Page 95 of 117
LM1117/LM1117I
Connection Diagrams
SOT-223
Top View
TO-220
Top View
TO-252
Top View
10091904
10091938
10091901
TO-263
10091944
Top View
10091945
Side View
LLP
10091902
10091946
When using the LLP package
Pins 2,3&4must be connected together and
Pins 5,6&7must be connected together
Top View
Page 96
FEATURES SUMMARY
harman/kardon
Service manual DVD37EU
Page 96 of 117
■SUPPLY VOLTAGE
–V
2.7V to 3.6V for Program, Erase
CC =
and Read
■ACCESS TIMES: 70, 90ns
■PROGRAMMING TIME
–10µs per Byte/Word typical
■35 MEMORY BLOCKS
–1 Boot Block (Top or Bottom Location)
–2 Parameter and 32 Main Blocks
The M29W160E is a 16 Mbit (2Mb x8 or 1Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V)
supply. On power-up th e memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to pres erve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase com m ands are wri tten to the Command Interface of t he memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
The end of a program or erase operation can be
detected and any error conditions identified. The
Figure 2. Logic DiagramTable 1. Signal Names
command set required to control the memory is
consistent with JEDEC standards.
The blocks in the memory are asymmetrically arranged, see Figures 5 and 6, Block Addresses.
The first or last 64 KBytes have been divided into
four additional blocks. The 16 KByte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 KByte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple conne ction to most m icroprocessors, often without additional logic.
The memory is offered TSOP48 (12 x 20mm) and
TFBGA48 (0.8mm pitch) packages. The memory
is supplied with all the bits erased (set to ’1’).
A0-A19
W
RP
BYTE
A0-A19Address Inputs
V
CC
20
E
G
M29W160ET
M29W160EB
V
SS
15
DQ0-DQ14
DQ15A–1
RB
AI06849B
DQ0-DQ7Data Inputs/Outputs
DQ8-DQ14Data Inputs/Outputs
DQ15A–1Data Input/Output or Address Input
E
G
W
RP
RB
BYTE
V
RAM (stack) - bytes1024 (256)512 (256)384 (256)512 (256)384 (256)
Voltage Range 2.85 to 3.6V
Temp. Range up to -40°C to +85°C
PackagesTQFP44 10x10, SDIP32, TQFP32 7x7
Flash 32KFlash 16KFlash 8KROM 16KROM 8K
TQFP32
7 x 7
SDIP32
400 mil
Rev. 3
1
Page 100
ST72F324L, ST72324BL
harman/kardon
Service manual DVD37EU
Page 100 of 117
1 INTRODUCTION
The ST72F324L and ST72324BL devices are
members of the ST7 microcontroller family designed for the 3V operating range. They can be
grouped as follows:
– The 32-pin devices are designed for mid-range
applications
– The 44-pin devices target the same range of ap-
plications requiring more than 24 I/O ports.
All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruc-
Figure 1. Device Block Diagram
8-BIT CORE
ALU
RESET
V
PP
V
SS
V
DD
OSC1
OSC2
PF7:6,4,2:0
(6 bits on J devices)
(5 bits on K devices)
CONTROL
OSC
MCC/RTC/BEEP
PORT F
TIMER A
BEEP
tion set and are available with FLASH or ROM program memory.
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or stand-by state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes.
PROGRAM
MEMORY
(8K - 60K Bytes)
RAM
(384 - 2048 Bytes)
WATCHDOG
ADDRESS AND DATA BUS
PORT A
PORT B
PA7:3
(5 bits on J devices)
(4 bits on K devices)
PB4:0
(5 bits on J devices)
(3 bits on K devices)
(6 bits on J devices)
(2 bits on K devices)
PE1:0
(2 bits)
PD5:0
V
AREF
V
SSA
PORT E
SCI
PORT D
10-BIT ADC
PORT C
TIMER B
SPI
PC7:0
(8 bits)
3
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