Freescale MCF5253 DATA SHEET
Freescale Semiconductor
Data Sheet: Technical Data
MCF5253 ColdFire®
Document Number: MCF5253DS
Rev. 2, 03/2007
MCF5253
Package Information
MAPBGA–225
Microprocessor Data
Sheet
1 Introduction
This document provides an overview of the MCF5253
ColdFire processor and general descriptions of the
MCF5253 features and modules. Also provided are
electrical specifications, pin assignments, and package
diagrams for MCF5253 ColdFire® processor. For
functional characteristics, refer to the MCF5253
Reference Manual (MCF5253RM).
The MCF5253 is a general purpose system controller
with over 125 Dhrystone 2.1 MIPS @ 140 MHz
performance. The integrated peripherals and EMAC
allow the MCF5253 to replace both the microcontroller
and the DSP in certain applications. Most peripheral pins
can also be remapped as general purpose I/O pins.
Ordering Information: See Table 1 on page 2
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Orderable Part Numbers . . . . . . . . . . . . . . 2
1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 3
2 Functional Description . . . . . . . . . . . . . . . . . . . 4
2.1 Version 2 ColdFire Core . . . . . . . . . . . . . . . 4
2.2 Module Inventory . . . . . . . . . . . . . . . . . . . . 4
3 Signal Description . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical Specifications . . . . . . . . . . . . . . . . . 11
4.1 SDRAM Bus Timing . . . . . . . . . . . . . . . . . 14
4.2 SPDIF Timing . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Serial Audio Interface Timing . . . . . . . . . . 16
4.4 DDATA/PST/PSTCLK Debug Interface . . 16
4.5 BDM and JTAG Timing . . . . . . . . . . . . . . 16
5 Package Information and Pinout . . . . . . . . . . 18
5.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . 18
5.2 Package Drawing . . . . . . . . . . . . . . . . . . . 24
6 Product Documentation . . . . . . . . . . . . . . . . . 31
6.1 Revision History . . . . . . . . . . . . . . . . . . . . 31
Low power features include flexible PLL (with
power-down mode) with dynamic clock switching, a
hardwired CD ROM decoder, advanced 0.13 µm CMOS
process technology, 1.2 V core power supply, and
on-chip 128K-byte SRAM.
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Introduction
For additional information regarding software drivers and applications, refer to
http://www.freescale.com/coldfire.
1.1 Orderable Part Numbers
Table 1 lists the orderable part numbers for the MCF5253 processor.
Table 1. Orderable Part Numbers
Orderable Part
Number
MCF5253VM140 140 MHz 225 MAPBGA -20 to +70°C Lead free
Maximum Clock
Frequency
Package Type
Operating Temperature
Range
Part Status
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 2
2 Freescale Semiconductor
1.2 Block Diagram
Figure 1 illustrates the functional block diagram of the MCF5253 processor.
Introduction
Instruction
8K
Cache
64K
KRAM1
64K
KRAM0
“Backdoor” Interface
FlexCAN Pins
Debug
Module
with JTAG
ColdFire
CF2 Core
140 MHz
2x FlexCAN
Controller
Standard ColdFire Peripheral Blocks
Timer
I2C
5x08
DMA
5x08
Arbiter
Translator
UART (3)
5x08
Interrupt
E-bus
SDRAM
Interface
E-bus
Interrupt
Controller
MUX
SmartMedia
Timer Pins
I2C Pins
UART P ins
SDRAM
SRAM
IDE
BUFENB1
BUFENB
IDE
IDE_DIOW
IDE_IORDY
2
_DIOR
CRIN/CROUT Pins
RTC Pins
16 Kbyte
SRAM
Clock
PLL
XTAL
Oscillator
Real-Time
Clock
ARB
DMA
SPI
Interface
Audio
Interfaces
AD
Logic
Memory Stick/SD
Interface
USB 2.0
OTG Controller
ATA
Controller
USB
PHY
USB XTAL
Oscillator
Figure 1. MCF5253 Block Diagram
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 2
SPI Pins
Audio Interface
Pins
AD IN Pins
FlashMedia
Pins
USB Analog
USB XTAL Pins
ATA Pins
Freescale Semiconductor 3
Functional Description
2 Functional Description
2.1 Version 2 ColdFire Core
The V ersion 2 ColdFire (CF2) core consists of two independent, decoupled pipeline structures to maximize
performance while minimizing core size. The instruction fetch pipeline (IFP) is a two-stage pipeline for
prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand
execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then executes
the required function.
2.2 Module Inventory
Table 2 shows an alphabetical listing of the modules in the processor.
Table 2. Digital and Analog Modules
Block
Mnemonic
ATA Advanced Technology
ADC Battery Level/Keypad
AB Audio Bus Audio
AIM Audio Interface Audio
BROM Bootloader Boot ROM The MCF5253 incorporates a ROM Bootloader, which enables booting
FlexCAN Twin Controller Area
CSM Chip Select Module Connectivity
DMAC Direct Memory
Block Name
Attachment Controller
Analog/Digital
Converter
Network 2.0B
Communication Unit
Access Controller
Module
Functional
Grouping
Connectivity
Peripheral
Analog Input The six-channel ADC is based on the Sigma-Delta concept with 12-bit
Interface
Interface
Connectivity
Peripheral
Peripheral
Connectivity
Peripheral
The ATA block is an AT attachment host interface. Its main use is to
interface with IDE hard disc drives and ATAPI optical disc drives.
resolution. Both the analog comparator and digital sections are integrated
in the MCF5253.
The audio interfaces connect to an internal bus that carries all audio data.
Each receiver places its received data on the audio bus and each
transmitter takes data from the audio bus for transmission.
The audio interface module provides the necessary input and output
features to receive and transmit digital audio signals over serial audio
interfaces (IIS/EIAJ) and over digital audio interfaces (IEC958).
from UART, I2C, SPI, or IDE devices.
The FlexCan module is a full implementation of the Bosch CAN protocol
specification 2.0B, which supports both standard and extended message
frames.
Three programmable chip-select outputs (CS0
provide signals that enable glueless connection to external memory and
peripheral circuits.
There are four fully programmable DMA channels for quick data transfer.
Brief Description
/CS4, CS1, and CS2)
eMAC enhanced Multiply
Accumulate Module
MBUS Memory Bus Interface Bus Operation The bus interface controller transfers data between the ColdFire core or
MMC/SD Multimedia
Card/Secure Digital
Interface
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 2
4 Freescale Semiconductor
Core The integrated eMAC unit provides a common set of DSP operations and
enhances the integer multiply instructions in the ColdFire architecture.
DMA and memory, peripherals, or other devices on the external bus.
Flash Memory
Card Interface
The interface is Sony® Memory Stick®, SecureDigital, and Multi-Media
card compatible.
Note: The Sony Memory Interface does not support Sony MagicGate™.
Table 2. Digital and Analog Modules (continued)
Functional Description
Block
Mnemonic
Block Name
GPIO General Purpose I/O
Interface
GPT General Timer
Module
IDE Integrated Drive
Electronics
Functional
Grouping
System
integration
Timer
peripheral
Connectivity
peripheral
Brief Description
GPIO signals are multiplexed with various other signals.
The timer module includes two general-purpose timers, each of which
contains a free-running 16-bit timer.
The IDE hardware consists of bus buffers for address and data and are
intended to reduce the load on the bus and prevent SDRAM and Flash
accesses from propagating to the IDE bus.
INC Instruction Cache Core The instruction cache improves system performance by providing cached
instructions to the execution unit in a single clock cycle.
2
C Inter IC
I
Communication
Module
SRAM Internal 128-KB
SRAM
LIN Internal Voltage
Regulator
Connectivity
peripheral
Internal
memory
Linear
regulator
The two-wire I2C bus interfaces, compliant with the Philips I2C bus
standard, are bidirectional serial buses that exchange data between
devices.
The 128-Kbyte on-chip SRAM is split over two banks, SRAM0 (64K) and
SRAM1 (64K). It provides single clock-cycle access for the ColdFire core.
An internal 1.2 V regulator is used to supply the CPU and PLL sections of
the MCF5253, reducing the number of external components required and
allowing operation from a single supply rail, typically 3.3 volts.
JTAG Joint Test Action
Group
Test and
debug
To help with system diagnostics and manufacturing testing, the MCF5253
includes dedicated user-accessible test logic that complies with the IEEE
1149.1A standard for boundary scan testability, often referred to as Joint
Test Action Group, or JTAG.
QSPI Queued Serial
Peripheral Interface
Connectivity
Interface
RTC Real-Time Clock Timer
Peripheral
BDM Background Debug
Interface
SDRAMC Synchronous DRAM
Memory Controller
SIM System Integration
Module
PLL System Oscillator and
Phase Lock Loop
Test and
debug
Peripheral
Interface
System
Integration
System
Clocking
The QSPI module provides a serial peripheral interface with queued
transfer capability.
The RTC is a clock that keeps track of the current time even if the clock is
turned off.
A background-debug mode (BDM) interface provides system debug.
The SDRAM controller provides a glueless interface for one bank of
SDRAM, and can address up to 32MB. The controller supports a 16-bit
data bus. The controller operates in page mode, non-page mode, and
burst-page mode and supports SDRAMs.
The SIM provides overall control of the internal and external buses and
serves as the interface between the ColdFire core and the internal
peripherals or external devices. The SIM is responsible for the two
interrupt controllers (setting priorities and levels). And it also configures
the GPIO ports.
The oscillator operates from an external crystal connected across CRIN
and CROUT. The circuit can also operate from an external clock
connected to CRIN. The on-chip programmable PLL, which generates the
processor clock, allows the use of almost any low frequency external clock
(5–35 MHz).
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 2
Freescale Semiconductor 5
Signal Description
UART Universal
Asynchronous
Receiver
/Transmitter Module
USBOTG USB 2.0 High-Speed
On-The-Go
Connectivity
Peripheral
Connectivity
Peripheral
Three UARTs handle asynchronous serial communication.
The USB module is used for communication to a PC or communication to
slave devices; for example, to download data from a hard disc player to a
flash player, and to other devices.
3 Signal Description
This chapter describes the MCF5253 input and output signals. The signal descriptions as shown in Table 3
are grouped according to relevant functionality. For additional signal information, see “Chapter 2, Signal
Description” in the MCF5253 reference manual.
Table 3. MCF5253 Signal Index
Signal Name Mnemonic Function
Address A[24:1]
A[23]/GPO54
Read-write control RW Bus write enable—indicates if read
24 address lines—address 23 is
multiplexed with GPO54 and
address 24 is multiplexed with A20
(SDRAM access only).
or write cycle in progress.
Input/
Output
Out X
Out H
Reset
State
Output enable OE
Output enable for asynchronous
memorier TD-0.6(e5(e7(tc25)5.h(.)-4.8pus l6(es(.)]TJ18.1133 1.67 TD-0.0604 Tc0 Tw[(Out230m)4.n(l)-6.6ga(l)-6.te(l)-6.d(H)]TJ-47.3133 -3.67 TD-0.0025 Tc0.3005 TwData(l909)12.D[31:16]or)-23012.Data 4(b)2211()221 is uson)-5.7( )6.7(ttrmm)1)85non f3r l17158[(/[(Out261012.Hi-Zs )]TJ0267 TD-0.0019 Tc0.0039 TwSasynchrotp)-5.9s r do
addre sontbe1]
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 2
6 Freescale Semiconductor
Out230mlllH
SDMo
Signal Description
ISA bus read strobe IDE_DIOR/GPIO31
(CS2)
ISA bus write strobe IDE_DIOW/GPIO32
)
(CS2
1 ISA bus read strobe and 1 ISA bus
write strobe—allow connection of an
independent ISA bus peripheral,
such as an IDE slave device.
ISA bus wait signal IDE_IORDY/GPIO33 ISA bus wait line available for both
busses
Chip Selects[2:0] CS0/CS4
CS1/QSPICS3/GPIO28
Chip selects bits 2 through 0—
enable peripherals at programmed
addresses. C
S0 provides boot ROM
selection.
Buffer enable 1 BUFENB1/GPIO29 Two programmable buffer
In/Out –
In/Out –
In/Out –
Out
negated
In/Out
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 2
Freescale Semiconductor 7
Signal Description
Table 3. MCF5253 Signal Index (continued)
Signal Name Mnemonic Function
Serial data out SDATAO1/TOUT0/GPIO18
SDATAO2/GPIO34
Word clock LRCK1/GPIO19
Audio interfaces to serial data
outputs
Audio interfaces to serial word clocks In/Out –
Input/
Output
In/Out
Out
Reset
State
LRCK2/GPIO23
LRCK3/AUDIOCLOCK/GPIO43
Bit clock SCLK1/GPIO20
Audio interfaces to serial bit clocks In/Out –
SCLK2/GPIO22
SCLK3/GPIO35
Serial input EF/RXD2/GPIO6 Error flag serial in In/Out –
Serial input CFLG/GPIO5 C-flag serial in In/Out –
Subcode clock RCK/QSPIDIN/QSPIDOUT/
Audio interfaces to subcode clock In/Out –
GPIO26
Subcode sync QSPIDOUT/SFSY/GPIO27 Audio interfaces to subcode sync In/Out –
Subcode data QSPICLK/SUBR/GPIO25 Audio interfaces to subcode data In/Out –
Clock frequency trim XTRIM/TXD2/GPIO0 Clock trim control Out –
Audio clocks out MCLK1/GPIO11
DAC output clocks Out –
QSPICS2/MCLK2/GPIO24
Audio clock in LRCK3/AUDIOCLOCK/GPIO43 Optional audio clock input –
–
MemoryStick/
SecureDigital interface
EBUIN3/CMD_SDIO2/GPIO14 Secure Digital command lane—
In/Out –
MemoryStick interface 2 data I/O
EBUIN2/SCLKOUT/GPIO13 Clock out for both MemoryStick
In/Out –
interfaces and for Secure Digital
DDATA0/CTS1
/SDATA0_SDIO1/GPIO1 SecureDigital serial data bit 0—
In/Out –
MemoryStick interface 1 data I/O
SCL0/SDATA1_BS1/GPIO41 SecureDigital serial data bit 1—
In/Out –
MemoryStick interface 1 strobe
DDATA1/RTS1
/SDATA2_BS2/GPIO2 SecureDigital serial data bit 2—
In/Out –
MemoryStick interface 2 strobe
Reset output signal
SDA0/SDATA3/GPIO42 SecureDigital serial data bit 3 In/Out –
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 2
8 Freescale Semiconductor
Table 3. MCF5253 Signal Index (continued)
Signal Description
Signal Name Mnemonic Function
AT attachment interface
(IDE interface)
ATA_DIOW ATA write strobe signal Out –
ATA_DIOR ATA read strobe signal Out –
Input/
Output
Reset
State
ATA_IORDY ATA I/O ready input In –
ATA_DMARQ ATA DMA request In –
ATA_DMACK ATA DMA acknowledge Out –
ATA_INTRQ ATA interrupt request In –
ATA_CS0 ATA chip select 0 Out –
ATA_CS1 ATA chip select 1 Out –
ATA_A[2:0] 3-bit ATA address bus Out –
ATA_D[15:0] 16-bit ATA data bus In/Out –
CAN interface CAN0_TX CAN 0 transmit Out –
CAN0_RX CAN 0 receive In –
CAN1_TX CAN 1 transmit Out –
CAN1_RX CAN 1 receive In –
USB PHY interface USBVBUS USB Vbus input In –
USBID USB ID input In –
USBRES USB current programming resistor
Analog –
pin
USBDN USB DM signalling line In/Out –
USBDP USB DP signalling line In/Out –
USB oscillator USB_CRIN
USB_CROUT
RTC oscillator RTC_CRIN
RTCCROUT
AD IN ADIN0/GPI52
ADIN1/GPI53
Connections for USB oscillator
crystal (24 MHz)
Connections for real-time clock
crystal (32.768 kHz)
Analog-to-Digital Converter input
signals
In
Out
In
Out
In –
ADIN2/GPI54
ADIN3/GPI55
ADIN4/GPI56
ADIN5/GPI57
AD OUT ADREF
ADOUT/SCLK4/GPIO58
Analog-to-Digital Converter output
signal—connects to ADREF via
In/Out –
integrator network.
QSPI clock QSPICLK/SUBR/GPIO25 QSPI clock signal In/Out –
QSPI data in RCK/QSPIDIN/QSPIDOUT/GPIO26 QSPI data input In/Out –
–
–
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 2
Freescale Semiconductor 9
Signal Description
Table 3. MCF5253 Signal Index (continued)
Signal Name Mnemonic Function
QSPI data out RCK/QSPIDIN/QSPIDOUT/GPIO26
QSPI data out In/Out –
Input/
Output
Reset
State
QSPIDOUT/SFSY/GPIO27
QSPI chip selects QSPICS0/EBUIN4/GPIO15
QSPI chip selects In/Out –
QSPICS1/EBUOUT2/GPIO16
QSPICS2/MCLK2/GPIO24
CS1/QSPICS3/GPIO28
System oscillator in CRIN System input In –
System oscillator out CROUT System output Out –
Reset In RSTI Processor reset input In –
Freescale Test Mode TEST[2:0] TEST pins. In –
Linear regulator output LINOUT Output of 1.2 V to supply core Out –
Linear regulator input LININ Input, typically I/O supply (3.3V) In –
Linear regulator ground LINGND –
High Impedance HI_Z Assertion tri-states output signal pins In
Debug Data DDATA0/CTS1/SDATA0_SDIO1/GPIO1
DDATA1/RTS1
/SDATA2_BS2/GPIO2
Display of captured processor data
and break-point statuses
In/Out Hi-Z
DDATA2/CTS0/GPIO3
DDATA3/RTS0/GPIO4
Processor Status PST0/GPIO50
PST1/GPIO49
Indication of internal processor
status.
In/Out Hi-Z
PST2/INTMON2/GPIO48
PST3/INTMON1/GPIO47
Processor clock PSTCLK/GPIO51 Processor clock output Out –
Test Clock TCK Clock signal for IEEE 1149.1A JTAG In –
Test Reset/
Development Serial
Clock
DSCLK/TRST
Multiplexed signal that is
asynchronous reset for JTAG
controller. Also, clock input for debug
In –
module.
Test Mode Select/Break
Point
TMS/BKPT
Multiplexed signal that is test mode
select in JTAG mode and a hardware
In –
break-point in debug mode
Test Data Input/
Development Serial
TDI/DSI Multiplexed serial input for the JTAG
or background debug module.
In –
Input
Test Data
Output/Development
TDO/DSO Multiplexed serial output for the
JTAG or background debug module
Out –
Serial Output
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 2
10 Freescale Semiconductor
Loading...