Fintek F81216 Schematics

F81216D

LPC to 4 UART Datasheet

Release Date: July, 2004

Version: V0.26P

F81216D July, 2004

V0.26P

F81216D Datasheet Revision History

Version Date Page Revision History

0.22P 2003/07/22

0.23P 2003/07/31 14 Updated WDT enable timer as power-on setting

48MHz clock input : 5 sec

0.24P 2003/09/12 3 Updated pin description(CLKIN: pin12)

0.25P 2003/09/16 32 Updated Application circuit

F81216D

24MHz clock input : 10 sec

0.26P 2004/7/29 3 Revised pin 2 description

Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunctio n of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from

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such improper use or sales.

Table of Content

F81216D

1. General Description

2. Feature List................................................................................................................................................1

3. Pin Configuration........................................................................................................................................2

4. Pin Description ...........................................................................................................................................3

4.1 ISA/LPC Interface..................................................................................................................................................3

4.2 UART Interface......................................................................................................................................................4

4.3 Power ....................................................................................................................................................................7

5. Functional Description

5.1 LPC Interface......................................................................................................................................................8

5.2 UART ..................................................................................................................................................................8

5.2.1 UART Port Register...................................................................................................................................9

5.3 IR Function........................................................................................................................................................13

5.4 Watch Dog Timer Function...............................................................................................................................14

5.4.1 Watchdog Port Register........................................................................................................................14

5.5 Serial IRQ .........................................................................................................................................................15

5.5.1 Start Frame..............................................................................................................................................15

5.5.2 IRQ/Data Frame ......................................................................................................................................15

....................................................................................................................................1

.................................................................................................................................8

5.5.3 Stop Frame..............................................................................................................................................16

Register Description..................................................................................................................................17

6.1 Global Control Register ....................................................................................................................................19

6.1.1 Software Reset Register – index 02h......................................................................................................19

6.1.2 Logic Device Select Register – index 07h...............................................................................................19

6.1.3 Device ID Register– index 20h, 21h........................................................................................................19

6.1.4 Device Reversion Register– index 22h ...................................................................................................20

6.1.5 Vendor ID Register– index 23h, 24h........................................................................................................20

6.1.6 Clock Source Select Register – index 25h..............................................................................................20

6.1.8 Test Mode Register – index 2Fh..............................................................................................................20

6.2 UART 1 Device Control Register (LDN 0)...........................................................................................................21

6.2.1 Device Enable Register – index 30h...............................................................................................21

6.2.2 I/O Port Select Register – index 60h...............................................................................................21

6.2.3 I/O Port Select Register – index 61h...............................................................................................21

6.2.4 IRQ Channel Select Register – index 70h ............................................................................................21

6.2.5 UART 1 Clock Select Register – index F0h..........................................................................................22

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F81216D

6.2.6 IR1 Control Register – index F1h..........................................................................................................22

6.3 UART 2 Device Control Register (LDN 1)...........................................................................................................23

6.3.1 Device Enable Register – index 30h...............................................................................................23

6.3.2 I/O Port Select Register – index 60h...............................................................................................23

6.3.3 I/O Port Select Register – index 61h...............................................................................................23

6.3.4 IRQ Channel Select Register – index 70h ............................................................................................23

6.3.5 UART 2 Clock Select Register – index F0h..........................................................................................24

6.4 UART 3 Device Control Register (LDN 2)...........................................................................................................24

6.4.1 Device Enable Register – index 30h...............................................................................................24

6.4.2 I/O Port Select Register – index 60h...............................................................................................24

6.4.3 I/O Port Select Register – index 61h...............................................................................................24

6.4.4 IRQ Channel Select Register – index 70h ............................................................................................25

6.4.5 UART 3 Clock Select Register – index F0h..........................................................................................25

6.5 UART 4 Device Control Register (LDN 3)...........................................................................................................25

6.5.1 Device Enable Register – index 30h...............................................................................................25

6.5.2 I/O Port Select Register – index 60h...............................................................................................26

6.5.3 I/O Port Select Register – index 61h...............................................................................................26

6.5.4 IRQ Channel Select Register – index 70h ............................................................................................26

6.5.6 UART 4 Clock Select Register – index F0h..........................................................................................26

6.6 Watch Dog Timer Device Control Register (LDN 8) .........................................................................................27

6.6.1 Device Enable Register – index 30h...............................................................................................27

6.6.2 I/O Port Select Register – index 60h...............................................................................................27

6.6.3 I/O Port Select Register – index 61h...............................................................................................27

6.6.4 IRQ Channel Select Register – index 70h ......................................................................................27

6.6.5 Timer Status and Control Register – index F0h ..............................................................................28

6.6.6 Timer Count Number Register – index F1h.....................................................................................28

7. Electron Characteristic

7.1 Absolute Maximum Ratings..............................................................................................................................29

7.2 DC Characteristics...............................................................................................................................................29

8. Ordering Information

9. Package Dimensions ..............................................................................................................................31

10. Application Circuit .................................................................................................................................32

............................................................................................................................29

...............................................................................................................................30

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F81216D

1. General Description

The F81216D mainly provides 3 pure UART ports and one UAR T+ IR port through LPC. Each UART includes 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability and an interrupt system.

One watch dog timer is provided for system controlling and the time interval can be programmed by register or hardware power on setting pin. One clock 24/48MHz input is necessary, and default is 24MHz. Powered by 3.3V voltage, the F81216D is in the small 48pin LQFP package (7mm x 7mm).

2. Feature List

Supports LPC interface Totally provides 4 UART (16550 asynchronous) ports

¾ 3 Pure UART ¾ 1 UART+IR

1 watch dog timer with WDTOUT# signal 1 frequency input 24/48MHz Powered by 3Vcc 48-LQFP(7mm x 7mm)

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3. Pin Configuration

F81216D

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4. Pin Description

F81216D

I/O

8t5V-d100

- TTL level bi-directional pin with 8 mA source-sink capability, 5V tolerance, pull-down 100K ohms

I/O

- TTL level bi-directional pin with 12 mA source-sink capability

12t

I/OD

PCI5V - bi-direction pin, slew rate control, 5V tolerance.

OUT

- Open-drain output pin with 12 mA sink capability

- TTL level input pin

- TTL level input pin and 5V tolerance.

t5V

- TTL level input pin and schmitt trigger

ts5V

- TTL level input pin and Schmitt trigger, 5V tolerance.

- TTL level bi-directional pin, Open-drain outpu with 12 mA sink capability

- Output pin with 12 mA source-sink capability

P - Power

4.1 ISA/LPC Interface

Pin No. Pin Name Ty pe Description

1 PCIRST# INts System PCI reset active low. 2 WDT_OUT# OD12 Watch dog timer output. When pin 24 power on setting

PS_WDT=0(default), Watch Dog timer time interval setting is programmed by register. Once power on setting PS_WDT=1, watch dog timer time interval will be fixed to 10 sec.

4~7 LPC_LAD[3:0]

8 LCLK IN

9 FRAME#

10 SERIRQ PCI5V In LPC mode, Serial IRQ input/Output.

12 CLKIN IN

PCI

ts5V

t5V

When in LPC mode, these signal lines communicate address,

control, and data information over the LPC bus between a host and a peripheral.

In LPC mode, this pin acts as PCI clock input.

In LPC mode, indicates start of a new cycle or termination of a broken cycle.

Clock Input

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4.2 UART Interface

Pin No. Pin Name Ty pe Description

F81216D

13 CTS4# IN 14 DSR4# IN

15 RTS4# I/O

16 DTR4# I/O

17 SIN4 IN

SOUT4

PS_2E8_IRQD

I/O

Clear To Send is the modem control input.

t5V

Data Set Ready. An active low signal indicates the modem or

t5V

data set is ready to establish a communication link and transfer data to the UART.

UART 4 Request To Send. An active low signal informs the

8t5V-d100

modem or data set that the controller is ready to send data.

UART 4 Data Terminal Ready. An active low signal informs

8t5V-d100

the modem or data set that controller is ready to communicate.

Serial Input. Used to receive serial data through the

t5V

communication link. UART 4 Serial Output. Used to transmit serial data out to the

8t5V-d100

communication link. Power setting pin to define the IRQD index.

Default PS_2E8_IRQD = 0, IRQF index is programmed by register. If PS_2E8_IRQD = 1, setting IRQF index to 0x2E8.

19 DCD4# IN

20 RI4# IN

21 CTS3# IN 22 DSR3# IN

RTS3#

I/O

PS_CONF_KE Y0

DTR3#

I/O

PS_WDT

Data Carrier Detect. An active low signal indicates the

t5V

modem or data set has detected a data carrie r.

Ring Indicator. An active low signal indicates that a ring

t5V

signal is being received from the modem or data set.

Clear To Send is the modem control input.

t5V

Data Set Ready. An active low signal indicates the modem or

t5V

data set is ready to establish a communication link and transfer

8t5V-d100

data to the UART. UART 3 Request To Send. An active low signal informs the modem or data set that the controller is ready to send data.

Power on configuration setting pin. As for detail description, please refer to register description.

UART 3 Data Terminal Ready. An active low signal informs

8t5V-d100

the modem or data set that controller is ready to communicate. Power on setting pin to enable the watch dog timer.

Default PS_WDT=0, WDT time programmed by register. When PS_WDT=1, WDT time is defined as 10 sec.

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F81216D

25 SIN3 IN

SOUT3

I/O

PS_3E8_IRQC

27 DCD3# IN

28 RI3# IN

31 CTS2# IN 32 DSR2# IN

Serial Input. Used to receive serial data through the

t5V

communication link. UART 3 Serial Output. Used to transmit serial data out to the

8t5V-d100

communication link. Power setting pin to define the IRQC index. Default PS_3E8_IRQC = 0, IRQF index is programmed by

Data Carrier Detect. An active low signal indicates the

t5V

modem or data set has detected a data carrie r.

Ring Indicator. An active low signal indicates that a ring

t5V

signal is being received from the modem or data set.

Clear To Send is the modem control input.

t5V

Data Set Ready. An active low signal indicates the modem or

t5V

data set is ready to establish a communication link and transfer

RTS2#

I/O

PS_CONF_KE Y1

DTR2#

I/O

PS_2E0_IRQB

35 SIN2 IN

SOUT2 UART 2 Serial Output. Used to transmit serial data out to the

I/O

data to the UART. UART 2 Request To Send. An active low signal informs the

8t5V-d100

modem or data set that the controller is ready to send data. Power on configuration setting pin. As for detail description,

please refer to register description. UART 2 Data Terminal Ready. An active low signal informs

8t5V-d100

the modem or data set that controller is ready to communicate. Power setting pin to define the IRQB index.

Default PS_2E0_IRQB = 0, IRQB index is programmed by register.

If PS_2E0_IRQB = 1, setting IRQB index to 0x2E0.

Serial Input. Used to receive serial data through the

t5V

communication link.

8t5V-d100

communication link.

PS_2F8_IRQB

Power setting pin to define the IRQB index. Default PS_2F8_IRQB = 0, IRQB index is programmed by

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F81216D

37 DCD2# IN

38 RI2# IN

39 CTS1# IN 40 DSR1# IN

RTS1#

I/O

PS_CONF_2E

DTR1#

I/O

Data Carrier Detect. An active low signal indicates the

t5V

modem or data set has detected a data carrie r.

Ring Indicator. An active low signal indicates that a ring

t5V

signal is being received from the modem or data set.

Clear To Send is the modem control input.

t5V

Data Set Ready. An active low signal indicates the modem or

t5V

data set is ready to establish a communication link and transfer data to the UART.

UART 1 Request To Send. An active low signal informs the

8t5V-d100

modem or data set that the controller is ready to send data. Power on configuration setting. Default PS_CONF_2E = 0,

setting the configuration to 0x4E. If PS_CONF_2E =1, setting the configuration to 0x2E.

UART 1 Data Terminal Ready. An active low signal informs

8t5V-d100

the modem or data set that controller is ready to communicate.

PS_3E0_IRQA

SIN1 IN

SOUT1

I/O

PS_3F8_IRQA

45 DCD1# IN

46 RI1# IN

Power setting pin to define the IRQA index. Default PS_3E0_IRQA = 0, IRQB index is programmed by

Serial Input. Used to receive serial data through the

t5T

communication link. UART 1 Serial Output. Used to transmit serial data out to the

8t5T-d100

communication link.

Power setting pin to define the IRQA index. Default PS_3F8_IRQA = 0, IRQA index is programmed by

Data Carrier Detect. An active low signal indicates the

t5T

modem or data set has detected a data carrie r.

Ring Indicator. An active low signal indicates that a ring

t5T

signal is being received from the modem or data set.

47 IRRX1 IN

Infrared Receiver input.

ts5T

48 IRTX1 OUT12 Infrared Transmitter Output.

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F81216D

4.3 Power

Pin No. Pin Name Ty pe Description

11,30 VCC P 3.3V power supply. 3, 29 GND P Ground.

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F81216D

5. Functional Description

The F81216D totally provides 4 UART ports through LPC interface. Among 4 UART ports, one ports can support serial infrared communication. Besides, each UART includes 16-byte send/receive FIFO, a programmable baud rate generator, completed modem control capability and interrupt system.

One watch dog timer is provided for system controlling and the time interval can be programmed by register or hardware power on setting pin. This IC needs one clock 24/48MHz input, and default is 24MHz. Powered by 3.3V voltage, the F81216D is in 48 pin LQFP

5.1 LPC Interface

The F81216D can support LPC interface serving as a bus interface between host (chipset) and peripheral (I/O chip) by hardware trapping. This interface provides much less pins and more efficient transmission. Data transfer on the LPC bus is serialized over a 4 bit bus. The general characteristics of the interface implemented in F81216D are listed a s below:

 One control line, namely LPC_FRAME#, which is used by the host to start or stop

transfers. No peripherals drive this signal.

 The LPC_LAD[3:0] bus, which communicates information serially. The information

conveyed is cycle type, cycle direction, chip selection, address, data, and wait states.

 PCIRST# is an active low reset signal.  An additional 33 MHz PCI clock is needed in the F81216D for synchronization.  Interrupt requests are issued through LPC_SERIRQ.  Power management events are issued through PME#.

5.2 UART

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Fintek F81216 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual