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F71883
F71883
Super Hardware Monitor + LPC I/O
Release Date: Nov., 2006
Version: V0.23P
Nov., 2006
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F71883 Datasheet Revision History
Version Date Page Revision History
0.20P 2005/10/14 - Release Version
0.21P 2006/01/20 - Added new functions ( Intel PECI/SST interface) and
0.22P 2006/09/04 125 Updated 80-Port application circuit.
0.23P 2006/11/23 60 Modified the description of Wakeup Control Register 2Dh
F71883
updated registers description and schematic
bit 7(SPI_CS1_EN)
Please note that all data and specifications are subject to change without notice. All the trade marks of products
and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from
such improper use or sales.
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F71883
Table of Content
1. General Description........................................................................................................................1
2. Feature List .....................................................................................................................................1
3. Key Specification............................................................................................................................4
4. Block Diagram................................................................................................................................4
5. Pin Configuration............................................................................................................................5
6. Pin Description................................................................................................................................5
6.1 Power Pin....................................................................................................................................6
6.2 LPC Interface..............................................................................................................................6
6.3 FDC.............................................................................................................................................6
6.4 UART, SIR and 80-Port ..............................................................................................................7
6.5 Parallel Port.................................................................................................................................9
6.6 Hardware Monitor.....................................................................................................................10
6.7 ACPI Function Pins ..................................................................................................................11
6.8 VID Controller..........................................................................................................................12
6.9 KPC Function............................................................................................................................13
7. Function Description.....................................................................................................................14
7.1 Power on Strapping Option.......................................................................................................14
7.2 FDC...........................................................................................................................................14
7.3 UART........................................................................................................................................28
7.4 Parallel Port...............................................................................................................................32
7.5 Hardware Monitor.....................................................................................................................35
7.6 Keyboard Controller .................................................................................................................45
7.7 SPI Interface..............................................................................................................................46
7.8 80 Port.......................................................................................................................................47
7.9 ACPI Function..........................................................................................................................47
7.10 AMDSI and Intel SST PECI Function......................................................................................50
8. Register Description......................................................................................................................51
8.1 Global Control Registers...........................................................................................................55
8.2 FDC Registers (CR00)..............................................................................................................62
8.3 UART1 Registers (CR01).........................................................................................................65
8.4 UART 2 Registers (CR02)........................................................................................................66
8.5 Parallel Port Registers (CR03)..................................................................................................68
8.6 Hardware Monitor Registers (CR04)........................................................................................70
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F71883
8.6.2.1 HW Monitor Config. Register Index 01h.....................................................................71
8.6.2.2 BEEP OVT ALERT Config. Register Index 02h...........................................................71
8.6.2.3 Case Open Config. Register Index 03h..........................................................................71
8.6.2.4 PECI AMDSI Select Register Index 0Ah......................................................................72
8.6.2.5 PECI CPU Select Register Index 0Bh (MEAS_TYPE == 2’b01)..............................72
8.6.2.6 AMDSI Version Register Index 0Bh (MEAS_TYPE ==2’b10).................................72
8.6.2.7 TCC Temp. Register Index 0Ch (MEAS_TYPE == 2’b01).......................................72
8.6.2.8 AMDSI Node ID Register Index 0Ch (MEAS_TYPE ==2’b10)...............................72
8.6.2.9 SST Address Register Index 0Dh ..................................................................................72
8.6.2.10 VID Divide Register Index 0Eh...................................................................................73
8.6.2.11 Configuration Register Index 0Fh................................................................................73
8.6.2.12 Voltage1 PME# Enable Register Index 10h.................................................................74
8.6.2.13 Voltage1 Interrupt Status Register Index 11h ..............................................................74
8.6.2.14 Voltage1 Exceeds Real Time Status Register 1 Index 12h ..........................................74
8.6.2.15 Voltage1 BEEP Enable Register Index 13h.................................................................74
8.6.2.16 Voltage reading and limit Index 20h- 4Fh ....................................................................74
8.6.2.17 Temperature PME# Enable Register Index 60h...........................................................75
8.6.2.18 Temperature Interrupt Status Register Index 61h ........................................................75
8.6.2.19 Temperature Real Time Status Register Index 62h......................................................76
8.6.2.20 Temperature BEEP Enable Register Index 63h...........................................................77
8.6.2.21 OVT Output Enable Register 1 Index 66h...................................................................77
8.6.2.22 Temperature Sensor Type Register Index 6Bh ............................................................77
8.6.2.23 TEMP1 Limit Hystersis Select Register -- Index 6Ch.....................................................78
8.6.2.24 TEMP2 and TEMP3 Limit Hystersis Select Register -- Index 6Dh................................78
8.6.2.25 DIODE OPEN Status Register -- Index 6Fh....................................................................78
8.6.2.26 Temperature Filter Select Register -- Index 8Eh .............................................................79
8.6.2.27 FAN PME# Enable Register
8.6.2.28 FAN Interrupt Status Register
Index 90h.......................................................................80
Index 91h.....................................................................80
8.6.2.29 FAN Real Time Status Register Index 92h..................................................................81
8.6.2.30 FAN BEEP# Enable Register Index 93h .....................................................................81
8.6.2.31 Fan Type Select Register -- Index 94h.............................................................................81
8.6.2.32 Fan mode Select Register -- Index 96h............................................................................82
8.6.2.33 Auto Fan1 and Fan2 Boundary Hystersis Select Register -- Index 98h..........................83
8.6.2.34 Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 99h..........................84
8.6.2.35 Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 9Bh..........................84
8.6.2.36 FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE
8.6.2.37 FAN3 and FAN4 START UP DUTY-CYCLE/VOLTAGE
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Index 9Ch........................84
Index 9Dh........................85
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F71883
8.6.2.38 Fan Fault Time Register -- Index 9Fh..............................................................................85
8.6.2.39 VT1 BOUNDARY 1 TEMPERATURE – Index A6h......................................................86
8.6.2.40 VT1 BOUNDARY 2 TEMPERATURE – Index A7........................................................86
8.6.2.41 VT1 BOUNDARY 3 TEMPERATURE – Index A8h......................................................87
8.6.2.42 VT1 BOUNDARY 4 TEMPERATURE – Index A9........................................................87
8.6.2.43 FAN1 SEGMENT 1 SPEED COUNT – Index AAh ....................................................87
8.6.2.44 FAN1 SEGMENT 2 SPEED COUNT – Index ABh.....................................................88
8.6.2.45 FAN1 SEGMENT 3 SPEED COUNT – Index ACh...................................................88
8.6.2.46 FAN1 SEGMENT 4 SPEED COUNT – Index ADh ..................................................88
8.6.2.47 FAN1 SEGMENT 5 SPEED COUNT – Index AEh...................................................88
8.6.2.48 FAN1 Temperature Mapping Select – Index AFh.......................................................88
8.6.2.49 VT2 BOUNDARY 1 TEMPERATURE – Index B6h......................................................90
8.6.2.50 VT2 BOUNDARY 2 TEMPERATURE – Index B7........................................................90
8.6.2.51 VT2 BOUNDARY 3 TEMPERATURE – Index B8h......................................................90
8.6.2.52 VT2 BOUNDARY 4 TEMPERATURE – Index B9........................................................90
8.6.2.53 FAN2 SEGMENT 1 SPEED COUNT – Index BAh ....................................................91
8.6.2.54 FAN2 SEGMENT 2 SPEED COUNT – Index BBh.....................................................91
8.6.2.55 FAN2 SEGMENT 3 SPEED COUNT – Index BCh...................................................91
8.6.2.56 FAN2 SEGMENT 4 SPEED COUNT – Index BDh ..................................................91
8.6.2.57 FAN2 SEGMENT 5 SPEED COUNT – Index BEh...................................................92
8.6.2.58 FAN2 Temperature Mapping Select – Index BFh.......................................................92
8.6.2.59 VT3 BOUNDARY 1 TEMPERATURE – Index C6h......................................................93
8.6.2.60 VT3 BOUNDARY 2 TEMPERATURE – Index C7........................................................93
8.6.2.61 VT3 BOUNDARY 3 TEMPERATURE – Index C8h......................................................94
8.6.2.62 VT3 BOUNDARY 4 TEMPERATURE – Index C9........................................................94
8.6.2.63 FAN3 SEGMENT 1 SPEED COUNT – Index CAh ....................................................94
8.6.2.64 FAN3 SEGMENT 2 SPEED COUNT – Index CBh.....................................................95
8.6.2.65 FAN3 SEGMENT 3 SPEED COUNT – Index CCh...................................................95
8.6.2.66 FAN3 SEGMENT 4 SPEED COUNT – Index CDh ..................................................95
8.6.2.67 FAN3 SEGMENT 5 SPEED COUNT – Index CEh...................................................95
8.6.2.68 FAN3 Temperature Mapping Select – Index CFh.......................................................95
8.6.2.69 VT4 BOUNDARY 1 TEMPERATURE – Index D6h .....................................................97
8.6.2.70 VT4 BOUNDARY 2 TEMPERATURE – Index D7 .......................................................97
8.6.2.71 VT4 BOUNDARY 3 TEMPERATURE – Index D8h .....................................................97
8.6.2.72 VT4 BOUNDARY 4 TEMPERATURE – Index D9 .......................................................98
8.6.2.73 FAN4 SEGMENT 1 SPEED COUNT – Index DAh....................................................98
8.6.2.74 FAN4 SEGMENT 2 SPEED COUNT – Index DBh ....................................................98
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F71883
8.6.2.75 FAN4 SEGMENT 3 SPEED COUNT – Index DCh ..................................................98
8.6.2.76 FAN4 SEGMENT 4 SPEED COUNT – Index DDh ..................................................99
8.6.2.77 FAN4 SEGMENT 5 SPEED COUNT – Index DEh...................................................99
8.6.2.78 FAN4 Temperature Mapping Select – Index DFh ......................................................99
8.7 KBC Registers (CR05) ...........................................................................................................100
8.8 GPIO Registers (CR06) ..........................................................................................................102
8.9 VID Registers (CR07).............................................................................................................109
8.10 SPI Registers (CR08)..............................................................................................................113
8.11 PME and ACPI Registers (CR0A)..........................................................................................118
9. Electron Characteristic................................................................................................................121
9.1 Absolute Maximum Ratings...................................................................................................121
9.2 DC Characteristics..................................................................................................................121
9.3 DC Characteristics Continued.................................................................................................121
10. Ordering Information..................................................................................................................122
11. Package Dimensions.................................................................................................................123
12. Application Circuit......................................................................................................................124
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F71883
1. General Description
The F71883 is the featured IO chip for PC system. Equipped with one IEEE 1284
parallel port, two UART ports, KBC, Serial Peripheral Interface (SPI), 80-Port, SIR and one
FDC. The F71883 integrated with hardware monitor, 9 sets of voltage sensor, 4 sets of
creative auto-controlling fans and 4 temperature sensor pins for the accurate dual current type
temp. measurement for CPU thermal diode or external transistors 2N3906.
The F71883 provides flexible features for multi-directional application. For instance,
supports 6/12 pins CPU VID controlling for VRM9.0/10.0/11* and CPU VID OTF (On The Fly),
provides 32 GPIO pins (multi-pin), IRQ sharing function also designed in UART feature for
particular usage and accurate current mode H/W monitor will be worth in measurement of
temperature, provides 3 modes fan speed control mechanism included Manual Mode/Speed
Mode/Temperature Mode for users’ selection Additionally, provides easy voltage sensor input
(VSI) function for sensing Vcore voltage, then output (VSO) the offset voltage for over/under
voltage change use.
of over-clocking or under-clocking. This function provides Turbo# pins by external trigger
signal to improve the CPU’s performance by voltage offset automatically when system is
going to run over-clocking or under-clocking. Due to achieve this action, suggest F75133S
Loading Gauge chip can be the part which detects system/CPU loading to decide when
issues the over-clocking/under-clocking signal for system executing. Briefly, user can gain
more features on motherboard by these two parts which improve performance and efficiency.
usage including bridge function and back up function, and the 80-Port is for engineering
usage. Others, the F71883 supports newest AMDSI and Intel PECI/SST interfaces for
temperature use. These features will help you more and improve product value. Finally, the
F71883 is powered by 3.3V voltage, with the LPC interface in the package of 128-QFP green
package.
Further, the F71883 supports an automatic/dynamic over-voltage function for application
The F71883 also integrated SPI interface and 80-Port. The SPI interface is for BIOS
2. Feature List
General Functions
¾ Comply with LPC Spec. 1.0
¾ Support DPM (Device Power Management), ACPI
¾ 6/12 VID pins for VRM9.0/10.0/11.0* and CPU VID OTF (On The Fly)
¾ Easy voltage sensor I/O (VSI/VSO) for Vcore change use.
¾ Support automatic and dynamic voltage change function (Turbo pins)
¾ Provides one FDC, two UARTs, KBC and Parallel Port
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F71883
¾ H/W monitor functions
¾ SPI interface for BIOS use
¾ 80-Port interface.
¾ Support AMD SID/SIC interface and Intel SST/PECI interface
¾ 32 GPIO Pins for flexible application
¾ 24/48 MHz clock input
¾ Packaged in 128-PQFP green package and powered by 3.3VCC
FDC
¾ Compatible with IBM PC AT disk drive systems
¾ Variable write pre-compensation with track selectable capability
¾ Support vertical recording format
¾ DMA enable logic
¾ 16-byte data FIFOs
¾ Support floppy disk drives and tape drives
¾ Detects all overrun and under run conditions
¾ Built-in address mark detection circuit to simplify the read electronics
¾ Completely compatible with industry standard 82077
¾ 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
UART
¾ Two high-speed 16C550 compatible UART with 16-byte FIFOs
¾ Fully programmable serial-interface characteristics
¾ Baud rate up to 115.2K
¾ Support IRQ sharing
Infrared
¾ Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
Parallel Port
¾ One PS/2 compatible bi-directional parallel port
¾ Support Enhanced Parallel Port (EPP)
¾ Support Extended Capabilities Port (ECP)
¾ Enhanced printer port back-drive current protection
− Compatible with IEEE 1284 specification
− Compatible with IEEE 1284 specification
Keyboard Controller
¾ 8042 based with optional F/W from AMIKKEYTM-2, with 2K bytes of programmable
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F71883
ROM, and 256 bytes of RAM
¾ Asynchronous Access to Two Data Registers and One status Register
¾ Software compatibility with the 8042
¾ Support PS/2 mouse
¾ Support both interrupt and polling modes
¾ Fast Gate A20 and Hardware Keyboard Reset
¾ 6 MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency
Hardware Monitor Functions
¾ 3 dual current type (±3℃) thermal inputs for CPU thermal diode and 2N3906 transistors
¾ Temperature range -20℃~145 (One is from ℃ -20~127 , ℃ two sets are from 0~ 145℃)
¾ 9 sets voltage monitoring (6 external and 3 internal powers)
¾ High limit signal (SMI#) for Vcore level
¾ 4 fan speed monitoring inputs
¾ 4 fan speed PWM/DC control outputs(support 3 wire and 4 wire fans)
¾ Issue PME# and OVT# hardware signals output
¾ Case intrusion detection circuit
¾ WATCHDOG# comparison of all monitored values
Serial Peripheral Interface Compatible
¾ Support SPI bridge function for BIOS use
¾ Support Back Up BIOS function
80-Port Interface
¾ Monitor 0x80 Port status and output the value via the signals defined for 7-segment display.
¾ High nibble and low nibble are outputted interleaved at 1KHz frequency.
Integrate AMD SI Interface
Integrate Intel PECI/SST Interface
Package
¾ 128-pin PQFP green package
Noted: Patented TW207103 TW207104 TW220442 US6788131 B1 TWI235231 TW237183 TWI263778
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3. Key Specification
Supply Voltage 3.0V to 3.6V
Operating Supply Current ----- mA typ.
4. Block Diagram
CPU
Chipset
(NB+SB)
Super H/W Monitor + I/O
F71883
IDE
USB
AC’97
Temperature
Voltage
Fan
AMDSI
A PECI
SST
KBC
IrDA
Parallel
ACPI
SPI
LED(GPIO)
COM
Floppy
VID
Controlle
80-Port
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5. Pin Configuration
6. Pin Description
I/O
- TTL level bi-directional pin with 12 mA source-sink cap ability.
12t
I/OOD
I/OD
16t5v
OD
16-u10-5v
I/OD
12ts5v
ILv/O
D8-S1
ILv/OD
- TTL level bi-directional pin, can select to OD or OUT by register, with 12 mA
12t
source-sink capability.
- TTL level bi-directional pin,Open-drain output with 16 mA source-sink capability, 5V
tolerance.
- Open-drain output pin with 16 mA sink capability, pull-up 10k ohms, 5V tolerance.
- TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink
capability, 5V tolerance.
- Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.). Output with 8mA drive and
1mA sink capability.
- Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.). Output with 12mA sink
12
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O
O
O
O30
AOUT - Output pin(Analog).
OD
OD
OD24
IN
INts
IN
AIN - Input pin(Analog).
P - Power.
8-u47-5v
8
12
12
12-5v
t5v
- TTL level input pin and schmitt trigger, 5V tolerance.
ts5v
6.1 Power Pin
Pin No. Pin Name Type Description
4,37,99 VCC P Power supply voltage input with 3.3V
68 VSB P Stand-by power supply voltage input 3.3V
86 VBAT P Battery voltage input
88 AGND(D-) P Analog GND
20, 48, 73, 117 GND P Digital GND
capability.
- Open-drain pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance.
- Output pin with 8 mA source-sink capability.
- Output pin with 12 mA source-sink capability.
- Output pin with 30 mA source-sink capability.
- Open-drain output pin with 12 mA sink capability.
- Open-drain output pin with 12 mA sink capability, 5V tolerance.
- Open-drain output pin with 24 mA sink capability.
- TTL level input pin,5V tolerance.
- TTL level input pin and schmitt trigger.
6.2 LPC Interface
Pin No. Pin Name Type PWR Description
29 LRESET# IN
30 LDRQ# O12 VCC Encoded DMA Request signal.
31 SERIRQ I/O
32 LFRAM# INts VCC Indicates start of a new cycle or termination of a
36-33 LAD[3:0] I/O
38 PCICLK INts VCC 33MHz PCI clock input.
39 CLKIN INts VCC System clock input. According to the input frequency
VCC Reset signal. It can connect to PCIRST# signal on the
ts5v
host.
VCC Serial IRQ input/Output.
12t
broken cycle.
VCC These signal lines communicate address, control, and
12t
data information over the LPC bus between a host and
a peripheral.
24/48MHz.
6.3 FDC
Pin No. Pin Name Type PWR Description
7
8
DENSEL#
OD24 VCC Motor A On. When set to 0, this pin enables disk drive
MOA#
OD24 VCC Drive Density Select.
Set to 1 - High data rate.(500Kbps, 1Mbps)
Set to 0 – Low data rate. (250Kbps, 300Kbps)
0. This is an open drain output.
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9 DRVA# OD24 VCC Drive Select A. When set to 0, this pin enables disk
drive A. This is an open drain output.
10 WDATA# OD24 VCC Write data. This logic low open drain writes
pre-compensation serial data to the selected FDD. An
open drain output.
11 DIR# OD24 VCC Direction of the head step motor. An open drain output.
Logic 1 = outward motion
Logic 0 = inward motion
12 STEP# OD24 VCC Step output pulses. This active low open drain output
produces a pulse to move the head to another track.
13 HDSEL# OD24 VCC Head select. This open drain output determines which
disk drive head is active.
14 WGATE# OD24 VCC Write enable. An open drain output.
15 RDATA# IN
16 TRK0# IN
17 INDEX# IN
VCC The read data input signal from the FDD.
ts5v
VCC Track 0. This Schmitt-triggered input from the disk
ts5v
VCC This Schmitt-triggered input from the disk drive is
ts5v
18 WPT# IN
19 DSKCHG# IN
VCC Write protected. This active low Schmitt input from the
ts5v
VCC Diskette change. This signal is active low at power on
ts5v
Logic 1 = side 0
Logic 0 = side 1
drive is active low when the head is positioned over
the outermost track.
active low when the head is positioned over the
beginning of a track marked by an index hole.
disk drive indicates that the diskette is write-protected.
and whenever the diskette is removed.
6.4 UART, SIR and 80-Port
Pin No. Pin Name Type PWR Description
IRTX O12 Infrared Transmitter Output. 27
GPIO42 I/OOD
IRRX INts Infrared Receiver input. 28
GPIO43 I/OOD
118 DCD1# IN
119 RI1# IN
120 CTS1# IN
121
DTR1# O
FAN60_100 IN
VCC Data Carrier Detect. An active low signal indicates the
t5v
VCC Ring Indicator. An active low signal indicates that a ring
t5v
VCC Clear To Send is the modem control input.
t5v
8-u47,5v
t5v
VCC
12t
General Purpose IO
VSB
12t
General Purpose IO.
modem or data set has detected a data carrier.
signal is being received from the modem or data set.
VCC
UART 1 Data Terminal Ready. An active low signal
informs the modem or data set that controller is ready
to communicate. Internal 47k ohms pulled high and
disable after power on strapping.
Power on strapping pin:
1(Default): (Internal pull high)
Power on fan speed default duty is 60%.(PWM)
0: (External pull down)
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F71883
Power on fan speed default duty is 100%.(PWM)
122
RTS1#
O
VIDOUT_TRAP IN
123 DSR1# IN
124
SOUT1
Config4E_2E IN
O
VCC
UART 1 Request To Send. An active low signal informs
8-u47,5v
the modem or data set that the controller is ready to
send data. Internal 47k ohms pulled high and disable
after power on strapping.
t5v
Power on strapping pin:
1(Default) :
1. VIDIN[5-0]/OUT[5-0] pins will be VIDIN function.
2. VIDOUT[5-0]/GPIO0[5-0] pins will be VIDOUT function
0 :
1. VIDIN[5-0]/OUT[5-0] pins will be VIDIN[5-0]/OUT[5-0]
function.(In-Out on the same pins)
2. VIDOUT[5-0]/GPIO0[5-0] pins will be GPIO0 function.
VCC Data Set Ready. An active low signal indicates the
t5v
modem or data set is ready to establish a
communication link and transfer data to the UART.
UART 1 Serial Output. Used to transmit serial data
8-u47,5v
VCC
out to the communication link. Internal 47k ohms pulled
high and disable after power on strapping.
t5v
Power on strapping:
125 SIN1 IN
126
DCD2#
IN
SEGG O
127
RI2#
IN
SEGF O
CTS2# IN
H# O
1
DTR2#
O
SEGD O8 SEGD for 7-segment display
FWH_TRAP IN
2 RTS2#
O
1(Default): Configuration register Æ4E
0 : Configuration register Æ2E
VCC Serial Input. Used to receive serial data through the
t5v
communication link.
Data Carrier Detect. An active low signal indicates
t5v
VCC
the modem or data set has detected a data carrier.
8
Ring Indicator. An active low signal indicates that a
t5v
VCC
SEGG for 7-segment display
ring signal is being received from the modem or data
set.
8
Clear To Send is the modem control input. 128
t5v
30
8-u47,5v
VCC
VCC
UART 2 Data Terminal Ready. An active low signal
SEGF for 7-segment display
H# for 7-segment display
informs the modem or data set that controller is ready
to communicate. Internal 47k ohms pulled high and
disable after power on strapping.
t5v
Power on strapping :
1(Default): SPI as a backup BIOS
0 : SPI as a primary BIOS
VCC UART 2 Request To Send. An active low signal
8-u47,5v
informs the modem or data set that the controller is
ready to send data. Internal 47k ohms pulled high and
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F71883
disable after power on strapping.
SEGC O8 SEGC for 7-segment display
3
PWM_DC IN
DSR2# IN
L#
t5v
O30
t5v
Power on strapping :
1 (Default): Fan control method will be PWM Mode
0 Drive :Fan control method will be Linear Mode
VCC
Data Set Ready. An active low signal indicates the
modem or data set is ready to establish a
communication link and transfer data to the UART.
L# for 7-segment display
5
SOUT2
O
8-u47,5v
UART 2 Serial Output. Used to transmit serial data
VCC
out to the communication link. Internal 47k ohms
pulled high and disable after power on strapping.
SEGB O8 SEGB for 7-segment display.
SPI_TRAP
IN
t5v
Power on strapping:
1(Default) : SPI function disable
0 : SPI function enable
12t
General Purpose IO 66
VCC
communication link.
SEGE for 7-segment display
VSB
SEGA for 7-segment display
6
SIN2 IN
SEGE O
GPIO17 I/OOD
SEGA O
Serial Input. Used to receive serial data through the
t5v
8
8
6.5 Parallel Port
Pin No. Pin Name Type PWR Description
100 SLCT IN
101 PE IN
102 BUSY IN
103 ACK# IN
104 SLIN# OD
105 INIT# OD
VCC An active high input on this pin indicates that the
ts5v
printer is selected. Refer to the description of the
parallel port for definition of this pin in ECP and EPP
mode.
VCC An active high input on this pin indicates that the
ts5v
printer has detected the end of the paper. Refer to the
description of the parallel port for the definition of this
pin in ECP and EPP mode.
VCC An active high input indicates that the printer is not
ts5v
ready to receive data. Refer to the description of the
parallel port for definition of this pin in ECP and EPP
mode.
VCC An active low input on this pin indicates that the printer
ts5v
has received data and is ready to accept more data.
Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.
VCC Output line for detection of printer selection. Refer to
12-5v
the description of the parallel port for the definition of
this pin in ECP and EPP mode.
VCC Output line for the printer initialization. Refer to the
12-5v
Nov., 2006
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F71883
description of the parallel port for the definition of this
pin in ECP and EPP mode.
106 ERR#
107 AFD# OD
108 STB# OD
109
I/O
PD0
110
111
112
113
114
115
116
I/O
PD1
I/O
PD2
I/O
PD3
I/O
PD4
I/O
PD5
I/O
PD6
I/O
PD7
IN
ts5v
VCC An active low input on this pin indicates that the printer
has encountered an error condition. Refer to the
description of the parallel port for the definition of this
pin in ECP and EPP mode.
VCC An active low output from this pin causes the printer to
12-5v
auto feed a line after a line is printed. Refer to the
description of the parallel port for the definition of this
pin in ECP and EPP mode.
VCC An active low output is used to latch the parallel data
12-5v
into the printer. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
VCC Parallel port data bus bit 0. Refer to the description of
12ts5v
the parallel port for the definition of this pin in ECP and
EPP mode.
VCC Parallel port data bus bit 1.
12ts5v
VCC Parallel port data bus bit 2.
12ts5v
VCC Parallel port data bus bit 3.
12ts5v
VCC Parallel port data bus bit 4.
12ts5v
VCC Parallel port data bus bit 5.
12ts5v
VCC Parallel port data bus bit 6.
12ts5v
VCC Parallel port data bus bit 7.
12ts5v
6.6 Hardware Monitor
Pin No. Pin Name Type PWR Description
93-97 VIN6~VIN2 AIN VCC Voltage Input 2 ~ 6.
98 Vcore(VIN1) AIN VCC Voltage Input for Vcore.
21 FANIN1 IN
22 FANCTL1 OD
ts5v
12-5v
AOUT
23 FANIN2 IN
24 FANCTL2 OD
ts54v
12-5v
AOUT
FANIN3 IN
ts5v
GPIO40 I/OOD
26
FANCTL3
OD
12-5V
AOUT
GPIO41 I/OOD
89 D3+(System) AIN VCC Thermal diode/transistor temperature sensor input for
VCC Fan 1 tachometer input.
VCC Fan 1 control output. This pin provides PWM
duty-cycle output or a voltage output.
VCC Fan 2 tachometer input.
VCC Fan 2 control output. This pin provides PWM
duty-cycle output or a voltage output.
12t
VCC
VCC
Fan 3 speed input. 25
General purpose IO.
Fan 3 control output. This pin provides PWM
duty-cycle output or a voltage output.
*This pin default function is FANCTL (PWM signal
output), please take care the application if user want to
implement GPIO function.
12t
General purpose IO.
system use.
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F71883
90 D2+ AIN VCC Thermal diode/transistor temperature sensor input.
91 D1+(CPU) AIN VCC CPU thermal diode/transistor temperature sensor
input. This pin is for CPU use.
92 VREF AOUT
79
PME#
OD
12-5v
GPIO25 I/OOD
59
GPIO10 I/OOD
SPI_SLK O12 Serial clock output pin for SPI device.
60
FANIN4 IN
GPIO11 I/OOD
SPI_CS0# O12 Function A: When using firmware hub BIOS for
ts5v
61
FANCTL4 OD
GPIO12 I/OOD
SPI_MISO IN
12-5v
AOUT
t5v
VCC Voltage sensor output.
VSB
Generated PME event. It supports the PCI PME#
interface. This signal allows the peripheral to request
the system to wake up from the S3 state.
12t
General purpose IO.
VSB
12t
General purpose IO.
VSB
12t
General Purpose IO.
Fan 4 tachometer input
primary BIOS and SPI BIOS for second BIOS, please
connect this pin to SPI BIOS chip select pin.
Function B: When using two SPI Flashes for primary
and back up BIOS, please connect this pin to primary
BIOS chip select pin.
Fan 4 control output. This pin provides PWM
duty-cycle output or a voltage output.
General purpose IO.
VSB
12t
SPI master in/slave out pin.
62
63
FANCTL1_1 OD
GPIO13 I/OOD
SPI_MOSI O12
BEEP OD24
GPIO14 I/OOD
12-5v
General purpose IO.
VSB
12t
Fan 1 control output. This pin provides PWM
duty-cycle open drain output for Intel 4-pin Fan.
SPI master out/slave in pin.
Beep pin.
General purpose IO.
VSB
12t
FWH_DIS O12 Firmware hub disable
WDTRST# OD
SPI_CS1# O
Watch dog timer signal output.
12-5v
12
When using two SPI Flashes for primary and back up
BIOS, please connect this pin to back up BIOS chip
select pin.
67 OVT# OD
VSB Over temperature signal output.
12-5v
6.7 ACPI Function Pins
Pin No. Pin Name Type PWR Description
64
65
GPIO15 I/OOD
LED_VSB OD12 Power LED for VSB.
ALERT# OD
GPIO16 I/OOD
LED_VCC OD12 Power LED for VCC.
Turbo2# IN
General purpose IO.
VSB
12t
12
General purpose IO.
VSB
12t
ts5v
Alert a signal when temperature over limit setting.
VID Turbo 2 enable control pin. (Patent Issue)
Nov., 2006
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F71883
74
PCIRST1# OD12 It is a output buffer of RSTCON# and LRESET#.
GPIO20 I/OOD
PCIRST2# O12 It is a output buffer of RSTCON# and LRESET#. 75
GPIO21 I/OOD
PCIRST3# O12 It is a output buffer of RSTCON# and LRESET#. 76
GPIO22 I/OOD
GPIO23 I/OOD12 General purpose IO. (Default) 77
RSTCON#
OD
ATXPG_IN AIN ATX Power Good input. 78
GPIO24 I/OOD
PWSIN# IN
GPIO26 I/OOD
81
PWSOUT#
OD12 VSB Panel Switch Output. This pin is low active and pulse
GPIO27 I/OOD
S3# IN
GPIO30 I/OOD
83
PSON#
OD
GPIO31 I/OOD
84
PWROK OD12 VSB PWROK function, It is power good signal of VCC,
GPIO32 I/OOD
85
RSMRST#
OD12 Resume Reset# function, It is power good signal of
GPIO33 I/OOD
87 COPEN# IN
VSB
12
General purpose IO.
VSB
12
General purpose IO.
VSB
12
General purpose IO.
VSB
12
RESET Connect# with 50ms debouce function, it
connects to reset button, and also other reset source
on the motherboard.
VSB
ts5v
12t
Main power switch button input. 80
VSB
12t
General purpose IO.
General purpose IO.
output. It is power on request output#.
General purpose IO.
12t
ts5v
12-5v
12t
12t
VSB
VSB
S3# Input is Main power on-off switch input. 82
General purpose IO.
Power supply on-off control output. Connect to ATX
power supply PS_ON# signal.
General purpose IO.
which is delayed 400ms (default) as VCC arrives at
2.8V.
General purpose IO.
12t
VBAT
VSB, which is delayed 66ms as VSB arrives at 2.3V.
12t
VBAT Case Open Detection #. This pin is connected to a
ts5v
General purpose IO.
specially designed low power CMOS flip-flop backed
by the battery for case open state preservation during
power loss.
6.8 VID Controller
Pin No. Pin Name Type PWR Description
46-42
VIDIN[4:0]
OUT[4:0] O
IN
12
ts5v
VCC
CPU VID input pins.
Special level input VIHÆ 0.9, VIL Æ 0.6
CPU VID output pins.
(These is for VID in-out function at the same pin)
(Power On Trapping by pin 122)
47
VIDIN5
OUT5 O
IN
12
ts5v
VCC
CPU VID input pins.
Special level input VIHÆ 0.9, VIL Æ 0.6
CPU VID output pins.
(These is for VID in-out function at the same pin)
(Power On Trapping by pin 122)
Nov., 2006
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F71883
SID ILv/OD12 AMDSI interface data input.
VIDOUT[4:0] OD12 CPU VID output pins. 53-49
GPIO[4:0] I/OOD
54
56
VIDOUT5 OD12 CPU VID output pins.
GPIO5 I/OOD
SIC OD
SLOTOCC# IN
GPIO06 I/OOD
GPIO07 I/OOD
Turbo1# IN
WDTRST# OD
VSI AIN Easy voltage sensor input for Vcore change use. 57
SST I
VSO AOUT Easy voltage sensor output for Vcore change use. 58
PECI I
ts5v
ts5v
12-5v
Lv/OD8-S1
Lv/OD8-S1
6.9 KPC Function
Pin No. Pin Name Type PWR Description
40 KBRST#
41 GA20
69 KDATA I/OD
70 KCLK I/OD
71 MDAT I/OD
72 MCLK I/OD
D
16-u10,5V
D
16-u10,5V
16t,5V
16t,5V
16t,5V
16t,5V
VSB
12t
VSB
General purpose pin. (Power On Trapping by pin 122)
12t
12
VSB
12t
General purpose pin.
VSB
12t
VID Turbo 1 enable control pin. (Patent Issue)
VSB
VSB
VCC Keyboard reset. This pin is high after system reset.
VCC Gate A20 output. This pin is high after system reset.
VSB Keyboard Data.
VSB Keyboard Clock.
VSB PS2 Mouse Data.
VSB PS2 Mouse Clock.
General purpose pin. (Power On Trapping by pin 122)
AMDSI interface clock output.
CPU SLOTOCC# input. 55
General purpose pin.
Watch dog timer signal output.
Intel SST hardware monitor interface.
Intel PECI hardware monitor interface.
Internal pull high 3.3V with 10k ohms. (KBC P20)
Internal pull high 3.3V with 10k ohms. (KBC P21)
Nov., 2006
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F71883
7. Function Description
7.1 Power on Strapping Option
The F71883 provides four pins for power on hardware strapping to select functions. There is
a form to describe how to set the functions you want.
Pin No. Symbol Value Description
1 SPI as a backup BIOS (Default) 1 FWH_TRAP
0 SPI as a primary BIOS
1 Fan control mode: PWM mode. ( Default) 2 PWM_DC
0 Fan control mode: Linear mode.
1 SPI function disable (Default) 5 SPI_TRAP
0 SPI function enable
1 Power on Fan speed default duty is 60%(PWM)(Default) 121 FAN60_100
0 Power on Fan speed default duty is 100%(PWM)
1 6 pins VIDIN and 6 pins VIDOUT (Default) 122 VIDOUT
0 VIDIN/OUT on 6 pins , Original VIDOUT pins will be GPIO
pins.
1 Configuration Register I/O port is 4E/4F. (Default) 124 Config4E_2E
0 Configuration Register I/O port is 2E/2F.
7.2 FDC
The Floppy Disk Controller provides the interface between a host processor and one
floppy disk drives. It integrates a controller and a digital data separator with write
pre-compensation, data rate selection logic, microprocessor interface, and a set of registers.
The FDC supports data transfer rates of 250 Kbps, 300 Kbps, 500 Kbps, and 1 Mbps. It
operates in PC/AT mode and supports 3-mode type drives.
The FDC configuration is handled by software and a set of Configuration registers.
Status, Data, and Control registers facilitate the interface between the host microprocessor
and the disk drive, providing information about the condition and/or state of the FDC. These
configuration registers can select the data rate, enable interrupts, drives, and DMA modes,
and indicate errors in the data or operation of the FDC/FDD. The controller manages data
transfers using a set of data transfer and control commands. These commands are handled in
three phases: Command, Execution, and Result. Not all commands utilize all these three
phases.
The below content is about the FDC device register descriptions. All the registers are for
software porting reference.
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F71883
Status Register A (PS/2 mode) Base + 0
Bit Name R/W Default Description
7 INTPEND R 0 This bit indicates the state of the interrupt output.
6 DRV2_N R - 0: a second drive has been installed.
1: a second drive has not been installed.
5 STEP R 0 This bit indicates the complement of STEP# disk interface output.
4 TRK0_N R - This bit indicates the state of TRK0# disk interface input.
3 HDSEL R 0 This bit indicates the complement of HDSEL# disk interface output.
0: side 0.
1: side 1.
2 INDEX_N R - This bit indicates the state of INDEX# disk interface input.
1 WPT_N R - This bit indicates the state of WPT# disk interface input.
0 DIR R 0 This bit indicates the complement of DIR# disk interface output.
Status Register A (Model 30 mode) Base + 0
Bit Name R/W Default Description
0: disk is write-protected.
1: disk is not write-protected.
7 INTPEND R 0 This bit indicates the state of the interrupt output.
6 DRQ R 0 This bit indicates the state of the DRQ signal.
5 STEP_FF R 0 This bit indicates the complement of latched STEP# disk interface output.
4 TRK0 R - This bit indicates the complement of TRK0# disk interface input.
3 HDSEL_N R 1 This bit indicates the state of HDSEL# disk interface output.
0: side 0.
1: side 1.
2 INDEX R - This bit indicates the complement of INDEX# disk interface input.
1 WPT R - This bit indicates the complement of WPT# disk interface input.
0: disk is write-protected.
1: disk is not write-protected.
0 DIR_N R 1 This bit indicates the state of DIR# disk interface output.
0: head moves in inward direction.
1: head moves in outward direction.
Status Register B (PS/2 Mode) Base + 1
Bit Name R/W Default Description
7-6 Reserved R 11 Reserved. Return 11b when read.
5 DR0 R 0 Drive select 0. This bit reflects the bit 0 of Digital Output Register.
4 WDATA R 0 This bit changes state at every rising edge of WDATA#.
3 RDATA R 0 This bit changes state at every rising edge of RDATA#.
2 WGATE R 0 This bit indicates the complement of WGATE# disk interface output.
1 MOTEN1 R 0 This bit indicates the complement of MOB# disk interface output. Not support
in this design.
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F71883
0 MOTEN0 R 0 This bit indicates the complement of MOA# disk interface output.
Status Register B (Model 30 Mode) Base + 1
Bit Name R/W Default Description
7 DRV2_N R - 0: a second drive has been installed.
1: a second drive has not been installed.
6 DSB_N R 1 This bit indicates the state of DRVB# disk interface output. Not support in this
design.
5 DSA_N R 1 This bit indicates the state of DRVA# disk interface output.
4 WDATA_FF R 0 This bit is latched at the rising edge of WDATA# and is cleared by a read from
the Digital Input Register.
3 RDATA_FF R 0 This bit is latched at the rising edge of RDATA# and is cleared by a read form
2 WGATE_FF R 0 This bit is latched at the falling edge of WGATE# and is cleared by a read from
1 DSD_N R 1 This bit indicates the complement of DRVD# disk interface output. Not support
0 DSC_N R 1 This bit indicates the complement of DRVC# disk interface output. Not support
the Digital Input Register.
the Digital Input Register.
in this design.
in this design.
Digital Output Register Base + 2
Bit Name R/W Default Description
7 MOTEN3 R 0 Motor enable 3. Not support in this design.
6 MOTEN2 R 0 Motor enable 2. Not support in this design.
5 MOTEN1 R/W 0 Motor enable 1. Used to control MOB#. MOB# is not support in this design.
4 MOTEN0 R/W 0 Motor enable 0. Used to control MOA#.
3 DAMEN R/W 0 DMA enable. This bit has two mode of operation.
PC-AT and Model 30 mode: write 1 will enable DMA and IRQ, write 0 will
disable DMA and IRQ.
PS/2 mode: This bit is reserved. DMA and IRQ are always enabled in PS/2
mode.
2 RESET R 0 Write 0 to this bit will reset the controller. I will remain in reset condition until a 1
is written.
1 DSD_N R 1 This bit indicates the complement of DRVD# disk interface output. Not support
in this design.
0 DSC_N R 1 This bit indicates the complement of DRVC# disk interface output. Not support
in this design.
Tape Drive Register Base + 3
Bit Name R/W Default Description
7-6 Reserved R 00 Reserved. Return 00b when read.
5-4 TYPEID R 11 Reserved in normal function, return 11b when read.
If 3 mode FDD function is enabled. These bits indicate the drive type ID.
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F71883
3-2 Reserved R 11 Reserved. Return 11b when read in normal function.
Return 00b when read in 3 mode FDD function.
1-0 TAPESEL R/W 0 These bits assign a logical drive number to be a tape drive.
Main Status Register Base + 4
Bit Name R/W Default Description
7 RQM R 0 Request for Master indicates that the controller is ready to send or receive data
from the uP through the FIFO.
6 DIO R 0 Data I/O (direction):
0: the controller is expecting a byte to be written to the Data Register.
1: the controller is expecting a byte to be read from the Data Register.
5 NON_DMA R 0 Non DMA Mode:
4 FDC_BUSY R 0 This bit indicate that a read or write command is in process.
3 DRV3_BUSY R 0 FDD number 3 is in seek or calibration condition. FDD number 3 is not support
2 DRV2_BUSY R 0 FDD number 2 is in seek or calibration condition. FDD number 2 is not support
1 DRV1_BUSY R 0 FDD number 1 is in seek or calibration condition. FDD number 1 is not support
0 DRV0_BUSY R 0 FDD number 0 is in seek or calibration condition.
0: the controller is in DAM mode.
1: the controller is interrupt or software polling mode.
in this design.
in this design.
in this design.
Data Rate Select Register Base + 4
Bit Name R/W Default Description
7 SOFTRST W 0 A 1 written to this bit will software reset the controller. Auto clear after reset.
6 PWRDOWN W 0 A 1 to this bit will put the controller into low power mode which will turn off the
5 Reserved - - Return 0 when read.
4-2 PRECOMP W 000 Select the value of write precompensation:
oscillator and data separator circuits.
250K-1Mbps 2Mbps
000: default delays default delays
001: 41.67ns 20.8ns
010: 83.34ns 41.17ns
011: 125.00ns 62.5ns
100: 166.67ns 83.3ns
101: 208.33ns 104.2ns
110: 250.00ns 125.00ns
111: 0.00ns (disabled) 0.00ns (disabled)
The default value of corresponding data rate:
250Kbps: 125ns
300Kbps: 125ns
500Kbps: 125ns
1Mbps: 41.67ns
2Mbps: 20.8ns
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F71883
1-0 DRATE W 10 Data rate select:
MFM FM
00: 500Kbps 250Kbps
01: 300Kbps 150Kbps
10: 250Kbps 125Kbps
11: 1Mbps illegal
Data (FIFO) Register Base + 5
Bit Name R/W Default Description
7-0 DATA R/W 00h The FIFO is used to transfer all commands, data and status between controller
and the system. The Data Register consists of four status registers in a stack
with only one register presented to the data bus at a time. The FIFO is default
Status Registers 0
disabled and could be enabled via the CONFIGURE command.
Bit Name R/W Default Description
7-6 IC R - Interrupt code :
5 SE R - Seek end.
4 EC R - Equipment check.
3 NR R - Not ready.
2 HD R - Head address.
1-0 DS R - Drive select.
00: Normal termination of command.
01: Abnormal termination of command.
10: Invalid command.
11: Abnormal termination caused by poling.
Set when a SEEK or RECALIBRATE or a READ or WRITE with implied seek
command is completed.
0: No error
1: When a fault signal is received form the FDD or the TRK0# signal fails to
occur after 77 step pulses.
0: Drive is ready
1: Drive is not ready.
The current head address.
00: Drive A selected.
01: Drive B selected.
10: Drive C selected.
11: Drive D selected.
Status Registers 1
Bit Name R/W Default Description
7 EN R - End of Track.
Set when the FDC tries to access a sector beyond the final sector of a cylinder.
6 DE R - Data Error.
The FDC detect a CRC error in either the ID field or the data field of a sector.
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F71883
4 OR R - Overrun/Underrun.
Set when the FDC is not serviced by the host system within a certain time
interval during data transfer.
3 Reserved - - Unused. This bit is always “0”
2 ND R - No Data.
Set when the following conditions occurred:
1. The specified sector is not found during any read command.
2. The ID field cannot be read without errors during a READ ID command.
3. The proper sector sequence cannot be found during a READ TRACK
command.
1 NW R - No Writable
Set when WPT# is active during execution of write commands.
0 MA R - Missing Address Mark.
Set when the following conditions occurred:
1. Cannot detect an ID address mark at the specified track after
encountering the index pulse form the INDEX# pin twice.
2. Cannot detect a data address mark or a deleted data address mark on the
specified track.
Status Registers 2
Bit Name R/W Default Description
7 Reserved - - Unused. This bit is always “0”.
6 CM R - Control Mark.
5 DD R - Data Error in Data Field.
4 WC R - Wrong Cylinder.
3 SE R - Scan Equal.
2 SN R - Scan Not Satisfied.
1 BC R - Bad Cylinder.
0 MD R - Missing Data Address Mark.
Set when following conditions occurred:
1. Encounters a deleted data address mark during a READ DATA command.
2. Encounters a data address mark during a READ DELETED DATA
command.
The FDC detects a CRC error in the data field.
Set when the track address from the sector ID field is different from the track
address maintained inside the FDC.
Set if the equal condition is satisfied during execution of the SCAN command.
Set when the FDC cannot find a sector on the track which meets the desired
condition during any scan command.
The track address from the sector ID field is different from the track address
maintained inside the FDC and is equal to FFh which indicates a bad track.
Set when the FDC cannot detect a data address mark or a deleted data
address mark.
Status Registers 3
Bit Name R/W Default Description
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F71883
7 Reserved - - Unused. This bit is always “0”.
6 WP R - Write Protect.
Indicates the status of WPT# pin.
5 Reserved R - Unused. This bit is always “1”.
4 T0 R - Track 0.
Indicates the status of the TRK0# pin.
3 Reserved. R - Unused. This bit is always “1”.
2 HD R - Head Address.
Indicates the status of the HDSEL# pin.
1 DS1 R -
0 DS0 R -
Digital Input Register (PC-AT Mode) Base + 7
Bit Name R/W Default Description
Drive Select.
These two bits indicate the DS1, DS0 bits in the command phase.
7 DSKCHG R - This bit indicates the complement of DSKCHG# disk interface input.
6-0 Reserved R - Reserved.
Digital Input Register (PS/2 Mode) Base + 7
Bit Name R/W Default Description
7 DSKCHG R - This bit indicates the complement of DSKCHG# disk interface input.
6-3 Reserved - - Reserved.
2-1 DRATE R 10 These bits indicate the status of the DRATE programmed through the Data
Rate Select Register or Configuration Control Register.
0 HIGHDEN_N R 1 0: 1Mbps or 500Kbps data rate is chosen.
1: 300Kbps or 250Kbps data rate is chosen.
Digital Input Register (Model 30 Mode) Base + 7
Bit Name R/W Default Description
7 DSKCHG_N R - This bit indicates the state of DSKCHG# disk interface input.
6-4 Reserved - - Reserved.
3 DMAEN R 0 This bit reflects the DMA bit in Digital Output Register.
2 NOPRE R 0 This bit reflects the NOPRE bit in Configuration Control Register.
1-0 DRATE R 10 These bits indicate the status of DRATE programmed through the Data Rate
Select Register or Configuration Control Register.
Configuration Control Register (PC-AT and PS/2 Mode) Base + 7
Bit Name R/W Default Description
7-2 Reserved - - Reserved.
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F71883
1-0 DRATE W 10 These bit determine the data rate of the floppy controller. See DRATE bits in
Data Rate Select Register.
Configuration Control Register (Model 30 Mode) Base + 7
Bit Name R/W Default Description
7-3 Reserved - - Reserved.
2 NOPRE W 0 This bit could be programmed through Configuration Control Register and be
read through the bit 2 in Digital Input Register in Model 30 Mode. But it has no
functionality.
1-0 DRATE W 10 These bit determine the data rate of the floppy controller. See DRATE bits in
Data Rate Select Register.
FDC Commands
Terminology:
C Cylinder Number 0 -256
D Data Pattern
DIR Step Direction
0: step out
1: step in
DS0 Drive Select 0
DS1 Drive Select 1
DTL Data Length
EC Enable Count
EOT End of Track
EFIFO Enable FIFO
0: FIFO is enabled.
1: FIFO is disabled.
EIS Enable Implied Seek
FIFOTHR FIFO Threshold
GAP Alters Gap Length
GPL Gap Length
H/HDS Head Address
HLT Head Load Time
HUT Head Unload Time
LOCK Lock EFIFO, FIFOTHR, PTRTRK bits.
Prevent these bits from being affected by software reset.
MFM MFM or FM mode
0: FM
1: MFM
MT Multi-Track
N Sector Size Code. All values up to 07h are allowable.
00: 128 bytes
01: 256 bytes
.. ..
07 16 Kbytes
NCN New Cylinder Number
ND Non-DMA Mode
OW Overwritten
PCN Present Cylinder Number
POLL Polling disa ble
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F71883
0: polling is enabled.
1: polling is disabled.
PRETRK Precompensation Start Track Number
R Sector address
RCN Relative Cylinder Number
SC Sector per Cylinder
SK Skip deleted data address mark
SRT Step Rate Time
ST0 Status Register 0
ST1 Status Register 1
ST2 Status Register 2
ST3 Status Register 3
WGATE Write Gate alters timing of WE.
Read Data
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W MT MFM SK 0 0 1 1 0 Command code
W 0 0 0 0 0 HDS DS1 DS0
W ----------------------------- C ---------------------------
W ----------------------------- H ---------------------------
W ----------------------------- R ---------------------------
W ------------------------------ N ---------------------------
W ---------------------------- EOT --------------------------
W ---------------------------- GPL --------------------------
W ---------------------------- DTL --------------------------
Execution Data transfer
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
R ----------------------------- N ---------------------------
Sector ID
information prior to
command
execution
between the FDD
and system
Status information
after command
execution.
Sector ID
information after
command
execution.
Read Deleted Data
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W MT MFM SK 0 1 1 0 0 Command code
W 0 0 0 0 0 HDS DS1 DS0
W ----------------------------- C ---------------------------
W ----------------------------- H ---------------------------
Nov., 2006
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Sector ID
information prior to
command
execution
V0.23P
Page 29
F71883
W ----------------------------- R ---------------------------
W ------------------------------ N ---------------------------
W ---------------------------- EOT --------------------------
W ---------------------------- GPL --------------------------
W ---------------------------- DTL --------------------------
Execution Data transfer
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
R ----------------------------- N ---------------------------
Read A Track
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 MFM 0 0 0 0 1 0 Command code
W 0 0 0 0 0 HDS DS1 DS0
W ----------------------------- C ---------------------------
W ----------------------------- H ---------------------------
W ----------------------------- R ---------------------------
between the FDD
and system
Status information
after command
execution.
Sector ID
information after
command
execution.
Sector ID
information prior to
command
execution
W ------------------------------ N ---------------------------
W ---------------------------- EOT --------------------------
W ---------------------------- GPL --------------------------
W ---------------------------- DTL --------------------------
Execution Data transfer
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
R ----------------------------- N ---------------------------
Nov., 2006
-23-
between the FDD
and system. FDD
reads contents of
all cylinders from
index hole to EOT.
Status information
after command
execution.
Sector ID
information after
command
execution.
V0.23P
Page 30
F71883
Read ID
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 MFM 0 0 1 0 1 0 Command code
W 0 0 0 0 0 HDS DS1 DS0
Execution The first correct ID
information on the
cylinder is stored in
Data Register.
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
Status information
after command
execution.
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
Disk status after
the command has
been completed.
R ----------------------------- N ---------------------------
Verify
Command W MT MFM SK 1 0 1 1 0 Command code
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
W EC 0 0 0 0 HDS DS1 DS0
W ----------------------------- C ---------------------------
W ----------------------------- H ---------------------------
W ----------------------------- R ---------------------------
W ------------------------------ N ---------------------------
W ---------------------------- EOT --------------------------
W ---------------------------- GPL --------------------------
Sector ID
information prior to
command
execution
W -------------------------- DTL/SC ------------------------
Execution No data transfer
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
R ----------------------------- N ---------------------------
Version
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Nov., 2006
-24-
Status information
after command
execution.
Sector ID
information after
command
execution.
V0.23P
Page 31
F71883
Command W 0 0 0 1 0 0 0 0 Command code
Result R 1 0 0 1 0 0 0 0 Enhanced
controller
Write Data
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W MT MFM 0 0 0 1 0 1 Command code
W 0 0 0 0 0 HDS DS1 DS0
W ----------------------------- C ---------------------------
W ----------------------------- H ---------------------------
W ----------------------------- R ---------------------------
W ------------------------------ N ---------------------------
W ---------------------------- EOT --------------------------
Sector ID
information prior to
command
execution
W ---------------------------- GPL --------------------------
W ---------------------------- DTL --------------------------
Execution Data transfer
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
between the FDD
and system.
Status information
after command
execution.
Sector ID
information after
command
execution.
Write Deleted Data
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W MT MFM 0 0 1 0 0 1 Command code
R ----------------------------- N ---------------------------
W 0 0 0 0 0 HDS DS1 DS0
W ----------------------------- C ---------------------------
W ----------------------------- H ---------------------------
W ----------------------------- R ---------------------------
W ------------------------------ N ---------------------------
W ---------------------------- EOT --------------------------
W ---------------------------- GPL --------------------------
W ---------------------------- DTL --------------------------
Nov., 2006
-25-
Sector ID
information prior to
command
execution
V0.23P
Page 32
F71883
Execution Data transfer
between the FDD
and system.
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
Status information
after command
execution.
Format A Track
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
R ----------------------------- N ---------------------------
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 MFM 0 0 1 1 0 1 Command code
W 0 0 0 0 0 HDS DS1 DS0
W ------------------------------ N --------------------------- Bytes/Sector
Sector ID
information after
command
execution.
W ---------------------------- SC -------------------------- Sectors/Cylinder
W ---------------------------- GPL -------------------------- Gap 3 Length
W ----------------------------- D --------------------------- Data Pattern
Execution
for each
sector
( repeat )
------------------------------ C ---------------------------
W ------------------------------ H ---------------------------
W ------------------------------ R ---------------------------
Input sector
parameter.
W ----------------------------- N --------------------------
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
R ------------------------- Undefined ----------------------
R ------------------------- Undefined ----------------------
R -------------------------- Undefined -----------------------
Status information
after command
execution.
R ------------------------- Undefined ----------------------
Recalibrate
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 0 0 1 1 1 Command code
W 0 0 0 0 0 0 DS1 DS0
Execution Head retracted to
track 0
Nov., 2006
-26V0.23P
Page 33
Sense Interrupt Status
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 0 1 0 0 0 Command code
Result R ---------------------------- ST0 --------------------------
R ---------------------------- PCN --------------------------
Specify
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 0 0 0 1 1 Command code
W |------------------ SRT -------------------| |------------------ HUT -------------------|
W |------------------------------------- SRT ---------------------------------------| ND
Seek
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 0 1 1 1 1 Command code
W 0 0 0 0 0 HDS DS1 DS0
W ---------------------------- NCN --------------------------
Execution Head positioned
F71883
over proper
cylinder on diskette
Configure
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 1 0 0 1 1 Command code
Execution Internal registers
Relative Seek
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 1 DIR 0 0 1 1 1 1 Command code
Perpendicular Mode
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 1 0 0 1 0 Command code
W 0 0 0 0 0 HDS DS1 DS0
W 0 EIS EFIFO POLL |---------------- FIFOTHR ---------------|
W ---------------------------- PRETRK --------------------------
written
W 0 0 0 0 0 HDS DS1 DS0
W ---------------------------- RCN --------------------------
W OW 0 D3 D2 D1 D0 GAP WGATE
Nov., 2006
-27V0.23P
Page 34
F71883
Lock
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W LOCK 0 0 1 0 1 0 0 Command code
Result R 0 0 0 LOCK 0 0 0 0
Dumpreg
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 0 1 1 1 0 Command code
Result R -------------------------- PCN ( Drive 0 ) ------------------------
R -------------------------- PCN ( Drive 0 ) ------------------------
R -------------------------- PCN ( Drive 0 ) ------------------------
R -------------------------- PCN ( Drive 0 ) ------------------------
Sense Drive Status
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 0 0 1 0 0 Command code
Result R ---------------------------- ST3 -------------------------- Status information
Invalid
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W ---------------------------- Invalid Codes -------------------------- FDC goes to
Result R ---------------------------- ST0 -------------------------- ST0 = 80h
R |------------------ SRT -------------------| |------------------ HUT -------------------|
R |------------------------------------- SRT ---------------------------------------| ND
R -------------------------- SC/EOT ------------------------
R LOCK 0 D3 D2 D1 D0 GAP WGATE
R 0 EIS EFIFO POLL |---------------- FIFOTHR ---------------|
R ---------------------------- PRETRK --------------------------
W 0 0 0 0 0 HDS DS1 DS0
abut disk drive
standby state.
7.3 UART
The F71883 provides two UART ports and supports IRQ sharing for system application.
The UARTs are used to convert data between parallel format and serial format. They convert
parallel data into serial format on transmission and serial format into parallel data on receiver
Nov., 2006
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F71883
side. The serial format is formed by one start bit, followed by five to eight data bits, a parity bit
if programmed and one ( 1.5 or 2 ) stop bits. The UARTs include complete modem control
capability and an interrupt system that may be software trailed to the computing time required
to handle the communication link. They have FIFO mode to reduce the number of interrupts
presented to the host. Both receiver and transmitter have a 16-byte FIFO.
The below content is about the UART1 and UART2 device register descriptions. All the
registers are for software porting reference.
Receiver Buffer Register Base + 0
Bit Name R/W Default Description
7-0 RBR R 00h
The data received.
Read only when LCR[7] is 0
Transmitter Holding Register Base + 0
Bit Name R/W Default Description
7-0 THR W 00h
Data to be transmitted.
Write only when LCR[7] is 0
Divisor Latch (LSB) Base + 0
Bit Name R/W Default Description
7-0 DLL R/W 01h
Divisor Latch (MSB) Base + 1
Bit Name R/W Default Description
7-0 DLM R/W 00h
Interrupt Enable Register Base + 1
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3 EDSSI R/W 0 Enable Modem Status Interrupt. Access only when LCR[7] is 0.
2 ELSI R/W 0 Enable Line Status Error Interrupt. Access only when LCR[7] is 0.
1 ETBFI R/W 0 Enable Transmitter Holding Register Empty Interrupt. Access only when
0 ERBFI R/W 0 Enable Received Data Available Interrupt. Access only when LCR[7] is 0.
Baud generator divisor low byte.
Access only when LCR[7] is 1.
Baud generator divisor high byte.
Access only when LCR[7] is 1.
LCR[7] is 0.
Interrupt Identification Register Base + 2
Bit Name R/W Default Description
7 FIFO_EN R 0
Nov., 2006
0: FIFO is disabled
1: FIFO is enabled.
-29V0.23P
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F71883
6 FIFO_EN R 0
5-4 Reserved - - Reserved.
3-1 IRQ_ID R 000
0 IRQ_PENDN R 1
FIFO Control Register Base + 2
Bit Name R/W Default Description
7-6 RCV_TRIG W 00
5-3 Reserved - - Reserved.
2 CLRTX R 0
1 CLRRX R 0
0 FIFO_EN R 0
0: FIFO is disabled
1: FIFO is enabled.
000: Interrupt is caused by Modem Status
001: Interrupt is caused by Transmitter Holding Register Empty
010: Interrupt is caused by Received Data Available.
110: Interrupt is caused by Character Timeout
011: Interrupt is caused by Line Status.
1: Interrupt is not pending.
0: Interrupt is pending.
00: Receiver FIFO trigger level is 1.
01: Receiver FIFO trigger level is 4.
10: Receiver FIFO trigger level is 8.
11: Receiver FIFO trigger level is 14.
Reset the transmitter FIFO.
Reset the receiver FIFO.
0: Disable FIFO.
1: Enable FIFO.
Line Control Register Base + 3
Bit Name R/W Default Description
7 DLAB R/W 0
6 SETBRK R/W 0
5 STKPAR R/W 0
4 EPS R/W 0
3 PEN R/W 0
2 STB R/W 0
1-0 WLS R/W 00
MODEM Control Register Base + 4
Bit Name R/W Default Description
7-5 Reserved - -
4 LOOP R/W 0
3 OUT2 R/W 0
0: Divisor Latch can’t be accessed.
1: Divisor Latch can be accessed via Base and Base+1.
0: Transmitter is in normal condition.
1: Transmit a break condition.
XX0: Parity Bit is disable
001: Parity Bit is odd.
011: Parity Bit is even
101: Parity Bit is logic 1
111: Parity Bit is logic 0
0: Stop bit is one bit
1: When word length is 5 bit stop bit is 1.5 bit
else stop bit is 2 bit
00: Word length is 5 bit
01: Word length is 6 bit
10: Word length is 7 bit
11: Word length is 8 bit
Reserved.
0: UART in normal condition.
1: UART is internal loop back
0: All interrupt is disabled.
1: Interrupt is enabled (disabled) by IER.
Nov., 2006
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F71883
2 OUT1 R/W 0
1 RTS R/W 0
0 DTR R/W 0
Line Status Register Base + 5
Bit Name R/W Default Description
7 RCR_ERR R 0
6 TEMT R 1
5 THRE R 1
4 BI R 0
3 FE R 0
2 PE R 0
1 OE R 0
0 DR R 0
Read from MSR[6] is loop back mode
0: RTS# is forced to logic 1
1: RTS# is forced to logic 0
0: DTR# is forced to logic 1
1: DTR# is forced to logic 0
0: No error in the FIFO when FIFO is enabled
1: Error in the FIFO when FIFO is enabled.
0: Transmitter is in transmitting.
1: Transmitter is empty.
0: Transmitter Holding Register is not empty.
1: Transmitter Holding Register is empty.
0: No break condition detected.
1: A break condition is detected.
0: Data received has no frame error.
1: Data received has frame error.
0: Data received has no parity error.
1: Data received has parity error.
0: No overrun condition occurred.
1: An overrun condition occurred.
0: No data is ready for read.
1: Data is received.
MODEM Status Register Base + 6
Bit Name R/W Default Description
7 DCD R -
6 RI R -
5 DSR R -
4 CTS R -
3 DDCD R 0
2 TERI R 0
1 DDSR R 0
0 DCTS R 0
Scratch Register Base + 7
Bit Name R/W Default Description
7-0 SCR R/W 00h
Complement of DCD# input. In loop back mode, this bit is equivalent to OUT2
in MCR.
Complement of RI# input. In loop back mode , this bit is equivalent to OUT1 in
MCR
Complement of DSR# input. In loop back mode , this bit is equivalent to DTR in
MCR
Complement of CTS# input. In loop back mode , this bit is equivalent to RTS in
MCR
0: No state changed at DCD#.
1: State changed at DCD#.
0: No Trailing edge at RI#.
1: A low to high transition at RI#.
0: No state changed at DSR#.
1: State changed at DSR#.
0: No state changed at CTS#.
1: State changed at CTS#.
Scratch register.
Nov., 2006
-31V0.23P
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F71883
7.4 Parallel Port
The parallel port in F71883 supports an IBM XT/AT compatible parallel port ( SPP ),
bi-directional paralle port ( BPP ), Enhanced Parallel Port ( EPP ), Extended Capabilities
Parallel Port ( ECP ) mode. Refer to the configuration registers for more information on
selecting the mode of operation.
The below content is about the Parallel Port device register descriptions. All the
registers are for software porting reference.
Parallel Port Data Register Base + 0
Bit Name R/W Default Description
7-0 DATA R/W 00h The output data to drive the parallel port data lines.
ECP Address FIFO Register Base + 0
Bit Name R/W Default Description
7-0 ECP_AFIFO R/W 00h
Device Status Register Base + 1
Bit Name R/W Default Description
7 BUSY_N R - Inverted version of parallel port signal BUSY.
6 ACK_N R - Version of parallel port signal ACK#.
Access only in ECP Parallel Port Mode and the ECP_MODE programmed in
the Extended Control Register is 011.
The data written to this register is placed in the FIFO and tagged as an
Address/RLE. It is auto transmitted by the hardware. The operation is only
defined for forward direction. It divide into two parts :
Bit 7 :
0: bits 6-0 are run length, indicating how many times the next byte to appear (0
= 1time, 1 = 2times, 2 = 3times and so on).
1: bits 6-0 are a ECP address.
Bit 6-0 :
Address or RLE depends on bit 7.
5 PERROR R - Version of parallel port signal PE.
4 SELECT R - Version of parallel port signal SLCT.
3 ERR_N R - Version of parallel port signal ERR#.
2-1 Reserved R 11 Reserved. Return 11b when read.
Nov., 2006
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F71883
0 TMOUT R - This bit is valid only in EPP mode. Return 1 when in other modes.
It indicates that a 10uS time out has occurred on the EPP bus.
0: no time out error.
1: time out error occurred, write 1 to clear.
Device Control Register Base + 2
Bit Name R/W Default Description
7-6 Reserved - 11 Reserved. Return 11b when read.
5 DIR R/W 0 0: the parallel port is in output mode.
1: the parallel port is in input mode.
It is auto reset to 0 when in SPP mode.
4 ACKIRQ_EN R/W 0 Enable an interrupt at the rising edge of ACK#.
3 SLIN R/W 0 Inverted and then drives the parallel port signal SLIN#.
2 INIT_N R/W 0 Drives the parallel port signal INIT#.
1 AFD R/W 0 Inverted and then drives the parallel port signal AFD#.
0 STB R/W 0 Inverted and then drives the parallel port signal STB#.
When read, the status of inverted SLIN# is return.
When read, the status of INIT# is return.
When read, the status of inverted AFD# is return.
When read, the status of inverted STB# is return.
EPP Address Register Base + 3
Bit Name R/W Default Description
7-0 EPP_ADDR R/W 00h
EPP Data Register Base + 4 – Base + 7
Bit Name R/W Default Description
7-0 EPP_DATA R/W 00h
Parallel Port Data FIFO Base + 400h
Bit Name R/W Default Description
7-0 C_FIFO R/W 00h Data written to this FIFO is auto transmitted by the hardware to the device by
Write this register will cause the hardware to auto transmit the written data to
the device with the EPP Address Write protocol.
Read this register will cause the hardware to auto receive data from the device
by with the EPP Address Read protocol.
Write this register will cause the hardware to auto transmit the written data to
the device with the EPP Data Write protocol.
Read this register will cause the hardware to auto receive data from the device
by with the EPP Data Read protocol.
using standard parallel port protocol.
It is only valid in ECP and the ECP_MODE is 010b.The operation is only for
forward direction.
Nov., 2006
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F71883
ECP Data FIFO Base + 400h
Bit Name R/W Default Description
7-0 ECP_DFIFO R/W 00h Data written to this FIFO when DIR is 0 is auto transmitted by the hardware to
the device by using ECP parallel port protocol.
Data is auto read from device into the FIFO when DIR is 1 by the hardware by
using ECP parallel port protocol. Read the FIFO will return the content to the
system.
It is only valid in ECP and the ECP_MODE is 011b.
ECP Test FIFO Base + 400h
Bit Name R/W Default Description
7-0 T_FIFO R/W 00h Data may be read, written from system to the FIFO in any Direction. But no
hardware handshake occurred on the parallel port lines. It could be used to test
ECP Configuration Register A Base + 400h
Bit Name R/W Default Description
the empty, full and threshold of the FIFO.
It is only valid in ECP and the ECP_MODE is 110b.
7 IRQ_MODE R 0 0: interrupt is ISA pulse.
1: interrupt is ISA level.
Only valid in ECP and ECP_MODE is 111b.
6-4 IMPID R 001 000: the design is 16-bit implementation.
001: the design is 8-bit implementation (default).
010: the design is 32-bit implementation.
011-111: Reserved.
Only valid in ECP and ECP_MODE is 111b.
3 Reserved - - Reserved.
2 BYTETRAN_N R 1 0: when transmitting there is 1 byte waiting in the transceiver that does not
affect the FIFO full condition.
1: when transmitting the state of the full bit includes the byte being transmitted.
Only valid in ECP and ECP_MODE is 111b.
1-0 Reserved R 00 Return 00 when read.
Only valid in ECP and ECP_MODE is 111b.
ECP Configuration Register B Base + 401h
Bit Name R/W Default Description
7 COMP R 0 0: only send uncompressed data.
1: compress data before sending.
Only valid in ECP and ECP_MODE is 111b.
6 Reserved R 1 Reserved. Return 1 when read.
Only valid in ECP and ECP_MODE is 111b.
Nov., 2006
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F71883
5-3 ECP_IRQ_CH R 001 000: the interrupt selected with jumper.
001: select IRQ 7 (default).
010: select IRQ 9.
011: select IRQ 10.
100: select IRQ 11.
101: select IRQ 14.
110: select IRQ 15.
111: select IRQ 5.
Only valid in ECP and ECP_MODE is 111b.
2-0 ECP_DMA_CH R 011 Return the DMA channel of ECP parallel port.
Only valid in ECP and ECP_MODE is 111b.
Extended Control Register Base + 402h
Bit Name R/W Default Description
7-5 ECP_MODE R/W 000 000: SPP Mode.
4 ERRINTR_EN R/W 0 0: disable the interrupt generated on the falling edge of ERR#.
3 DAMEN R/W 0 0: disable DMA.
2 SERVICEINTR R/W 1 0: enable the following case of interrupt.
1 FIFOFULL R 0 0: The FIFO has at least 1 free byte.
0 FIFOEMPTY R 0 0: The FIFO contains at least 1 byte.
001: PS/2 Parallel Port Mode.
010: Parallel Port Data FIFO Mode.
011: ECP Parallel Port Mode.
100: EPP Mode.
101: Reserved.
110: Test Mode.
111: Configuration Mode.
Only valid in ECP.
1: enable the interrupt generated on the falling edge of ERR#.
1: enable DMA. DMA starts when SERVICEINTR is 0.
DMAEN = 1: DMA mode.
DMAEN = 0, DIR = 0: set to 1 whenever there are writeIntrThreshold or more
bytes are free in the FIFO.
DMAEN = 0, DIR = 0: set to 1 whenever there are readIntrThreshold or more
bytes are valid to be read in the FIFO.
1: The FIFO is completely full.
1: The FIFO is completely empty.
7.5 Hardware Monitor
For the 8-bit ADC has the 8mv LSB, the maximum input voltage of the analog pin is
2.048V. Therefore the voltage under 2.048V (ex:1.5V) can be directly connected to these
analog inputs. The voltage higher than 2.048V should be reduced by a factor with external
Nov., 2006
-35V0.23P
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F71883
resistors so as to obtain the input range. Only 3Vcc is an exception for it is main power of the
F71883. Therefore 3Vcc can directly connect to this chip’s power pin and need no external
resistors. There are two functions in this pin with 3.3V. The first function is to supply internal
analog power of the F71883 and the second function is that voltage with 3.3V is connected to
internal serial resistors to monitor the +3.3V voltage. The internal serial resistors are two 150K
ohm, so that the internal reduced voltage is half of +3.3V.
There are four voltage inputs in the F71883 and the voltage divided formula is shown as
follows:
R
2
×=
VVIN
V
+
If we choose R1=27K, R2=5.1K, the exact input voltage for V+12v will be 1.907V, which
is within the tolerance. As for application circuit, it can be refer to the figure shown as follows.
12
RR
+
21
where V
is the analog input voltage, for example.
+12V
Voltage Inputs
3Vcc
VIN (Lower than 2.304V)
VIN(Higher than
(directly connect to the chip)
(directly connect to the chip)
VIN1(Max2.304V)
R1
R2
150K
VIN3.3
150K
8-bit ADC
with
VREF
Typical BJT
Connection
2N3906
R
10K, 1%
R
THM
10K, 25 C
Pin 1
Pin 3, 4 or 5
Typical Thermister
Connection
8 mV LSB
D+
D-
Fig 7-1
SMI# interrupt for voltage is shown as figure. Voltage exceeding or going below high
limit will cause an interrupt if the previous interrupt has been reset by writing “1” all the
interrupt Status Register. Voltage exceeding or going below low limit will result the same
condition as voltage exceeding or going below high limit.
Nov., 2006
-36-
V0.23P
Page 43
(
)
(p
)
F71883
ulse mode
level mode
*Interrupt Reset when Interrupt Status Registers are written 1
**
Voltage SMI# Mode
*
* * * *
*
Fig 7-2
The F71883 monitors three remote temperature sensors. One of these sensors can be
measured from -20°C to 127°C. The others can be measured from 0°C to 145°C (2 Sets) .More
detail please refer register description.
Remote-sensor transistor manufacturers
Manufacturer Model Number
Panasonic 2SB0709 2N3906
Philips PMBT3906
Monitor Temperature from “thermistor”
The F71883 can connect three thermistor to measure environment temperature or
remote temperature. The specification of thermistor should be considered to (1) β value is
3435K (2) resistor value is 10K ohm at 25°C. In the Figure 7-1, the thermistor is connected by
a serial resistor with 10K ohm, then connected to VREF.
Monitor Temperature from “thermal diode”
Also, if the CPU, GPU or external circuits provide thermal diode for temperature
measurement, the F71883 is capable to these situations. The build-in reference table is for
PNP 2N3906 transistor, and each different kind of thermal diode should be matched with
specific offset and BJT gain. In the Figure 7-1, the transistor is directly connected into
temperature pins.
ADC Noise Filtering
The ADC is integrating type with inherently good noise rejection. Micro-power operation
Nov., 2006
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F71883
places constraints on high-frequency noise rejection; therefore, careful PCB board layout and
suitable external filtering are required for high-accuracy remote measurement in electronically
noisy environment. High frequency EMI is best filtered at D+ and D- with an external 2200pF
capacitor. Too high capacitance may introduce errors due to the rise time of the switched
current source. Nearly all noise sources tested cause the ADC measurement to be higher
than the actual temperature, depending on the frequency and amplitude.
Over Temperature Signal (OVT#)
OVT# alert for temperature is shown as figure 7-3. When monitored temperature
exceeds the over-temperature threshold value, OVT# will be asserted until the temperature
goes below the hysteresis temperature.
To
T
HYST
OVT#
Fig 7-3
Temperature PME#
PME# interrupt for temperature is shown as figure 7-4. Temperature exceeding high limit
or going below hysteresis will cause an interrupt if the previous interrupt has been reset by
writing “1” all the interrupt Status Register.
To
T
HYST
SMI#
(pulse mode)
(level mode
active low)
*Interrupt Reset when Interrupt Status Registers are written 1
*
*
*
*
Nov., 2006
-38V0.23P
Page 45
R
F71883
Fig 7-4
Fan speed count
Inputs are provided by the signals from fans equipped with tachometer outputs. The
level of these signals should be set to TTL level, and maximum input voltage cannot be over
5V. If the input signals from the tachometer outputs are over the 5V, the external trimming
circuit should be added to reduce the voltage to obtain the input specification. The normal
circuit and trimming circuits are shown as follows:
+12V
+12V
FAN Out
GND
Pull-up resister
4.7K Ohms
22K~30K
Fan Input
10K
FANIN 1
F71883
Fan with Tach Pull-Up to +12V, or Totern-Pole
Output and Register Attenuator
Fig 7-5 / 7-6
+5V
Pull-up resister
4.7K Ohms
+5V
FAN Out
GND
1K~2.7K
Fan Input
10K
FANIN1
F71883
+12V
Pull-up resister < 1K
or totem-pole output
+12V
FAN Out
GND
FAN
Connector
Fan with Tach Pull-Up to +12V, or
Totem-Pole Putput and Zener Clamp
+5V
+5V
FAN Out
GND
FAN
Connector
> 1K
3.3V Zener
Pull-up resister < 1K
or totem-pole output
> 1K
3.3V Zener
Fan Input
Fan Input
FANIN 1
F71883
FANIN1
F71883
Fan with Tach Pull-Up to +5V, or Totern-Pole
Output and Register Attenuator
Fig 7-7 / 7-8
Fan with Tach Pull-Up to +5V, or
Totem-Pole Putput and Zener Clamp
Determine the fan counter according to:
6
105.1 ×
=
Count
In other words, the fan speed counter has been read from register, the fan speed can be
evaluated by the following equation. As for fan, it would be best to use 2 pulses tachometer
output per round.
Nov., 2006
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PM
V0.23P
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F71883
6
=
105.1 ×
Count
RPM
Fan speed control
The F71883 provides 2 fan speed control methods:
1. LINEAR FAN CONTROL 2. PWM DUTY CYCLE
Linear Fan Control
The range of DC output is 0~3.3V, controlled by 8-bit register. 1 LSB is about 0.013V.
The output DC voltage is amplified by external OP circuit, thus to reach maximum FAN
OPERATION VOLTAGE, 12V. The output voltage will be given as followed:
ValueRegister 8bit Programmed
3.3(V) tageOutput_vol ×=
255
And the suggested application circuit for linear fan control would be:
12V
84
PMOS
1
JP1
R10K
DC FAN Control with OP
C
47u
CON3
3
2
1
1N4148
D1
C
0.1u
R
4.7K
R27K
R
10K
FANIN MONITOR
DC OUTPUT VOLTAGE
3.9K
3
+
2
-
LM358
R
Fig 7-9
PWM duty Fan Control
The duty cycle of PWM can be programmed by a 8-bit register. The default duty cycle is
set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be
represented as follows.
(%)Duty_cycle ×=
ValueRegister 8bit Programmed
%100
255
Nov., 2006
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F71883
+12V
+5V
R1
R2
D
G
NMOS
S
+
-
PWM Clock Input
R1
R2
D
G
NMOS
S
PNP Transistor
+
C
-
PWM Clock Input
FAN
Fig 7-10
Fan speed control mechanism
There are some modes to control fan speed and they are 1.Manual mode, 2.Stage auto
mode, 3. Linear auto mode. More detail, please refer the description of registers.
Manual mode
For manual mode, it generally acts as software fan speed control.
Stage auto mode
PNP Transistor
C
FAN
At this mode, the F71883 provides automatic fan speed control related to temperature
variation of CPU/GPU or the system. The F71883 can provide four temperature boundaries
and five intervals, and each interval has its related fan speed count. All these values should
be set by BIOS first. Take figure 7-11 as example. When temperature boundaries are set as
45, 55, 65, and 75°C and there are five intervals (each interval is 10(C). The related desired
fan speed counts for each interval are 0500h, 0400h, 0300h, 0200h and 0100h. When the
temperature is within 55~65(C, the fan speed count 300h will be load into FAN EXPECT
COUNT that define in registers. Then, the F71883 will adjust PWMOUT duty-cycle to meet the
expected value. It can be said that the fan will be turned on with a specific speed set by BIOS
and automatically controlled with the temperature variation. The F71883 will take charge of all
the fan speed control and need no software support.
Desired Counts
75 Degree C
65 Degree C
55 Degree C
45 Degree C
0100h
0200h
0300h
0400h
0500h
Figure 7-11
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F71883
There are some examples as below:
A. Stage auto mode (PWM Duty)
Set temperature as 60°C, 50°C, 40°C, 30°C and Duty as 100%, 90%, 80%, 70%, 60%
PWM duty
60 Degree C
50 Degree C
hysteresis 47 Degree C
40 Degree C
30 Degree C
Temp.
Fan Speed
100%
90%
80%
70%
60%
ab cd
0xFF
0xE5
0xCC
0xB2
0x99
a. Once temp. is under 30°C, the lowest fan speed keeps 60% PWM duty
b. Once temp. is over 30°C,40°C,50°C, the fan speed will vary from 60% to 90% PWM duty
and increase with temp. level.
c. Once temp. keeps in 55°C, fan speed keeps in 90% PWM duty
d. If set the hysteresis as 3°C (default 4°C), once temp reduces under 47°C, fan speed
reduces to 80% PWM duty and stays there.
B. Stage auto mode (RPM%)
Set temperature as 60°C, 50°C, 40°C, 30°C and assume the Full Speed is 6000rpm, set
90% of full speed RPM(5400rpm), 80%(4800rpm), 70%(4200rpm), 60%(3600rpm) of full
speed RPM
60 Degree C
50 Degree C
hysteresis 47 Degree C
40 Degree C
30 Degree C
Temp.
Fan Speed
ab cd
6000RPM
90%(5400RPM)
80%(4800RPM)
70%(4200RPM)
60%(3600RPM)
a. Once temp. is under 30°C, the lowest fan speed keeps 60% of full speed (3600RPM).
b. Once temp. is over 30°C,40°C,50°C, the fan speed will vary from 3600RPM to 5400RPM
and increase with temp. level.
c. Once temp. keeps in 55°C, fan speed keeps in 90% of full speed (5400RPM)
d. If set the hysteresis as 3°C (default 4°C), once temp reduces under 47°C, fan speed
reduces to 4800RPM and stays there.
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F71883
Linear auto mode
Otherwise, F71883 supports linear auto mode. Below has two examples to describe this
mode. More detail, please refer the register description.
A. Linear auto mode (PWM Duty I)
Set temperature as 70°C, 60°C, 50°C, 40°C and Duty as 100%, 70%, 60%, 50%, 40%
PWM duty
70 Degree C
hysteresis 65 Degree C
60 Degree C
50 Degree C
40 Degree C
Temp.
Fan Speed
a. Once temp. is under 40°C, the lowest fan speed keeps 40% PWM duty
ab c d
100%
70%
60%
50%
40%
b. Once temp. is over 40°C,50°C,60°C, the fan speed will vary from 40% to 70% PWM duty
and linearly increase with temp. variation. The temp.-fan speed monitoring and flash
interval is 1sec.
c. Once temp. goes over 70°C, fan speed will directly increase to 100% PWM duty (full
speed)
d. If set the hysteresis as 5°C(default is 4°C), once temp reduces under 65°C (not 70°C),
fan speed reduces from 100% PWM duty and decrease linearly with temp..
B. Linear auto mode (RPM%)
Set temperature as 70°C, 60°C, 50°C, 40°C and if full speed is 6000RPM, setting 100%,
70%, 60%, 50%, 40% of full speed.
70 Degree C
hysteresis 65 Degree C
60 Degree C
50 Degree C
40 Degree C
Temp.
Fan Speed
ab c d
6000RPM
70%(4200RPM)
60%(3600RPM)
50%(3000RPM)
40%(2400RPM)
a. Once temp. is under 40°C, the lowest fan speed keeps 40% of full speed (2400RPM)
b. Once temp. is over 40°C,50°C,60°C, the fan speed will vary from 40% to 70% of full
Nov., 2006
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F71883
speed and almost linearly increase with temp. variation. The temp.-fan speed
monitoring and flash interval is 1sec.
c. Once temp. goes over 70°C, fan speed will directly increase to full speed 6000RPM.
If set the hysteresis as 5°C, once temp reduces under 65°C (not 70°C), fan speed reduces from
full speed and decrease linearly with temp..
PWMOUT Duty-cycle operating process
In both “Manual RPM” and “Temperature RPM” modes, the F71883 adjust PWMOUT
duty-cycle according to current fan count and expected fan count. It will operate as follows:
(1). When expected count is 0xFFF, PWMOUT duty-cycle will be set to 0x00 to turn off
fan.
(2). When expected count is 0x000, PWMOUT duty-cycle will be set to 0xFF to turn on
fan with full speed.
(3). If both (1) and (2) are not true,
(4). When PWMOUT duty-cycle decrease to MIN_DUTY(≠ 00h), obviously the
duty-cycle will decrease to 00h next, the F71883 will keep duty-cycle at 00h for 1.6
seconds. After that, the F71883 starts to compare current fan count and expected
count in order to increase or decrease its duty-cycle. This ensures that if there is
any glitch during the period, the F71883 will ignore it.
Start Duty
Stop Duty
Fig 7-12
FAN_FAULT#
Fan_Fault# will be asserted when the fan speed doesn’t meet the expected fan speed
within a programmable period (default is 11 seconds) or when fan stops with respect to PWM
duty-cycle which should be able to turn on the fan. There are two conditions may cause the
FAN_FAULT# event.
(1). When PWM_Duty reaches 0xFF, the fan speed count can’t reach the fan expected
count in time. (Figure 7-13)
Nov., 2006
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)
F71883
Current Fan Count
Expected Fan Count
100%
Duty-cycle
Fan_Fault#
(2). After the period of detecting fan full speed, when PWM_Duty > Min. Duty, and fan
11 sec(default
Fig 7-13
count still in 0xFFF.
7.6 Keyboard Controller
used with IBM(-compatible personal computers or PS/2-based systems. The controller
receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and
presents the data to the system as a byte of data in its output buffer. The controller will assert
an interrupt to the system when data are placed in its output buffer.
software porting reference.
Status Register
The status register is an 8 bits register at I/O address 64h that provides information about the status of the KBC
Bit Name R/W Default Description
7 Parity error R 0 0:odd parity
6 Time out R 0 0:no time out error
5 Auxiliary device
OBF
4 Inhinit R 0 0:keyboard is inhibited
3 Command/data R 0 0:data byte
2 SYSTEM_FLAG
1 IBF
0 OBF
The KBC provides the functions included a keyboard and a PS/2 mouse, and can be
The below content is about the KBC device register descriptions. All the registers are for
1:even parity
1:time out error
R 0 0: Auxiliary output buffer empty
1: Auxiliary output buffer full
1: keyboard is not inhibited
1:command byte
R
R
R
0 This bit is set or clear by command byte of KBC
0 0:input buffer empty
1: input buffer full
0 0:output buffer empty
1: output buffer full
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F71883
Command register
The internal KBC operation is controlled by the KBC command byte (KCCB). The KCCB resides in I/O address
64h that is read with a 20h command and written with a 60h command data.
Bit Name R/W Default Description
7 Reserved - - Reserved
6 Translate code R/W 1 0: Pass un-translated scan code.
1: Translate scan code to IBM PC standard.
5 Disable Auxiliary
Device
4 Disable Keyboard R/W 0 1: Disable keyboard inhibit function.
3 Reserved - - Reserved
2 System flag R/W 1 0: The system is executing POST as a result of a cold boot.
1 Enable Auxiliary
0 Enable keyboard
Interrupt
Interrupt
R/W 0 1: Disable Auxiliary inhibit function.
1: The system is executing POST as a result of a shutdown or warm boot.
R/W 1 0: Ao interrupt
1: A system interrupt is generated when a byte is placed in output buffer
(IRQ12).
R/W 1 0:No interrupt
1: A system interrupt is generated when a byte is placed in output buffer
(IRQ1).
DATA register
The DATA register is an 8 bits register at I/O address 60h. the KBC used the output buffer to send the scan code
received from keyboard and data byte replay by command to the system.
Power on default <7:0> = 00000000 binary
7.7 SPI Interface
Communication between the two devices is handling the serial peripheral interface (SPI).
Every SPI system consist of one master and one or more slaves, where a master provides the
SPI clock and slave receives clock from the master.
This design is only master function, for basic signal, master-out/slave-in (MOSI),
master-in/slave-out (MISO), serial clock (SCK), and 4 slaves select (SS), are needed for SPI
interface. Each of slave select supports from 512kbits to 4096kbits flash is decided by
configuration register. Serial clock (SCK) signal frequency is varied from 24MHz to 187.5 KHz.
The serial data (MOSI) for SPI interface translates to depend on SCK rising edge or falling
edge is decided by configuration register.
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F71883
7.8 80 Port
Monitor the value of 0x80 port and output the value via the signals defined for 7-segment
display. High nibble and low nibble are outputted interleaved at 1KHz frequency.
7.9 ACPI Function
The Advanced Configuration and Power Interface (ACPI) is a system for controlling the use
of power in a computer. It lets computer manufacturer and user to determine the computer’s
power usage dynamically.
There are three ACPI states that are of primary concern to the system designer and they are
designated S0, S3 and S5. S0 is a full-power state; the computer is being actively used in this
state. The other two are called sleep states and reflect different power consumption when
power-down. S3 is a state that the processor is powered down but the last procedural state is
being stored in memory which is still active. S5 is a state that memory is off and the last
procedural state of the processor has been stored to the hard disk. Take S3 and S5 as
comparison, since memory is fast, the computer can quickly come back to full-power state, the
disk is slower than the memory and the computer takes longer time to come back to full-power
state. However, since the memory is off, S5 draws the minimal power comparing to S0 and S3.
Among them, S3→S5 is illegal transition and won’t be allowed by state machine. It is necessary
to enter S0 first in order to get to S5 from S3. As for transition S5→S3 will occur only as an
immediate state during state transition from S5→S0. It isn’t allowed in the normal state transition.
be set in control register. In keep last state mode, one register will keep the status of before
power loss. If it is power on before power loss, it will remain power on when power is resumed,
otherwise, if it is power off before power loss, it will remain power off when power is resumed.
It is anticipated that only the following state transitions may happen:
S0→S3, S0→S5, S5→S0, S3→S0 and S3→S5.
The below diagram described the timing, the always on and always off, keep last state could
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F71883
VBAT
VSB
RSMRST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
DEFAULT TIMING
Always off
VBAT
VSB
RSMRST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
ALways ON TIMING
PCI Reset and PWROK Signals
The F71883 supports 3 output buffers for 3 reset signals. If the register RSTCON_EN is set to
1, the pin RSTCON# will infect PCIRST1# ~ PCIRST3# outcome. Then, the result of PCIRST#
outcome will be affected by conditions as below:
PCIRST1# Æ Output buffer of RSTCON# and LRESET#.
PCIRST2# Æ Output buffer of RSTCON# and LRESET#.
PCIRST3# Æ Output buffer of RSTCON# and LRESET#.
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F71883
+3.3V
ATXPG
RSTCON#
Delay
PWROK
RSTCON#
LRESET#
PCIRST1~3#
So far as the PWROK issue is as the figure above. PWROK is delayed 400ms (default) as
VCC arrives 2.8V, and the delay timing can be programmed by register. (100ms ~ 400ms)
In the figure, the RSTCON# will be implemented by register RSTCON_EN. If RSTCON_EN be
set to 0, the RSTCON# pin will affect PWROK output(Default). If RSTCON_EN be set to 1, the
RSTCON# pin will affect PCIRST outputs.
NORTH BRIDGE
SOUTH BRIDGE
VCC3
VCORE
CPU
5 6 4.7K
7 8 4.7K
PWOK
IDE
ATA 133
SATA*2
PCIR ST3#
PCIR ST2#
VSI
VSO
to PWM VCOR E SENSE
PCI
PCLK_1,2,3(33MHz)
VCC3
12
R89
1K
PCIR ST#
LRESET#
SUSB# S3#
PWSOUT#
RSMRST#
PCIR ST1#
1 2 4.7K
3 4 4.7K
1 21K
VSB5
12
R85
4.7K
-12V
11
12
13
14
15
16
17
18
19
20
F71882
F71883
VSB3
VCC3
ATX1
3V3
-12V
GND
PS-ON
GND
GND
GND
-5V
5V
5V
ATX CONNECTOR
3V3
3V3
GND
GND
GND
PW-OK
5VSB
12V
1
2
3
4
5V
5
6
5V
7
8
9
10
ATX CONNECTOR
ACPI Reference Circuit
RSTCON#
PWSIN #
ATXPG_I N
PS_ON#
+12V
VCC3
VCC5
12
TC1
22uF
VSB3
FRONT PANEL
12
R88
R90
4.7K
1 2
33
VSB5
12
R87
4.7K
VSB5VCC5
Tit le
Size Docum ent N umber Rev
A
Date: Sheet of
5
7
RSTGND
RESET
Front Panel
PSW+
PSW-
6
8
Featu re Integrat ion Technology Inc.
ACPI & VSI/VSO 0.1
-PWR_BTN
1 2
R91
56Monday, July 11, 2005
VSB3
12
2 1
R86
4.7K
C42
0.1UF
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F71883
7.10 AMDSI and Intel SST PECI Function
The F71883 provides Intel SST/PECI/AMDSI interfaces for new generational CPU temperature
sensing. In AMDSI interface, there are SIC and SID signals for temperature information reading from
AMD CPU. The SIC signal is for clocking use, the other is for data transferring. More detail please
refer register description.
VDDIO
300 300
AMD CPU
SIC
SID
SIC
F71883
SID
In Intel SST and PECI interfaces, the F71883 can connect to CPU/SST directly. The F71883 can
read the temperature data from CPU, than the fan control machine of F71883 can implement the Fan
to cool down CPU temperature. As same as PECI, chipset can get information from F71883
including CPU temperature, system temperature (F71883 provides D+/D- for system temperature
sensing), fan speed status by SST. The application circuit is as below. More detail please refer the
register description.
Intel
ICH8
SST
100K
avoid pre-BIOS floating
F71883
SST
Intel
CPU
PECI
avoid pre-BIOS floating
100K
F71883
PECI
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F71883
8. Register Description
The configuration register is used to control the behavior of the corresponding devices. To
configure the register, using the index port to select the index and then writing data port to alter the
parameters. The default index port and data port are 0x4E and 0x4F respectively. Pull down the
SOUT1 pin to change the default value to 0x2E/0x2F. To enable configuration, the entry key 0x87
must be written to the index port. To disable configuration, write exit key 0xAA to the index port.
Following is a example to enable configuration and disable configuration by using debug.
-o 4e 87
-o 4e 87 ( enable configuration )
-o 4e aa ( disable configuration )
The Following is a register map (total devices) grouped in hexadecimal address order, which
shows a summary of all registers and their default value. Please refer each device chapter if you
want more detail information.
Global Control Registers
Register
0x[HEX]
02 Software Reset Register - - - - - - - 0
07 Logic Device Number Register (LDN) 0 0 0 0 0 0 0 0
20 Chip ID Register 0 0 0 0 0 1 0 1
21 Chip ID Register 0 1 0 0 0 0 0 1
23 Vender ID Register 0 0 0 1 1 0 0 1
24 Vender ID Register 0 0 1 1 0 1 0 0
25 Software Power Down Register - - 0 0 0 0 0 0
26 UART IRQ Sharing Register 0 - - - - - 0 0
“-“ Reserved or Tri-State
Global Control Registers
Register Name Default Value
MSB LSB
27 ROM Address Select Register 0 0/1 1/0 1/0 0/1 0/1 0/1 0
28 Power LED Function Select Register - 1/0 0/1 0 0 0 0 0
29 Muti Function Select 1 Register 0 0 0 0 0 0 0 0
2A Multi Function Select 2 Register 0 0 0 0 0 0 0 0
2B Multi Function Select 3 Register 0 0 0 0 0 0 0 0
2C Multi Function Select 4 Register 0 0 0 0 0 0 0 0
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F71883
2D Wakeup Control Register 0 - - - 1 0 0 0
Device Configuration Registers
“-“ Reserved or Tri-State
FDC Device Configuration Registers (LDN CR00)
Register
0x[HEX]
30 FDC Device Enable Register - - - - - - - 1
60 Base Address High Register 0 0 0 0 0 0 1 1
61 Base Address Low Register 1 1 1 1 0 0 0 0
70 IRQ Channel Select Register - - - - 0 1 1 0
74 DMA Channel Select Register - - - - - 0 1 0
F0 FDD Mode Register - - - - 1 1 1 0
F2 FDD Drive Type Register - - - - - - 1 1
F4 FDD Selection Register - - - 0 0 - 0 0
Register
0x[HEX]
30 UART1 Device Enable Register - - - - - - - 1
60 Base Address High Register 0 0 0 0 0 0 1 1
Register Name Default Value
MSB LSB
UART1 Device Configuration Registers (LDN CR01)
Register Name Default Value
MSB LSB
61 Base Address Low Register 1 1 1 1 1 0 0 0
70 IRQ Channel Select Register - - - - 0 1 0 0
F0 RS485 Enable Register - - - 0 - - - -
UART2 Device Configuration Registers (LDN CR02)
Register
0x[HEX]
30 UART2 Device Enable Register - - - - - - - 1
60 Base Address High Register 0 0 0 0 0 0 1 0
61 Base Address Low Register 1 1 1 1 1 0 0 0
70 IRQ Channel Select Register - - - - 0 0 1 1
F0 RS485 Enable Register - - - 0 0 0 - -
F1 SIR Mode Control Register - - - 0 0 1 0 0
Register
0x[HEX]
30 Parallel Port Device Enable Register - - - - - - - 1
60 Base Address High Register 0 0 0 0 0 0 1 1
Register Name Default Value
MSB LSB
Parallel Port Device Configuration Registers (LDN CR03)
Register Name Default Value
MSB LSB
61 Base Address Low Register 0 1 1 1 1 0 0 0
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F71883
70 IRQ Channel Select Register - - - - 0 1 1 1
74 DMA Channel Select Register - - - 0 - 0 1 1
F0 PRT Mode Select Register 0 1 0 0 0 0 1 0
Hardware Monitor Device Configuration Registers (LDN CR04)
Register
0x[HEX]
30 H/W Monitor Device Enable Register - - - - - - - 1
60 Base Address High Register 0 0 0 0 0 0 1 0
61 Base Address Low Register 1 0 0 1 0 1 0 1
70 IRQ Channel Select Register - - - - 0 0 0 0
Register
0x[HEX]
30 KBC Device Enable Register - - - - - - - 1
60 Base Address High Register 0 0 0 0 0 0 0 0
61 Base Address Low Register 0 1 1 0 0 0 0 0
70 KB IRQ Channel Select Register - - - - 0 0 0 0
72 Mouse IRQ Channel Select Register - - - - 0 0 0 0
Register Name Default Value
MSB LSB
KBC Device Configuration Registers (LDN CR05)
Register Name Default Value
MSB LSB
F0 Clock Select Register 1 0 - - - - 1 1
GPIO Device Configuration Registers (LDN CR06)
Register
0x[HEX]
F0 GPIO Output Enable Register 0 0 0 0 0 0 0 0
F1 GPIO Output Data Register 1 1 1 1 1 1 1 1
F2 GPIO Pin Status Register - - - - - - - -
F3 GPIO Drive Enable Register 0 0 0 0 0 0 0 0
E0 GPIO1 Output Enable Register 0 0 0 0 0 0 0 0
E1 GPIO1 Output Data Register 1 1 1 1 1 1 1 1
E2 GPIO1 Pin Status Register - - - - - - - -
E3 GPIO1 Drive Enable Register 0 0 0 0 0 0 0 0
D0 GPIO2 Output Enable Register 0 0 0 0 0 0 0 0
D1 GPIO2 Output Data Register 1 1 1 1 1 1 1 1
D2 GPIO2 Pin Status Register - - - - - - - -
D3 GPIO2 Drive Enable Register 0 0 0 0 0 0 0 0
C0 GPIO3 Output Enable Register - - - - 0 0 0 0
Register Name Default Value
MSB LSB
C1 GPIO3 Output Data Register - - - - 1 1 1 1
C2 GPIO3 Pin Status Register - - - - - - - -
C3 GPIO3 Drive Enable Register - - - - 0 0 0 0
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F71883
B0 GPIO4 Output Enable Register - - - - 0 0 0 0
B1 GPIO4 Output Data Register - - - - 1 1 1 1
B2 GPIO4 Pin Status Register - - - - - - - -
B3 GPIO4 Drive Enable Register - - - - 0 0 0 0
VID Device Configuration Registers (LDN CR07)
Register
0x[HEX]
30 VID Device Enable Register - - - - - - - 0
60 Base Address High Register 0 0 0 0 0 0 0 0
61 Base Address Low Register 0 0 0 0 0 0 0 0
Register
0x[HEX]
F0 SPI Control Register 0 0 0 1 0 0 0 0
F1 SPI Timeout Value Register 0 0 0 0 0 1 0 0
F2 SPI Baud Rate Divisor Register - - - - - 0 0 1
F3 SPI Status Register 0 - - - 0 - - -
F4 SPI High Byte Data Register 0 0 0 0 0 0 0 0
Register Name Default Value
MSB LSB
SPI Device Configuration Registers (LDN CR08)
Register Name Default Value
MSB LSB
F5 SPI Command Data Register 0 0 0 0 0 0 0 0
F6 SPI Chip Select Register - - - - 0 0 0 0
F7 SPI Memory Mapping Register - - - - - - - -
F8 SPI Operate Register 0 0 0 0 0 0 0 0
FA SPI Low Byte Data Register 0 0 0 0 0 0 0 0
FB SPI Address High Byte Register 0 0 0 0 0 0 0 0
FC SPI Address Medium Byte Register 0 0 0 0 0 0 0 0
FD SPI Address Low Byte Register 0 0 0 0 0 0 0 0
FE SPI Program Byte Register 0 0 0 0 0 0 0 0
FF SPI Write Data Register 0 0 0 0 0 0 0 0
PME and ACPI Device Configuration Registers (LDN CR0A )
Register
0x[HEX]
30 PME Device Enable Register - - - - - - - 0
F0 PME Event Enable Register - 0 0 0 0 0 0 0
F1 PME Event Status Register - 0 0 0 0 0 0 1
F4 ACPI Control Register - 0 0 0 0 1 1 0
Register Name Default Value
MSB LSB
F5 ACPI Control Register 0 - 0 1 1 1 - -
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F71883
8.1 Global Control Registers
8.1.1 Software Reset Register Index 02h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 SOFT_RST R/W 0 Write 1 to reset the register and device powered by VDD ( VCC ).
8.1.2 Logic Device Number Register (LDN) Index 07h
Bit Name R/W Default Description
7-0 LDN R/W 00h 00h: Select FDC device configuration registers.
01h: Select UART 1 device configuration registers.
02h: Select UART 2 device configuration registers.
03h: Select Parallel Port device configuration registers.
04h: Select Hardware Monitor device configuration registers.
05h: Select KBC device configuration registers.
06h: Select GPIO device configuration registers.
07h: Select VID device configuration registers.
08h: Select SPI device configuration registers.
0ah: Select PME & ACPI device configuration registers.
8.1.3 Chip ID Register Index 20h
Bit Name R/W Default Description
7-0 CHIP_ID1 R 05h Chip ID 1 of F71883.
8.1.4 Chip ID Register Index 21h
Bit Name R/W Default Description
7-0 CHIP_ID2 R 41h Chip ID2 of F71883.
8.1.5 Vendor ID Register Index 23h
Bit Name R/W Default Description
7-0 VENDOR_ID1 R 19h Vendor ID 1 of Fintek devices.
8.1.6 Vendor ID Register Index 24h
Bit Name R/W Default Description
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7-0 VENDOR_ID2 R 34h Vendor ID 2 of Fintek devices.
8.1.7 Software Power Down Register Index 25h
Bit Name R/W Default Description
7-6 Reserved - - Reserved
5 SOFTPD_KBC R/W 0
4 SOFTPD_HM R/W 0
3 SOFTPD_PRT R/W 0
2 SOFTPD_UR2 R/W 0
1 SOFTPD_UR1 R/W 0
0 SOFTPD_FDC R/W 0
Power down the KBC device. This will stop the KBC clock.
Power down the Hardware Monitor device. This will stop the Hardware Monitor
clock.
Power down the Parallel Port device. This will stop the Parallel Port clock.
Power down the UART 2 device. This will stop the UART 2 clock.
Power down the UART 1 device. This will stop the UART 1 clock.
Power down the FDC device. This will stop the FDC clock.
8.1.8 UART IRQ Sharing Register Index 26h
Bit Name R/W Default Description
7 CLK24M_SEL R/W 0
6-2 Reserved - -
1 IRQ_MODE R/W 0
0: CLKIN is 48MHz
1: CLKIN is 24MHz
Reserved.
0: PCI IRQ sharing mode (low level).
1: ISA IRQ sharing mode (low pulse).
o IRQ_SHAR R/W 0
8.1.9 ROM Address Select Register Index 27h
Bit Name R/W Default Description
7 ROM_WR_EN R/W 0
6 SPI_EN R/W -
Nov., 2006
0: disable IRQ sharing of two UART devices.
1: enable IRQ sharing of two UART devices.
0: disable ROM writing
1: enable ROM writing
0: SPI disable
1: SPI enable
This register is power on trapped by SOUT2/SPI_TRAP. Pull down to enable
SPI.
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5 BACKUP_BIOS_EN R/W -
4 PORT_4E_EN R/W -
3 SEG_000E_EN R/W -
2 SEG_FFF8_EN R/W -
0: use SPI as primary BIOS
1: use SPI as backup BIOS
This register is power on trapped by DTR2#/FWH_TRAP. Pull down to select
SPI as primary BIOS.
0: The configuration register port is 2E/2F.
1: The configuration register port is 4E/4F.
This register is power on trapped by SOUT1/ Config4E_2E. Pull down to select
port 2E/2F.
0: disable address 0x000E0000 – 0x000EFFFF decode
1: enable address 0x000E0000 – 0x000EFFFF decode
This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable.
0: disable address 0xFFF80000 – 0xFFFFFFFF and 0x000F0000 –
0x000FFFFF decode
1: enable address 0xFFF80000 – 0xFFFFFFFF and 0x000F0000 –
0x000FFFFF decode
This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable.
1 SEG_FFEF_EN R/W -
0 SEG_FFF0_EN R/W 0
8.1.10 Power LED Function Select Register Index 28h
Bit Name R/W Default Description
7 Reserved - -
6 VIDOUT_EN R/W -
0: disable address 0xFFEE – 0xFFEFFFFF decode
1: enable address 0xFFEE0000 – 0xFFEFFFFF decode
This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable.
0: disable address 0xFFF00000 – 0xFFF7FFFF decode
1: enable address 0xFFF00000 – 0xFFF7FFFF decode
Reserved.
0: The VID_OUT[5:0]/GPIO0[5:0] functions as GPIO0[5:0], and the
SLOTOTCC#/GPIO06 functions as GPIO06.
1: The VID_OUT[5:0]/GPIO0[5:0] functions as VID_OUT[5:0], and the
SLOTOTCC#/GPIO06 functions as SLOTOCC#.
This register is power on trapped by RTS1#/VIDOUT_TRAP. Pull down to
select GPIOs function.
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5 DPORT_EN R/W -
4 Reserved R/W -
3 GPIO43_SEL R/W 0
2 GPIO42_SEL R/W 0
1 GPIO41_SEL R/W 0
0 GPIO40_SEL R/W 0
8.1.11 Multi Function Select 1 Register Index 29h (Powered by VSB3V)
Bit Name R/W Default Description
0: The 80 port function is disabled.
1: The 80 port function is enabled.
Reserved.
0: IRRX/GPIO43 functions as IRRX.
1: IRRX/GPIO43 functions as GPIO43.
0: IRTX/GPIO42 functions as IRTX.
1: IRTX/GPIO42 functions as GPIO42.
0: FANCTRL3/GPIO41 functions as FANCTRL3.
1: FANCTRL3/GPIO41 functions as GPIO41.
0: FANIN3/GPIO40 functions as FANIN3.
1: FANIN3/GPIO40 functions as GPIO40.
7-2 Reserved R/W 0
1 WDT_GP07_EN R/W 0
0 ALERT_GP_EN R/W 0
8.1.12 Multi Function Select 2 Register Index 2Ah (Pow ered by VSB3V)
Bit Name R/W Default Description
7-6 VSBLED_SEL R/W 2’b00
Reserved
0: GPIO07/Turbo1#/WDTRST# will function as GPIO07/Turbo1#.
1: GPIO07/Turbo1#/WDTRST# will function as WDTRST#.
0: GPIO15/LED_VSB/ALERT# will function as GPIO15/LED_VSB controlled
by GPIO15_SEL register.
1: GPIO15/LED_VSB/ALERT# will function as ALERT#.
VSBLED function select, powered by VSB.
00: VSBLED always output low.
01: VSBLED tri-state
10: VSBLED output 0.5Hz clock.
11: VSBLED output 1Hz clock.
( clock output is inverse with VDDLED clock output )
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5-4 VDDLED_SEL R/W 2’b00
3 GPIO33_SEL R/W 0
2 GPIO32_SEL R/W 0
1 GPIO31_SEL R/W 0
0 GPIO30_SEL R/W 0
VDDLED function select, powered by VDD.
00: VDDLED always output low.
01: VDDLED tri-state
10: VDDLED output 0.5Hz clock.
11: VDDLED output 1Hz clock.
( clock output is inverse with VSBLED clock output )
0: RSMRST#/GPIO33 functions as RSMRST#.
1: RSMRST#/GPIO33 functions as GPIO33.
0: PWROK/GPIO32 functions as PWROK.
1: PWROK/GPIO32 functions as GPIO32.
0: PS_ON#/GPIO31 functions as PS_ON#.
1: PS_ON#/GPIO31 functions as GPIO31.
0: S3#/GPIO30 functions as S3#.
1: S3#/GPIO30 functions as GPIO30.
8.1.13 Multi Function Select 3 Register Index 2Bh (Powered by VSB3V)
Bit Name R/W Default Description
7 Reserved R/W 0
6 GPIO16_SEL R/W 0
5 GPIO15_SEL R/W 0
4 GPIO14_SEL R/W 0
3 GPIO13_SEL R/W 0
2 GPIO12_SEL R/W 0
Dummy register.
0: GPIO16/LED_VCC functions as GPIO16.
1: GPIO16/LED_VCC functions as LED_VCC.
When register ALERT_GP_EN is 0, the register functions as:
0: GPIO15/LED_VSB/ALERT# functions as GPIO15.
1: GPIO15/LED_VSB/ALERT# functions as LED_VSB.
0: GPIO14/FWH_DIS/WDTRST# functions as GPIO14 when SPI is disabled.
1: GPIO14/FWH_DIS/WDTRST# functions as WDTRST# when SPI is
disabled.
0: GPIO13/SPI_MOSI/BEEP functions as GPIO13 when SPI is disabled.
1: GPIO13/SPI_MOSI/BEEP functions as BEEP when SPI is disabled.
0: GPIO12/SPI_MISO/FANCTRL1_1 functions as GPIO12 when SPI is
disabled.
1: GPIO12/SPI_NISO/FANCTRL1_1 functions as FANCTRL1_1 when SPI is
disabled.
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1 GPIO11_SEL R/W 0
0 GPIO10_SEL R/W 0
8.1.14 Multi Function Select 4 Register Index 2Ch (Powered by VSB3V)
Bit Name R/W Default Description
7 GPIO27_SEL R/W 0
6 GPIO26_SEL R/W 0
5 GPIO25_SEL R/W 0
0: GPIO11/SPI_CS/FANCTRL4 functions as GPIO11 when SPI is disabled.
1: GPIO11/SPI_CS/FANCTRL4 functions as FANCTRL4 when SPI is disabled.
0: GPIO10/SPI_CLK/FANIN4 functions as GPIO10 when SPI is disabled.
1: GPIO10/SPI_CLK/FANIN4 functions as FANIN4 when SPI is disabled.
0: PWSOUT#/GPIO27 functions as PWSOUT#.
1: PWSOUT#/GPIO27 functions as GPIO27.
0: PWSIN#/GPIO26 functions as PWSIN#.
1: PWSIN#/GPIO26 functions as GPIO26.
0: PME#/GPIO25 functions as PME#.
1: PME#/GPIO25 functions as GPIO25.
4 GPIO24_SEL R/W 0
0: ATXPG_IN/GPIO24 functions as ATXPG_IN.
1: ATXPG_IN/GPIO24 functions as GPIO24.
3 GPIO23_SEL R/W 0
2 GPIO22_SEL R/W 0
1 GPIO21_SEL R/W 0
0 GPIO20_SEL R/W 0
8.1.15 Wakeup Control Register Index 2Dh (Powered by VBAT)
Bit Name R/W Default Description
7 SPI_CS1_EN R/W 0
0: RSTCON#/GPIO23 functions as RSTCON#.
1: RSTCON#/GPIO23 functions as GPIO23.
0: PCIRST3#/GPIO22 functions as PCIRST3#.
1: PCIRST3#/GPIO22 functions as GPIO22.
0: PCIRST2#/GPIO21 functions as PCIRST2#.
1: PCIRST2#/GPIO21 functions as GPIO21.
0: PCIRST1#/GPIO20 functions as PCIRST1#.
1: PCIRST1#/GPIO20 functions as GPIO20.
This register decides the architecture of SPI when used as primary BIOS.
1: use two 4Mbits. (FWH_DIS will multi-functions as SPI_CS1#)
0: use one 8Mbits. (Divided into two 4Mbits. Originally use the higher part. If
the higher part is booting fail, the memory address will be auto mapped to
lower part.)
6-4 Reserved - -
Nov., 2006
Reserved.
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3 WAKEUP_EN R/W 1
2-1 KEY_SEL R/W 00
0 MO_SEL R/W 0
0: disable keyboard/mouse wake up.
1: enable keyboard/mouse wake up.
This registers select the keyboard wake up key.
00: Wake up key is Ctrl + Esc.
01: Wake up key is Ctrl + F1.
10: Wake up key is Ctrl + Space.
11: Wake up key is any key.
This register select the mouse wake up key.
0: Wake up by click.
1: Wake up by click and movement.
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8.2 FDC Registers (CR00)
8.2.1 FDC Configuration Registers
FDC Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 FDC_EN R/W 1 0: disable FDC.
F71883
Base Address High Register Index 60h
Bit Name R/W Default Description
1: enable FDC.
7-0 BASE_ADDR_HI R/W 03h The MSB of FDC base address.
Base Address Low Register Index 61h
Bit Name R/W Default Description
7-0 BASE_ADDR_LO R/W F0h The LSB of FDC base address.
IRQ Channel Select Register Index 70h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3-0 SELFDCIRQ R/W 06h Select the IRQ channel for FDC.
DMA Channel Select Register Index 74h
Bit Name R/W Default Description
7-3 Reserved - - Reserved.
2-0 SELFDCDMA R/W 010 Select the DMA channel for FDC.
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FDD Mode Register Index F0h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3-2 IF_MODE R/W 11 00: Model 30 mode.
1 FDMAMODE R/W 1 0: enable burst mode.
F71883
01: PS/2 mode.
10: Reserved.
11: AT mode (default).
1: non-busrt mode (default).
0 EN3MODE R/W 0 0: normal floppy mode (default).
1: enhanced 3-mode FDD.
FDD Drive Type Register Index F2h
Bit Name R/W Default Description
7-2 Reserved - - Reserved.
1-0 FDD_TYPE R/W 11 FDD drive type.
FDD Selection Register Index F4h
Bit Name R/W Default Description
7-5 Reserved - - Reserved.
4-3 FDD_DRT R/W 00 Data rate table select, refer to table A.
00: select regular drives and 2.88 format.
01: 3-mode drive.
10: 2 mega tape.
11: reserved.
2 Reserved - - Reserved.
1-0 FDD_DT R/W 00 Drive type select, refer to table B.
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TABLE A
Data Rate Table Select Data Rate Selected Data Rate DENSEL
FDD_DRT[1] FDD_DRT[0] DATARATE1 DATARATE0 MFM FM
0 0 500K 250K 1
0 0
0 1
1 0
TABLE B
FDD_DT1 FDD_DT0
0
Drive Type
0 DENSEL 4/2/1 MB 3.5”
0 1 300K 150K 0
1 0 250K 125K 0
1 1 1Meg --- 1
0 0 500K 250K 1
0 1 500K 250K 0
1 0 250K 125K 0
1 1 1Meg --- 1
0 0 500K 250K 1
0 1 2Meg --- 0
1 0 250K 125K 0
1 1 1Meg --- 1
DRVDEN0 Remark
2/1 MB 5.25”
1/1.6/1 MB 3.5” (3-Mode )
0 1 DATARATE1
1 0 DENSEL#
1 1 DATARATE0
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8.3 UART1 Registers (CR01)
8.3.1 UART 1 Configuration Registers
UART 1 Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 UR1_EN R/W 1 0: disable UART 1.
F71883
Base Address High Register Index 60h
Bit Name R/W Default Description
1: enable UART 1.
7-0 BASE_ADDR_HI R/W 03h The MSB of UART 1 base address.
Base Address Low Register Index 61h
Bit Name R/W Default Description
7-0 BASE_ADDR_LO R/W F8h The LSB of UART 1 base address.
IRQ Channel Select Register Index 70h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3-0 SELUR1IRQ R/W 4h Select the IRQ channel for UART 1.
RS485 Enable Register Index F0h
Bit Name R/W Default Description
7-5 Reserved - - Reserved.
4 RS485_EN R/W 0 0: RS232 driver.
1: RS485 driver. Auto drive RTS# low when transmitting data.
3-0 Reserved - - Reserved.
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8.4 UART 2 Registers (CR02)
8.4.1 UART 2 Configuration Registers
UART 2 Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 UR2_EN R/W 1 0: disable UART 2.
F71883
Base Address High Register Index 60h
Bit Name R/W Default Description
1: enable UART 2.
7-0 BASE_ADDR_HI R/W 02h The MSB of UART 2 base address.
Base Address Low Register Index 61h
Bit Name R/W Default Description
7-0 BASE_ADDR_LO R/W F8h The LSB of UART 2 base address.
IRQ Channel Select Register Index 70h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3-0 SELUR2IRQ R/W 3h Select the IRQ channel for UART 2.
RS485 Enable Register Index F0h
Bit Name R/W Default Description
7-5 Reserved - - Reserved.
4 RS485_EN R/W 0 0: RS232 driver.
1: RS485 driver. Auto drive RTS# low when transmitting data.
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3 RXW4C_IR R/W 0 0: No reception delay when SIR is changed form TX to RX.
2 TXW4C_IR R/W 0 0: No transmission delay when SIR is changed form RX to TX.
1-0 Reserved - - Reserved.
SIR Mode Control Register Index F1h
F71883
1: Reception delays 4 characters time when SIR is changed form TX to RX.
1: Transmission delays 4 characters time when SIR is changed form RX to TX.
Bit Name R/W Default Description
7 Reserved - - Reserved.
6 Reserved - - Reserved.
5 Reserved - - Reserved.
4-3 IRMODE R/W 00 00: disable IR function.
2 HDUPLX R/W 1 0: SIR is in full duplex mode for loopbak test. TXW4C_IR and RXW4C_IR are
1 TXINV_IR R/W 0 0: IRTX is in normal condition.
0 RXINV_IR R/W 0 0: IRRX is in normal condition.
01: disable IR function.
10: IrDA function, active pulse is 1.6uS.
11: IrDA function, active pulse is 3/16 bit time.
of no use.
1: SIR is in half duplex mode.
1: inverse the IRTX.
1: inverse the IRRX.
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8.5 Parallel Port Registers (CR03)
8.5.1 Parallel Port Configuration Registers
Parallel Port Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 PRT_EN R/W 1 0: disable Parallel Port.
Base Address High Register Index 60h
Bit Name R/W Default Description
7-0 BASE_ADDR_HI R/W 03h The MSB of Parallel Port base address.
Base Address Low Register Index 61h
F71883
1: enable Parallel Port.
Bit Name R/W Default Description
7-0 BASE_ADDR_LO R/W 78h The LSB of Parallel Port base address.
IRQ Channel Select Register Index 70h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3-0 SELPRTIRQ R/W 7h Select the IRQ channel for Parallel Port.
DMA Channel Select Register Index 74h
Bit Name R/W Default Description
7-5 Reserved - - Reserved.
4 ECP_DMA_MODE R/W 0 0: non-burst mode DMA.
1: enable burst mode DMA.
3 Reserved - - Reserved.
2-0 SELPRTDMA R/W 011 Select the DMA channel for Parallel Port.
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PRT Mode Select Register Index F0h
Bit Name R/W Default Description
7 SPP_IRQ_MODE R/W 0 Interrupt mode in non-ECP mode.
6-3 ECP_FIFO_THR R/W 1000 ECP FIFO threshold.
2-0 PRT_MODE R/W 010 000: Standard and Bi-direction (SPP) mode.
F71883
0: Level mode.
1: Pulse mode.
001: EPP 1.9 and SPP mode.
010: ECP mode (default).
011: ECP and EPP 1.9 mode.
100: Printer mode.
101: EPP 1.7 and SPP mode.
110: Reserved.
111: ECP and EPP1.7 mode.
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8.6 Hardware Monitor Registers (CR04)
8.6.1 Hardware Monitor Configuration Registers
Hardware Monitor Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 HM_EN R/W 1 0: disable Hardware Monitor.
Base Address High Register Index 60h
F71883
1: enable Hardware Monitor.
Bit Name R/W Default Description
7-0 BASE_ADDR_HI R/W 02h The MSB of Hardware Monitor base address.
Base Address Low Register Index 61h
Bit Name R/W Default Description
7-0 BASE_ADDR_LO R/W 95h The LSB of Hardware Monitor base address.
IRQ Channel Select Register Index 70h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3-0 SELHMIRQ R/W 0000 Select the IRQ channel for Hardware Monitor.
8.6.2 Device Registers
Before the device registers, the following is a register map order which shows a summary of all registers.
Please refer each one register if you want more detail information.
Register CR01 ~ CR03 Æ Configuration Registers
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Register CR10 ~ CR4F Æ Vo ltage Setting Register
Register CR60 ~ CR8E Æ Temperature Setting Register
Register CR90 ~ CRDF Æ Fan Control Setting Register
ÆFan1 Detail Setting CRA0 ~ CRAF
ÆFan2 Detail Setting CRB0 ~ CRBF
ÆFan3 Detail Setting CRC0 ~ CRCF
ÆFan4 Detail Setting CRD0 ~ CRDF
8.6.2.1 HW Monitor Config. Register Index 01h
Bit Name R/W Default Description
7-3 Reserved 0h 0 Reserved
2 POWER_DOWN R/W
1 FAN_START R/W
0 V_T_START R/W
8.6.2.2 BEEP OVT ALERT Config. Register Index 02h
Bit Name R/W Default Description
7 Reserved R/W 0 Dummy register.
6 CASE_BEEP_EN R/W
5-4 OVT_MODE R/W
3 Reserved R/W 0 Dummy register.
0
Hardware monitor function power down.
1
Set one to enable startup of fan monitoring operations; a zero puts the part
in standby mode.
1
Set one to enable startup of temperature and voltage monitoring
operations; a zero puts the part in standby mode.
0
0: Disable case open event output via BEEP.
1: Enable case open event output via BEEP.
00: The OVT# will be low active level mode.
0
01: The OVT# will be high active level mode.
10: The OVT# will indicate by 1Hz LED function.
11: The OVT# will indicate by (400/800HZ) BEEP output.
0
2 CASE_SMI_EN R / W
1-0 ALERT_MODE R/W
8.6.2.3 Case Open Config. Register Index 03h
Bit Name R/W Default Description
7-1 Reserved R/W 0 Return 0 when read.
0 CASE_STS R/W 0 Case open event status, write 1 to clear if case open event cleared.
Nov., 2006
0: Disable case open event output via PME.
1: Enable case open event output via PME.
00: The ALERT# will be low active level mode.
0
01: The ALERT# will be high active level mode.
10: The ALERT# will indicate by 1Hz LED function.
11: The ALERT# will indicate by (400/800HZ) BEEP output.
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8.6.2.4 PECI AMDSI Select Register Index 0Ah
Bit Name R/W Default Description
7-6 Reserved - 00
5 T1_IIR_EN R/W
4 SST_EN R/W 0
3-2 VTT_SEL R/W
1-0 MEAS_TYPE R/W
8.6.2.5 PECI CPU Select Register Index 0Bh (MEAS_TYPE = = 2’b01)
Bit Name R/W Default Description
7-4 CPU_SEL R/W
3-1 Reserved - 0
0 DOMAIN1_EN R/W
Reserved.
Set 1 to enable IIR for AMDSI/PECI reading.
0
The reading will be more stable.
Set 1 to enable SST interface.
PECI (Vtt) voltage select.
0
00: Vtt is 1.23V
01: Vtt is 1.13V
10: Vtt is 1.00V
11: Vtt is 1.00V
CPU Temperature Measurement method.
00
00: with external diode.
01: with PECI interface.
10: with AMDSI interface.
11: reserved.
Select the Intel CPU socket number.
0
0000: no CPU presented. PECI host will use Ping() command to find CPU
address.
0001: CPU is in socket 0, i.e. PECI address is 0x30.
0010: CPU is in socket 0, i.e. PECI address is 0x31.
0100: CPU is in socket 0, i.e. PECI address is 0x32.
1000: CPU is in socket 0, i.e. PECI address is 0x33.
Otherwise are reserved.
Reserved.
If the CPU selected is dual core. Set this register 1 to read the temperature
0
of domain1.
8.6.2.6 AMDSI Version Register Index 0Bh (MEAS_TYPE ==2’b10)
Bit Name R/W Default Description
7-0 AMDSI_VER R - Return the AMDSI version.
8.6.2.7 TCC Temp. Register Index 0Ch (MEAS_TYPE == 2’b01)
Bit Name R/W Default Description
8’h55
7-0 TCC_TEMP R/W
8.6.2.8 AMDSI Node ID Register Index 0Ch (MEAS_TYPE ==2’b10)
Bit Name R/W Default Description
7-0 NODE_ID R - Return the AMDSI node id.
8.6.2.9 SST Address Register Index 0Dh
Bit Name R/W Default Description
Nov., 2006
TCC Activation Temperature.
The absolute value of CPU temperature is calculated by the equation:
CPU_TEMP = TCC_TEMP + PECI Reading.
The range of this register is 0 ~ 255.
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F71883
7-0 SST_ADDR R/W 8’h4C Address for SST interface. Programmable.
8.6.2.10 VID Divide Register Index 0Eh
Bit Name R/W Default Description
The value indicates the divisor of the voltage source.
0
00: voltage source is directly connected to VIN6.
7-6 VIN6_DIV R/W
5-4 VIN5_DIV R/W
3 PECI_SCALE_ADD R / W
2- 0 PECI_SCALE R / W
01: voltage source is divided by 2 and connect to VIN6.
10: voltage source is divided by 4 and connect to VIN6.
11: voltage source is divided by 16 and connect to VIN6.
The value indicates the divisor of the voltage source.
0
00: voltage source is directly connected to VIN5.
01: voltage source is divided by 2 and connect to VIN5.
10: voltage source is divided by 4 and connect to VIN5.
11: voltage source is divided by 16 and connect to VIN5.
This register is used to indicate how to calculate the PECI reading with
0
PECI_SCALE register.
0: The real value is the reading adds the value calculated by
PECI_SCALE.
1: The real value is the reading adds the value calculated by
PECI_SCALE.
This register is used to control the PECI reading slope. See also
0
PECI_SCALE_ADD register.
000: The real value is the PECI reading.
001: The real value is (1 ± 1/2) PECI reading.
010: The real value is (1 ± 1/4) PECI reading.
011: The real value is (1 ± 1/8) PECI reading.
100: The real value is (1 ± 1/16) PECI reading.
101: The real value is (1 ± 1/32) PECI reading.
110: The real value is (1 ± 1/64) PECI reading.
111: The real value is (1 ± 1/128) PECI reading.
8.6.2.11 Configuration Regi ster Index 0Fh
Bit Name R/W Default Description
The value indicates the divisor of the voltage source.
0
00: voltage source is directly connected to VIN4.
7-6 VIN4_DIV R/W
5-4 VIN3_DIV R/W
3-2 VIN2_DIV R/W
1-0 VIN1_DIV R/W
01: voltage source is divided by 2 and connect to VIN4.
10: voltage source is divided by 4 and connect to VIN4.
11: voltage source is divided by 16 and connect to VIN4.
The value indicates the divisor of the voltage source.
0
00: voltage source is directly connected to VIN3.
01: voltage source is divided by 2 and connect to VIN3.
10: voltage source is divided by 4 and connect to VIN3.
11: voltage source is divided by 16 and connect to VIN3.
The value indicates the divisor of the voltage source.
0
00: voltage source is directly connected to VIN2.
01: voltage source is divided by 2 and connect to VIN2.
10: voltage source is divided by 4 and connect to VIN2.
11: voltage source is divided by 16 and connect to VIN2.
The value indicates the divisor of the voltage source.
0
00: voltage source is directly connected to VIN1.
01: voltage source is divided by 2 and connect to VIN1.
10: voltage source is divided by 4 and connect to VIN1.
11: voltage source is divided by 16 and connect to VIN1.
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Voltage Setting
8.6.2.12 Voltage1 PME# Enable Register Index 10h
Bit Name R/W Default Description
7-2 Reserved -- 0 Reserved
F71883
1
0 Reserved -- 0 Reserved
8.6.2.13 Voltage1 Interrupt Status Regi ster Index 11h
Bit Name R/W Default Description
7-2 Reserved -- 0 Reserved
1 V1_ EXC _STS R/W
0 Reserved -- 0 Reserved
EN_V1_PME
R/W
0
A one enables the corresponding interrupt status bit for PME# interrupt.
Set this bit 1 to enable PME# function for VIN1.
0
This bit is set when the VIN1 is over the high limit. Write 1 to clear this bit,
write 0 will be ignored.
8.6.2.14 Voltage1 Exceeds Real Time Status Register 1 Index 12h
Bit Name R/W Default Description
7-2 Reserved -- 0 Reserved
1 V1_EXC RO
A one indicates VIN1 exceeds the high or low limit. A zero indicates VIN1
0
is in the safe region.
0 Reserved -- 0 Reserved
8.6.2.15 Voltage1 BEEP Enable Register Index 13h
Bit Name R/W Default Description
7-2 Reserved -- 0 Reserved
1
EN_V1_BEEP
R/W
0
A one enables the corresponding interrupt status bit for BEEP output of
VIN1.
0 Reserved -- 0 Reserved
8.6.2.16 Voltage reading and limit Index 20h- 4Fh
Address Attribute
20h RO -21h RO --
22h RO --
Default
Value
Description
VCC3V reading. The unit of reading is 8mV.
V1 (Vcore) reading. The unit of reading is 8mV.
V2 reading. The unit of reading is 8mV.
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23h RO --
24h RO --
25h RO --
26h RO --
27h RO --
28h RO --
29~2Fh RO FF
30~31h RO FF
32h R/W FF
33h RO FF
34~4Fh RO FF
Temperature Setting
8.6.2.17 Temperature PME# Enable Register Index 60h
V3 reading. The unit of reading is 8mV.
V4 reading. The unit of reading is 8mV.
V5 reading. The unit of reading is 8mV.
V6 reading. The unit of reading is 8mV.
VSB3V reading. The unit of reading is 8mV.
VBAT reading. The unit of reading is 8mV.
Reserved
Reserved
V1 High Limit setting register. The unit is 8mV.
Reserved
Reserved
Bit Name R/W Default Description
EN_ T3_OVT_PME
7
6 EN_ T2_ OVT_PME
EN_ T1_ OVT_PME
5
4 Reserved R/W
EN_ T3_EXC_PME
3
2 EN_ T2_EXC_PME
EN_ T1_EXC_PME
1
0 Reserved R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
If set this bit to 1, PME# signal will be issued when TEMP3 exceeds OVT
limit setting.
0
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds OVT
setting.
0
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds OVT
setting.
0
Reserved
0
If set this bit to 1, PME# signal will be issued when TEMP3 exceeds high
limit setting.
0
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds high
limit setting.
0
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds high
limit setting.
0
Reserved
8.6.2.18 Temperature Interrupt Status Register Index 61h
Bit Name R/W Default Description
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0
A one indicates TEMP3 temperature sensor has exceeded OVT limit or
7 T3_OVT_STS R/W
6 T2_OVT _STS R/W
5 T1_OVT _STS R/W
4 Reserved R/W
3 T3_EXC _STS R/W
2 T2_EXC _STS R/W
below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be
ignored.
0
A one indicates TEMP2 temperature sensor has exceeded OVT limit or
below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be
ignored.
0
A one indicates TEMP1 temperature sensor has exceeded OVT limit or
below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be
ignored.
0
Reserved
0
A one indicates TEMP3 temperature sensor has exceeded high limit or
below the “high limit –hysteresis”. Write 1 to clear this bit, write 0 will be
ignored.
0
A one indicates TEMP2 temperature sensor has exceeded high limit or
below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 will
be ignored.
0
A one indicates TEMP1 temperature sensor has exceeded high limit or
1 T1_EXC _STS R/W
0 Reserved R/W
8.6.2.19 Temperature Real Time Status Register Index 62h
Bit Name R/W Default Description
7 T3_OVT R/W
6 T2_OVT R/W
5 T1_OVT R/W
4 Reserved R/W 0 Reserved
3 T3_EXC R/W
2 T2_EXC R/W
below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 will
be ignored.
0
Reserved
0
Set when the TEMP3 exceeds the OVT limit. Clear when the TEMP3 is
below the “OVT limit –hysteresis” temperature.
0
Set when the TEMP2 exceeds the OVT limit. Clear when the TEMP2 is
below the “OVT limit –hysteresis” temperature.
0
Set when the TEMP1 exceeds the OVT limit. Clear when the TEMP1 is
below the “OVT limit –hysteresis” temperature.
0
Set when the TEMP3 exceeds the high limit. Clear when the TEMP3 is
below the “high limit –hysteresis” temperature.
0
Set when the TEMP2 exceeds the high limit. Clear when the TEMP2 is
below the “high limit –hysteresis” temperature.
0
1 T1_EXC R/W
Nov., 2006
Set when the TEMP1 exceeds the high limit. Clear when the TEMP1 is
below the “high limit –hysteresis” temperature.
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0 Reserved R/W 0 Reserved
8.6.2.20 Temperature BEEP Enable Register Index 63h
Bit Name R/W Default Description
EN_ T3_OVT_BEEP
7
R/W
0
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds OVT
limit setting.
6 EN_ T2_ OVT_BEEP
EN_ T1_ OVT_BEEP
5
4 Reserved R/W
3
2 EN_ T2_EXC_BEEP
EN_ T3_EXC_BEEP
R/W
R/W
R/W
R/W
EN_ T1_EXC_BEEP
1
0 Reserved R/W
8.6.2.21 OVT Output Enable Register 1 In dex 66h
Bit Name R/W Default Description
7 EN_T3_ALERT R
6 EN_T2_ALERT R
5 EN_T1_ALERT R
4 Reserved R 0
3 EN_T3_OVT R/W 0 Enable over temperature (OVT) mechanism of temperature3.
R/W
0
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds OVT
limit setting.
0
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds OVT
limit setting.
0
Reserved
0
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds high
limit setting.
0
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds high
limit setting.
0
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds high
limit setting.
0
Reserved
Enable temperature 3 alert event (asserted when temperature over high
0
limit)
Enable temperature 2 alert event (asserted when temperature over high
0
limit)
Enable temperature 1 alert event (asserted when temperature over high
0
limit)
Reserved
2 EN_T2_OVT R/W 0 Enable over temperature (OVT) mechanism of temperature2.
1 EN_T1_OVT R/W 1 Enable over temperature (OVT) mechanism of temperature1.
0 Reserved R
8.6.2.22 Temperature Sensor Type Register Index 6Bh
Bit Name R/W Default Description
7-4 Reserved RO 0 --
3 T3_MODE R/W
Nov., 2006
0h
Reserved.
0: TEMP3 is connected to a thermistor
1
1: TEMP3 is connected to a BJT.(default)
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0: TEMP2 is connected to a thermistor.
2 T2_MODE R/W
1 T1_MODE R/W
0 Reserved R
8.6.2.23 TEMP1 Limit Hystersis Select Register -- Index 6Ch
Bit Name R/W Default Description
7-4 TEMP1_HYS R/W
1
1: TEMP2 is connected to a BJT. (default)
0: TEMP1 is connected to a thermistor
1
1: TEMP1 is connected to a BJT.(default)
0h
--
4h
Limit hysteresis. (0~15 degree C)
Temperature and below the ( boundary – hysteresis ).
3-0 Reserved R
8.6.2.24 TEMP2 and TEMP3 Limit Hystersis Select Register -- Index 6Dh
Bit Name R/W Default Description
7-4 TEMP3_HYS R/W
3-0 TEMP2_HYS R/W
8.6.2.25 DIODE OPEN Status Register -- Index 6Fh
Bit Name R/W Default Description
7-4 Reserved RO
3 T3_DIODE_OPEN RO 0h External diode 3 is open
2 T2_DIODE_OPEN RO 0h External diode 2 is open
1 T1_DIODE_OPEN RO 0h This register indicates the abnormality of temperature 1 measurement.
0 Reserved R
0h
--
2h
Limit hysteresis. (0~15 degree C)
Temperature and below the ( boundary – hysteresis ).
4h
Limit hysteresis. (0~15 degree C)
Temperature and below the ( boundary – hysteresis ).
0h
Reserved
When AMDSI interface is enabled, it indicates the error of not receiving
ACK bit when read TCON command is asserted.
When PECI interface is enabled, it indicates a error code is received from
PECI slave.
When external diode is used, it indicates the BJT is open or short.
0h
--
Temperature Index 70h- 8Fh
Address Attribute
70h Reserved FFh
71h Reserved FFh
Default
Value
Reserved
Reserved
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º
72h RO --
73h RO -- Reserved
74h RO --
75h RO -- Reserved
76h RO --
77-7Bh RO -- Reserved
7C-7Fh RO FFh Reserved
Temperature 1 reading. The unit of reading is 1
register.
Temperature 2 reading. The unit of reading is 1
register.
Temperature 3 reading. The unit of reading is 1
register.
C.At the moment of reading this
º
C.At the moment of reading this
º
C.At the moment of reading this
80h Reserved FFh
81h Reserved FFh
Reserved
Reserved
82h R/W 64h Temperature sensor 1 OVT limit. The unit is 1ºC.
83h R/W 55h Temperature sensor 1 high limit. The unit is 1ºC.
84h R/W 64h Temperature sensor 2 OVT limit. The unit is 1ºC.
85h R/W 55h Temperature sensor 2 high limit. The unit is 1ºC.
86h R/W 55h Temperature sensor 3 OVT limit. The unit is 1ºC.
87h R/W 46h Temperature sensor 3 high limit. The unit is 1ºC.
88-8Bh RO -- Reserved
8C~8Dh RO FFH Reserved
8.6.2.26 Temperature Filter Select Register -- Index 8Eh
Bit Name R/W Default Description
The queue time for second filter to quickly update values.
00: disable.
7-6 IIR-QUEUR3 R/W
Nov., 2006
01: 16 times.
0h
10: 32 times. (default)
11: 48 times.
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The queue time for second filter to quickly update values.
00: disable.
5-4 IIR-QUEUR2 R/W
3-2 IIR-QUEUR1 R/W
0 Reserved R
Fan Control Setting
8.6.2.27 FAN PME# Enable Register Index 90h
Bit Name R/W Default Description
7-4 Reserved RO
01: 16 times.
0h
10: 32 times. (default)
11: 48 times.
The queue time for second filter to quickly update values.
00: disable.
01: 16 times.
0h
10: 32 times. (default)
11: 48 times.
0h
--
0h
Reserved
0h
3 EN_FAN4_PME R/W
EN_FAN3_PME R/W
2
1 EN_FAN2_PME R/W
EN_FAN1_PME R/W
0
8.6.2.28 FAN Interrupt Status Register Index 91h
Bit Name R/W Default Description
7-4 Reserved RO
3 FAN4_STS R/W
2 FAN3_STS R/W
A one enables the corresponding interrupt status bit for PME# interrupt.
Set this bit 1 to enable PME# function for Fan4.
0h
A one enables the corresponding interrupt status bit for PME# interrupt..
Set this bit 1 to enable PME# function for Fan3.
0h
A one enables the corresponding interrupt status bit for PME# interrupt.
Set this bit 1 to enable PME# function for Fan2.
0h
A one enables the corresponding interrupt status bit for PME# interrupt.
Set this bit 1 to enable PME# function for Fan1.
0
Reserved
This bit is set when the fan4 count exceeds the count limit. Write 1 to
-clear this bit, write 0 will be ignored.
This bit is set when the fan3 count exceeds the count limit. Write 1 to
-clear this bit, write 0 will be ignored.
1 FAN2_STS R/W
--
Nov., 2006
This bit is set when the fan2 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
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0 FAN1_STS R/W
8.6.2.29 FAN Real Time Status Register Index 92h
Bit Name R/W Default Description
7-4 Reserved -- 0 Reserved
3 FAN4_EXC RO
2 FAN3_EXC RO
1 FAN2_EXC RO
0 FAN1_EXC RO
8.6.2.30 FAN BEEP# Enable Register Index 93h
This bit is set when the fan1 count exceeds the count limit. Write 1 to
-clear this bit, write 0 will be ignored.
This bit set to high mean that fan4 count can’t meet expect count over than
-SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
This bit set to high mean that fan3 count can’t meet expect count over than
-SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
This bit set to high mean that fan2 count can’t meet expect count over than
-SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
This bit set to high mean that fan1 count can’t meet expect count over than
-SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
Bit Name R/W Default Description
7 FULL_WITH_T3_EN R/W 0
6 FULL_WITH_T2_EN R/W 0
5 FULL_WITH_T1_EN R/W 0
4 Reserved R/W 0
3 EN_FAN4_BEEP R/W
2 EN_FAN3_ BEEP R/W
1 EN_FAN2_ BEEP R/W
0 EN_FAN1_ BEEP R/W
8.6.2.31 Fan Type Select Register -- Index 94h
Bit Name R/W Default Description
7-6 FAN4_TYPE R/W
2’b0S
Set one will enable FAN to force full speed when T3 over high limit.
Set one will enable FAN to force full speed when T2 over high limit.
Set one will enable FAN to force full speed when T1 over high limit.
Reserved for local temperature.
0
A one enables the corresponding interrupt status bit for BEEP.
0
A one enables the corresponding interrupt status bit for BEEP.
0
A one enables the corresponding interrupt status bit for BEEP.
0
A one enables the corresponding interrupt status bit for BEEP.
00: Output PWM mode (pushpull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
terminal .
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
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00: Output PWM mode (pushpull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
5-4 FAN3_TYPE R/W
3-2 FAN2_TYPE R/W
1-0 FAN1_TYPE R/W
S: Register default values are decided by trapping.
8.6.2.32 Fan mode Select Register -- Index 96h
2’b 0S
2’b 0S
2’b 0S
terminal .
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
00: Output PWM mode (pushpull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
terminal .
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
00: Output PWM mode (push pull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
terminal .
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
Bit Name R/W Default Description
00: Auto fan speed control, fan speed will follow different temperature by
different RPM that define in 0xD6-0xDE.
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle that define in 0xD6-0xDE.
7-6 FAN4_MODE R/W
10: Manual mode fan control, user can write expect RPM count to
1h
0xD2-0xD3, and F71883 will auto control duty cycle (PWM fan type) or
voltage(linear fan type) to control fan speed.
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage(linear fan type) to 0xD3, and F71883 will output this value
duty or voltage to control fan speed.
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00: Auto fan speed control, fan speed will follow different temperature by
different RPM that define in 0xC6-0xCE.
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle that define in 0xC6-0xCE.
5-4 FAN3_MODE R/W
3-2 FAN2_MODE R/W
10: Manual mode fan control, user can write expect RPM count to
1h
0xC2-0xC3, and F71883 will auto control duty cycle (PWM fan type) or
voltage(linear fan type) to control fan speed.
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage(linear fan type) to 0xC3, and F71883 will output this value
duty or voltage to control fan speed.
00: Auto fan speed control, fan speed will follow different temperature by
different RPM that define in 0xB6-0xBE.
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle (voltage) that define in 0xB6-0xBE.
10: Manual mode fan control, user can write expect RPM count to
1h
0xB2-0xB3, and F71883 will auto control duty cycle (PWM fan type) or
voltage (linear fan type) to control fan speed.
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage (linear fan type) to 0xB3, and F71883 will output this value
duty or voltage to control fan speed.
00: Auto fan speed control, fan speed will follow different temperature by
different RPM that define in 0xA6-0xAE.
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle that define in 0xA6-0xAE.
1-0 FAN1_MODE R/W
8.6.2.33 Auto Fan1 and Fan2 Boundary Hystersis Select Register -- Index 98h
Bit Name R/W Default Description
7-4 FAN2_HYS R/W
10: Manual mode fan control, user can write expect RPM count to
1h
0xA2-0xA3, and F71883 will auto control duty cycle (PWM fan type) or
voltage(linear fan type) to control fan speed.
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage(linear fan type) to 0xA3, and F71883 will output this value
duty or voltage to control fan speed.
4h
0000: Boundary hysteresis. (0~15 degree C)
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
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4h
0000: Boundary hysteresis. (0~15 degree C)
3-0 FAN1_HYS R/W
8.6.2.34 Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 99h
Bit Name R/W Default Description
7-4 FAN4_HYS R/W
3-0 FAN3_HYS R/W
8.6.2.35 Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 9Bh
Bit Name R/W Default Description
7-6 FAN4_RATE_SEL R/W
5-4 FAN3_RATE_SEL R/W
3-2 FAN2_RATE_SEL R/W
1-0 FAN1_RATE_SEL R/W
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
2h
0000: Boundary hysteresis. (0~15 degree C)
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
2h
0000: Boundary hysteresis. (0~15 degree C)
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
Fan4 duty update rate:
1h
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
Fan3 duty update rate:
1h
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
Fan2 duty update rate:
1h
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
Fan1 duty update rate:
1h
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
8.6.2.36 FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE Index 9Ch
Bit Name R/W Default Description
5h
When fan start, the FAN_CTRL2 will increase duty-cycle from 0 to this
7-4
FAN2_STOP_DUTY
R/W
Nov., 2006
(value x 8) directly. And if fan speed is down, the FAN_CTRL 2 will
decrease duty-cycle to 0 when the PWM duty cycle is less than this (value
x 4).
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5h
When fan start, the FAN_CTRL 1 will increase duty-cycle from 0 to this
3-0
FAN1_STOP_DUTY
8.6.2.37 FAN3 and FAN4 START UP DUTY-CYCLE/VOLTAGE Index 9Dh
Bit Name R/W Default Description
7-4
FAN4_STOP_DUTY
R/W
R/W
3-0
FAN3_STOP_DUTY
R/W
(value x 8 directly. And if fan speed is down, the FAN_CTRL 1 will
decrease duty-cycle to 0 when the PWM duty cycle is less than this (value
x 4).
5h
When fan start, the FAN_CTRL 4 will increase duty-cycle from 0 to this
(value x 8) directly. And if fan speed is down, the FAN_CTRL 4 will
decrease duty-cycle to 0 when the PWM duty cycle is less than this (value
x 4).
5h
When fan start, the FAN_CTRL 3 will increase duty-cycle from 0 to this
(value x 8 directly. And if fan speed is down, the FAN_CTRL 3 will
decrease duty-cycle to 0 when the PWM duty cycle is less than this (value
x 4).
8.6.2.38 Fan Fault Time Register -- Index 9Fh
Bit Name R/W Default Description
7-5
4
3-0 F_FAULT_TIME R/W
Reserved
FULL_DUTY_SEL
Fan1 Index A0h- AFh
--
R/W
--
Reservd
0: the full duty is 100%.
-1: the full duty is 60% (default).
This register is power on trap by DTR1#.
This register determines the time of fan fault. The condition to cause fan
fault event is:
When PWM_Duty reaches FFh, if the fan speed count can’t reach the fan
expect count in time.
The unit of this register is 1 second. The default value is 11 seconds.
Ah
(Set to 0 , means 1 seconds. ; Set to 1, means 2 seconds.
Set to 2, means 3 seconds. …. )
Another condition to cause fan fault event is fan stop and the PWM duty is
greater than the minimum duty programmed by the register index 9C-9Dh.
Address Attribute
Default
Value
Nov., 2006
Description
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FAN1 count reading (MSB). At the moment of reading this register, the LSB will
A0h RO 8’h0f
be latched. This will prevent from data updating when reading. To read the fan
count correctly, read MSB first and followed read the LSB.
A1h RO 8’hff
A2h R/W 8’h00
A3h R/W 8’h01
A4h R/W 8’h03
A5h R/W 8’hff
FAN1 count reading (LSB).
RPM mode(CR96 bit0=0):
FAN1 expect speed count value (MSB), in auto fan mode (CR96 bit1Î0) this
register is auto updated by hardware.
Duty mode(CR96 bit0=1):
This byte is reserved byte.
RPM mode(CR96 bit0=0):
FAN1 expect speed count value (LSB) or expect PWM duty, in auto fan mode
this register is auto updated by hardware and read only.
Duty mode(CR96 bit0=1):
The Value programming in this byte is duty value. In auto fan mode(CR96
bit1Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Î 100%
FAN1 full speed count reading (MSB). At the moment of reading this register,
the LSB will be latched. This will prevent from data updating when reading. To
read the fan count correctly, read MSB first and followed read the LSB.
FAN1 full speed count reading (LSB).
8.6.2.39 VT1 BOUNDARY 1 TEMPERATURE – Index A6h
Bit Name R/W Default Description
7 Reserved RO 0 Return 0 when read.
3Ch
o
(60
C)
6-0 BOUND1TMP1 R/W
8.6.2.40 VT1 BOUNDARY 2 TEMPERAT URE – Index A7
Bit Name R/W Default Description
7 Reserved RO 0 Return 0 when read.
st
BOUNDARY temperature for VT1 in temperature mode.
The 1
When VT1 temperature is exceed this boundary, FAN1 expect value will
load from segment 1 register (index AA)h.
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
value will load from segment 2 register (index AAh).
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st
BOUNDARY temperature for VT1 in temperature mode.
The 2
When VT1 temperature is exceed this boundary, FAN1 expect value will
(50
32
o
C)
6-0 BOUND2TMP1 R/W
8.6.2.41 VT1 BOUNDARY 3 TEMPERATURE – Index A8h
Bit Name R/W Default Description
7 Reserved RO 0 Return 0 when read.
6-0 BOUND3TMP1 R/W
(40
load from segment 2 register (index AB)h.
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
value will load from segment 3 register (index ABh).
28h
o
C)
st
BOUNDARY temperature for VT1 in temperature mode.
The 3
When VT1 temperature is exceed this boundary, FAN1 expect value will
load from segment 3 register (index AC)h.
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
value will load from segment 4 register (index ACh).
8.6.2.42 VT1 BOUNDARY 4 TEMPERAT URE – Index A9
Bit Name R/W Default Description
7 Reserved RO 0 Return 0 when read.
1Eh
(30
o
C)
st
BOUNDARY temperature for VT1 in temperature mode.
The 4
When VT1 temperature is exceed this boundary, FAN1 expect value will
6-0 BOUND4TMP1 R/W
8.6.2.43 FAN1 SEGMENT 1 SPEED COUNT – Index AAh
Bit Name R/W Default Description
(100%)
7- 0 SEC1SPEED1 R / W
load from segment 4 register (index ADh).
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
value will load from segment 5 register (index ADh).
FFh
The meaning of this register is depending on the FAN1_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
Ex:
100%:full speed: User must set this register to 0.
60% full speed: (100-60)*32/60, so user must program 21 to this reg.
X% full speed: The value programming in this byte is Î (100-X)*32/X
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
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8.6.2.44 FAN1 SEGMENT 2 SPEED COUNT – Index ABh
Bit Name R/W Default Description
D9h
The meaning of this register is depending on the FAN1_MODE(CR96)
(85%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7- 0 SEC2SPEED1 R/ W
8.6.2.45 FAN1 SEGMENT 3 SPEED COUNT – Index ACh
Bit Name R/W Default Description
7- 0 SEC3SPEED1 R/ W
(70%)
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
B2h
The meaning of this register is depending on the FAN1_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.46 FAN1 SEGMENT 4 SPEED COUNT – Index ADh
Bit Name R/W Default Description
99h
The meaning of this register is depending on the FAN1_MODE(CR96)
(60%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7- 0 SEC4SPEED1 R / W
8.6.2.47 FAN1 SEGMENT 5 SPEED COUNT – Index AEh
Bit Name R/W Default Description
(50%)
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
80h
The meaning of this register is depending on the FAN1_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
7- 0 SEC5SPEED1 R / W
8.6.2.48 FAN1 Temper ature Mapping Select – Index AFh
Bit Name R/W Default Description
7-6 Reserved -- 0 Reserved
5 FAN1_UP_T_EN R /W 0
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
Set 1 to force FAN1 to full speed if any temperature over its high limit.
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4 FAN1_INTERPOLATION_EN R/W 0
3 FAN1_JUMP_HIGH_EN R/ W
2 FAN1_JUMP_LOW_EN R /W
Set 1 will enable the interpolation of the fan expect table.
This register controls the FAN1 duty movement when temperature over
0
highest boundary.
0: The FAN1 duty will increases with the slope selected by
FAN1_RATE_SEL register.
1: The FAN1 duty will directly jumps to the value of SEC1SPEED1
register.
This bit only activates in duty mode.
This register controls the FAN1 duty movement when temperature under
0
(highest boundary – hysteresis).
0: The FAN1 duty will decreases with the slope selected by
FAN1_RATE_SEL register.
1: The FAN1 duty will directly jumps to the value of SEC2SPEED1
register.
This bit only activates in duty mode.
0: reserved.
1-0 Fan1_temp_sel R/W
Fan2 Index B0h- BFh
Address Attribute
B0h RO 8’h0f
B1h RO 8’hff
B2h R/W 8’h00
1: fan1 follow temperature 1.
1
2: fan1 follow temperature 2.
3: fan1 follow temperature 3.
Default
Description
Value
FAN2 count reading (MSB). At the moment of reading this register, the LSB will
be latched. This will prevent from data updating when reading. To read the fan
count correctly, read MSB first and followed read the LSB.
FAN2 count reading (LSB).
RPM mode(CR96 bit2=0):
FAN2 expect speed count value (MSB), in auto fan mode(CR96 bit3Î0) this
register is auto updated by hardware.
Duty mode(CR96 bit2=1):
This byte is reserved byte.
RPM mode(CR96 bit2=0):
FAN2 expect speed count value (LSB) or expect PWM duty , in auto fan mode
this register is auto updated by hardware and read only.
Duty mode(CR96 bit2=1):
B3h R/W 8’h01
The Value programming in this byte is duty value. In auto fan mode(CR96
bit3Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Î 100%
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FAN2 full speed count reading (MSB). At the moment of reading this register,
B4h R/W 8’h03
B5h R/W 8’hff
8.6.2.49 VT2 BOUNDARY 1 TEMPERATURE – Index B6h
Bit Name R/W Default Description
7 Reserved RO 0 Return 0 when read.
the LSB will be latched. This will prevent from data updating when reading. To
read the fan count correctly, read MSB first and followed read the LSB.
FAN2 full speed count reading (LSB).
3Ch
(60
o
C)
st
BOUNDARY temperature for VT2 in temperature mode.
The 1
When VT2 temperature is exceed this boundary, FAN2 expect value will
6-0 BOUND1TMP2 R/W
8.6.2.50 VT2 BOUNDARY 2 TEMPERATURE – Index B7
Bit Name R/W Default Description
7 Reserved RO 0 Return 0 when read.
6-0 BOUND2TMP2 R/W
8.6.2.51 VT2 BOUNDARY 3 TEMPERATURE – Index B8h
Bit Name R/W Default Description
7 Reserved RO 0 Return 0 when read.
load from segment 1 register (index BA)h.
When VT2 temperature is below this boundary – hysteresis, FAN2 expect
value will load from segment 2 register (index BAh).
st
BOUNDARY temperature for VT2 in temperature mode.
The 2
When VT2 temperature is exceed this boundary, FAN2 expect value will
load from segment 2 register (index BB)h.
When VT2 temperature is below this boundary – hysteresis, FAN2 expect
value will load from segment 3 register (index BBh).
st
BOUNDARY temperature for VT2 in temperature mode.
The 3
When VT2 temperature is exceed this boundary, FAN2 expect value will
(50
(40
32
o
28h
o
C)
C)
6-0 BOUND3TMP2 R/W
8.6.2.52 VT2 BOUNDARY 4 TEMPERATURE – Index B9
Bit Name R/W Default Description
7 Reserved RO 0 Return 0 when read.
Nov., 2006
load from segment 3 register (index BC)h.
When VT2 temperature is below this boundary – hysteresis, FAN2 expect
value will load from segment 4 register (index BCh).
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1Eh
(30
o
C)
st
BOUNDARY temperature for VT2 in temperature mode.
The 4
When VT2 temperature is exceed this boundary, FAN2 expect value will
6-0 BOUND4TMP2 R/W
8.6.2.53 FAN2 SEGMENT 1 SPEED COUNT – Index BAh
Bit Name R/W Default Description
7- 0 SEC1SPEED2 R / W
(100%)
load from segment 4 register (index BDh).
When VT2 temperature is below this boundary – hysteresis, FAN2 expect
value will load from segment 5 register (index BDh).
FFh
The meaning of this register is depending on the FAN2_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
Ex:
100%:full speed: User must set this register to 0.
60% full speed: (100-60)*32/60, so user must program 21 to this reg.
X% full speed: The value programming in this byte is Î (100-X)*32/X
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.54 FAN2 SEGMENT 2 SPEED COUNT – Index BBh
Bit Name R/W Default Description
D9h
The meaning of this register is depending on the FAN2_MODE(CR96)
(85%)
7- 0 SEC2SPEED2 R/ W
8.6.2.55 FAN2 SEGMENT 3 SPEED COUNT – Index BCh
Bit Name R/W Default Description
(70%)
7- 0 SEC3SPEED2 R/ W
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
B2h
The meaning of this register is depending on the FAN2_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.56 FAN2 SEGMENT 4 SPEED COUNT – Index BDh
Bit Name R/W Default Description
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99h
The meaning of this register is depending on the FAN2_MODE(CR96)
(60%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7- 0 SEC4SPEED2 R / W
8.6.2.57 FAN2 SEGMENT 5 SPEED COUNT – Index BEh
Bit Name R/W Default Description
7- 0 SEC5SPEED2 R / W
(50%)
8.6.2.58 FAN2 Temper ature Mapping Select – Index BFh
Bit Name R/W Default Description
7-6 Reserved -- 0 Reserved
5 FAN2_UP_T_EN R /W 0
4 FAN2_INTERPOLATION_EN R/W 0
3 FAN2_JUMP_HIGH_EN R/ W
2 FAN2_JUMP_LOW_EN R /W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
80h
The meaning of this register is depending on the FAN2_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
Set 1 to force FAN2 to full speed if any temperature over its high limit.
Set 1 will enable the interpolation of the fan expect table.
This register controls the FAN2 duty movement when temperature over
0
highest boundary.
0: The FAN2 duty will increases with the slope selected by
FAN2_RATE_SEL register.
1: The FAN2 duty will directly jumps to the value of SEC1SPEED2
register.
This bit only activates in duty mode.
This register controls the FAN2 duty movement when temperature under
0
(highest boundary – hysteresis).
0: The FAN2 duty will decreases with the slope selected by
FAN2_RATE_SEL register.
1: The FAN2 duty will directly jumps to the value of SEC2SPEED2
register.
This bit only activates in duty mode.
0: reserved.
1-0 Fan2_temp_sel R/W
Fan3 Index C0h- CFh
1: fan2 follow temperature 1.
2
2: fan2 follow temperature 2.
3: fan2 follow temperature 3.
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Address Attribute
C0h RO 8’h0F
C1h RO 8’hff
C2h R/W 8’h00
Default
Value
C3h R/W 8’h01
Description
FAN3 count reading (MSB). At the moment of reading this register, the LSB will
be latched. This will prevent from data updating when reading. To read the fan
count correctly, read MSB first and followed read the LSB.
FAN3 count reading (LSB).
RPM mode(CR96 bit4=0):
FAN3 expect speed count value (MSB), in auto fan mode(CR96 bit5Î0) this
register is auto updated by hardware.
Duty mode(CR96 bit4=1):
This byte is reserved byte.
RPM mode(CR96 bit4=0):
FAN3 expect speed count value (LSB) or expect PWM duty , in auto fan mode
this register is auto updated by hardware and read only.
Duty mode(CR96 bit4=1):
The Value programming in this byte is duty value. In auto fan mode(CR96
bit5Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Î 100%
FAN3 full speed count reading (MSB). At the moment of reading this register,
C4h R/W 8’h03
C5h R/W 8’hff
8.6.2.59 VT3 BOUNDARY 1 TEMPERATURE – Index C6h
Bit Name R/W Default Description
7 Reserved RO 0 Return 0 when read.
6-0 BOUND1TMP3 R/W
8.6.2.60 VT3 BOUNDARY 2 TEMPERATURE – Index C7
the LSB will be latched. This will prevent from data updating when reading. To
read the fan count correctly, read MSB first and followed read the LSB.
FAN3 full speed count reading (LSB).
3Ch
(60
o
C)
st
BOUNDARY temperature for VT3 in temperature mode.
The 1
When VT3 temperature is exceed this boundary, FAN3 expect value will
load from segment 1 register (index CA)h.
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
value will load from segment 2 register (index CAh).
Bit Name R/W Default Description
7 Reserved RO 0 Return 0 when read.
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st
BOUNDARY temperature for VT3 in temperature mode.
The 2
When VT3 temperature is exceed this boundary, FAN3 expect value will
(50
32
o
C)
6-0 BOUND2TMP3 R/W
8.6.2.61 VT3 BOUNDARY 3 TEMPERATURE – Index C8h
Bit Name R/W Default Description
7 Reserved RO 0 Return 0 when read.
6-0 BOUND3TMP3 R/W
(40
load from segment 2 register (index CB)h.
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
value will load from segment 3 register (index CBh).
28h
o
C)
st
BOUNDARY temperature for VT3 in temperature mode.
The 3
When VT3 temperature is exceed this boundary, FAN3 expect value will
load from segment 3 register (index CC)h.
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
value will load from segment 4 register (index CCh).
8.6.2.62 VT3 BOUNDARY 4 TEMPERATURE – Index C9
Bit Name R/W Default Description
7 Reserved RO 0 Return 0 when read.
1Eh
(30
o
C)
st
BOUNDARY temperature for VT3 in temperature mode.
The 4
When VT3 temperature is exceed this boundary, FAN3 expect value will
6-0 BOUND4TMP3 R/W
8.6.2.63 FAN3 SEGMENT 1 SPEED COUNT – Index CAh
Bit Name R/W Default Description
(100%)
7- 0 SEC1SPEED3 R / W
load from segment 4 register (index CDh).
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
value will load from segment 5 register (index CDh).
FFh
The meaning of this register is depending on the FAN3_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
Ex:
100%:full speed: User must set this register to 0.
60% full speed: (100-60)*32/60, so user must program 21 to this reg.
X% full speed: The value programming in this byte is Î (100-X)*32/X
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
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