Page 1
F71862
F71862FG
Super Hardware Monitor + LPC I/O
Release Date: Nov., 2006
Version: V0.21P
Nov., 2006
V0.21P
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F71862 Datasheet Revision History
Version Date Page Revision History
0.10P 2006/04/21 - Preliminary Version
0.20P 2006/06/14 - Release Version
0.21P 2006/11/23 62 Modified the description of Wakeup Control Register 2Dh
F71862
bit 7(SPI_CS1_EN)
Please note that all data and specifications are subject to change without notice. All the trade marks of products
and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from
such improper use or sales.
Nov., 2006
V0.21P
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F71862
Table of Content
1. General Description........................................................................................................................6
2. Feature List .....................................................................................................................................6
3. Key Specification............................................................................................................................9
4. Block Diagram................................................................................................................................9
5. Pin Configuration..........................................................................................................................10
6. Pin Description..............................................................................................................................10
6.1 Power Pin..................................................................................................................................11
6.2 LPC Interface............................................................................................................................11
6.3 FDC...........................................................................................................................................11
6.4 UART and SIR..........................................................................................................................12
6.5 Parallel Port...............................................................................................................................14
6.6 Hardware Monitor.....................................................................................................................15
6.7 ACPI Function Pins ..................................................................................................................16
6.8 VID Controller and Others........................................................................................................17
6.9 KPC Function............................................................................................................................17
7. Function Description.....................................................................................................................18
7.1 Power on Strapping Option.......................................................................................................18
7.2 FDC...........................................................................................................................................18
7.3 UART........................................................................................................................................32
7.4 Parallel Port...............................................................................................................................35
7.5 Keyboard Contoller...................................................................................................................39
7.6 Hardware Monitor.....................................................................................................................41
7.7 SPI Interface..............................................................................................................................49
7.8 ACPI Function..........................................................................................................................49
7.9 AMDSI and Intel PECI Function..............................................................................................52
8. Register Description......................................................................................................................54
8.1 Global Control Registers...........................................................................................................58
8.2 FDC Registers (CR00)..............................................................................................................63
8.3 UART1 Registers (CR01).........................................................................................................65
8.4 UART 2 Registers (CR02)........................................................................................................66
8.5 Parallel Port Registers (CR03)..................................................................................................68
8.6 Hardware Monitor Registers (CR04)........................................................................................70
8.6.2.1 Configuration Register Index 01h..................................................................................70
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F71862
8.6.2.2 Configuration Register Index 02h..................................................................................70
8.6.2.3 Configuration Register Index 03h..................................................................................71
8.6.2.4 Configuration Register Index 0Ah.................................................................................71
8.6.2.5 Configuration Register Index 0Bh (MEAS_TYPE == 2’b01) ...................................71
8.6.2.6 Configuration Register Index 0Bh (MEAS_TYPE ==2’b10) ....................................72
8.6.2.7 Configuration Register Index 0Ch (MEAS_TYPE == 2’b01) ...................................72
8.6.2.8 Configuration Register Index 0Ch (MEAS_TYPE ==2’b10) ....................................72
8.6.2.9 Configuration Register Index 0Dh.................................................................................72
8.6.2.10 Configuration Register Index 0Eh...............................................................................72
8.6.2.11 Configuration Register Index 0Fh................................................................................72
8.6.2.12 Voltage1 Voltage reading and limit Index 20h- 4Fh .....................................................72
8.6.2.13 Temperature PME# Enable Register Index 60h...........................................................73
8.6.2.14 Temperature Interrupt Status Register Index 61h ........................................................73
8.6.2.15 Temperature Real Time Status Register Index 62h......................................................74
8.6.2.16 Temperature BEEP Enable Register Index 63h...........................................................74
8.6.2.17 OVT Output Enable Register 1 Index 66h...................................................................74
8.6.2.18 Temperature Sensor Type Register Index 6Bh ............................................................75
8.6.2.19 TEMP1 Limit Hystersis Select Register -- Index 6Ch.....................................................75
8.6.2.20 TEMP2 and TEMP3 Limit Hystersis Select Register -- Index 6Dh................................75
8.6.2.21 DIODE OPEN Status Register -- Index 6Fh....................................................................75
8.6.2.22 Temperature Filter Select Register -- Index 8Eh .............................................................76
8.6.2.23 FAN PME# Enable Register Index 90h.......................................................................76
8.6.2.24 FAN Interrupt Status Register
Index 91h.....................................................................76
8.6.2.25 FAN Real Time Status Register Index 92h..................................................................77
8.6.2.26 FAN BEEP# Enable Register Index 93h .....................................................................77
8.6.2.27 Fan Type Select Register -- Index 94h.............................................................................77
8.6.2.28 Fan mode Select Register -- Index 96h............................................................................78
8.6.2.29 Auto Fan1 and Fan2 Boundary Hystersis Select Register -- Index 98h..........................78
8.6.2.30 Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 99h..........................78
8.6.2.31 Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 9Bh..........................78
8.6.2.32 FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE
Index 9Ch........................79
8.6.2.33 FAN3 START UP DUTY-CYCLE/VOLTAGE Index 9Dh .........................................79
8.6.2.34 Fan Fault Time Register -- Index 9Fh..............................................................................79
8.6.2.35 VT1 BOUNDARY 1 TEMPERATURE – Index A6h......................................................80
8.6.2.36 VT1 BOUNDARY 2 TEMPERATURE – Index A9........................................................80
8.6.2.37 FAN1 SEGMENT 1 SPEED COUNT – Index ABh.....................................................80
8.6.2.38 FAN1 SEGMENT 2 SPEED COUNT – Index AEh...................................................80
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F71862
8.6.2.39 FAN1 Temperature Mapping Select – Index AFh.......................................................80
8.6.2.40 VT2 BOUNDARY 1 TEMPERATURE – Index B6h......................................................81
8.6.2.41 VT2 BOUNDARY 2 TEMPERATURE – Index B9........................................................81
8.6.2.42 FAN2 SEGMENT 1 SPEED COUNT – Index BBh.....................................................81
8.6.2.43 FAN2 SEGMENT 2 SPEED COUNT – Index BEh...................................................82
8.6.2.44 FAN2 Temperature Mapping Select – Index BFh.......................................................82
8.6.2.45 VT3 BOUNDARY 1 TEMPERATURE – Index C6h......................................................83
8.6.2.46 VT3 BOUNDARY 2 TEMPERATURE – Index C9........................................................83
8.6.2.47 FAN3 SEGMENT 1 SPEED COUNT – Index CBh.....................................................83
8.6.2.48 FAN3 SEGMENT 2 SPEED COUNT – Index CEh...................................................83
8.6.2.49 FAN3 Temperature Mapping Select – Index CFh.......................................................83
8.7 KBC Registers (CR05) .............................................................................................................84
8.8 GPIO Registers (CR06) ............................................................................................................85
8.9 VID Registers (CR07)...............................................................................................................92
8.10 SPI Registers (CR08)................................................................................................................94
8.11 PME and ACPI Registers (CR0A)............................................................................................97
9. Electron Characteristic................................................................................................................100
9.1 Absolute Maximum Ratings...................................................................................................100
9.2 DC Characteristics..................................................................................................................100
9.3 DC Characteristics Continued.................................................................................................100
10. Ordering Information..................................................................................................................101
11. Package Dimensions...................................................................................................................102
12. Application Circuit......................................................................................................................103
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F71862
1. General Description
The F71862 is the featured IO chip for PC system. Equipped with one IEEE 1284
Parallel Port, two UART Ports, Hardware Keyboard Controller, Serial Peripheral Interface
(SPI), SIR and one FDC. The F71862 integrated with hardware monitor, 9 sets of voltage
sensor, 3 sets of creative auto-controlling fans and 3 temperature sensor pins for the
accurate dual current type temp. measurement for CPU thermal diode or external
transistors 2N3906. Others, the F71862 supports newest AMDSI and Intel PECI interfaces
for temperature sensing.
The F71862 provides flexible features for multi-directional application. For instance,
supports 4-In and 4-Out pins CPU VID controlling with offset implement., provides 30 GPIO
pins (multi-pin), IRQ sharing function also designed in UART feature for particular usage
and accurate current mode H/W monitor will be worth in measurement of temperature,
provides 3 modes fan speed control mechanism included Manual Mode/Stage Auto
Mode/Linear Auto Mode for users’ selection.
The F71862 also integrated SPI interface. The SPI interface is for BIOS usage
including bridge function and back up function. User can implement BIOS data in second
flash to boot system when primary BIOS error. These features as above description will help
you more and improve product value. Finally, the F71862 is powered by 3.3V voltage, with
the LPC interface in the green package of 128-PQFP.
2. Feature List
General Functions
¾ Comply with LPC Spec. 1.0
¾ Support DPM (Device Power Management), ACPI
¾ 4-VIDIN and 4-VIDOUT for Vcore use.
¾ Provides one FDC, two UARTs, Hardware KBC and Parallel Port
¾ H/W monitor functions
¾ SPI interface for BIOS usage
¾ Support AMD SID/SIC interface and Intel PECI interface
¾ 30 GPIO Pins for flexible application
¾ 24/48 MHz clock input
¾ Packaged in 128-PQFP and powered by 3.3VCC
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F71862
FDC
¾ Compatible with IBM PC AT disk drive systems
¾ Variable write pre-compensation with track selectable capability
¾ Support vertical recording format
¾ DMA enable logic
¾ 16-byte data FIFOs
¾ Support floppy disk drives and tape drives
¾ Detects all overrun and under run conditions
¾ Built-in address mark detection circuit to simplify the read electronics
¾ Completely compatible with industry standard 82077
¾ 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
UART
¾ Two high-speed 16C550 compatible UART with 16-byte FIFOs
¾ Fully programmable serial-interface characteristics
¾ Baud rate up to 115.2K
¾ Support IRQ sharing
Infrared
¾ Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
Parallel Port
¾ One PS/2 compatible bi-directional parallel port
¾ Support Enhanced Parallel Port (EPP)
¾ Support Extended Capabilities Port (ECP)
specification
¾ Enhanced printer port back-drive current protection
− Compatible with IEEE 1284 specification
− Compatible with IEEE 1284
Keyboard Controller
¾ LPC interface support serial interrupt channel 1, 12.
¾ Two 16bit Programmable Address fully decoder, default 0x60 and 0x64.
¾ Support two PS/2 interface, one for PS/2 mouse and the other for keyboard.
¾ Keyboard’s scan code support set1, set2.
¾ Programmable compatibility with the 8042.
¾ Support both interrupt and polling modes.
¾ Fast Gate A20 and Hardware Keyboard Reset.
Hardware Monitor Functions
¾ 3 dual current type (±3℃) thermal inputs for CPU thermal diode and 2N3906 transistors
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¾ Temperature range -40℃~127 ℃
¾ 9 sets voltage monitoring (6 external and 3 internal powers)
¾ High limit signal (PME#) for Vcore level
¾ 3 fan speed monitoring inputs
¾ 3 fan speed PWM/DC control outputs(support 3 wire and 4 wire fans)
¾ Stage auto mode ( 2-Limit and 3-Stage)/Linear auto mode/Manual mode
¾ Issue PME# and OVT# hardware signals output
¾ Case intrusion detection circuit
¾ WATCHDOG comparison of all monitored values
Serial Peripheral Interface Compatible
¾ Support SPI Bridge Function for BIOS use
¾ Support Back Up BIOS function
Integrate AMD SI Interface
Integrate Intel PECI Interface
F71862
Package
¾ 128-pin PQFP Green Package
Noted: Patented TW207103 TW207104 TW220442 US6788131 B1 TWI235231 TW237183 TW235553
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3. Key Specification
r
Supply Voltage 3.0V to 3.6V
Operating Supply Current 10 mA typ.
4. Block Diagram
CPU
Chipset
(NB+SB)
F71862
Super H/W Monitor + I/O
F71862
IDE
USB
AC’97
Temperature
Voltage
Fan
AMDSI
A PECI
KBC
IrDA
Parallel
ACPI
SPI
LED(GPIO)
COM
Floppy
VID
Controlle
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5. Pin Configuration
F71862
6. Pin Description
I/O
- TTL level bi-directional pin with 12 mA source-sink cap ability.
12t
I/OOD
I/OD
16t5v
OD
16-u10-5v
I/OD
12ts5v
ILv/O
D8-S1
ILv/OD
- TTL level bi-directional pin, can select to OD or OUT by register, with 12 mA
12t
source-sink capability.
- TTL level bi-directional pin,Open-drain output with 16 mA source-sink capability, 5V
tolerance.
- Open-drain output pin with 16 mA sink capability, pull-up 10k ohms, 5V tolerance.
- TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink
capability, 5V tolerance.
- Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.). Output with 8mA drive and
1mA sink capability.
- Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.). Output with 12mA sink
12
capability.
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F71862
O
O
O
O30
AOUT - Output pin(Analog).
OD
OD
OD24
IN
INts
IN
AIN - Input pin(Analog).
P - Power.
6.1 Power Pin
Pin No. Pin Name Type Description
4,37,99 VCC P Power supply voltage input with 3.3V
68 VSB P Stand-by power supply voltage input 3.3V
86 VBAT P Battery voltage input
88 AGND(D-) P Analog GND
20, 48, 73, 117 GND P Digital GND
- Open-drain pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance.
8-u47-5v
8
12
- Output pin with 8 mA source-sink capability.
- Output pin with 12 mA source-sink capability.
- Output pin with 30 mA source-sink capability.
12
12-5v
- Open-drain output pin with 12 mA sink capability.
- Open-drain output pin with 12 mA sink capability, 5V tolerance.
- Open-drain output pin with 24 mA sink capability.
t5v
- TTL level input pin,5V tolerance.
- TTL level input pin and schmitt trigger.
- TTL level input pin and schmitt trigger, 5V tolerance.
ts5v
6.2 LPC Interface
Pin No. Pin Name Type PWR Description
29 LRESET# IN
VCC Reset signal. It can connect to PCIRST# signal on the
ts5v
host.
30 LDRQ# O12 VCC Encoded DMA Request signal.
31 SERIRQ I/O
VCC Serial IRQ input/Output.
12t
32 LFRAM# INts VCC Indicates start of a new cycle or termination of a
broken cycle.
36-33 LAD[3:0] I/O
VCC These signal lines communicate address, control, and
12t
data information over the LPC bus between a host and
a peripheral.
38 PCICLK INts VCC 33MHz PCI clock input.
39 CLKIN INts VCC System clock input. According to the input frequency
24/48MHz.
6.3 FDC
Pin No. Pin Name Type PWR Description
7
DENSEL#
OD24 VCC Drive Density Select.
Set to 1 - High data rate.(500Kbps, 1Mbps)
Set to 0 – Low data rate. (250Kbps, 300Kbps)
8
OD24 VCC Motor A On. When set to 0, this pin enables disk drive
MOA#
0. This is an open drain output.
9 DRVA# OD24 VCC Drive Select A. When set to 0, this pin enables disk
drive A. This is an open drain output.
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F71862
e
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e
10 WDATA# OD24 VCC Write data. This logic low open drain writes
pre-compensation serial data to the selected FDD. An
open drain output.
11 DIR# OD24 VCC Direction of the head step motor. An open drain output.
Logic 1 = outward motion
Logic 0 = inward motion
12 STEP# OD24 VCC Step output pulses. This active low open drain output
produces a pulse to move the head to another track.
13 HDSEL# OD24 VCC Head select. This open drain output determines which
disk drive head is active.
Logic 1 = side 0
Logic 0 = side 1
14 WGATE# OD24 VCC Write enable. An open drain output.
15 RDATA# IN
16 TRK0# IN
17 INDEX# IN
18 WPT# IN
19 DSKCHG# IN
VCC The read data input signal from the FDD.
ts5v
VCC Track 0. This Schmitt-triggered input from the disk
ts5v
drive is active low when the head is positioned over
the outermost track.
VCC This Schmitt-triggered input from the disk drive is
ts5v
active low when the head is positioned over the
beginning of a track marked by an index hole.
VCC Write protected. This active low Schmitt input from the
ts5v
disk drive indicates that the diskette is write-protected.
VCC Diskette change. This signal is active low at power on
ts5v
and whenever the diskette is removed.
6.4 UART and SIR
Pin No. Pin Name Type PWR Description
IRTX O12 Infrared Transmitter Output. 27
GPIO42 I/OOD
IRRX INts Infrared Receiver input. 28
GPIO43 I/OOD
118 DCD1# IN
119 RI1# IN
120 CTS1# IN
121
DTR1#
O
FAN60_100 IN
VCC Data Carrier Detect. An active low signal indicates th
t5v
VCC Ring Indicator. An active low signal indicates that a ring
t5v
VCC Clear To Send is the modem control input.
t5v
8-u47,5v
t5v
VCC
12t
General Purpose IO
VSB
12t
General Purpose IO.
modem or data set has detected a data carrier.
signal is being received from the modem or data set.
VCC
UART 1 Data Terminal Ready. An active low signa
informs the modem or data set that controller is ready t
communicate. Internal 47k ohms pulled high and disabl
after power on strapping.
Power on strapping pin:
1(Default): (Internal pull high)
Power on fan speed default duty is 60%.(PWM)
0: (External pull down)
Power on fan speed default duty is 100%.(PWM)
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122 RTS1#
s
o
e
e
a
t
h
e
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t
d
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O
123 DSR1# IN
124
SOUT1
O
Config4E_2E IN
125 SIN1 IN
126 DCD2# IN
F71862
VCC UART 1 Request To Send. An active low signal inform
8-u47,5v
the modem or data set that the controller is ready t
send data. Internal 47k ohms pulled high and disabl
after power on strapping.
VCC Data Set Ready. An active low signal indicates th
t5v
modem or data set is ready to establish
communication link and transfer data to the UART.
VCC
UART 1 Serial Output. Used to transmit serial data ou
8-u47,5v
to the communication link. Internal 47k ohms pulled hig
and disable after power on strapping.
t5v
VCC Serial Input. Used to receive serial data through th
t5v
VCC Data Carrier Detect. An active low signal indicates th
t5v
Power on strapping: 1(Default)Configuration register:4E
0 Configuration register:2E
communication link.
modem or data set has detected a data carrier.
127 RI2#
IN
128 CTS2# IN
1
DTR2#
O
FWH_TRAP IN
2
RTS2#
O
HPWM_DC IN
3 DSR2# IN
5
SOUT2
O
SPI_TRAP
IN
t5v
VCC Ring Indicator. An active low signal indicates that a rin
signal is being received from the modem or data set.
VCC Clear To Send is the modem control input.
t5v
VCC
UART 2 Data Terminal Ready. An active low signa
8-u47,5v
informs the modem or data set that controller is ready t
communicate. Internal 47k ohms pulled high and disabl
after power on strapping.
t5v
Power on strapping :
1(Default): SPI as a backup BIOS
0 : SPI as a primary BIOS
VCC
UART 2 Request To Send. An active low signal inform
8-u47,5v
the modem or data set that the controller is ready t
send data. Internal 47k ohms pulled high and disabl
after power on strapping.
t5v
Power on strapping :
1 (Default): Fan control method will be PWM Mode
0 Drive :Fan control method will be DAC Mode
VCC Data Set Ready. An active low signal indicates th
t5v
modem or data set is ready to establish
communication link and transfer data to the UART.
VCC
UART 2 Serial Output. Used to transmit serial data ou
8-u47,5v
to the communication link. Internal 47k ohms pulle
high and disable after power on strapping.
t5v
Power on strapping:
1(Default) : SPI function disable
0 : SPI function enable
6 SIN2 IN
66 GPIO17 I/OOD
t5v
VCC Serial Input. Used to receive serial data through th
communication link.
VSB General Purpose IO
12t
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F71862
6.5 Parallel Port
Pin No. Pin Name Type PWR Description
100 SLCT IN
101 PE IN
102 BUSY IN
103 ACK# IN
104 SLIN# OD
105 INIT#
106 ERR#
107 AFD# OD
108 STB# OD
109
110
111
112
113
114
115
116
I/O
PD0
I/O
PD1
I/O
PD2
I/O
PD3
I/O
PD4
I/O
PD5
I/O
PD6
I/O
PD7
VCC An active high input on this pin indicates that the
ts5v
printer is selected. Refer to the description of the
parallel port for definition of this pin in ECP and EPP
mode.
VCC An active high input on this pin indicates that the
ts5v
printer has detected the end of the paper. Refer to the
description of the parallel port for the definition of this
pin in ECP and EPP mode.
VCC An active high input indicates that the printer is not
ts5v
ready to receive data. Refer to the description of the
parallel port for definition of this pin in ECP and EPP
mode.
VCC An active low input on this pin indicates that the printer
ts5v
has received data and is ready to accept more data.
Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.
VCC Output line for detection of printer selection. Refer to
12-5v
the description of the parallel port for the definition of
this pin in ECP and EPP mode.
OD
VCC Output line for the printer initialization. Refer to the
12-5v
description of the parallel port for the definition of this
pin in ECP and EPP mode.
IN
ts5v
VCC An active low input on this pin indicates that the printer
has encountered an error condition. Refer to the
description of the parallel port for the definition of this
pin in ECP and EPP mode.
VCC An active low output from this pin causes the printer to
12-5v
auto feed a line after a line is printed. Refer to the
description of the parallel port for the definition of this
pin in ECP and EPP mode.
VCC An active low output is used to latch the parallel data
12-5v
into the printer. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
VCC Parallel port data bus bit 0. Refer to the description of
12ts5v
the parallel port for the definition of this pin in ECP and
EPP mode.
VCC Parallel port data bus bit 1.
12ts5v
VCC Parallel port data bus bit 2.
12ts5v
VCC Parallel port data bus bit 3.
12ts5v
VCC Parallel port data bus bit 4.
12ts5v
VCC Parallel port data bus bit 5.
12ts5v
VCC Parallel port data bus bit 6.
12ts5v
VCC Parallel port data bus bit 7.
12ts5v
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F71862
6.6 Hardware Monitor
Pin No. Pin Name Type PWR Description
93-97 VIN6~VIN2 AIN VCC Voltage Input 2 ~ 6.
98 Vcore(VIN1) AIN VCC Voltage Input for Vcore.
21 FANIN1 IN
22 FAN_CTL1 OD
ts5v
12-5v
AOUT
23 FANIN2 IN
24 FAN_CTL2 OD
ts5v
12-5v
AOUT
FANIN3 IN
ts5v
GPIO40 I/OOD
26
FAN_CTL3*
OD
12-5V
AOUT
GPIO41 I/OOD
89 D3+(System) AIN VCC Thermal diode/transistor temperature sensor input for
90 D2+ AIN VCC Thermal diode/transistor temperature sensor input.
91 D1+(CPU) AIN VCC CPU thermal diode/transistor temperature sensor
92 VREF AOUT
79
PME#
OD
12-5v
GPIO25 I/OOD
GPIO10 I/OOD
SPI_SLK O12
GPIO11 I/OOD
SPI_CS0# O12
61
GPIO12 I/OOD
SPI_MISO IN
t5v
VCC Fan 1 tachometer input.
VCC Fan 1 control output. This pin provides PWM
duty-cycle output or a voltage output.
VCC Fan 2 tachometer input.
VCC Fan 2 control output. This pin provides PWM
duty-cycle output or a voltage output.
VCC
12t
VCC
Fan 3 speed input. 25
General purpose IO.
Fan 3 control output. This pin provides PWM
duty-cycle output or a voltage output.
*This pin default function is FANCTL (PWM signal
output), please take care the application if user want to
implement GPIO function.
12t
General purpose IO.
system use.
input. This pin is for CPU use.
VCC Voltage sensor output.
VSB
Generated PME event. It supports the PCI PME#
interface. This signal allows the peripheral to request
the system to wake up from the S3 state.
12t
12t
VSB
General Purpose IO.
General purpose IO. 59
Serial clock output pin for SPI device.
12t
VSB
General purpose IO. 60
Function A: When using firmware hub BIOS for
primary BIOS and SPI BIOS for second BIOS, please
connect this pin to SPI BIOS chip select pin.
Function B: When using two SPI Flashes for primary
and back up BIOS, please connect this pin to primary
BIOS chip select pin.
VSB
12t
General purpose IO.
SPI master in/slave out pin.
FANCTL1_1 OD
12-5v
62
GPIO13 I/OOD
SPI_MOSI O12
BEEP OD24
63 GPIO14 I/OOD
Fan 1 control output. This pin provides PWM
duty-cycle open drain output for Intel 4-pin Fan.
12t
VSB
General purpose IO.
SPI master out/slave in pin.
Beep pin.
VSB General purpose IO.
12t
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F71862
67 OVT# OD
FWH_DIS O12 Firmware hub disable
WDTRST# OD
SPI_CS1# O
12
12-5v
12-5v
6.7 ACPI Function Pins
Pin No. Pin Name Type PWR Description
64
GPIO15 I/OOD
LED_VSB OD12 Power LED for VSB.
ALERT# OD
12
GPIO16 I/OOD
LED_VCC OD
12
PCIRST1# OD12 It is a output buffer of RSTCON# and LRESET#. 74
GPIO20 I/OOD
PCIRST2# O12 It is a output buffer of RSTCON# and LRESET#. 75
GPIO21 I/OOD
PCIRST3# O12 It is a output buffer of RSTCON# and LRESET#. 76
Watch dog timer signal output.
When using two SPI Flashes for primary and back up
BIOS, please connect this pin to back up BIOS chip
select pin.
VSB Over temperature signal output.
VSB
12t
VSB
12t
General purpose IO.
Alert a signal when temperature over limit setting.
General purpose IO. 65
Power LED for VCC.
VSB
12
General purpose IO.
VSB
12
General purpose IO.
VSB
GPIO22 I/OOD
77
S5# IN
GPIO23 I/OOD12 General purpose IO. (Default)
RSTCON#
OD
ATXPG_IN AIN ATX Power Good input. 78
84
GPIO24 I/OOD
PWROK OD12 PWROK function, It is power good signal of VCC,
GPIO32 I/OOD
PWSIN# IN
GPIO26 I/OOD
81
PWSOUT#
OD12 Panel Switch Output. This pin is low active and pulse
GPIO27 I/OOD
S3# IN
GPIO30 I/OOD
83
PSON#
OD
GPIO31 I/OOD
85
RSMRST#
OD12 Resume Reset# function, It is power good signal of
GPIO33 I/OOD
87 COPEN# IN
12
S5# signal input.
ts5v
12
VSB
General purpose IO.
RESET Connect# with 50ms debouce function, it
connects to reset button, and also other reset source
on the motherboard.
VSB
12t
General purpose IO.
VSB
which is delayed 400ms (default) as VCC arrives at
2.8V.
General purpose IO.
ts5v
12t
VSB Main power switch button input. 80
General purpose IO.
12t
VSB
output. It is power on request output#.
12t
ts5v
12-5v
VSB
12t
VSB Power supply on-off control output. Connect to ATX
General purpose IO.
S3# Input is Main power on-off switch input. 82
General purpose IO.
power supply PS_ON# signal.
General purpose IO.
12t
VBAT
VSB, which is delayed 66ms as VSB arrives at 2.3V.
12t
VBAT Case Open Detection #. This pin is connected to a
ts5v
General purpose IO.
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Nov., 2006
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specially designed low power CMOS flip-flop backed
by the battery for case open state preservation during
power loss.
6.8 VID Controller and Others
Pin No. Pin Name Type PWR Description
45-42 VIDIN[D:A] IN
52-49 VIDOUT[D:A] OD12 VSB CPU VID output pins.
ts5v
VCC CPU VID input pins.
Special level input VIHÆ 0.9, VIL Æ 0.6
F71862
46 GPIO44 I/OOD
47 GPIO45 I/OOD
53 GPIO00 I/OOD
54 GPIO01 I/OOD
55
ST2 OD
VCC General purpose IO.
12t
VCC General purpose IO.
12t
VSB General purpose pin.
12t
VSB General purpose pin.
12t
12
VSB
Status Pin2 for S0#/S3#/S5# states application.
In S0# Æ ST2 pin status is Tri-state.
In S3# Æ ST2 pin status is Low level.
In S5# Æ ST2 pin status is Low level, and can be
programmed to Tri-state.
56
SLOTOCC# IN
GPIO02 I/OOD
ST1 OD12 Status Pin1 for S0#/S3#/S5# states application.
ts5v
12t
VSB
CPU SLOTOCC# input.
General purpose pin.
In S0# Æ ST1 pin status is Tri-state.
In S3# Æ ST1 pin status is Low level.
In S5# Æ ST1 pin status is Tri-state.
GPIO03 I/OOD
WDTRST# OD
12-5v
12t
General purpose pin.
Watch dog timer signal output.
57 SIC OD12 VSB AMDSI interface clock output.
PECI ILv/O
SID I
Lv
/OD
D8-S1
12
VSB
Intel PECI hardware monitor interface. 58
AMDSI interface data input.
6.9 KPC Function
Pin No. Pin Name Type PWR Description
40 KBRST#
41 GA20
69 KDATA I/OD
70 KCLK I/OD
71 MDAT I/OD
72 MCLK I/OD
D
16-u10,5V
D
16-u10,5V
16t,5V
16t,5V
16t,5V
16t,5V
VCC Keyboard reset. This pin is high after system reset.
Internal pull high 3.3V with 10k ohms. (KBC P20)
VCC Gate A20 output. This pin is high after system reset.
Internal pull high 3.3V with 10k ohms. (KBC P21)
VSB Keyboard Data.
VSB Keyboard Clock.
VSB PS2 Mouse Data.
VSB PS2 Mouse Clock.
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F71862
7. Function Description
7.1 Power on Strapping Option
The F71862 provides four pins for power on hardware strapping to select functions. There
is a form to describe how to set the functions you want.
Pin No. Symbol Value Description
1 SPI as a backup BIOS (Default) 1 FWH_TRAP
0 SPI as a primary BIOS
1 Fan control mode: PWM mode. ( Default) 2 PWM_DC
0 Fan control mode: Linear mode.
1 SPI function disable (Default) 5 SPI_TRAP
0 SPI function enable
1 Power on Fan speed default duty is 60%(PWM)(Default) 121 FAN60_100
0 Power on Fan speed default duty is 100%(PWM)
1 Configuration Register I/O port is 4E/4F. (Default) 124 Config4E_2E
0 Configuration Register I/O port is 2E/2F.
7.2 FDC
The Floppy Disk Controller provides the interface between a host processor and one
floppy disk drives. It integrates a controller and a digital data separator with write
pre-compensation, data rate selection logic, microprocessor interface, and a set of registers.
The FDC supports data transfer rates of 250 Kbps, 300 Kbps, 500 Kbps, and 1 Mbps. It
operates in PC/AT mode and supports 3-mode type drives.
The FDC configuration is handled by software and a set of Configuration registers.
Status, Data, and Control registers facilitate the interface between the host microprocessor
and the disk drive, providing information about the condition and/or state of the FDC. These
configuration registers can select the data rate, enable interrupts, drives, and DMA modes,
and indicate errors in the data or operation of the FDC/FDD. The controller manages data
transfers using a set of data transfer and control commands. These commands are handled
in three phases: Command, Execution, and Result. Not all commands utilize all these three
phases.
The below content is about the FDC device register descriptions. All the registers are
for software porting reference.
Status Register A (PS/2 mode) Base + 0
Bit Name R/W Default Description
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F71862
7 INTPEND R 0 This bit indicates the state of the interrupt output.
6 DRV2_N R - 0: a second drive has been installed.
1: a second drive has not been installed.
5 STEP R 0 This bit indicates the complement of STEP# disk interface output.
4 TRK0_N R - This bit indicates the state of TRK0# disk interface input.
3 HDSEL R 0 This bit indicates the complement of HDSEL# disk interface output.
0: side 0.
1: side 1.
2 INDEX_N R - This bit indicates the state of INDEX# disk interface input.
1 WPT_N R - This bit indicates the state of WPT# disk interface input.
0: disk is write-protected.
1: disk is not write-protected.
0 DIR R 0 This bit indicates the complement of DIR# disk interface output.
Status Register A (Model 30 mode) Base + 0
Bit Name R/W Default Description
7 INTPEND R 0 This bit indicates the state of the interrupt output.
6 DRQ R 0 This bit indicates the state of the DRQ signal.
5 STEP_FF R 0 This bit indicates the complement of latched STEP# disk interface output.
4 TRK0 R - This bit indicates the complement of TRK0# disk interface input.
3 HDSEL_N R 1 This bit indicates the state of HDSEL# disk interface output.
0: side 0.
1: side 1.
2 INDEX R - This bit indicates the complement of INDEX# disk interface input.
1 WPT R - This bit indicates the complement of WPT# disk interface input.
0: disk is write-protected.
1: disk is not write-protected.
0 DIR_N R 1 This bit indicates the state of DIR# disk interface output.
0: head moves in inward direction.
1: head moves in outward direction.
Status Register B (PS/2 Mode) Base + 1
Bit Name R/W Default Description
7-6 Reserved R 11 Reserved. Return 11b when read.
5 DR0 R 0 Drive select 0. This bit reflects the bit 0 of Digital Output Register.
4 WDATA R 0 This bit changes state at every rising edge of WDATA#.
3 RDATA R 0 This bit changes state at every rising edge of RDATA#.
2 WGATE R 0 This bit indicates the complement of WGATE# disk interface output.
1 MOTEN1 R 0 This bit indicates the complement of MOB# disk interface output. Not support
in this design.
0 MOTEN0 R 0 This bit indicates the complement of MOA# disk interface output.
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F71862
Status Register B (Model 30 Mode) Base + 1
Bit Name R/W Default Description
7 DRV2_N R - 0: a second drive has been installed.
1: a second drive has not been installed.
6 DSB_N R 1 This bit indicates the state of DRVB# disk interface output. Not support in this
design.
5 DSA_N R 1 This bit indicates the state of DRVA# disk interface output.
4 WDATA_FF R 0 This bit is latched at the rising edge of WDATA# and is cleared by a read from
the Digital Input Register.
3 RDATA_FF R 0 This bit is latched at the rising edge of RDATA# and is cleared by a read form
the Digital Input Register.
2 WGATE_FF R 0 This bit is latched at the falling edge of WGATE# and is cleared by a read from
the Digital Input Register.
1 DSD_N R 1 This bit indicates the complement of DRVD# disk interface output. Not support
in this design.
0 DSC_N R 1 This bit indicates the complement of DRVC# disk interface output. Not support
in this design.
Digital Output Register Base + 2
Bit Name R/W Default Description
7 MOTEN3 R 0 Motor enable 3. Not support in this design.
6 MOTEN2 R 0 Motor enable 2. Not support in this design.
5 MOTEN1 R/W 0 Motor enable 1. Used to control MOB#. MOB# is not support in this design.
4 MOTEN0 R/W 0 Motor enable 0. Used to control MOA#.
3 DAMEN R/W 0 DMA enable. This bit has two mode of operation.
PC-AT and Model 30 mode: write 1 will enable DMA and IRQ, write 0 will
disable DMA and IRQ.
PS/2 mode: This bit is reserved. DMA and IRQ are always enabled in PS/2
mode.
2 RESET R 0 Write 0 to this bit will reset the controller. I will remain in reset condition until a 1
is written.
1 DSD_N R 1 This bit indicates the complement of DRVD# disk interface output. Not support
in this design.
0 DSC_N R 1 This bit indicates the complement of DRVC# disk interface output. Not support
in this design.
Tape Drive Register Base + 3
Bit Name R/W Default Description
7-6 Reserved R 00 Reserved. Return 00b when read.
5-4 TYPEID R 11 Reserved in normal function, return 11b when read.
If 3 mode FDD function is enabled. These bits indicate the drive type ID.
3-2 Reserved R 11 Reserved. Return 11b when read in normal function.
Return 00b when read in 3 mode FDD function.
1-0 TAPESEL R/W 0 These bits assign a logical drive number to be a tape drive.
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F71862
Main Status Register Base + 4
Bit Name R/W Default Description
7 RQM R 0 Request for Master indicates that the controller is ready to send or receive data
from the uP through the FIFO.
6 DIO R 0 Data I/O (direction):
0: the controller is expecting a byte to be written to the Data Register.
1: the controller is expecting a byte to be read from the Data Register.
5 NON_DMA R 0 Non DMA Mode:
0: the controller is in DAM mode.
1: the controller is interrupt or software polling mode.
4 FDC_BUSY R 0 This bit indicate that a read or write command is in process.
3 DRV3_BUSY R 0 FDD number 3 is in seek or calibration condition. FDD number 3 is not support
in this design.
2 DRV2_BUSY R 0 FDD number 2 is in seek or calibration condition. FDD number 2 is not support
in this design.
1 DRV1_BUSY R 0 FDD number 1 is in seek or calibration condition. FDD number 1 is not support
in this design.
0 DRV0_BUSY R 0 FDD number 0 is in seek or calibration condition.
Data Rate Select Register Base + 4
Bit Name R/W Default Description
7 SOFTRST W 0 A 1 written to this bit will software reset the controller. Auto clear after reset.
6 PWRDOWN W 0 A 1 to this bit will put the controller into low power mode which will turn off the
5 Reserved - - Return 0 when read.
4-2 PRECOMP W 000 Select the value of write precompensation:
1-0 DRATE W 10 Data rate select:
oscillator and data separator circuits.
250K-1Mbps 2Mbps
000: default delays default delays
001: 41.67ns 20.8ns
010: 83.34ns 41.17ns
011: 125.00ns 62.5ns
100: 166.67ns 83.3ns
101: 208.33ns 104.2ns
110: 250.00ns 125.00ns
111: 0.00ns (disabled) 0.00ns (disabled)
The default value of corresponding data rate:
250Kbps: 125ns
300Kbps: 125ns
500Kbps: 125ns
1Mbps: 41.67ns
2Mbps: 20.8ns
MFM FM
00: 500Kbps 250Kbps
01: 300Kbps 150Kbps
10: 250Kbps 125Kbps
11: 1Mbps illegal
Data (FIFO) Register Base + 5
Bit Name R/W Default Description
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F71862
7-0 DATA R/W 00h The FIFO is used to transfer all commands, data and status between controller
and the system. The Data Register consists of four status registers in a stack
with only one register presented to the data bus at a time. The FIFO is default
disabled and could be enabled via the CONFIGURE command.
Status Registers 0
Bit Name R/W Default Description
7-6 IC R - Interrupt code :
00: Normal termination of command.
01: Abnormal termination of command.
10: Invalid command.
11: Abnormal termination caused by poling.
5 SE R - Seek end.
Set when a SEEK or RECALIBRATE or a READ or WRITE with implied seek
command is completed.
4 EC R - Equipment check.
0: No error
1: When a fault signal is received form the FDD or the TRK0# signal fails to
occur after 77 step pulses.
3 NR R - Not ready.
0: Drive is ready
1: Drive is not ready.
2 HD R - Head address.
The current head address.
1-0 DS R - Drive select.
00: Drive A selected.
01: Drive B selected.
10: Drive C selected.
11: Drive D selected.
Status Registers 1
Bit Name R/W Default Description
7 EN R - End of Track.
Set when the FDC tries to access a sector beyond the final sector of a cylinder.
6 DE R - Data Error.
The FDC detect a CRC error in either the ID field or the data field of a sector.
4 OR R - Overrun/Underrun.
Set when the FDC is not serviced by the host system within a certain time
interval during data transfer.
3 Reserved - - Unused. This bit is always “0”
2 ND R - No Data.
Set when the following conditions occurred:
1. The specified sector is not found during any read command.
2. The ID field cannot be read without errors during a READ ID command.
3. The proper sector sequence cannot be found during a READ TRACK
command.
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1 NW R - No Writable
Set when WPT# is active during execution of write commands.
0 MA R - Missing Address Mark.
Set when the following conditions occurred:
1. Cannot detect an ID address mark at the specified track after
encountering the index pulse form the INDEX# pin twice.
2. Cannot detect a data address mark or a deleted data address mark on the
specified track.
Status Registers 2
Bit Name R/W Default Description
7 Reserved - - Unused. This bit is always “0”.
6 CM R - Control Mark.
Set when following conditions occurred:
1. Encounters a deleted data address mark during a READ DATA command.
2. Encounters a data address mark during a READ DELETED DATA
command.
5 DD R - Data Error in Data Field.
The FDC detects a CRC error in the data field.
4 WC R - Wrong Cylinder.
Set when the track address from the sector ID field is different from the track
address maintained inside the FDC.
3 SE R - Scan Equal.
Set if the equal condition is satisfied during execution of the SCAN command.
2 SN R - Scan Not Satisfied.
Set when the FDC cannot find a sector on the track which meets the desired
condition during any scan command.
1 BC R - Bad Cylinder.
The track address from the sector ID field is different from the track address
maintained inside the FDC and is equal to FFh which indicates a bad track.
0 MD R - Missing Data Address Mark.
Set when the FDC cannot detect a data address mark or a deleted data
address mark.
F71862
Status Registers 3
Bit Name R/W Default Description
7 Reserved - - Unused. This bit is always “0”.
6 WP R - Write Protect.
Indicates the status of WPT# pin.
5 Reserved R - Unused. This bit is always “1”.
4 T0 R - Track 0.
Indicates the status of the TRK0# pin.
3 Reserved. R - Unused. This bit is always “1”.
2 HD R - Head Address.
Indicates the status of the HDSEL# pin.
1 DS1 R - Drive Select.
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F71862
0 DS0 R -
Digital Input Register (PC-AT Mode) Base + 7
Bit Name R/W Default Description
7 DSKCHG R - This bit indicates the complement of DSKCHG# disk interface input.
6-0 Reserved R - Reserved.
Digital Input Register (PS/2 Mode) Base + 7
Bit Name R/W Default Description
7 DSKCHG R - This bit indicates the complement of DSKCHG# disk interface input.
6-3 Reserved - - Reserved.
2-1 DRATE R 10 These bits indicate the status of the DRATE programmed through the Data
0 HIGHDEN_N R 1 0: 1Mbps or 500Kbps data rate is chosen.
Digital Input Register (Model 30 Mode) Base + 7
These two bits indicate the DS1, DS0 bits in the command phase.
Rate Select Register or Configuration Control Register.
1: 300Kbps or 250Kbps data rate is chosen.
Bit Name R/W Default Description
7 DSKCHG_N R - This bit indicates the state of DSKCHG# disk interface input.
6-4 Reserved - - Reserved.
3 DMAEN R 0 This bit reflects the DMA bit in Digital Output Register.
2 NOPRE R 0 This bit reflects the NOPRE bit in Configuration Control Register.
1-0 DRATE R 10 These bits indicate the status of DRATE programmed through the Data Rate
Select Register or Configuration Control Register.
Configuration Control Register (PC-AT and PS/2 Mode) Base + 7
Bit Name R/W Default Description
7-2 Reserved - - Reserved.
1-0 DRATE W 10 These bit determine the data rate of the floppy controller. See DRATE bits in
Data Rate Select Register.
Configuration Control Register (Model 30 Mode) Base + 7
Bit Name R/W Default Description
7-3 Reserved - - Reserved.
2 NOPRE W 0 This bit could be programmed through Configuration Control Register and be
read through the bit 2 in Digital Input Register in Model 30 Mode. But it has no
functionality.
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F71862
1-0 DRATE W 10 These bit determine the data rate of the floppy controller. See DRATE bits in
Data Rate Select Register.
FDC Commands
Terminology:
C Cylinder Number 0 -256
D Data Pattern
DIR Step Direction
0: step out
1: step in
DS0 Drive Select 0
DS1 Drive Select 1
DTL Data Length
EC Enable Count
EOT End of Track
EFIFO Enable FIFO
0: FIFO is enabled.
1: FIFO is disabled.
EIS Enable Implied Seek
FIFOTHR FIFO Threshold
GAP Alters Gap Length
GPL Gap Length
H/HDS Head Address
HLT Head Load Time
HUT Head Unload Time
LOCK Lock EFIFO, FIFOTHR, PTRTRK bits.
Prevent these bits from being affected by software reset.
MFM MFM or FM mode
0: FM
1: MFM
MT Multi-Track
N Sector Size Code. All values up to 07h are allowable.
00: 128 bytes
01: 256 bytes
.. ..
07 16 Kbytes
NCN New Cylinder Number
ND Non-DMA Mode
OW Overwritten
PCN Present Cylinder Number
POLL Polling disa ble
0: polling is enabled.
1: polling is disabled.
PRETRK Precompensation Start Track Number
R Sector address
RCN Relative Cylinder Number
SC Sector per Cylinder
SK Skip deleted data address mark
SRT Step Rate Time
ST0 Status Register 0
ST1 Status Register 1
ST2 Status Register 2
ST3 Status Register 3
WGATE Write Gate alters timing of WE.
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F71862
Read Data
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W MT MFM SK 0 0 1 1 0 Command code
W 0 0 0 0 0 HDS DS1 DS0
W ----------------------------- C ---------------------------
W ----------------------------- H ---------------------------
W ----------------------------- R ---------------------------
W ------------------------------ N ---------------------------
W ---------------------------- EOT --------------------------
W ---------------------------- GPL --------------------------
W ---------------------------- DTL --------------------------
Execution Data transfer
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
R ----------------------------- N ---------------------------
Sector ID
information prior to
command
execution
between the FDD
and system
Status information
after command
execution.
Sector ID
information after
command
execution.
Read Deleted Data
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W MT MFM SK 0 1 1 0 0 Command code
Execution Data transfer
Result R ---------------------------- ST0 --------------------------
W 0 0 0 0 0 HDS DS1 DS0
W ----------------------------- C ---------------------------
W ----------------------------- H ---------------------------
W ----------------------------- R ---------------------------
W ------------------------------ N ---------------------------
W ---------------------------- EOT --------------------------
W ---------------------------- GPL --------------------------
W ---------------------------- DTL --------------------------
R ----------------------------- ST1 --------------------------
Sector ID
information prior to
command
execution
between the FDD
and system
Status information
after command
execution.
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R ---------------------------- ST2 --------------------------
F71862
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
R ----------------------------- N ---------------------------
Read A Track
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 MFM 0 0 0 0 1 0 Command code
W 0 0 0 0 0 HDS DS1 DS0
W ----------------------------- C ---------------------------
W ----------------------------- H ---------------------------
W ----------------------------- R ---------------------------
W ------------------------------ N ---------------------------
W ---------------------------- EOT --------------------------
W ---------------------------- GPL --------------------------
W ---------------------------- DTL --------------------------
Execution Data transfer
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
Sector ID
information after
command
execution.
Sector ID
information prior to
command
execution
between the FDD
and system. FDD
reads contents of
all cylinders from
index hole to EOT.
Status information
after command
execution.
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
R ----------------------------- N ---------------------------
Read ID
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 MFM 0 0 1 0 1 0 Command code
W 0 0 0 0 0 HDS DS1 DS0
Execution The first correct ID
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
Sector ID
information after
command
execution.
information on the
cylinder is stored in
Data Register.
Status information
after command
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R ---------------------------- ST2 --------------------------
F71862
execution.
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
R ----------------------------- N ---------------------------
Verify
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W MT MFM SK 1 0 1 1 0 Command code
W EC 0 0 0 0 HDS DS1 DS0
W ----------------------------- C ---------------------------
W ----------------------------- H ---------------------------
W ----------------------------- R ---------------------------
W ------------------------------ N ---------------------------
W ---------------------------- EOT --------------------------
W ---------------------------- GPL --------------------------
Disk status after
the command has
been completed.
Sector ID
information prior to
command
execution
W -------------------------- DTL/SC ------------------------
Execution No data transfer
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
R ----------------------------- N ---------------------------
Version
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 1 0 0 0 0 Command code
Result R 1 0 0 1 0 0 0 0 Enhanced
Write Data
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W MT MFM 0 0 0 1 0 1 Command code
Status information
after command
execution.
Sector ID
information after
command
execution.
controller
W 0 0 0 0 0 HDS DS1 DS0
W ----------------------------- C --------------------------- Sector ID
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F71862
W ----------------------------- H ---------------------------
W ----------------------------- R ---------------------------
W ------------------------------ N ---------------------------
W ---------------------------- EOT --------------------------
W ---------------------------- GPL --------------------------
W ---------------------------- DTL --------------------------
Execution Data transfer
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
information prior to
command
execution
between the FDD
and system.
Status information
after command
execution.
Write Deleted Data
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W MT MFM 0 0 1 0 0 1 Command code
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
R ----------------------------- N ---------------------------
W 0 0 0 0 0 HDS DS1 DS0
W ----------------------------- C ---------------------------
W ----------------------------- H ---------------------------
W ----------------------------- R ---------------------------
W ------------------------------ N ---------------------------
W ---------------------------- EOT --------------------------
W ---------------------------- GPL --------------------------
Sector ID
information after
command
execution.
Sector ID
information prior to
command
execution
W ---------------------------- DTL --------------------------
Execution Data transfer
between the FDD
and system.
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
R ----------------------------- C ---------------------------
R ----------------------------- H ---------------------------
R ----------------------------- R ---------------------------
R ----------------------------- N ---------------------------
29
Status information
after command
execution.
Sector ID
information after
command
execution.
Nov., 2006
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Page 30
Format A Track
F71862
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 MFM 0 0 1 1 0 1 Command code
W 0 0 0 0 0 HDS DS1 DS0
W ------------------------------ N --------------------------- Bytes/Sector
W ---------------------------- SC -------------------------- Sectors/Cylinder
W ---------------------------- GPL -------------------------- Gap 3 Length
W ----------------------------- D --------------------------- Data Pattern
Execution
for each
sector
( repeat )
Result R ---------------------------- ST0 --------------------------
R ----------------------------- ST1 --------------------------
R ---------------------------- ST2 --------------------------
------------------------------ C ---------------------------
W ------------------------------ H ---------------------------
W ------------------------------ R ---------------------------
W ----------------------------- N --------------------------
Input sector
parameter.
Status information
after command
execution.
R ------------------------- Undefined ----------------------
R ------------------------- Undefined ----------------------
R -------------------------- Undefined -----------------------
R ------------------------- Undefined ----------------------
Recalibrate
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 0 0 1 1 1 Command code
W 0 0 0 0 0 0 DS1 DS0
Execution Head retracted to
Sense Interrupt Status
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 0 1 0 0 0 Command code
Result R ---------------------------- ST0 --------------------------
R ---------------------------- PCN --------------------------
Specify
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 0 0 0 1 1 Command code
track 0
W |------------------ SRT -------------------| |------------------ HUT -------------------|
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W |------------------------------------- SRT ---------------------------------------| ND
Seek
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 0 1 1 1 1 Command code
W 0 0 0 0 0 HDS DS1 DS0
W ---------------------------- NCN --------------------------
Execution Head positioned
over proper
cylinder on diskette
Configure
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 1 0 0 1 1 Command code
W 0 0 0 0 0 HDS DS1 DS0
W 0 EIS EFIFO POLL |---------------- FIFOTHR ---------------|
W ---------------------------- PRETRK --------------------------
Execution Internal registers
Relative Seek
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 1 DIR 0 0 1 1 1 1 Command code
W 0 0 0 0 0 HDS DS1 DS0
W ---------------------------- RCN --------------------------
Perpendicular Mode
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 1 0 0 1 0 Command code
W OW 0 D3 D2 D1 D0 GAP WGATE
Lock
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W LOCK 0 0 1 0 1 0 0 Command code
Result R 0 0 0 LOCK 0 0 0 0
written
Dumpreg
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 0 1 1 1 0 Command code
Result R -------------------------- PCN ( Drive 0 ) ------------------------
R -------------------------- PCN ( Drive 0 ) ------------------------
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Sense Drive Status
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
Command W 0 0 0 0 0 1 0 0 Command code
Result R ---------------------------- ST3 -------------------------- Status information
Invalid
Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark
F71862
R -------------------------- PCN ( Drive 0 ) ------------------------
R -------------------------- PCN ( Drive 0 ) ------------------------
R |------------------ SRT -------------------| |------------------ HUT -------------------|
R |------------------------------------- SRT ---------------------------------------| ND
R -------------------------- SC/EOT ------------------------
R LOCK 0 D3 D2 D1 D0 GAP WGATE
R 0 EIS EFIFO POLL |---------------- FIFOTHR ---------------|
R ---------------------------- PRETRK --------------------------
W 0 0 0 0 0 HDS DS1 DS0
abut disk drive
Command W ---------------------------- Invalid Codes -------------------------- FDC goes to
standby state.
Result R ---------------------------- ST0 -------------------------- ST0 = 80h
7.3 UART
The F71862 provides two UART ports and supports IRQ sharing for system
application. The UARTs are used to convert data between parallel format and serial format.
They convert parallel data into serial format on transmission and serial format into parallel
data on receiver side. The serial format is formed by one start bit, followed by five to eight
data bits, a parity bit if programmed and one ( 1.5 or 2 ) stop bits. The UARTs include
complete modem control capability and an interrupt system that may be software trailed to
the computing time required to handle the communication link. They have FIFO mode to
reduce the number of interrupts presented to the host. Both receiver and transmitter have a
16-byte FIFO.
The below content is about the UART1 and UART2 device register descriptions. All
the registers are for software porting reference.
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Receiver Buffer Register Base + 0
Bit Name R/W Default Description
7-0 RBR R 00h
Transmitter Holding Register Base + 0
Bit Name R/W Default Description
7-0 THR W 00h
Divisor Latch (LSB) Base + 0
Bit Name R/W Default Description
7-0 DLL R/W 01h
Divisor Latch (MSB) Base + 1
Bit Name R/W Default Description
7-0 DLM R/W 00h
The data received.
Read only when LCR[7] is 0
Data to be transmitted.
Write only when LCR[7] is 0
Baud generator divisor low byte.
Access only when LCR[7] is 1.
Baud generator divisor high byte.
Access only when LCR[7] is 1.
F71862
Interrupt Enable Register Base + 1
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3 EDSSI R/W 0 Enable Modem Status Interrupt. Access only when LCR[7] is 0.
2 ELSI R/W 0 Enable Line Status Error Interrupt. Access only when LCR[7] is 0.
1 ETBFI R/W 0 Enable Transmitter Holding Register Empty Interrupt. Access only when
LCR[7] is 0.
0 ERBFI R/W 0 Enable Received Data Available Interrupt. Access only when LCR[7] is 0.
Interrupt Identification Register Base + 2
Bit Name R/W Default Description
7 FIFO_EN R 0
6 FIFO_EN R 0
5-4 Reserved - - Reserved.
3-1 IRQ_ID R 000
0 IRQ_PENDN R 1
0: FIFO is disabled
1: FIFO is enabled.
0: FIFO is disabled
1: FIFO is enabled.
000: Interrupt is caused by Modem Status
001: Interrupt is caused by Transmitter Holding Register Empty
010: Interrupt is caused by Received Data Available.
110: Interrupt is caused by Character Timeout
011: Interrupt is caused by Line Status.
1: Interrupt is not pending.
0: Interrupt is pending.
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FIFO Control Register Base + 2
Bit Name R/W Default Description
7-6 RCV_TRIG W 00
5-3 Reserved - - Reserved.
2 CLRTX R 0
1 CLRRX R 0
0 FIFO_EN R 0
Line Control Register Base + 3
Bit Name R/W Default Description
7 DLAB R/W 0
6 SETBRK R/W 0
5 STKPAR R/W 0
4 EPS R/W 0
3 PEN R/W 0
2 STB R/W 0
1-0 WLS R/W 00
00: Receiver FIFO trigger level is 1.
01: Receiver FIFO trigger level is 4.
10: Receiver FIFO trigger level is 8.
11: Receiver FIFO trigger level is 14.
Reset the transmitter FIFO.
Reset the receiver FIFO.
0: Disable FIFO.
1: Enable FIFO.
0: Divisor Latch can’t be accessed.
1: Divisor Latch can be accessed via Base and Base+1.
0: Transmitter is in normal condition.
1: Transmit a break condition.
XX0: Parity Bit is disable
001: Parity Bit is odd.
011: Parity Bit is even
101: Parity Bit is logic 1
111: Parity Bit is logic 0
0: Stop bit is one bit
1: When word length is 5 bit stop bit is 1.5 bit
else stop bit is 2 bit
00: Word length is 5 bit
01: Word length is 6 bit
10: Word length is 7 bit
11: Word length is 8 bit
F71862
MODEM Control Register Base + 4
Bit Name R/W Default Description
7-5 Reserved - -
4 LOOP R/W 0
3 OUT2 R/W 0
2 OUT1 R/W 0
1 RTS R/W 0
0 DTR R/W 0
Line Status Register Base + 5
Bit Name R/W Default Description
7 RCR_ERR R 0
6 TEMT R 1
Reserved.
0: UART in normal condition.
1: UART is internal loop back
0: All interrupt is disabled.
1: Interrupt is enabled (disabled) by IER.
Read from MSR[6] is loop back mode
0: RTS# is forced to logic 1
1: RTS# is forced to logic 0
0: DTR# is forced to logic 1
1: DTR# is forced to logic 0
0: No error in the FIFO when FIFO is enabled
1: Error in the FIFO when FIFO is enabled.
0: Transmitter is in transmitting.
1: Transmitter is empty.
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5 THRE R 1
4 BI R 0
3 FE R 0
2 PE R 0
1 OE R 0
0 DR R 0
MODEM Status Register Base + 6
Bit Name R/W Default Description
7 DCD R -
6 RI R -
5 DSR R -
4 CTS R -
3 DDCD R 0
2 TERI R 0
1 DDSR R 0
0 DCTS R 0
0: Transmitter Holding Register is not empty.
1: Transmitter Holding Register is empty.
0: No break condition detected.
1: A break condition is detected.
0: Data received has no frame error.
1: Data received has frame error.
0: Data received has no parity error.
1: Data received has parity error.
0: No overrun condition occurred.
1: An overrun condition occurred.
0: No data is ready for read.
1: Data is received.
Complement of DCD# input. In loop back mode, this bit is equivalent to OUT2
in MCR.
Complement of RI# input. In loop back mode , this bit is equivalent to OUT1 in
MCR
Complement of DSR# input. In loop back mode , this bit is equivalent to DTR in
MCR
Complement of CTS# input. In loop back mode , this bit is equivalent to RTS in
MCR
0: No state changed at DCD#.
1: State changed at DCD#.
0: No Trailing edge at RI#.
1: A low to high transition at RI#.
0: No state changed at DSR#.
1: State changed at DSR#.
0: No state changed at CTS#.
1: State changed at CTS#.
F71862
Scratch Register Base + 7
Bit Name R/W Default Description
7-0 SCR R/W 00h
Scratch register.
7.4 Parallel Port
The parallel port in F71862 supports an IBM XT/AT compatible parallel port ( SPP ),
bi-directional paralle port ( BPP ), Enhanced Parallel Port ( EPP ), Extended Capabilities
Parallel Port ( ECP ) mode. Refer to the configuration registers for more information on
selecting the mode of operation.
The below content is about the Parallel Port device register descriptions. All the
registers are for software porting reference.
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Parallel Port Data Register Base + 0
Bit Name R/W Default Description
7-0 DATA R/W 00h The output data to drive the parallel port data lines.
ECP Address FIFO Register Base + 0
Bit Name R/W Default Description
F71862
7-0 ECP_AFIFO R/W 00h
Device Status Register Base + 1
Bit Name R/W Default Description
7 BUSY_N R - Inverted version of parallel port signal BUSY.
6 ACK_N R - Version of parallel port signal ACK#.
5 PERROR R - Version of parallel port signal PE.
4 SELECT R - Version of parallel port signal SLCT.
3 ERR_N R - Version of parallel port signal ERR#.
Access only in ECP Parallel Port Mode and the ECP_MODE programmed in
the Extended Control Register is 011.
The data written to this register is placed in the FIFO and tagged as an
Address/RLE. It is auto transmitted by the hardware. The operation is only
defined for forward direction. It divide into two parts :
Bit 7 :
0: bits 6-0 are run length, indicating how many times the next byte to appear (0
= 1time, 1 = 2times, 2 = 3times and so on).
1: bits 6-0 are a ECP address.
Bit 6-0 :
Address or RLE depends on bit 7.
2-1 Reserved R 11 Reserved. Return 11b when read.
0 TMOUT R - This bit is valid only in EPP mode. Return 1 when in other modes.
It indicates that a 10uS time out has occurred on the EPP bus.
0: no time out error.
1: time out error occurred, write 1 to clear.
Device Control Register Base + 2
Bit Name R/W Default Description
7-6 Reserved - 11 Reserved. Return 11b when read.
5 DIR R/W 0 0: the parallel port is in output mode.
1: the parallel port is in input mode.
It is auto reset to 0 when in SPP mode.
4 ACKIRQ_EN R/W 0 Enable an interrupt at the rising edge of ACK#.
3 SLIN R/W 0 Inverted and then drives the parallel port signal SLIN#.
When read, the status of inverted SLIN# is return.
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2 INIT_N R/W 0 Drives the parallel port signal INIT#.
When read, the status of INIT# is return.
1 AFD R/W 0 Inverted and then drives the parallel port signal AFD#.
When read, the status of inverted AFD# is return.
0 STB R/W 0 Inverted and then drives the parallel port signal STB#.
When read, the status of inverted STB# is return.
EPP Address Register Base + 3
Bit Name R/W Default Description
F71862
7-0 EPP_ADDR R/W 00h
EPP Data Register Base + 4 – Base + 7
Bit Name R/W Default Description
7-0 EPP_DATA R/W 00h
Parallel Port Data FIFO Base + 400h
Bit Name R/W Default Description
7-0 C_FIFO R/W 00h Data written to this FIFO is auto transmitted by the hardware to the device by
Write this register will cause the hardware to auto transmit the written data to
the device with the EPP Address Write protocol.
Read this register will cause the hardware to auto receive data from the device
by with the EPP Address Read protocol.
Write this register will cause the hardware to auto transmit the written data to
the device with the EPP Data Write protocol.
Read this register will cause the hardware to auto receive data from the device
by with the EPP Data Read protocol.
using standard parallel port protocol.
It is only valid in ECP and the ECP_MODE is 010b.The operation is only for
forward direction.
ECP Data FIFO Base + 400h
Bit Name R/W Default Description
7-0 ECP_DFIFO R/W 00h Data written to this FIFO when DIR is 0 is auto transmitted by the hardware to
the device by using ECP parallel port protocol.
Data is auto read from device into the FIFO when DIR is 1 by the hardware by
using ECP parallel port protocol. Read the FIFO will return the content to the
system.
It is only valid in ECP and the ECP_MODE is 011b.
ECP Test FIFO Base + 400h
Bit Name R/W Default Description
7-0 T_FIFO R/W 00h Data may be read, written from system to the FIFO in any Direction. But no
hardware handshake occurred on the parallel port lines. It could be used to test
the empty, full and threshold of the FIFO.
It is only valid in ECP and the ECP_MODE is 110b.
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F71862
ECP Configuration Register A Base + 400h
Bit Name R/W Default Description
7 IRQ_MODE R 0 0: interrupt is ISA pulse.
1: interrupt is ISA level.
Only valid in ECP and ECP_MODE is 111b.
6-4 IMPID R 001 000: the design is 16-bit implementation.
001: the design is 8-bit implementation (default).
010: the design is 32-bit implementation.
011-111: Reserved.
Only valid in ECP and ECP_MODE is 111b.
3 Reserved - - Reserved.
2 BYTETRAN_N R 1 0: when transmitting there is 1 byte waiting in the transceiver that does not
affect the FIFO full condition.
1: when transmitting the state of the full bit includes the byte being transmitted.
Only valid in ECP and ECP_MODE is 111b.
1-0 Reserved R 00 Return 00 when read.
Only valid in ECP and ECP_MODE is 111b.
ECP Configuration Register B Base + 401h
Bit Name R/W Default Description
7 COMP R 0 0: only send uncompressed data.
1: compress data before sending.
Only valid in ECP and ECP_MODE is 111b.
6 Reserved R 1 Reserved. Return 1 when read.
Only valid in ECP and ECP_MODE is 111b.
5-3 ECP_IRQ_CH R 001 000: the interrupt selected with jumper.
001: select IRQ 7 (default).
010: select IRQ 9.
011: select IRQ 10.
100: select IRQ 11.
101: select IRQ 14.
110: select IRQ 15.
111: select IRQ 5.
Only valid in ECP and ECP_MODE is 111b.
2-0 ECP_DMA_CH R 011 Return the DMA channel of ECP parallel port.
Only valid in ECP and ECP_MODE is 111b.
Extended Control Register Base + 402h
Bit Name R/W Default Description
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7-5 ECP_MODE R/W 000 000: SPP Mode.
001: PS/2 Parallel Port Mode.
010: Parallel Port Data FIFO Mode.
011: ECP Parallel Port Mode.
100: EPP Mode.
101: Reserved.
110: Test Mode.
111: Configuration Mode.
Only valid in ECP.
4 ERRINTR_EN R/W 0 0: disable the interrupt generated on the falling edge of ERR#.
1: enable the interrupt generated on the falling edge of ERR#.
3 DAMEN R/W 0 0: disable DMA.
1: enable DMA. DMA starts when SERVICEINTR is 0.
2 SERVICEINTR R/W 1 0: enable the following case of interrupt.
DMAEN = 1: DMA mode.
DMAEN = 0, DIR = 0: set to 1 whenever there are writeIntrThreshold or more
bytes are free in the FIFO.
DMAEN = 0, DIR = 0: set to 1 whenever there are readIntrThreshold or more
bytes are valid to be read in the FIFO.
1 FIFOFULL R 0 0: The FIFO has at least 1 free byte.
1: The FIFO is completely full.
0 FIFOEMPTY R 0 0: The FIFO contains at least 1 byte.
1: The FIFO is completely empty.
F71862
7.5 Keyboard Contoller
The KBC circuit provides the functions included a keyboard and/or a PS/2 mouse, and
can be used with IBM-compatible personal computers or PS/2-based systems. The
controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the
data, and presents the data to the system as a byte of data in its output buffer. The controller
will assert an interrupt to the system when data are placed in its output buffer.
Output Buffer
The output buffer is an 8-bit read-only register at I/O address 60H. The keyboard
controller uses the output buffer to send the scan code received from the keyboard and data
bytes required by commands to the system.
Input Buffer
The input buffer is an 8-bit write-only register at I/O address 60H or 64H. Writing to
address 60H sets a flag to indicate a data write; writing to address 64H sets a flag to
indicate a command write. Data written to I/O address 60H is sent to keyboard through the
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F71862
controller's input buffer only if the input buffer full bit in the status register is “0”.
Status Register
The status register is an 8-bit read-only register at I/O address 64H, that holds
information about the status of the keyboard controller and interface. It may be read at any
time.
BIT BIT FUNCTION DESCRIPTION
0 Output Buffer Full
1 Input Buffer Full
2 System Flag
3 Command/Data 0: Data byte
4 Inhibit Switch 0: Keyboard is inhibited
0: Output buffer empty
1: Output buffer full
0: Input buffer empty
1: Input buffer full
This bit may be set to 0 or 1 by writing to the system flag bit in the
command byte of the keyboard controller (KCCB). It defaults to
0 after a power-on reset.
1: Command byte
1: Keyboard is not inhibited
Commands
5 Mouse Output Buffer 0: Muse output buffer empty
1: Mouse output buffer full
6 General Purpose
Time-out
7 Parity Error 0: Odd parity
COMMAND FUNCTION
20h Read Command Byte
60h Write Command Byte
0: No time-out error
1: Time-out error
1: Even parity (error)
BIT DESCRIPTION
0 Enable Keyboard Interrupt
1 Enable Mouse Interrupt
2 System flag
3 Reserve
4 Disable Keyboard Interface
5 Disable Mouse interface
6 IBM keyboard Translate Mode
7 Reserve
A7h Disable Auxiliary Device Interface
A8h Enable Auxiliary Device Interface
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F71862
A9h Auxiliary Interface Test
8’h00: indicate Auxiliary interface is ok.
8’h01: indicate Auxiliary clock is low.
8’h02: indicate Auxiliary clock is high
8’h03: indicate Auxiliary data is low
8’h04: indicate Auxiliary data is high
AAh Self-test
Returns 055h if self test succeeds
ABh keyboard Interface Test
8’h00: indicate keyboard interface is ok.
8’h01: indicate keyboard clock is low.
8’h02: indicate keyboard clock is high
8’h03: indicate keyboard data is low
8’h04: indicate keyboard data is high
ADh Disable Keyboard Interface
AEh Enable Keyboard Interface
C0h Read Input Port(P1) and send data to the system
C1h Continuously puts the lower four bits of Port1 into STATUS register
C2h Continuously puts the upper four bits of Port1 into STATUS register
D0h Send Port2 value to the system
D1h Only set/reset GateA20 line based on the system data bit 1
D2h Send data back to the system as if it came from Keyboard
D3h Send data back to the system as if it came from Muse
D4h Output next received byte of data from system to Mouse
FEh Pulse only RC(the reset line) low for 6µS if Command byte is even
KBC Command Description
PS2 wakeup function
The KBC supports keyboard and mouse wakeup function, keyboard wakeup
function has 4 kinds of conditions, when key is pressed combinational key (1) CTRL +ESC
(2) CTRL+F1 (3) CTRL+SPACE (4) ANY KEY (5) windows 98 wakeup up key, KBC will
assert PME signal. Mouse wakeup function has 2 kinds of conditions, when mouse (1)
BUTTON CLICK or (2) BUTTON CLICK AND MOVEMENT, KBC will assert PME signal.
Those wakeup conditions are controlled by configuration register.
7.6 Hardware Monitor
For the 8-bit ADC has the 8mv LSB, the maximum input voltage of the analog pin is
2.048V. Therefore the voltage under 2.048V (ex:1.5V) can be directly connected to these
analog inputs. The voltage higher than 2.048V should be reduced by a factor with external
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resistors so as to obtain the input range. Only 3VCC/VSB/VBAT is an exception for it is main
power of the F71862. Therefore 3VCC/VSB/VBAT can directly connect to this chip’s power
pin and need no external resistors. There are two functions in this pin with 3.3V. The first
function is to supply internal analog power of the F71862 and the second function is that
voltage with 3.3V is connected to internal serial resistors to monitor the +3.3V voltage. The
internal serial resistors are two 150K ohm, so that the internal reduced voltage is half of
+3.3V.
follows:
which is within the tolerance. As for application circuit, it can be refer to the figure shown as
follows.
F71862
There are four voltage inputs in the F71862 and the voltage divided formula is shown as
R
2
×=
VVIN
V
+
12
If we choose R1=27K, R2=5.1K, the exact input voltage for V+12v will be 1.907V,
RR
+
21
where V
is the analog input voltage, for example.
+12V
150K
VIN3.3
150K
8-bit ADC
with
8 mV LSB
D+
D-
Voltage Inputs
Typical BJT
Connection
3VCC/VSB
VIN (Lower than 2.048V)
VIN(Higher than 2.048V)
R
2N3906
R
(directly connect to the chip)
(directly connect to the chip)
VIN1(Max2.048V)
R1
R2
VREF
10K, 1%
Typical Thermister
Connection
THM
10K, 25 C
Fig 7-1
The F71862 monitors three remote temperature sensors.These sensors can be measured
from -40°C to 127°C. More detail please refer register description.
Remote-sensor transistor manufacturers
Manufacturer Model Number
Panasonic 2SB0709 2N3906
Philips PMBT3906
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F71862
Monitor Temperature from “thermistor”
The F71862 can connect three thermistor to measure environment temperature or
remote temperature. The specification of thermistor should be considered to (1) β value is
3435K (2) resistor value is 10K ohm at 25°C. In the Figure 7-1, the thermistor is connected
by a serial resistor with 10K ohm, then connected to VREF.
Monitor Temperature from “thermal diode”
Also, if the CPU, GPU or external circuits provide thermal diode for temperature
measurement, the F71862 is capable to these situations. The build-in reference table is for
PNP 2N3906 transistor. In the Figure 7-1, the transistor is directly connected into
temperature pins.
ADC Noise Filtering
The ADC is integrating type with inherently good noise rejection. Micro-power
operation places constraints on high-frequency noise rejection; therefore, careful PCB
board layout and suitable external filtering are required for high-accuracy remote
measurement in electronically noisy environment. High frequency EMI is best filtered at D+
and D- with an external 2200pF capacitor. Too high capacitance may introduce errors due to
the rise time of the switched current source. Nearly all noise sources tested cause the ADC
measurement to be higher than the actual temperature, depending on the frequency and
amplitude.
Over Temperature Signal (OVT#)
OVT# alert for temperature is shown as figure 7-2. When monitored temperature
exceeds the over-temperature threshold value, OVT# will be asserted until the temperature
goes below the hysteresis temperature.
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F71862
To
T
HYST
OVT#
Fig 7-2
Temperature PME#
PME# interrupt for temperature is shown as figure 7-3. Temperature exceeding high
limit or going below hysteresis will cause an interrupt if the previous interrupt has been reset
by writing “1” all the interrupt Status Register.
To
T
HYST
SMI#
(pulse mode)
(level mode
active low)
*Interrupt Reset when Interrupt Status Registers are written 1
*
Fig 7-3
Fan speed count
*
*
*
Inputs are provided by the signals from fans equipped with tachometer outputs. The
level of these signals should be set to TTL level, and maximum input voltage cannot be over
5V. If the input signals from the tachometer outputs are over the 5V, the external trimming
circuit should be added to reduce the voltage to obtain the input specification. The normal
circuit and trimming circuits are shown as follows:
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+12V
R
FAN Out
GND
+12V
Pull-up resister
4.7K Ohms
22K~30K
Fan Input
10K
FANIN 1
F71862
FAN Out
FAN
Connector
+12V
GND
+12V
Pull-up resister < 1K
or totem-pole output
> 1K
3.3V Zener
F71862
Fan Input
FANIN 1
F71862
Fan with Tach Pull-Up to +12V, or Totern-Pole
Output and Register Attenuator
+5V
Pull-up resister
4.7K Ohms
+5V
FAN Out
GND
Fan with Tach Pull-Up to +5V, or Totern-Pole
Output and Register Attenuator
1K~2.7K
Fan Input
10K
Determine the fan counter according to:
Fig 7-4 / 7-5
FANIN1
F71862
Fig 7-6 / 7-7
Count
Fan with Tach Pull-Up to +12V, or
Totem-Pole Putput and Zener Clamp
+5V
Pull-up resister < 1K
or totem-pole output
+5V
FAN Out
GND
FAN
Connector
Fan with Tach Pull-Up to +5V, or
Totem-Pole Putput and Zener Clamp
6
105.1 ×
=
PM
> 1K
3.3V Zener
Fan Input
FANIN1
F71862
In other words, the fan speed counter has been read from register, the fan speed can
be evaluated by the following equation. As for fan, it would be best to use 2 pulses
tachometer output per round.
=
105.1 ×
Count
RPM
6
Fan speed control
The F71862 provides 2 fan speed control methods:
1. DAC FAN CONTROL 2. PWM DUTY CYCLE
DAC Fan Control
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F71862
The range of DC output is 0~3.3V, controlled by 8-bit register. 1 LSB is about 0.013V.
The output DC voltage is amplified by external OP circuit, thus to reach maximum FAN
OPERATION VOLTAGE, 12V. The output voltage will be given as followed:
ValueRegister 8bit Programmed
R
4.7K
R27K
R
10K
FANIN MONITOR
3.3(V) tageOutput_vol ×=
255
And the suggested application circuit for linear fan control would be:
12V
84
PMOS
1
JP1
R10K
DC FAN Control with OP
C
47u
CON3
3
2
1
1N4148
D1
C
0.1u
DC OUTPUT VOLTAGE
3.9K
3
+
2
-
LM358
R
Fig 7-8
PWM duty Fan Control
The duty cycle of PWM can be programmed by a 8-bit register. The default duty cycle
is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be
represented as follows.
(%)Duty_cycle ×=
ValueRegister 8bit Programmed
%100
255
R1
D
NMOS
S
+5V
R2
PNP Transistor
+
C
-
FAN
PWM Clock Input
+12V
R1
R2
D
G
NMOS
S
PNP Transistor
+
C
-
FAN
PWM Clock Input
G
Fig 7-9
Fan speed control mechanism
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F71862
There are some modes to control fan speed and they are 1.Manual mode, 2.Stage
auto mode, 3. Linear auto mode. More detail, please refer the description of registers.
Manual mode
For manual mode, it generally acts as software fan speed control.
Stage auto mode
At this mode, the F71862 provides automatic fan speed control related to temperature
variation of CPU/GPU or the system. The F71862 can provide two temperature boundaries
and three intervals, and each interval has its related fan speed PWM duty. All these values
should be set by BIOS first. Take figure 7-10 as example. When temperature boundaries are
set as 45 and 75°
C and there are three intervals. The related desired fan speed for each
interval are 40%, 80% and 100% (fixed). When the temperature is within 45~75’C, the fan
speed will follow 80% PWM duty and that define in registers. It can be said that the fan will
be turned on with a specific speed set by BIOS and automatically controlled with the
temperature variation. The F71862 will take charge of all the fan speed control and need no
software support.
Temperature
75 Degree C
45 Degree C
Temperature
Fan Speed
PWM Duty
100%
80%
40%
Figure 7-10
Below is a sample for Stage auto mode:
Set temperature as 60°C, 40°C and Duty as 100%, 70%, 50%
60 Degree C
hysteresis 57 Degree C
40 Degree C
Temp.
Fan Speed
a
47
bcd
PWM duty
100%
70%
50%
Nov., 2006
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F71862
a. Once temp. is under 40°C, the lowest fan speed keeps 50% PWM duty
b. Once temp. is over 40°C,60°C, the fan speed will vary from 70% to 100% PWM duty
and increase with temp. level.
c. Once temp. keeps in 55°C, fan speed keeps in 70% PWM duty
d. If set the hysteresis as 3°C (default 4°C), once temp reduces under 57°C, fan speed
reduces to 70% PWM duty and stays there.
Linear auto mode
Otherwise, F71862 supports linear auto mode. Below has a example to describe this
mode. More detail, please refer the register description.
A. Linear auto mode (PWM Duty I)
Set temperature as 70°C, 40°C and Duty as 100%, 70%, 40%
PWM duty
70 Degree C
hysteresis 65 Degree C
40 Degree C
Temp.
Fan Speed
ab c d
100%
70%
40%
a. Once temp. is under 40°C, the lowest fan speed keeps 40% PWM duty
b. Once temp. is over 40°C and under 70°C, the fan speed will vary from 40% to 70%
PWM duty and linearly increase with temp. variation. The temp.-fan speed monitoring
and flash interval is 1sec.
c. Once temp. goes over 70°C, fan speed will directly increase to 100% PWM duty (full
speed)
d. If set the hysteresis as 5°C(default is 4°C), once temp reduces under 65°C (not 70°C),
fan speed reduces from 100% PWM duty and decrease linearly with temp..
FAN_FAULT#
Fan_Fault# will be asserted when the fan speed doesn’t meet the expected fan speed
within a programmable period (default is 11 seconds) or when fan stops with respect to
PWM duty-cycle which should be able to turn on the fan. There are two conditions may
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Page 49
cause the FAN_FAULT# event.
)
(1). When PWM_Duty reaches 0xFF, the fan speed count can’t reach the fan expected
count in time. (Figure 7-11)
Current Fan Count
Expected Fan Count
100%
Duty-cycle
Fan_Fault#
11 sec(default
Fig 7-11
(2). After the period of detecting fan full speed, when PWM_Duty > Min. Duty, and fan
F71862
count still in 0xFFF.
7.7 SPI Interface
Communication between the two devices is handling the serial peripheral interface
(SPI). Every SPI system consist of one master and one or more slaves, where a master
provides the SPI clock and slave receives clock from the master.
This design is only master function, for basic signal, master-out/slave-in (MOSI),
master-in/slave-out (MISO), serial clock (SCK), and 4 slaves select (SS), are needed for
SPI interface. Each of slave select supports from 512kbits to 4096kbits flash is decided by
configuration register. Serial clock (SCK) signal frequency is varied from 24MHz to 187.5
KHz. The serial data (MOSI) for SPI interface translates to depend on SCK rising edge or
falling edge is decided by configuration register.
7.8 ACPI Function
The Advanced Configuration and Power Interface (ACPI) is a system for controlling the
use of power in a computer. It lets computer manufacturer and user to determine the
computer’s power usage dynamically.
There are three ACPI states that are of primary concern to the system designer and they
are designated S0, S3 and S5. S0 is a full-power state; the computer is being actively used in
this state. The other two are called sleep states and reflect different power consumption when
power-down. S3 is a state that the processor is powered down but the last procedural state is
being stored in memory which is still active. S5 is a state that memory is off and the last
procedural state of the processor has been stored to the hard disk. Take S3 and S5 as
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F71862
comparison, since memory is fast, the computer can quickly come back to full-power state, the
disk is slower than the memory and the computer takes longer time to come back to full-power
state. However, since the memory is off, S5 draws the minimal power comparing to S0 and S3.
It is anticipated that only the following state transitions may happen:
S0→S3, S0→S5, S5→S0, S3→S0 and S3→S5.
Among them, S3→S5 is illegal transition and won’t be allowed by state machine. It is
necessary to enter S0 first in order to get to S5 from S3. As for transition S5→S3 will occur only
as an immediate state during state transition from S5→S0. It isn’t allowed in the normal state
transition.
The below diagram described the timing, the always on and always off, keep last state
could be set in control register. In keep last state mode, one register will keep the status of
before power loss. If it is power on before power loss, it will remain power on when power is
resumed, otherwise, if it is power off before power loss, it will remain power off when power is
resumed.
VBAT
VSB
RSMRST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
DEFAULT TIMING
Always off
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VBAT
VSB
RSMRST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
F71862
ALways ON TIMING
PCI Reset and PWROK Signals
The F71862 supports 3 output buffers for 3 reset signals. If the register RSTCON_EN is set
to 1, the pin RSTCON# will infect PCIRST1# ~ PCIRST3# outcome. Then, the result of PCIRST#
outcome will be affected by conditions as below:
PCIRST1# Æ Output buffer of RSTCON# and LRESET#.
PCIRST2# Æ Output buffer of RSTCON# and LRESET#.
PCIRST3# Æ Output buffer of RSTCON# and LRESET#.
+3.3V
ATXPG
RSTCON#
Delay
PWROK
RSTCON#
LRESET#
PCIRST1~3#
So far as the PWROK issue is as the figure above. PWROK is delayed 400ms (default) as
VCC arrives 2.8V, and the delay timing can be programmed by register. (100ms ~ 400ms)
In the figure, the RSTCON# will be implemented by register RSTCON_EN. If RSTCON_EN
be set to 0, the RSTCON# pin will affect PWROK outputs(Default). If RSTCON_EN be set to 1,
the RSTCON# pin will affect PCIRST outputs.
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CPU
NORTH BRIDGE
1 2 1K-8P4R
3 4 1K-8P4R
F71862
VCC3
SOUTH BRIDGE
PCI
PCLK_1,2,3(33MHz)
S3#
PWSOUT#
RSMRST#
PCIR ST1#
IDE
ATA 133
SATA*2
VSB5
12
R90
4.7K
-12V
VCC5
PCIR ST3#
PCIR ST2#
LRESET#
F71862
1 2 4.7K
3 4 4.7K
1 21K
ATX1
11
3V3
12
13
14
15
16
17
18
19
20
3V3
-12V
3V3
GND
GND
PS-ON
5V
GND
GND
GND
5V
GND
GND
-5V
PW-OK
5V
5VSB
5V
12V
ATX CONNECTOR
ATX CONNECTOR
ACPI Reference Circuit
VSB3
1
2
3
4
5
6
7
8
9
10
VCC3
+12V
VSB3
R85
4.7K
VCC3
VCC5
12
12
R88
1 2
33
RSTCON#
VSB5
TC1
22uF
PCIR ST3#
PCIR ST2#
VSB5
12
FRONT PANEL
5
RSTGND
7
RESET
Front Panel
ATXPG_I N
PSON#
R91
4.7K
Tit le
Featur e Int egration Tec hnology Inc.
Size Document Number Rev
Exampl e_ACPI 0.10
A
Date: Sheet
PSW+
PSW-
6
8
-PWR_BTN
1 2
R87
VSB3
12
2 1
77Tuesday , May 16, 2006
R86
4.7K
C47
0.1UF
PWSIN#
of
7.9 AMDSI and Intel PECI Function
The F71862 provides Intel PECI/AMDSI interfaces for new generational CPU temperature
sensing. In AMDSI interface, there are SIC and SID signals for temperature information reading
from AMD CPU. The SIC signal is for clocking use, the other is for data transferring. More detail
please refer register description.
VDDIO
300 300
AMD CPU
SIC
SID
52
SIC
F71862
SID
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F71862
In Intel PECI interface, the F71862 can connect to CPU directly. The F71862 can read the
temperature data from CPU, than the fan control machine of F71862 can implement the Fan to cool
down CPU temperature. The application circuit is as below. More detail please refer the register
description.
Intel
CPU
PECI
avoid pre-BIOS floating
100K
F71862
PECI
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F71862
8. Register Description
The configuration register is used to control the behavior of the corresponding devices. To configure
the register, using the index port to select the index and then writing data port to alter the parameters. The
default index port and data port are 0x4E and 0x4F respectively. Pull down the SOUT1 pin to change the
default value to 0x2E/0x2F. To enable configuration, the entry key 0x87 must be written to the index port.
To disable configuration, write exit key 0xAA to the index port. Following is a example to enable
configuration and disable configuration by using debug.
-o 4e 87
-o 4e 87 ( enable configuration )
-o 4e aa ( disable configuration )
The Following is a register map (total devices) grouped in hexadecimal address order, which shows a
summary of all registers and their default value. Please refer each device chapter if you want more detail
information.
Global Control Registers
Register
0x[HEX]
02 Software Reset Register - - - - - - - 0
07 Logic Device Number Register (LDN) 0 0 0 0 0 0 0 0
20 Chip ID Register 0 0 0 0 0 1 1 0
21 Chip ID Register 0 0 0 0 0 0 0 1
23 Vender ID Register 0 0 0 1 1 0 0 1
24 Vender ID Register 0 0 1 1 0 1 0 0
25 Software Power Down Register - - 0 0 0 0 0 0
26 UART IRQ Sharing Register 0 - - - - - 0 0
27 ROM Address Select Register 0 0/1 1/0 1/0 0/1 0/1 0/1 0
“-“ Reserved or Tri-State
Global Control Registers
Register Name Default Value
MSB LSB
28 Power LED Function Select Register - - - - 0 0 0 0
29 Multi Function Select 1 Register - - - - - 0 0 0
2A Multi Function Select 2 Register 0 0 0 0 0 0 0 0
2B Multi Function Select 3 Register 0 0 0 0 0 0 0 0
2C Multi Function Select 4 Register 0 0 0 0 0 0 0 0
2D Wakeup Control Register 0 - - - 1 0 0 0
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F71862
Device Configuration Registers
FDC Device Configuration Registers (LDN CR00)
Register
0x[HEX]
30 FDC Device Enable Register - - - - - - - 1
60 Base Address High Register 0 0 0 0 0 0 1 1
61 Base Address Low Register 1 1 1 1 0 0 0 0
70 IRQ Channel Select Register - - - - 0 1 1 0
74 DMA Channel Select Register - - - - - 0 1 0
F0 FDD Mode Register - - - - 1 1 1 0
F2 FDD Drive Type Register - - - - - - 1 1
F4 FDD Selection Register - - - 0 0 - 0 0
Register
0x[HEX]
30 UART1 Device Enable Register - - - - - - - 1
Register Name Default Value
UART1 Device Configuration Registers (LDN CR01)
Register Name Default Value
“-“ Reserved or Tri-State
MSB LSB
MSB LSB
60 Base Address High Register 0 0 0 0 0 0 1 1
61 Base Address Low Register 1 1 1 1 1 0 0 0
70 IRQ Channel Select Register - - - - 0 1 0 0
F0 RS485 Enable Register - - - 0 - - - -
UART2 Device Configuration Registers (LDN CR02)
Register
0x[HEX]
30 UART2 Device Enable Register - - - - - - - 1
60 Base Address High Register 0 0 0 0 0 0 1 0
61 Base Address Low Register 1 1 1 1 1 0 0 0
70 IRQ Channel Select Register - - - - 0 0 1 1
F0 RS485 Enable Register - - - 0 0 0 - -
F1 SIR Mode Control Register - - - 0 0 1 0 0
Register
0x[HEX]
30 Parallel Port Device Enable Register - - - - - - - 1
Register Name Default Value
MSB LSB
Parallel Port Device Configuration Registers (LDN CR03)
Register Name Default Value
MSB LSB
60 Base Address High Register 0 0 0 0 0 0 1 1
61 Base Address Low Register 0 1 1 1 1 0 0 0
70 IRQ Channel Select Register - - - - 0 1 1 1
74 DMA Channel Select Register - - - 0 - 0 1 1
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F71862
F0 PRT Mode Select Register 0 1 0 0 0 0 1 0
Hardware Monitor Device Configuration Registers (LDN CR04)
Register
0x[HEX]
30 H/W Monitor Device Enable Register - - - - - - - 1
60 Base Address High Register 0 0 0 0 0 0 1 0
61 Base Address Low Register 1 0 0 1 0 1 0 1
70 IRQ Channel Select Register - - - - 0 0 0 0
Register
0x[HEX]
30 KBC Device Enable Register - - - - - - - 1
60 Base Address High Register 0 0 0 0 0 0 0 0
61 Base Address Low Register 0 1 1 0 0 0 0 0
70 KB IRQ Channel Select Register - - - - 0 0 0 0
72 Mouse IRQ Channel Select Register - - - - 0 0 0 0
Register Name Default Value
MSB LSB
KBC Device Configuration Registers (LDN CR05)
Register Name Default Value
MSB LSB
GPIO Device Configuration Registers (LDN CR06)
Register
0x[HEX]
F0 GPIO Output Enable Register - - - - 0 0 0 0
F1 GPIO Output Data Register - - - - 1 1 1 1
F2 GPIO Pin Status Register - - - - - - - -
F3 GPIO Drive Enable Register 0 0 0 0 0 0 0 0
E0 GPIO1 Output Enable Register 0 0 0 0 0 0 0 0
E1 GPIO1 Output Data Register 1 1 1 1 1 1 1 1
E2 GPIO1 Pin Status Register - - - - - - - -
E3 GPIO1 Drive Enable Register 0 0 0 0 0 0 0 0
D0 GPIO2 Output Enable Register 0 0 0 0 0 0 0 0
D1 GPIO2 Output Data Register 1 1 1 1 1 1 1 1
D2 GPIO2 Pin Status Register - - - - - - - -
D3 GPIO2 Drive Enable Register 0 0 0 0 0 0 0 0
C0 GPIO3 Output Enable Register - - - - 0 0 0 0
C1 GPIO3 Output Data Register - - - - 1 1 1 1
Register Name Default Value
MSB LSB
C2 GPIO3 Pin Status Register - - - - - - - -
C3 GPIO3 Drive Enable Register - - - - 0 0 0 0
B0 GPIO4 Output Enable Register - - 0 0 0 0 0 0
B1 GPIO4 Output Data Register - - 1 1 1 1 1 1
B2 GPIO4 Pin Status Register - - - - - - - -
B3 GPIO4 Drive Enable Register - - 0 0 0 0 0 0
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F71862
VID Device Configuration Registers (LDN CR07)
Register
0x[HEX]
30 VID Device Enable Register - - - - - - - 0
60 Base Address High Register 0 0 0 0 0 0 0 0
61 Base Address Low Register 0 0 0 0 0 0 0 0
Register
0x[HEX]
F0 SPI Control Register 0 0 0 1 0 0 0 0
F1 SPI Timeout Value Register 0 0 0 0 0 1 0 0
F2 SPI Baud Rate Divisor Register - - - - - 0 0 1
F3 SPI Status Register 0 - - - 0 - - -
F4 SPI High Byte Data Register 0 0 0 0 0 0 0 0
F5 SPI Command Data Register 0 0 0 0 0 0 0 0
F6 SPI Chip Select Register - - - - 0 0 0 0
F7 SPI Memory Mapping Register - - - - - - - -
Register Name Default Value
MSB LSB
SPI Device Configuration Registers (LDN CR08)
Register Name Default Value
MSB LSB
F8 SPI Operate Register 0 0 0 0 0 0 0 0
FA SPI Low Byte Data Register 0 0 0 0 0 0 0 0
FB SPI Address High Byte Register 0 0 0 0 0 0 0 0
FC SPI Address Medium Byte Register 0 0 0 0 0 0 0 0
FD SPI Address Low Byte Register 0 0 0 0 0 0 0 0
FE SPI Program Byte Register 0 0 0 0 0 0 0 0
FF SPI Write Data Register 0 0 0 0 0 0 0 0
PME and ACPI Device Configuration Registers (LDN CR0A )
Register
0x[HEX]
30 PME Device Enable Register - - - - - - - 0
F0 PME Event Enable Register - 0 0 0 0 0 0 0
F1 PME Event Status Register - - - - - - - -
F4 ACPI Control Register 0 0 0 0 0 1 1 0
F5 ACPI Control Register 0 0 0 1 1 1 0 0
Register Name Default Value
MSB LSB
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8.1 Global Control Registers
8.1.1 Software Reset Register Index 02h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 SOFT_RST R/W 0 Write 1 to reset the register and device powered by VDD ( VCC ).
8.1.2 Logic Device Number Register (LDN) Index 07h
Bit Name R/W Default Description
7-0 LDN R/W 00h 00h: Select FDC device configuration registers.
01h: Select UART 1 device configuration registers.
02h: Select UART 2 device configuration registers.
03h: Select Parallel Port device configuration registers.
04h: Select Hardware Monitor device configuration registers.
05h: Select KBC device configuration registers.
06h: Select GPIO device configuration registers.
07h: Select VID device configuration registers.
08h: Select SPI device configuration registers.
0ah: Select PME & ACPI device configuration registers.
F71862
8.1.3 Chip ID Register Index 20h
Bit Name R/W Default Description
7-0 CHIP_ID1 R 06h Chip ID 1 of F71862FG.
8.1.4 Chip ID Register Index 21h
Bit Name R/W Default Description
7-0 CHIP_ID2 R 01h Chip ID2 of F71862FG.
8.1.5 Vendor ID Register Index 23h
Bit Name R/W Default Description
7-0 VENDOR_ID1 R 19h Vendor ID 1 of Fintek devices.
8.1.6 Vendor ID Register Index 24h
Bit Name R/W Default Description
7-0 VENDOR_ID2 R 34h Vendor ID 2 of Fintek devices.
8.1.7 Software Power Down Register Index 25h
Bit Name R/W Default Description
7-6 Reserved - - Reserved
5 Reserved R/W 0
Dummy register.
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4 SOFTPD_HM R/W 0
3 SOFTPD_PRT R/W 0
2 SOFTPD_UR2 R/W 0
1 SOFTPD_UR1 R/W 0
0 SOFTPD_FDC R/W 0
8.1.8 UART IRQ Sharing Register Index 26h
Bit Name R/W Default Description
Power down the Hardware Monitor device. This will stop the Hardware Monitor
clock.
Power down the Parallel Port device. This will stop the Parallel Port clock.
Power down the UART 2 device. This will stop the UART 2 clock.
Power down the UART 1 device. This will stop the UART 1 clock.
Power down the FDC device. This will stop the FDC clock.
F71862
7 CLK24M_SEL R/W 0
6-2 Reserved - -
1 IRQ_MODE R/W 0
o IRQ_SHAR R/W 0
8.1.9 ROM Address Select Register Index 27h
Bit Name R/W Default Description
7 ROM_WR_EN R/W 0
6 SPI_EN R/W -
5 SPI_BIOS_EN R/W -
4 PORT_4E_EN R/W -
3 SEG_000E_EN R/W -
2 SEG_FFF8_EN R/W -
0: CLKIN is 48MHz
1: CLKIN is 24MHz
Reserved.
0: PCI IRQ sharing mode (low level).
1: ISA IRQ sharing mode (low pulse).
0: disable IRQ sharing of two UART devices.
1: enable IRQ sharing of two UART devices.
0: disable ROM writing
1: enable ROM writing
0: SPI disable
1: SPI enable
This register is power on trapped by SOUT2/SPI_TRAP. Pull down to enable
SPI.
0: use SPI bridge for BIOS
1: Reserved
This register is power on trapped by DTR2#/FWH_TRAP. Pull down to enable
SPI bridge for BIOS.
0: The configuration register port is 2E/2F.
1: The configuration register port is 4E/4F.
This register is power on trapped by SOUT1/ Config4E_2E. Pull down to select
port 2E/2F.
0: disable address 0x000E0000 – 0x000EFFFF decode
1: enable address 0x000E0000 – 0x000EFFFF decode
This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable.
0: disable address 0xFFF80000 – 0xFFFFFFFF and 0x000F0000 –
0x000FFFFF decode
1: enable address 0xFFF80000 – 0xFFFFFFFF and 0x000F0000 –
0x000FFFFF decode
This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable.
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F71862
1 SEG_FFEF_EN R/W -
0 SEG_FFF0_EN R/W 0
8.1.10 Power LED Function Select Register Index 28h
Bit Name R/W Default Description
0: disable address 0xFFEE – 0xFFEFFFFF decode
1: enable address 0xFFEE0000 – 0xFFEFFFFF decode
This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable.
0: disable address 0xFFF00000 – 0xFFF7FFFF decode
1: enable address 0xFFF00000 – 0xFFF7FFFF decode
7-4 Reserved - -
3 GPIO43_SEL R/W 0
2 GPIO42_SEL R/W 0
1 GPIO41_SEL R/W 0
0 GPIO40_SEL R/W 0
8.1.11 Multi Function Select 1 Register Index 29h (Powered by VSB3V)
Bit Name R/W Default Description
7-3 Reserved R/W 0
2 GPIO02_SEL R/W 0
1 WDT_GP03_EN R/W 0
0 ALERT_GP_EN R/W 0
Reserved.
0: IRRX/GPIO43 functions as IRRX.
1: IRRX/GPIO43 functions as GPIO43.
0: IRTX/GPIO42 functions as IRTX.
1: IRTX/GPIO42 functions as GPIO42.
0: FANCTRL3/GPIO41 functions as FANCTRL3.
1: FANCTRL3/GPIO41 functions as GPIO41.
0: FANIN3/GPIO40 functions as FANIN3.
1: FANIN3/GPIO40 functions as GPIO40.
Reserved
0: SLOTOCC#/GPIO02 will functions as SLOTOCC#.
1: SLOTOCC#/GPIO02 will functions as GPIO02.
0: GPIO03/WDTRST# will function as GPIO03
1: GPIO03/WDTRST# will function as WDTRST#.
0: GPIO15/LED_VSB/ALERT# will function as GPIO15/LED_VSB controlled
by GPIO15_SEL register.
1: GPIO15/LED_VSB/ALERT# will function as ALERT#.
8.1.12 Multi Function Select 2 Register Index 2Ah (Powered by VSB3V)
Bit Name R/W Default Description
7-6 VSBLED_SEL R/W 2’b00
VSBLED function select, powered by VSB.
00: VSBLED always output low.
01: VSBLED tri-state
10: VSBLED output 0.5Hz clock.
11: VSBLED output 1Hz clock.
( clock output is inverse with VDDLED clock output )
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5-4 VDDLED_SEL R/W 2’b00
3 GPIO33_SEL R/W 0
2 GPIO32_SEL R/W 0
1 GPIO31_SEL R/W 0
0 GPIO30_SEL R/W 0
8.1.13 Multi Function Select 3 Register Index 2Bh (Powered by VSB3V)
Bit Name R/W Default Description
VDDLED function select, powered by VDD.
00: VDDLED always output low.
01: VDDLED tri-state
10: VDDLED output 0.5Hz clock.
11: VDDLED output 1Hz clock.
( clock output is inverse with VSBLED clock output )
0: RSMRST#/GPIO33 functions as RSMRST#.
1: RSMRST#/GPIO33 functions as GPIO33.
0: PWROK/GPIO32 functions as PWROK.
1: PWROK/GPIO32 functions as GPIO32.
0: PS_ON#/GPIO31 functions as PS_ON#.
1: PS_ON#/GPIO31 functions as GPIO31.
0: S3#/GPIO30 functions as S3#.
1: S3#/GPIO30 functions as GPIO30.
F71862
7 Reserved R/W 0
6 GPIO16_SEL R/W 0
5 GPIO15_SEL R/W 0
4 GPIO14_SEL R/W 0
3 GPIO13_SEL R/W 0
2 GPIO12_SEL R/W 0
1-0 Reserved R/W 0
8.1.14 Multi Function Select 4 Register Index 2Ch (Powered by VSB3V)
Bit Name R/W Default Description
Dummy register.
0: GPIO16/LED_VCC functions as GPIO16.
1: GPIO16/LED_VCC functions as LED_VCC.
When register ALERT_GP_EN is 0, the register functions as:
0: GPIO15/LED_VSB/ALERT# functions as GPIO15.
1: GPIO15/LED_VSB/ALERT# functions as LED_VSB.
0: GPIO14/FWH_DIS/WDTRST# functions as GPIO14 when SPI is disabled.
1: GPIO14/FWH_DIS/WDTRST# functions as WDTRST# when SPI is
disabled.
0: GPIO13/SPI_MOSI/BEEP functions as GPIO13 when SPI is disabled.
1: GPIO13/SPI_MOSI/BEEP functions as BEEP when SPI is disabled.
0: GPIO12/SPI_MISO/FANCTRL1_1 functions as GPIO12 when SPI is
disabled.
1: GPIO12/SPI_NISO/FANCTRL1_1 functions as FANCTRL1_1 when SPI is
disabled.
Reserved
7 GPIO27_SEL R/W 0
6 GPIO26_SEL R/W 0
5 GPIO25_SEL R/W 0
0: PWSOUT#/GPIO27 functions as PWSOUT#.
1: PWSOUT#/GPIO27 functions as GPIO27.
0: PWSIN#/GPIO26 functions as PWSIN#.
1: PWSIN#/GPIO26 functions as GPIO26.
0: PME#/GPIO25 functions as PME#.
1: PME#/GPIO25 functions as GPIO25.
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4 GPIO24_SEL R/W 0
3 GPIO23_SEL R/W 0
2 GPIO22_SEL R/W 0
1 GPIO21_SEL R/W 0
0 GPIO20_SEL R/W 0
8.1.15 Wakeup Control Register Index 2Dh (Powered by VBAT)
Bit Name R/W Default Description
0: ATXPG_IN/GPIO24 functions as ATXPG_IN.
1: ATXPG_IN/GPIO24 functions as GPIO24.
0: RSTCON#/GPIO23 functions as RSTCON#.
1: RSTCON#/GPIO23 functions as GPIO23.
0: PCIRST3#/GPIO22 functions as PCIRST3#.
1: PCIRST3#/GPIO22 functions as GPIO22.
0: PCIRST2#/GPIO21 functions as PCIRST2#.
1: PCIRST2#/GPIO21 functions as GPIO21.
0: PCIRST1#/GPIO20 functions as PCIRST1#.
1: PCIRST1#/GPIO20 functions as GPIO20.
F71862
7 SPI_CS1_EN R/W 0
6-4 Reserved R/W 0
3 WAKEUP_EN R/W 1
2-1 KEY_SEL R/W 00
0 MO_SEL R/W 0
This register decides the architecture of SPI when used as primary BIOS.
1: use two 4Mbits. (FWH_DIS will multi-functions as SPI_CS1#)
0: use one 8Mbits. (Divided into two 4Mbits. Originally use the higher part. If
the higher part is booting fail, the memory address will be auto mapped to
lower part.)
Dummy register.
0: disable keyboard/mouse wake up.
1: enable keyboard/mouse wake up.
This registers select the keyboard wake up key.
When KEY_SEL_ADD is low, the register indicates
00: Wake up key is Ctrl + Esc.
01: Wake up key is Ctrl + F1.
10: Wake up key is Ctrl + Space.
11: Wake up key is any key.
Otherwise, wake up key is win98 wakeup key.
This register selects the mouse wake up key.
0: Wake up by click.
1: Wake up by click and movement.
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8.2 FDC Registers (CR00)
8.2.1 FDC Co nfiguration Registers
FDC Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 FDC_EN R/W 1 0: disable FDC.
1: enable FDC.
Base Address High Register Index 60h
Bit Name R/W Default Description
7-0 BASE_ADDR_HI R/W 03h The MSB of FDC base address.
Base Address Low Register Index 61h
Bit Name R/W Default Description
7-0 BASE_ADDR_LO R/W F0h The LSB of FDC base address.
IRQ Channel Select Register Index 70h
Bit Name R/W Default Description
F71862
7-4 Reserved - - Reserved.
3-0 SELFDCIRQ R/W 06h Select the IRQ channel for FDC.
DMA Channel Select Register Index 74h
Bit Name R/W Default Description
7-3 Reserved - - Reserved.
2-0 SELFDCDMA R/W 010 Select the DMA channel for FDC.
FDD Mode Register Index F0h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3-2 IF_MODE R/W 11 00: Model 30 mode.
01: PS/2 mode.
10: Reserved.
11: AT mode (default).
1 FDMAMODE R/W 1 0: enable burst mode.
1: non-busrt mode (default).
0 EN3MODE R/W 0 0: normal floppy mode (default).
1: enhanced 3-mode FDD.
FDD Drive Type Register Index F2h
Bit Name R/W Default Description
7-2 Reserved - - Reserved.
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F71862
1-0 FDD_TYPE R/W 11 FDD drive type.
FDD Selection Register Index F4h
Bit Name R/W Default Description
7-5 Reserved - - Reserved.
4-3 FDD_DRT R/W 00 Data rate table select, refer to table A.
00: select regular drives and 2.88 format.
01: 3-mode drive.
10: 2 mega tape.
11: reserved.
2 Reserved - - Reserved.
1-0 FDD_DT R/W 00 Drive type select, refer to table B.
TABLE A
Data Rate Table Select Data Rate Selected Data Rate DENSEL
FDD_DRT[1] FDD_DRT[0] DATARATE1 DATARATE0 MFM FM
0 0 500K 250K 1
0 1 300K 150K 0
0 0
1 0 250K 125K 0
0 1
1 0
TABLE B
Drive Type
FDD_DT1 FDD_DT0
0 DENSEL 4/2/1 MB 3.5”
0
0 1 DATARATE1
1 0 DENSEL#
1 1 DATARATE0
1 1 1Meg --- 1
0 0 500K 250K 1
0 1 500K 250K 0
1 0 250K 125K 0
1 1 1Meg --- 1
0 0 500K 250K 1
0 1 2Meg --- 0
1 0 250K 125K 0
1 1 1Meg --- 1
DRVDEN0 Remark
2/1 MB 5.25”
1/1.6/1 MB 3.5” (3-Mode )
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8.3 UART1 Registers (CR01)
8.3.1 UART 1 Configuration Registers
UART 1 Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 UR1_EN R/W 1 0: disable UART 1.
1: enable UART 1.
Base Address High Register Index 60h
Bit Name R/W Default Description
7-0 BASE_ADDR_HI R/W 03h The MSB of UART 1 base address.
Base Address Low Register Index 61h
Bit Name R/W Default Description
7-0 BASE_ADDR_LO R/W F8h The LSB of UART 1 base address.
IRQ Channel Select Register Index 70h
Bit Name R/W Default Description
F71862
7-4 Reserved - - Reserved.
3-0 SELUR1IRQ R/W 4h Select the IRQ channel for UART 1.
RS485 Enable Register Index F0h
Bit Name R/W Default Description
7-5 Reserved - - Reserved.
4 RS485_EN R/W 0 0: RS232 driver.
3-0 Reserved - - Reserved.
1: RS485 driver. Auto drive RTS# low when transmitting data.
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8.4 UART 2 Registers (CR02)
8.4.1 UART 2 Configuration Registers
UART 2 Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 UR2_EN R/W 1 0: disable UART 2.
1: enable UART 2.
Base Address High Register Index 60h
Bit Name R/W Default Description
7-0 BASE_ADDR_HI R/W 02h The MSB of UART 2 base address.
Base Address Low Register Index 61h
Bit Name R/W Default Description
7-0 BASE_ADDR_LO R/W F8h The LSB of UART 2 base address.
IRQ Channel Select Register Index 70h
Bit Name R/W Default Description
F71862
7-4 Reserved - - Reserved.
3-0 SELUR2IRQ R/W 3h Select the IRQ channel for UART 2.
RS485 Enable Register Index F0h
Bit Name R/W Default Description
7-5 Reserved - - Reserved.
4 RS485_EN R/W 0 0: RS232 driver.
1: RS485 driver. Auto drive RTS# low when transmitting data.
3 RXW4C_IR R/W 0 0: No reception delay when SIR is changed form TX to RX.
1: Reception delays 4 characters time when SIR is changed form TX to RX.
2 TXW4C_IR R/W 0 0: No transmission delay when SIR is changed form RX to TX.
1: Transmission delays 4 characters time when SIR is changed form RX to TX.
1-0 Reserved - - Reserved.
SIR Mode Control Register Index F1h
Bit Name R/W Default Description
7 Reserved - - Reserved.
6 Reserved - - Reserved.
5 Reserved - - Reserved.
4-3 IRMODE R/W 00 00: disable IR function.
01: disable IR function.
10: IrDA function, active pulse is 1.6uS.
11: IrDA function, active pulse is 3/16 bit time.
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F71862
2 HDUPLX R/W 1 0: SIR is in full duplex mode for loopbak test. TXW4C_IR and RXW4C_IR are
of no use.
1: SIR is in half duplex mode.
1 TXINV_IR R/W 0 0: IRTX is in normal condition.
1: inverse the IRTX.
0 RXINV_IR R/W 0 0: IRRX is in normal condition.
1: inverse the IRRX.
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8.5 Parallel Port Registers (CR03)
8.5.1 Parallel Port Configuration Registers
Parallel Port Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 PRT_EN R/W 1 0: disable Parallel Port.
1: enable Parallel Port.
Base Address High Register Index 60h
Bit Name R/W Default Description
7-0 BASE_ADDR_HI R/W 03h The MSB of Parallel Port base address.
Base Address Low Register Index 61h
Bit Name R/W Default Description
7-0 BASE_ADDR_LO R/W 78h The LSB of Parallel Port base address.
IRQ Channel Select Register Index 70h
Bit Name R/W Default Description
F71862
7-5 Reserved - - Reserved.
3-0 SELPRTIRQ R/W 7h Select the IRQ channel for Parallel Port.
DMA Channel Select Register Index 74h
Bit Name R/W Default Description
7-5 Reserved - - Reserved.
4 ECP_DMA_MODE R/W 0 0: non-burst mode DMA.
1: enable burst mode DMA.
3 Reserved - - Reserved.
2-0 SELPRTDMA R/W 011 Select the DMA channel for Parallel Port.
PRT Mode Select Register Index F0h
Bit Name R/W Default Description
7 SPP_IRQ_MODE R/W 0 Interrupt mode in non-ECP mode.
0: Level mode.
1: Pulse mode.
6-3 ECP_FIFO_THR R/W 1000 ECP FIFO threshold.
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F71862
2-0 PRT_MODE R/W 010 000: Standard and Bi-direction (SPP) mode.
001: EPP 1.9 and SPP mode.
010: ECP mode (default).
011: ECP and EPP 1.9 mode.
100: Printer mode.
101: EPP 1.7 and SPP mode.
110: Reserved.
111: ECP and EPP1.7 mode.
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8.6 Hardware Monitor Registers (CR04)
8.6.1 Hardware Monitor Configuration Registers
Hardware Monitor Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 HM_EN R/W 1 0: disable Hardware Monitor.
1: enable Hardware Monitor.
Base Address High Register Index 60h
Bit Name R/W Default Description
7-0 BASE_ADDR_HI R/W 02h The MSB of Hardware Monitor base address.
Base Address Low Register Index 61h
Bit Name R/W Default Description
7-0 BASE_ADDR_LO R/W 95h The LSB of Hardware Monitor base address.
IRQ Channel Select Register Index 70h
Bit Name R/W Default Description
F71862
7-4 Reserved - - Reserved.
3-0 SELHMIRQ R/W 0000 Select the IRQ channel for Hardware Monitor.
8.6.2 Device Registers
Before the device registers, the following is a register map order which shows a summary of all registers.
Please refer each one register if you want more detail information.
Register CR01 ~ CR03 Æ Configuration Registers
Register CR10 ~ CR4F Æ Vo ltage Setting Register
Register CR60 ~ CR8E Æ Temperature Setting Register
Register CR90 ~ CRDF Æ Fan Control Setting Register
ÆFan1 Detail Setting CRA0 ~ CRAF
ÆFan2 Detail Setting CRB0 ~ CRBF
ÆFan3 Detail Setting CRC0 ~ CRCF
8.6.2.1 Configuration Register Index 01h
Bit Name R/W Default Description
7-3 Reserved 0h 0
2 POWER_DOWN R/W 0
1 FAN_START R/W
0 V_T_START R/W
Reserved
Hardware monitor function power down.
Set one to enable startup of fan monitoring operations; a zero puts the part
1
in standby mode.
Set one to enable startup of temperature and voltage monitoring
1
operations; a zero puts the part in standby mode.
8.6.2.2 Configuration Register Index 02h
Bit Name R/W Default Description
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F71862
7 Reserved R/W 0
6 CASE_BEEP_EN R/W
5-4 OVT_MODE R/W
3 Reserved R/W 0
2 CASE_SMI_EN R / W
1-0 ALERT_MODE R/W
8.6.2.3 Configuration Register Index 03h
Bit Name R/W Default Description
7-1 Reserved R/W 0
0 CASE_STS R/W 0 Case open event status, write 1 to clear if case open event cleared.
Dummy register.
0: Disable case open event output via BEEP.
0
1: Enable case open event output via BEEP.
00: The OVT# will be low active level mode.
0
01: The OVT# will be high active level mode.
10: The OVT# will indicate by 1Hz LED function.
11: The OVT# will indicate by (400/800HZ) BEEP output.
Dummy register.
0: Disable case open event output via PME.
0
1: Enable case open event output via PME.
00: The ALERT# will be low active level mode.
0
01: The ALERT# will be high active level mode.
10: The ALERT# will indicate by 1Hz LED function.
11: The ALERT# will indicate by (400/800HZ) BEEP output.
Return 0 when read.
8.6.2.4 Configuration Register Index 0Ah
Bit Name R/W Default Description
7-6 Reserved - 00
5 T1_IIR_EN R/W
4 Reserved R/W 0
3-2 VTT_SEL R/W
1-0 MEAS_TYPE R/W
8.6.2.5 Configuration Register Index 0Bh (MEAS_TYPE == 2’b01)
Bit Name R/W Default Description
7-4 CPU_SEL R/W
3-1 Reserved - 0
0 DOMAIN1_EN R/W
Reserved.
Set 1 to enable IIR for AMDSI/PECI reading.
0
The reading will be more stable.
Reserved.
PECI (Vtt) voltage select.
0
00: Vtt is 1.23V
01: Vtt is 1.13V
10: Vtt is 1.00V
11: Vtt is 1.00V
CPU Temperature Measurement method.
00
00: with external diode.
01: with PECI interface.
10: with AMDSI interface.
11: reserved.
Select the Intel CPU socket number.
0
0000: no CPU presented. PECI host will use Ping() command to find CPU
address.
0001: CPU is in socket 0, i.e. PECI address is 0x30.
0010: CPU is in socket 0, i.e. PECI address is 0x31.
0100: CPU is in socket 0, i.e. PECI address is 0x32.
1000: CPU is in socket 0, i.e. PECI address is 0x33.
Otherwise are reserved.
Reserved.
If the CPU selected is dual core. Set this register 1 to read the temperature
0
of domain1.
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F71862
8.6.2.6 Configuration Register Index 0Bh (MEAS_TYPE ==2’b10)
Bit Name R/W Default Description
7-0 AMDSI_VER R - Return the AMDSI version.
8.6.2.7 Configuration Register Index 0Ch (MEAS_TYPE == 2’b01)
Bit Name R/W Default Description
8’h55
7-0 TCC_TEMP R/W
8.6.2.8 Configuration Register Index 0Ch (MEAS_TYPE ==2’b10)
Bit Name R/W Default Description
7-0 NODE_ID R - Return the AMDSI node id.
8.6.2.9 Configuration Register Index 0Dh
Bit Name R/W Default Description
7-0 Reserved - - Reserved.
TCC Activation Temperature.
The absolute value of CPU temperature is calculated by the equation:
CPU_TEMP = TCC_TEMP + PECI Reading.
The range of this register is 0 ~ 255.
8.6.2.10 Configuration Regi ster Index 0Eh
Bit Name R/W Default Description
7-4 Reserved R/W 0 Reserved.
3 PECI_SCALE_ADD R / W
2- 0 PECI_SCALE R / W
8.6.2.11 Configuration Regi ster Index 0Fh
Bit Name R/W Default Description
7-0 Reserved. - - Reserved
V oltage Setting
This register is used to indicate how to calculate the PECI reading with
0
PECI_SCALE register.
0: The real value is the reading adds the value calculated by
PECI_SCALE.
1: The real value is the reading adds the value calculated by
PECI_SCALE.
This register is used to control the PECI reading slope. See also
0
PECI_SCALE_ADD register.
000: The real value is the PECI reading.
001: The real value is (1 ± 1/2) PECI reading.
010: The real value is (1 ± 1/4) PECI reading.
011: The real value is (1 ± 1/8) PECI reading.
100: The real value is (1 ± 1/16) PECI reading.
101: The real value is (1 ± 1/32) PECI reading.
110: The real value is (1 ± 1/64) PECI reading.
111: The real value is (1 ± 1/128) PECI reading.
8.6.2.12 Voltage1 Voltage reading and limit Index 20h- 4Fh
Address Attribute
Default
Value
Description
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20h RO -- VCC3V reading. The unit of reading is 8mV.
21h RO -- V1 (Vcore) reading. The unit of reading is 8mV.
22h RO -- V2 reading. The unit of reading is 8mV.
23h RO -- V3 reading. The unit of reading is 8mV.
24h RO -- V4 reading. The unit of reading is 8mV.
25h RO -- V5 reading. The unit of reading is 8mV.
26h RO -- V6 reading. The unit of reading is 8mV.
27h RO -- VSB3V reading. The unit of reading is 8mV.
28h RO -- VBAT reading. The unit of reading is 8mV.
29~2Fh RO FF Reserved
30~4Fh RO FF Reserved
Temperature Setting
8.6.2.13 Temperature PME# Enable Register Index 60h
Bit Name R/W Default Description
EN_ T3_OVT_PME
7
6 EN_ T2_ OVT_PME
EN_ T1_ OVT_PME
5
Reserved R/W 0 Reserved
4
EN_ T3_EXC_PME
3
2 EN_ T2_EXC_PME
EN_ T1_EXC_PME
1
Reserved R/W 0 Reserved
0
R/W
R/W
R/W
R/W
R/W
R/W
F71862
If set this bit to 1, PME# signal will be issued when TEMP3 exceeds OVT
0
limit setting.
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds OVT
0
setting.
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds OVT
0
setting.
If set this bit to 1, PME# signal will be issued when TEMP3 exceeds high
0
limit setting.
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds high
0
limit setting.
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds high
0
limit setting.
8.6.2.14 Temperature Interrupt Status Register Index 61h
Bit Name R/W Default Description
A one indicates TEMP3 temperature sensor has exceeded OVT limit or
0
7 T3_OVT_STS R/W
6 T2_OVT _STS R/W
5 T1_OVT _STS R/W
4 Reserved R/W 0
3 T3_EXC _STS R/W
2 T2_EXC _STS R/W
1 T1_EXC _STS R/W
below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be
ignored.
A one indicates TEMP2 temperature sensor has exceeded OVT limit or
0
below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be
ignored.
A one indicates TEMP1 temperature sensor has exceeded OVT limit or
0
below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be
ignored.
Reserved
A one indicates TEMP3 temperature sensor has exceeded high limit or
0
below the “high limit –hysteresis”. Write 1 to clear this bit, write 0 will be
ignored.
A one indicates TEMP2 temperature sensor has exceeded high limit or
0
below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 will
be ignored.
A one indicates TEMP1 temperature sensor has exceeded high limit or
0
below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 will
be ignored.
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F71862
0 Reserved R/W 0
8.6.2.15 Temperature Real Time Status Register Index 62h
Bit Name R/W Default Description
7 T3_OVT R/W
6 T2_OVT R/W
5 T1_OVT R/W
4 Reserved R/W 0
3 T3_EXC R/W
2 T2_EXC R/W
1 T1_EXC R/W
0 Reserved R/W 0
8.6.2.16 Temperature BEEP Enable Register Index 63h
Bit Name R/W Default Description
EN_ T3_OVT_BEEP
7
6 EN_ T2_ OVT_BEEP
EN_ T1_ OVT_BEEP
5
Reserved R/W 0 Reserved
4
EN_ T3_EXC_BEEP
3
2 EN_ T2_EXC_BEEP
EN_ T1_EXC_BEEP
1
Reserved R/W 0 Reserved
0
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Set when the TEMP3 exceeds the OVT limit. Clear when the TEMP3 is
0
below the “OVT limit –hysteresis” temperature.
Set when the TEMP2 exceeds the OVT limit. Clear when the TEMP2 is
0
below the “OVT limit –hysteresis” temperature.
Set when the TEMP1 exceeds the OVT limit. Clear when the TEMP1 is
0
below the “OVT limit –hysteresis” temperature.
Reserved
Set when the TEMP3 exceeds the high limit. Clear when the TEMP3 is
0
below the “high limit –hysteresis” temperature.
Set when the TEMP2 exceeds the high limit. Clear when the TEMP2 is
0
below the “high limit –hysteresis” temperature.
Set when the TEMP1 exceeds the high limit. Clear when the TEMP1 is
0
below the “high limit –hysteresis” temperature.
Reserved
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds OVT
0
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds OVT
0
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds OVT
0
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds high
0
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds high
0
limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds high
0
limit setting.
8.6.2.17 OVT Output Enable Register 1 In dex 66h
Bit Name R/W Default Description
Enable temperature 3 alert event (asserted when temperature over high
7 EN_T3_ALERT R
6 EN_T2_ALERT R
5 EN_T1_ALERT R
4 Reserved R 0
3 EN_T3_OVT R/W 0
2 EN_T2_OVT R/W 0
1 EN_T1_OVT R/W 1
0 Reserved R 0h
0
limit)
Enable temperature 2 alert event (asserted when temperature over high
0
limit)
Enable temperature 1 alert event (asserted when temperature over high
0
limit)
Reserved for temp4
Enable over temperature (OVT) mechanism of temperature3.
Enable over temperature (OVT) mechanism of temperature2.
Enable over temperature (OVT) mechanism of temperature1.
Reserved.
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8.6.2.18 Temperature Sensor Type Register Index 6Bh
Bit Name R/W Default Description
7-4 Reserved RO 0
3 T3_MODE R/W
2 T2_MODE R/W
1 T1_MODE R/W
0 Reserved R 0h
8.6.2.19 TEMP1 Limit Hystersis Select Register -- Index 6Ch
Bit Name R/W Default Description
7-4 TEMP1_HYS R/W
3-0 Reserved R 0h
8.6.2.20 TEMP2 and TEMP3 Limit Hystersis Select Register -- Index 6Dh
Bit Name R/W Default Description
7-4 TEMP3_HYS R/W
3-0 TEMP2_HYS R/W
--
0: TEMP3 is connected to a thermistor
1
1: TEMP3 is connected to a BJT.(default)
0: TEMP2 is connected to a thermistor.
1
1: TEMP2 is connected to a BJT. (default)
0: TEMP1 is connected to a thermistor
1
1: TEMP1 is connected to a BJT.(default)
--
Limit hysteresis. (0~15 degree C)
4h
Temperature and below the ( boundary – hysteresis ).
--
Limit hysteresis. (0~15 degree C)
2h
Temperature and below the ( boundary – hysteresis ).
Limit hysteresis. (0~15 degree C)
4h
Temperature and below the ( boundary – hysteresis ).
F71862
8.6.2.21 DIODE OPEN Status Register -- Index 6Fh
Bit Name R/W Default Description
7-4 Reserved RO 0h
3 T3_DIODE_OPEN RO 0h External diode 3 is open
2 T2_DIODE_OPEN RO 0h External diode 2 is open
1 T1_DIODE_OPEN RO 0h This register indicates the abnormality of temperature 1 measurement.
0 Reserved R 0h
Temperature Index 70h- 8Fh
Address Attribute
70h Reserved FFh Reserved
71h Reserved FFh Reserved
72h RO --
73h RO -- Reserved
74h RO --
75h RO -- Reserved
Default
Value
Reserved
When AMDSI interface is enabled, it indicates the error of not receiving
ACK bit when read TCON command is asserted.
When PECI interface is enabled, it indicates a error code is received from
PECI slave.
When external diode is used, it indicates the BJT is open or short.
--
Description
Temperature 1 reading. The unit of reading is 1
register.
Temperature 2 reading. The unit of reading is 1
register.
º
C.At the moment of reading this
º
C.At the moment of reading this
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76h RO --
77-7Bh RO -- Reserved
7C-7Fh RO FFh Reserved
80h Reserved FFh Reserved
81h Reserved FFh Reserved
82h R/W 64h Temperature sensor 1 OVT limit. The unit is 1ºC.
83h R/W 55h Temperature sensor 1 high limit. The unit is 1ºC.
84h R/W 64h Temperature sensor 2 OVT limit. The unit is 1ºC.
85h R/W 55h Temperature sensor 2 high limit. The unit is 1ºC.
86h R/W 55h Temperature sensor 3 OVT limit. The unit is 1ºC.
87h R/W 46h Temperature sensor 3 high limit. The unit is 1ºC.
88-8Bh RO -- Reserved
8C~8Dh RO FFH Reserved
8.6.2.22 Temperature Filter Select Register -- Index 8Eh
Bit Name R/W Default Description
7-6 IIR-QUEUR3 R/W 0h
5-4 IIR-QUEUR2 R/W 0h
3-2 IIR-QUEUR1 R/W 0h
0 Reserved R 0h
Fan Control Setting
Temperature 3 reading. The unit of reading is 1
register.
The queue time for second filter to quickly update values.
00: disable.
01: 16 times.
10: 32 times. (default)
11: 48 times.
The queue time for second filter to quickly update values.
00: disable.
01: 16 times.
10: 32 times. (default)
11: 48 times.
The queue time for second filter to quickly update values.
00: disable.
01: 16 times.
10: 32 times. (default)
11: 48 times.
--
º
C.At the moment of reading this
F71862
8.6.2.23 FAN PME# Enable Register Index 90h
Bit Name R/W Default Description
7-3 Reserved RO 0h
EN_FAN3_PME R/W
2
1 EN_FAN2_PME R/W
EN_FAN1_PME R/W
0
8.6.2.24 FAN Interrupt Status Register Index 91h
Bit Name R/W Default Description
7-3 Reserved RO 0
Reserved
A one enables the corresponding interrupt status bit for PME# interrupt..
0h
Set this bit 1 to enable PME# function for Fan3.
A one enables the corresponding interrupt status bit for PME# interrupt.
0h
Set this bit 1 to enable PME# function for Fan2.
A one enables the corresponding interrupt status bit for PME# interrupt.
0h
Set this bit 1 to enable PME# function for Fan1.
Reserved
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F71862
2 FAN3_STS R/W --
1 FAN2_STS R/W --
0 FAN1_STS R/W --
8.6.2.25 FAN Real Time Status Register Index 92h
Bit Name R/W Default Description
7-3 Reserved -- 0 Reserved
2 FAN3_EXC RO --
1 FAN2_EXC RO --
0 FAN1_EXC RO --
8.6.2.26 FAN BEEP# Enable Register Index 93h
Bit Name R/W Default Description
7 FULL_WITH_T3_EN R/W 0
6 FULL_WITH_T2_EN R/W 0
5 FULL_WITH_T1_EN R/W 0
4 Reserved R/W 0
3 Reserved R 0
EN_FAN3_ BEEP R/W
2
1 EN_FAN2_ BEEP R/W 0
EN_FAN1_ BEEP R/W
0
This bit is set when the fan3 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
This bit is set when the fan2 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
This bit is set when the fan1 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
This bit set to high mean that fan3 count can’t meet expect count over than
SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
This bit set to high mean that fan2 count can’t meet expect count over than
SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
This bit set to high mean that fan1 count can’t meet expect count over than
SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
Set one will enable FAN to force full speed when T3 over high limit.
Set one will enable FAN to force full speed when T2 over high limit.
Set one will enable FAN to force full speed when T1 over high limit.
Reserved for local temperature.
Reserved.
A one enables the corresponding interrupt status bit for BEEP.
0
A one enables the corresponding interrupt status bit for BEEP.
A one enables the corresponding interrupt status bit for BEEP.
0
8.6.2.27 Fan Type Select Register -- Index 94h
Bit Name R/W Default Description
7-6 Reserved R 0
5-4 FAN3_TYPE R/W 2’b 0S
3-2 FAN2_TYPE R/W 2’b 0S
1-0 FAN1_TYPE R/W 2’b 0S
S: Register default values are decided by trapping.
Reserved.
00: Output PWM mode (pushpull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
terminal .
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
00: Output PWM mode (pushpull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
terminal .
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
00: Output PWM mode (push pull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
terminal .
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
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8.6.2.28 Fan mode Select Register -- Index 96h
Bit Name R/W Default Description
7-6 Reserved R 0
5-4 FAN3_MODE R/W 1h
3-2 FAN2_MODE R/W 1h
1-0 FAN1_MODE R/W 1h
Reserved.
00: Reserved
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle (voltage) that define in 0xB6-0xBE.
10: Reserved
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage(linear fan type) to 0xC3, and F71883FG will output this
value duty or voltage to control fan speed.
00: Reserved.
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle (voltage) that define in 0xB6-0xBE.
10: Reserved.
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage (linear fan type) to 0xB3, and F71883FG will output this
value duty or voltage to control fan speed.
00: Reserved.
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle that define in 0xA6-0xAE.
10: Reserved.
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage(linear fan type) to 0xA3, and F71883FG will output this
value duty or voltage to control fan speed.
F71862
8.6.2.29 Auto Fan1 and Fan2 Boundary Hystersis Select Register -- Index 98h
Bit Name R/W Default Description
0000: Boundary hysteresis. (0~15 degree C)
4h
7-4 FAN2_HYS R/W
3-0 FAN1_HYS R/W
8.6.2.30 Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 99h
Bit Name R/W Default Description
7-4 Reserved R 0
3-0 FAN3_HYS R/W
8.6.2.31 Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 9Bh
Bit Name R/W Default Description
7-6 Reserved R 0
5-4 FAN3_RATE_SEL R/W
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
0000: Boundary hysteresis. (0~15 degree C)
4h
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
Reserved.
0000: Boundary hysteresis. (0~15 degree C)
2h
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
Reserved.
Fan3 duty update rate:
1h
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
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F71862
Fan2 duty update rate:
1h
00: 2Hz
3-2 FAN2_RATE_SEL R/W
1-0 FAN1_RATE_SEL R/W
8.6.2.32 FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE Index 9Ch
Bit Name R/W Default Description
7-4
FAN2_STOP_DUTY
3-0
FAN1_STOP_DUTY
R/W
R/W
01: 5Hz (default)
10: 10Hz
11: 20Hz
Fan1 duty update rate:
1h
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
When fan start, the FAN_CTRL2 will increase duty-cycle from 0 to this
5h
(value x 8) directly. And if fan speed is down, the FAN_CTRL 2 will
decrease duty-cycle to 0 when the PWM duty cycle is less than this (value
x 4).
When fan start, the FAN_CTRL 1 will increase duty-cycle from 0 to this
5h
(value x 8 directly. And if fan speed is down, the FAN_CTRL 1 will
decrease duty-cycle to 0 when the PWM duty cycle is less than this (value
x 4).
8.6.2.33 FAN3 START UP DUTY-CYCLE/VOLTAGE Index 9Dh
Bit Name R/W Default Description
7-4 Reserved R 0
3-0
FAN3_STOP_DUTY
8.6.2.34 Fan Fault Time Register -- Index 9Fh
Bit Name R/W Default Description
7-5
4
3-0 Reserved R 0
Fan1 Index A0h- AFh
Address Attribute
Reserved
FULL_DUTY_SEL
R/W
-- --
R/W
Default
Value
Reserved.
When fan start, the FAN_CTRL 3 will increase duty-cycle from 0 to this
5h
(value x 8 directly. And if fan speed is down, the FAN_CTRL 3 will
decrease duty-cycle to 0 when the PWM duty cycle is less than this (value
x 4).
Reservd
0: the full duty is 100%.
-1: the full duty is 60% (default).
This register is power on trap by DTR1#.
Reserved.
Description
FAN1 count reading (MSB). At the moment of reading this register, the LSB will
A0h RO 8’h0f
A1h RO 8’hff FAN1 count reading (LSB).
A2h - - Reserved
A3h R/W 8’h01 The Value programming in this byte is duty value. In auto fan mode(CR96
be latched. This will prevent from data updating when reading. To read the fan
count correctly, read MSB first and followed read the LSB.
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F71862
bit5Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Æ 100%
FAN1 full speed count reading (MSB). At the moment of reading this register, the
A4h R/W 8’h03
A5h R/W 8’hff FAN1 full speed count reading (LSB).
8.6.2.35 VT1 BOUNDARY 1 TEMPERATURE – Index A6h
Bit Name R/W Default Description
7 Reserved RO 0
6-0 BOUND1TMP1 R/W
8.6.2.36 VT1 BOUNDARY 2 TEMPERAT URE – Index A9
Bit Name R/W Default Description
7 Reserved RO 0
6-0 BOUND4TMP1 R/W
LSB will be latched. This will prevent from data updating when reading. To read the
fan count correctly, read MSB first and followed read the LSB.
Return 0 when read.
st
The 1
3Ch
(60oC)
1Eh
(30oC)
BOUNDARY temperature for VT1 in temperature mode.
When VT1 temperature is exceed this boundary, FAN1 expect value will
load full speed duty 8’hFF.
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
value will load from segment 1 register (index ABh).
Return 0 when read.
st
The 2
BOUNDARY temperature for VT1 in temperature mode.
When VT1 temperature is exceed this boundary, FAN1 expect value will
load from segment 1 register (index ABh).
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
value will load from segment 2 register (index AEh).
8.6.2.37 FAN1 SEGMENT 1 SPEED COUNT – Index ABh
Bit Name R/W Default Description
The value that set in this byte is mean the expect PWM duty-cycle in this
7- 0 SEC1SPEED1 R/ W
8.6.2.38 FAN1 SEGMENT 2 SPEED COUNT – Index AEh
Bit Name R/W Default Description
7- 0 SEC2SPEED1 R / W
8.6.2.39 FAN1 Temper ature Mapping Select – Index AFh
Bit Name R/W Default Description
7-6 Reserved -- 0
5 FAN1_UP_T_EN R / W 0
FAN1_INTERPOLATION_
4
3 FAN1_JUMP_HIGH_EN R /W
EN
R/W
D9h
(85%)
80h
(50%)
1
1
temperature section.
The value that set in this byte is mean the expect PWM duty-cycle in this
temperature section.
Reserved
Set 1 to force FAN1 to full speed if any temperature over its high limit.
Set 1 will enable the interpolation of the fan expect table.
This register controls the FAN1 duty movement when temperature over
highest boundary.
0: The FAN1 duty will increases with the slope selected by
FAN1_RATE_SEL register (Index 9Bh).
1: The FAN1 duty will directly jumps to full speed.
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2 FAN1_JUMP_LOW_EN R / W
1-0 Fan1_temp_sel R/W 1
Fan2 Index B0h- BFh
Address Attribute
B0h RO 8’h0f
B1h RO 8’hff FAN1 count reading (LSB).
B2h R/W 8’h00 Reserved
B3h R/W 8’h01
B4h R/W 8’h03
B5h R/W 8’hff FAN1 full speed count reading (LSB).
Default
Value
F71862
This register controls the FAN1 duty movement when temperature under
1
(highest boundary – hysteresis).
0: The FAN1 duty will decreases with the slope selected by
FAN1_RATE_SEL register (Index 9Bh).
1: The FAN1 duty will directly jumps to the value of SEC1SPEED1
register.
0: reserved.
1: fan1 follow temperature 1.
2: fan1 follow temperature 2.
3: fan1 follow temperature 3.
Description
FAN1 count reading (MSB). At the moment of reading this register, the LSB will
be latched. This will prevent from data updating when reading. To read the fan
count correctly, read MSB first and followed read the LSB.
The Value programming in this byte is duty value. In auto fan mode(CR96
bit5Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Î 100%
FAN1 full speed count reading (MSB). At the moment of reading this register,
the LSB will be latched. This will prevent from data updating when reading. To
read the fan count correctly, read MSB first and followed read the LSB.
8.6.2.40 VT2 BOUNDARY 1 TEMPERATURE – Index B6h
Bit Name R/W Default Description
7 Reserved RO 0
(60oC)
6-0 BOUND1TMP2 R/W
8.6.2.41 VT2 BOUNDARY 2 TEMPERATURE – Index B9
Bit Name R/W Default Description
7 Reserved RO 0
(30oC)
6-0 BOUND2TMP1 R/W
8.6.2.42 FAN2 SEGMENT 1 SPEED COUNT – Index BBh
Bit Name R/W Default Description
Return 0 when read.
st
The 1
3Ch
1Eh
BOUNDARY temperature for VT2 in temperature mode.
When VT2 temperature is exceed this boundary, FAN2 expect value will
load full speed duty 8’hFF.
When VT2 temperature is below this boundary – hysteresis, FAN2 expect
value will load from segment 1 register (index BBh).
Return 0 when read.
st
The 2
BOUNDARY temperature for VT1 in temperature mode.
When VT1 temperature is exceed this boundary, FAN1 expect value will
load from segment 1 register (index BBh).
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
value will load from segment 2 register (index BEh).
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7- 0 SEC1SPEED2 R/ W
8.6.2.43 FAN2 SEGMENT 2 SPEED COUNT – Index BEh
Bit Name R/W Default Description
7- 0 SEC2SPEED2 R / W
8.6.2.44 FAN2 Temper ature Mapping Select – Index BFh
Bit Name R/W Default Description
7-6 Reserved -- 0
5 FAN2_UP_T_EN R / W 0
FAN2_INTERPOLATION_
4
3 FAN2_JUMP_HIGH_EN R /W
2 FAN2_JUMP_LOW_EN R / W
1-0 Fan2_temp_sel R/W 2
Fan3 Index C0h- CFh
Address Attribute
EN
R/W
Default
Value
The value that set in this byte is mean the expect PWM duty-cycle in this
D9h
(85%)
(50%)
temperature section.
The value that set in this byte is mean the expect PWM duty-cycle in this
80h
temperature section.
Reserved
Set 1 to force FAN2 to full speed if any temperature over its high limit.
Set 1 will enable the interpolation of the fan expect table.
1
This register controls the FAN2 duty movement when temperature over
1
highest boundary.
0: The FAN2 duty will increases with the slope selected by
1: The FAN2 duty will directly jumps to full speed.
This register controls the FAN2 duty movement when temperature under
1
(highest boundary – hysteresis).
0: The FAN2 duty will decreases with the slope selected by
1: The FAN2 duty will directly jumps to the value of SEC1SPEED2
0: reserved.
1: fan2 follow temperature 1.
2: fan2 follow temperature 2.
3: fan2 follow temperature 3.
Description
F71862
FAN2_RATE_SEL register (Index 9Bh).
FAN2_RATE_SEL register (Index 9Bh).
register.
FAN3 count reading (MSB). At the moment of reading this register, the LSB will
C0h RO 8’h0F
C1h RO 8’hff FAN3 count reading (LSB).
C2h - - Reserved.
C3h R/W 8’h01
C4h R/W 8’h03
C5h R/W 8’hff FAN3 full speed count reading (LSB).
be latched. This will prevent from data updating when reading. To read the fan
count correctly, read MSB first and followed read the LSB.
The Value programming in this byte is duty value. In auto fan mode(CR96
bit5Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Î 100%
FAN3 full speed count reading (MSB). At the moment of reading this register,
the LSB will be latched. This will prevent from data updating when reading. To
read the fan count correctly, read MSB first and followed read the LSB.
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F71862
8.6.2.45 VT3 BOUNDARY 1 TEMPERATURE – Index C6h
Bit Name R/W Default Description
7 Reserved RO 0
6-0 BOUND1TMP3 R/W
8.6.2.46 VT3 BOUNDARY 2 TEMPERATURE – Index C9
Bit Name R/W Default Description
7 Reserved RO 0
6-0 BOUND2TMP3 R/W
8.6.2.47 FAN3 SEGMENT 1 SPEED COUNT – Index CBh
Bit Name R/W Default Description
7- 0 SEC1SPEED3 R/ W
(60oC)
(30oC)
(85%)
Return 0 when read.
st
The 1
3Ch
1Eh
D9h
BOUNDARY temperature for VT3 in temperature mode.
When VT3 temperature is exceed this boundary, FAN3 expect value will
load the full speed duty 8’hFF.
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
value will load from segment 1 register (index CBh).
Return 0 when read.
st
The 2
BOUNDARY temperature for VT3 in temperature mode.
When VT3 temperature is exceed this boundary, FAN3 expect value will
load from segment 1 register (index CBh).
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
value will load from segment 2 register (index CEh).
The value that set in this byte is mean the expect PWM duty-cycle in this
temperature section.
8.6.2.48 FAN3 SEGMENT 2 SPEED COUNT – Index CEh
Bit Name R/W Default Description
The value that set in this byte is mean the expect PWM duty-cycle in this
7- 0 SEC2SPEED3 R / W
8.6.2.49 FAN3 Temper ature Mapping Select – Index CFh
Bit Name R/W Default Description
7-6 Reserved -- 0
5 FAN3_UP_T_EN R / W 0
FAN3_INTERPOLATION_
4
3 FAN3_JUMP_HIGH_EN R /W
2 FAN3_JUMP_LOW_EN R / W
1-0 Fan3_temp_sel R/W 3
EN
R/W
80h
(50%)
1
1
1
temperature section.
Reserved
Set 1 to force FAN3 to full speed if any temperature over its high limit.
Set 1 will enable the interpolation of the fan expect table.
This register controls the FAN3 duty movement when temperature over
highest boundary.
0: The FAN3 duty will increases with the slope selected by
FAN3_RATE_SEL register (Index 9Bh).
1: The FAN3 duty will directly jumps to full speed.
This register controls the FAN3 duty movement when temperature under
(highest boundary – hysteresis).
0: The FAN3 duty will decreases with the slope selected by
FAN3_RATE_SEL register (Index 9Bh).
1: The FAN3 duty will directly jumps to the value of SEC1SPEED3
register.
0: reserved.
1: fan3 follow temperature 1.
2: fan3 follow temperature 2.
3: fan3 follow temperature 3.
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8.7 KBC Registers (CR05)
8.7.1 KBC Configuration Registers
KBC Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 KBC_EN R/W 1 0: disable KBC.
Base Address High Register Index 60h
Bit Name R/W Default Description
7-0 BASE_ADDR_HI R/W 00h The MSB of KBC command port address. The address of data port is
Base Address Low Register Index 61h
Bit Name R/W Default Description
F71862
1: enable KBC.
command port address + 4;
7-0 BASE_ADDR_LO R/W 60h The LSB of KBC command port address. The address of data port is command
KB IRQ Channel Select Register Index 70h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3-0 SELKIRQ R/W 0h Select the IRQ channel for keyboard interrupt.
Mouse IRQ Channel Select Register Index 72h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3-0 SELMIRQ R/W 0h Select the IRQ channel for PS/2 mouse interrupt.
port address + 4.
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8.8 GPIO Registers (CR06)
8.8.1 GPIO0 Registers
GPIO0 Output Enable Register Index F0h
Bit Name R/W Default Description
7-4 Reserved - 0 Reserved
3 GPIO03_OE R/W 0 0: GPIO03 is in input mode.
1: GPIO03 is in output mode.
2 GPIO02_OE R/W 0 0: GPIO02 is in input mode.
1: GPIO02 is in output mode.
1 GPIO01_OE R/W 0 0: GPIO01 is in input mode.
1: GPIO01 is in output mode.
0 GPIO00_OE R/W 0 0: GPIO00 is in input mode.
1: GPIO00 is in output mode.
GPIO0 Output Data Register Index F1h
Bit Name R/W Default Description
7-4 Reserved - 0 Reserved
3 GPIO03_VAL R/W 1 0: GPIO03 outputs 0 when in output mode.
1: GPIO03 outputs 1 when in output mode.
2 GPIO02_VAL R/W 1 0: GPIO02 outputs 0 when in output mode.
1: GPIO02 outputs 1 when in output mode.
1 GPIO01_VAL R/W 1 0: GPIO01 outputs 0 when in output mode.
1: GPIO01 outputs 1 when in output mode.
0 GPIO00_VAL R/W 1 0: GPIO00 outputs 0 when in output mode.
1: GPIO00 outputs 1 when in output mode.
F71862
GPIO0 Pin Status Register Index F2h
Bit Name R/W Default Description
7-4 Reserved - 0 Reserved
3 GPIO03_IN R - The pin status of GPIO03/WDTRST#.
2 GPIO02_IN R - The pin status of SLOTOCC#/GPIO02.
1 GPIO01_IN R - The pin status of GPIO01.
0 GPIO00_IN R - The pin status of GPIO00.
GPIO0 Drive Enable Register Index F3h
Bit Name R/W Default Description
7-4 Reserved - 0 Reserved
3 GPIO03_DRV_EN R/W 0 0: GPIO03 is open drain in output mode.
1: GPIO03 is push pull in output mode.
2 GPIO02_DRV_EN R/W 0 0: GPIO02 is open drain in output mode.
1: GPIO02 is push pull in output mode.
1 GPIO01_DRV_EN R/W 0 0: GPIO01 is open drain in output mode.
1: GPIO01 is push pull in output mode.
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0 GPIO00_DRV_EN R/W 0 0: GPIO00 is open drain in output mode.
1: GPIO00 is push pull in output mode.
8.8.2 GPIO1 Registers
GPIO1 Output Enable Register Index E0h
Bit Name R/W Default Description
7 GPIO17_OE R/W 0 0: GPIO16 is in input mode.
1: GPIO16 is in output mode.
6 GPIO16_OE R/W 0 0: GPIO16 is in input mode.
1: GPIO16 is in output mode.
5 GPIO15_OE R/W 0 0: GPIO15 is in input mode.
1: GPIO15 is in output mode.
4 GPIO14_OE R/W 0 0: GPIO14 is in input mode.
1: GPIO14 is in output mode.
3 GPIO13_OE R/W 0 0: GPIO13 is in input mode.
1: GPIO13 is in output mode.
2 GPIO12_OE R/W 0 0: GPIO12 is in input mode.
1: GPIO12 is in output mode.
1 GPIO11_OE R/W 0 0: GPIO11 is in input mode.
1: GPIO11 is in output mode.
0 GPIO10_OE R/W 0 0: GPIO10 is in input mode.
1: GPIO10 is in output mode.
F71862
GPIO1 Output Data Register Index E1h
Bit Name R/W Default Description
7 GPIO17_VAL R/W 1 0: GPIO16 outputs 0 when in output mode.
1: GPIO16 outputs1 when in output mode.
6 GPIO16_VAL R/W 1 0: GPIO16 outputs 0 when in output mode.
1: GPIO16 outputs1 when in output mode.
5 GPIO15_VAL R/W 1 0: GPIO15 outputs 0 when in output mode.
1: GPIO15 outputs 1 when in output mode.
4 GPIO14_VAL R/W 1 0: GPIO14 outputs 0 when in output mode.
1: GPIO14 outputs 1 when in output mode.
3 GPIO13_VAL R/W 1 0: GPIO13 outputs 0 when in output mode.
1: GPIO13 outputs 1 when in output mode.
2 GPIO12_VAL R/W 1 0: GPIO12 outputs 0 when in output mode.
1: GPIO12 outputs 1 when in output mode.
1 GPIO11_VAL R/W 1 0: GPIO11 outputs 0 when in output mode.
1: GPIO11 outputs 1 when in output mode.
0 GPIO10_VAL R/W 1 0: GPIO10 outputs 0 when in output mode.
1: GPIO10 outputs 1 when in output mode.
GPIO1 Pin Status Register Index E2h
Bit Name R/W Default Description
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7 GPIO17_IN R - The pin status of GPIO17.
6 GPIO16_IN R - The pin status of GPIO16/LED_VCC
5 GPIO15_IN R - The pin status of GPIO15/LED_VSB/ALERT#.
4 GPIO14_IN R - The pin status of GPIO14/FWH_DIS/WDTRST#/SPI_CS1#.
3 GPIO13_IN R - The pin status of GPIO13/SPI_MOSI/BEEP.
2 GPIO12_IN R - The pin status of GPIO12/SPI_MISO/FANCTRL1_1.
1 GPIO11_IN R - The pin status of GPIO11/SPI_CS.
0 GPIO10_IN R - The pin status of GPIO10/SPI_CLK.
GPIO1 Drive Enable Register Index E3h
Bit Name R/W Default Description
7 GPIO17_DRV_EN R/W 0 0: GPIO17 is open drain in output mode.
1: GPIO17 is push pull in output mode.
6 GPIO16_DRV_EN R/W 0 0: GPIO16 is open drain in output mode.
1: GPIO16 is push pull in output mode.
5 GPIO15_DRV_EN R/W 0 0: GPIO15 is open drain in output mode.
1: GPIO15 is push pull in output mode.
4 GPIO14_DRV_EN R/W 0 0: GPIO14 is open drain in output mode.
1: GPIO14 is push pull in output mode.
3 GPIO13_DRV_EN R/W 0 0: GPIO13 is open drain in output mode.
1: GPIO13 is push pull in output mode.
2 GPIO12_DRV_EN R/W 0 0: GPIO12 is open drain in output mode.
1: GPIO12 is push pull in output mode.
1 GPIO11_DRV_EN R/W 0 0: GPIO11 is open drain in output mode.
1: GPIO11 is push pull in output mode.
0 GPIO10_DRV_EN R/W 0 0: GPIO10 is open drain in output mode.
1: GPIO10 is push pull in output mode.
F71862
8.8.3 GPIO2 Registers
GPIO2 Output Enable Register Index D0h
Bit Name R/W Default Description
7 GPIO27_OE R/W 0 0: GPIO27 is in input mode.
1: GPIO27 is in output mode.
6 GPIO26_OE R/W 0 0: GPIO26 is in input mode.
1: GPIO26 is in output mode.
5 GPIO25_OE R/W 0 0: GPIO25 is in input mode.
1: GPIO25 is in output mode.
4 GPIO24_OE R/W 0 0: GPIO24 is in input mode.
1: GPIO24 is in output mode.
3 GPIO23_OE R/W 0 0: GPIO23 is in input mode.
1: GPIO23 is in output mode.
2 GPIO22_OE R/W 0 0: GPIO22 is in input mode.
1: GPIO22 is in output mode.
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1 GPIO21_OE R/W 0 0: GPIO21 is in input mode.
1: GPIO21 is in output mode.
0 GPIO20_OE R/W 0 0: GPIO20 is in input mode.
1: GPIO20 is in output mode.
GPIO2 Output Data Register Index D1h
Bit Name R/W Default Description
7 GPIO27_VAL R/W 1 0: GPIO27 outputs 0 when in output mode.
1: GPIO27 outputs1 when in output mode.
6 GPIO26_VAL R/W 1 0: GPIO26 outputs 0 when in output mode.
1: GPIO26 outputs1 when in output mode.
5 GPIO25_VAL R/W 1 0: GPIO25 outputs 0 when in output mode.
1: GPIO25 outputs 1 when in output mode.
4 GPIO24_VAL R/W 1 0: GPIO24 outputs 0 when in output mode.
1: GPIO24 outputs 1 when in output mode.
3 GPIO23_VAL R/W 1 0: GPIO23 outputs 0 when in output mode.
1: GPIO23 outputs 1 when in output mode.
2 GPIO22_VAL R/W 1 0: GPIO22 outputs 0 when in output mode.
1: GPIO22 outputs 1 when in output mode.
1 GPIO21_VAL R/W 1 0: GPIO21 outputs 0 when in output mode.
1: GPIO21 outputs 1 when in output mode.
0 GPIO20_VAL R/W 1 0: GPIO20 outputs 0 when in output mode.
1: GPIO20 outputs 1 when in output mode.
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GPIO2 Pin Status Register Index D2h
Bit Name R/W Default Description
7 GPIO27_IN R - The pin status of PWSOUT#/GPIO27.
6 GPIO26_IN R - The pin status of PWSIN#/GPIO26.
5 GPIO25_IN R - The pin status of PME#/GPIO25.
4 GPIO24_IN R - The pin status of ATXPG_IN/GPIO24.
3 GPIO23_IN R - The pin status of GPIO23/RSTCON#.
2 GPIO22_IN R - The pin status of PCIRST3#/GPIO22.
1 GPIO21_IN R - The pin status of PCIRST2#/GPIO21.
0 GPIO20_IN R - The pin status of PCIRST1#/GPIO20.
GPIO2 Drive Enable Register Index D3h
Bit Name R/W Default Description
7 GPIO27_DRV_EN R/W 0 0: GPIO27 is open drain in output mode.
1: GPIO27 is push pull in output mode.
6 GPIO26_DRV_EN R/W 0 0: GPIO26 is open drain in output mode.
1: GPIO26 is push pull in output mode.
5 GPIO25_DRV_EN R/W 0 0: GPIO25 is open drain in output mode.
1: GPIO25 is push pull in output mode.
4 GPIO24_DRV_EN R/W 0 0: GPIO24 is open drain in output mode.
1: GPIO24 is push pull in output mode.
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3 GPIO23_DRV_EN R/W 0 0: GPIO23 is open drain in output mode.
1: GPIO23 is push pull in output mode.
2 GPIO22_DRV_EN R/W 0 0: GPIO22 is open drain in output mode.
1: GPIO22 is push pull in output mode.
1 GPIO21_DRV_EN R/W 0 0: GPIO21 is open drain in output mode.
1: GPIO21 is push pull in output mode.
0 GPIO20_DRV_EN R/W 0 0: GPIO20 is open drain in output mode.
1: GPIO20 is push pull in output mode.
8.8.4 GPIO3 Registers
GPIO3 Output Enable Register Index C0h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3 GPIO33_OE R/W 0 0: GPIO33 is in input mode.
1: GPIO33 is in output mode.
2 GPIO32_OE R/W 0 0: GPIO32 is in input mode.
1: GPIO32 is in output mode.
1 GPIO31_OE R/W 0 0: GPIO31 is in input mode.
1: GPIO31 is in output mode.
0 GPIO30_OE R/W 0 0: GPIO30 is in input mode.
1: GPIO30 is in output mode.
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GPIO3 Output Data Register Index C1h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3 GPIO33_VAL R/W 1 0: GPIO33 outputs 0 when in output mode.
1: GPIO33 outputs 1 when in output mode.
2 GPIO32_VAL R/W 1 0: GPIO32 outputs 0 when in output mode.
1: GPIO32 outputs 1 when in output mode.
1 GPIO31_VAL R/W 1 0: GPIO31 outputs 0 when in output mode.
1: GPIO31 outputs 1 when in output mode.
0 GPIO30_VAL R/W 1 0: GPIO30 outputs 0 when in output mode.
1: GPIO30 outputs 1 when in output mode.
GPIO3 Pin Status Register Index C2h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3 GPIO33_IN R - The pin status of RSMRST#/GPIO33.
2 GPIO32_IN R - The pin status of PWROK/GPIO32.
1 GPIO31_IN R - The pin status of PS_ON#/GPIO31.
0 GPIO30_IN R - The pin status of S3#/GPIO30.
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GPIO3 Drive Enable Register Index C3h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3 GPIO33_DRV_EN R/W 0 0: GPIO33 is open drain in output mode.
1: GPIO33 is push pull in output mode.
2 GPIO32_DRV_EN R/W 0 0: GPIO32 is open drain in output mode.
1: GPIO32 is push pull in output mode.
1 GPIO31_DRV_EN R/W 0 0: GPIO31 is open drain in output mode.
1: GPIO31 is push pull in output mode.
0 GPIO30_DRV_EN R/W 0 0: GPIO30 is open drain in output mode.
1: GPIO30 is push pull in output mode.
8.8.5 GPIO4 Registers
GPIO4 Output Enable Register Index B0h
Bit Name R/W Default Description
7-6 Reserved - - Reserved.
5 GPIO45_OE R/W 0 0: GPIO45 is in input mode.
1: GPIO45 is in output mode.
4 GPIO44_OE R/W 0 0: GPIO44 is in input mode.
1: GPIO44 is in output mode.
3 GPIO43_OE R/W 0 0: GPIO43 is in input mode.
1: GPIO43 is in output mode.
2 GPIO42_OE R/W 0 0: GPIO42 is in input mode.
1: GPIO42 is in output mode.
1 GPIO41_OE R/W 0 0: GPIO41 is in input mode.
1: GPIO41 is in output mode.
0 GPIO40_OE R/W 0 0: GPIO40 is in input mode.
1: GPIO40 is in output mode.
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GPIO4 Output Data Register Index B1h
Bit Name R/W Default Description
7-6 Reserved - - Reserved.
5 GPIO45_VAL R/W 1 0: GPIO45 outputs 0 when in output mode.
1: GPIO45 outputs 1 when in output mode.
4 GPIO44_VAL R/W 1 0: GPIO44 outputs 0 when in output mode.
1: GPIO44 outputs 1 when in output mode.
3 GPIO43_VAL R/W 1 0: GPIO43 outputs 0 when in output mode.
1: GPIO43 outputs 1 when in output mode.
2 GPIO42_VAL R/W 1 0: GPIO42 outputs 0 when in output mode.
1: GPIO42 outputs 1 when in output mode.
1 GPIO41_VAL R/W 1 0: GPIO41 outputs 0 when in output mode.
1: GPIO41 outputs 1 when in output mode.
0 GPIO40_VAL R/W 1 0: GPIO40 outputs 0 when in output mode.
1: GPIO40 outputs 1 when in output mode.
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GPIO4 Pin Status Register Index B2h
Bit Name R/W Default Description
7-6 Reserved - - Reserved.
5 GPIO45_IN R - The pin status of GPIO45
4 GPIO44_IN R - The pin status of GPIO44.
3 GPIO43_IN R - The pin status of IRRX/GPIO43
2 GPIO42_IN R - The pin status of IRTX/GPIO42.
1 GPIO41_IN R - The pin status of FANCTRL3/GPIO41.
0 GPIO40_IN R - The pin status of FANIN3/GPIO40.
GPIO4 Drive Enable Register Index B3h
Bit Name R/W Default Description
7-6 Reserved - - Reserved.
5 GPIO45_DRV_EN R/W 0 0: GPIO45 is open drain in output mode.
1: GPIO45 is push-pull in output mode.
4 GPIO44_DRV_EN R/W 0 0: GPIO44 is open drain in output mode.
1: GPIO44 is push-pull in output mode.
3 GPIO43_DRV_EN R/W 0 0: GPIO43 is open drain in output mode.
1: GPIO43 is push-pull in output mode.
2 GPIO42_DRV_EN R/W 0 0: GPIO42 is open drain in output mode.
1: GPIO42 is push-pull in output mode.
1 GPIO41_DRV_EN R/W 0 0: GPIO41 is open drain in output mode.
1: GPIO41 is push-pull in output mode.
0 GPIO40_DRV_EN R/W 0 0: GPIO40 is open drain in output mode.
1: GPIO40 is push-pull in output mode.
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8.9 VID Registers (CR07)
8.9.1 VID Con figuration Registers
VID Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - 0 Reserved
0 VID_EN R/W 0 0: disable VID.
Base Address High Register Index 60h
Bit Name R/W Default Description
7-0 BASE_ADDR_HI R/W 00h The MSB of VID base address.
Base Address Low Register Index 61h
Bit Name R/W Default Description
7-0 BASE_ADDR_LO R/W 00h The LSB of VID base address.
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1: enable VID.
8.9.2 Device Registers
8.9.2.1 Configuration Register Index 00h ( * cleared by slotocc_n and watch dog timeout)
Bit Name R/W Default Description
7 WDOUT_EN R/W 0
6-3 Reserved - 0
2* OTF_EN R/W 0
1:0 Dummy Reg R/W 0
8.9.2.2 VID Offset Register 0 Index 01h
Bit Name R/W Default Description
7:4 Reserved R -
3-0 VID_OFFSET R/W 0 VID offset. VID_OFFSET[3] is sign bit.
8.9.2.3 VID Manual Register Index 02h
Bit Name R/W Default Description
7* MANUAL_MODE R/W 0
6 KEY_OK R -
5-4 Reserved R -
3-0 VID_MANUAL R/W 0 Manually assigned VIDOUT value
If this bit is set to 1 and watchdog timeout event occurs, WDTRST# output
is enabled.
Return 0 when read.
This bit is used to enable vid on-the-fly function.
Dummy register.
Reserved
If this bit is set to 1 and OTF_EN is 0, VIDOUT will be VID_MANUAL
This bit is 1 represents that the serial key is entered correctly.
Return 0 when read.
8.9.2.4 Serial Key Data Register Index 03h
Bit Name R/W Default Description
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Write serial data to this register correctly, the KEY_OK bit will be set to 1.
0
7-0 KEY_DATA R/W
8.9.2.5 VIDIN Register Index 04h ( * cleared by slotocc_n and watch dog timeout)
Bit Name R/W Default Description
7-4
3-0
8.9.2.6 Watchdog Timer Configuration Register 1 Index 05h
Bit Name R/W Default Description
7 Reserved R 0
6 WDTMOUT_STS R/W 0
5 WD_EN R/W 0
4 WD_PULSE R/W 0
3 WD_UNIT R/W 0
2 WD_HACTIVE R/W 0
1:0 WD_PSWIDTH R/W 0
Reserved
VID_IN R - Return the VID_IN status.
R 0
Hence, users are able to write key protected registers. The sequence to
enable KEY_OK is 0x32, 0x5D, 0x42, 0xAC. When KEY_OK is set, write
this register 0x35 will clear KEY_OK.
Reserved
Reserved
If watchdog timeout event occurs, this bit will be set to 1. Write a 1 to this
bit will clear it to 0.
If this bit is set to 1, the counting of watchdog time is enabled.
Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit.
Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit.
Select output polarity of RSTOUT# (1: high active, 0: low active) by setting
this bit.
Select output pulse width of RSTOUT#
0: 1 ms 1: 25 ms
2: 125 ms 3: 5 sec
8.9.2.7 Watchdog Timer Configuration Register 2 Index 06h
Bit Name R/W Default Description
7:0 WD_TIME R/W 0
8.9.2.8 Output Voltage Control Register 1 Index 07h ( * cleared by slotocc_n and watch dog timeout)
Bit Name R/W Default Description
7-6 Dummy Reg R/W 0
5 REG_RST_SEL R/W
4 Reserved R/W 0
3-0 Dummy Reg R/W 0
Time of watchdog timer
Dummy register.
0: The VID registers is reseted when VDD power lose and watch dog
0
timeout.
1: The VID registers is reseted by slotcc_n and watch dog timeout.
Reserved
Dummy registers.
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8.10 SPI Registers (CR08)
8.10.1 Configuration Register
SPI Control Register Index F0h
Bit Name R/W Default Description
7-6 Reserved - - Reserved.
5 SPTIE R/W 0 SPI interrupt enable. Set to 1, SPIE interrupt enabled, set to 0 spie interrupt
disabled.
4 MSTR R/W 1 Master mode select. Set to 1, SPI function is master mode; set to 0 is disable
SPI function
3 CPOL R/W 0 Clock polarity this bit selects inverted or non-inverted SPI clock. Set to 1, active
low clock selected; SCK idles high. Set to 0, active high clock selected; SCK
idles low.
2 CPHA R/W 0 Clock phase. This bit is used to shift the SCK serial clock. Set to 1, the first
SCK edge is issued at the beginning of the transfer operation. Set to 0, the first
SCK edge is issued one-half cycle into the transfer operation.
1 Reserved - 0 Reserved
0 LSBFE R/W 0 This bit control data shift from lsb or msb. Set to 1, data is transferred from lsb
to msb. Set to 0, data is transferred from msb to lsb.
SPI Timeout Register Index F1h
Bit Name R/W Default Description
7-0 TIMER_VAL R/W 8’h04 The time in second to assert FWH_DIS signal when SPI in used as backup
BIOS.
SPI Baud Rate Divisor Register Index F2h
Bit Name R/W Default Description
7-3 Reserved - 0 Reserved
2-0 BAUD_VAL R/W 1 This register decides to SCK frequency. Baud rate divisor equation is
33MHz/2*(BAUD_VAL).
00: 33MHz.
01: 16.7MHz.
SPI Status Register Index F3h
Bit Name R/W Default Description
7 SPIE R/W 0 SPI interrupt status. When SPI is transferred or received data from device
finish, this bit will be set. Write 1 to clear this bit.
6 FWH_DIS R/W - When SPI is used as backup BIOS, this bit will set when time in second
reaches the value programmed in TIMER_VAL (CRF1). Write one to clear this
register.
When SPI is used as primary BIOS, this register will always be 1.
5 SPE R - This bit reflects the SPI_EN register. (which will be 1 when SPI is enabled.)
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4 SPI0_TIMER_DIS R/W - When SPI is used as primary BIOS, it will also have backup function as used in
backup BIOS. The bit will set to 1 when the time in second reaches the value
programmed in TIMER_VAL (CRF1). That is the first SPI could not function
well. Then a reset signal will asserted and reboot the system with the second
SPI. (I could be another SPI with chip-selected by FWH_DIS or another 4Mbits
of an 8Mbits SPI. The SPI_CS1_EN (CR2D[4]) determines the method). Write
one to clear this bit.
3 SPTEF R 0 SPI operation status. When SPI is transferred or received data from device,
this bit will be set 1, Clear by SPI operation finish.
2-0 Reserved - - Reserved
SPI High Byte Data Register Index F4h
Bit Name R/W Default Description
7-0 H_DATA R 0 When SPI is received 16 bits data from device. This register saves high byte
data.
SPI command data Register Index F5h
Bit Name R/W Default Description
7-0 CMD_DATA R/W 0 This register provides command value for flash command.
SPI chip select Register Index F6h
Bit Name R/W Default Description
7-4 Reserved - - Reserved
3 Dummy_Reg R/W 0 Dummy register.
2 Dummy_Reg R/W 0 Dummy register.
1 Dummy_Reg R/W 0 Dummy register.
0 CS0 R/W 0 Chip select 0. To select device 0
SPI memory mapping Register Index F7h
Bit Name R/W Default Description
7-3 Reserved - 0 Reserved
2-0 Mem_map R/W - This register decides memory size.
3’b000: one of the memory sizes is 512k bytes.
3’b001: one of the memory sizes is 1024k bytes.
3’b100: one of the memory sizes is 2048k bytes.
3’b011: one of the memory sizes is 4096k bytes.
3’b100: one of the memory sizes if 8092k bytes.
SPI operate Register Index F8h
Bit Name R/W Default Description
7 TYPE R/W 0 This bit decide flash continuous programming mode. Set to 1, if programming
continuous mode is same as the SST flash. Set to 0 if programming continuous
mode is same as the ATMEL flash
6 IO_SPI R/W 0 This bit control SPI function transfer 8 bit command to device. Clear 0 by
operation finish.
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5 RDSR R/W 0 This bit control SPI function read status from to device. Clear 0 by operation
finish.
4 WRSR R/W 0 This bit control SPI function write status to device. Clear 0 by operation finish.
3 SECTOR_ERASE R/W 0 This bit control SPI function sector erase device. Clear 0 by operation finish.
2 READ_ID R/W 0 This bit control SPI function read id from device. Clear 0 by operation finish.
1 PROG R/W 0 This bit control SPI function program data to device or set to 1 when memory
cycle for LPC interface program flash. Clear 0 by operation finish.
0 READ R/W 0 This bit control SPI function read data from device or set to 1 when memory
cycle for LPC interface read flash. Clear 0 by operation finish.
SPI Low Byte Data Register Index FAh
Bit Name R/W Default Description
7-0 L_DATA R 0 When SPI is received 16 bits or 8 bits data from device. This register saves low
byte data.
SPI address high byte Register Index FBh
Bit Name R/W Default Description
7-0 Addr_H_byte R/W 0 This register provides high byte address for sector erase, program, read
operation.
SPI address medium byte Register Index FCh
Bit Name R/W Default Description
7-0 Addr_M_byte R/W 0 This register provides medium byte address for sector erase, program, read
operation.
SPI address low byte Register Index FDh
Bit Name R/W Default Description
7-0 Addr_L_byte R/W 0 This register provides low byte address for sector erase, program, read
operation.
SPI program byte Register Index FEh
Bit Name R/W Default Description
7-0 PORG_BYTE R/W 0 This register provides number to program flash for continuous mode.
SPI write data Register Index FFh
Bit Name R/W Default Description
7-0 WR_dat R/W 0 This register provides data to write flash for program, write status function.
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8.11 PME and ACPI Registers (CR0A)
8.11.1 Configuration Register
Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 PME_EN R/W 0 0: disable PME.
1: enable PME.
PME Event Enable Register Index F0h
Bit Name R/W Default Description
7 Reserved - - Reserved
6 MO_PME_EN R/W 0 Mouse PME event enable.
0: disable mouse PME event.
1: enable mouse PME event.
5 KB_PME_EN R/W 0 Keyboard PME event enable.
0: disable keyboard PME event.
1: enable keyboard PME event.
4 HM_PME_EN R/W 0 Hardware monitor PME event enable.
0: disable hardware monitor PME event.
1: enable hardware monitor PME event.
3 PRT_PME_EN R/W 0 Parallel port PME event enable.
0: disable parallel port PME event.
1: enable parallel port PME event.
2 UR2_PME_EN R/W 0 UART 2 PME event enable.
0: disable UART 2 PME event.
1: enable UART 2 PME event.
1 UR1_PME_EN R/W 0 UART 1 PME event enable.
0: disable UART 1 PME event.
1: enable UART 1 PME event.
0 FDC_PME_EN R/W 0 FDC PME event enable.
0: disable FDC PME event.
1: enable FDC PME event.
PME Event Status Register Index F1h
Bit Name R/W Default Description
7 Reserved - - Reserved
6 MO_PME_ST R/W - Mouse PME event status.
0: Mouse has no PME event.
1: Mouse has a PME event to assert. Write 1 to clear to be ready for next PME
event.
5 KB_PME_ST R/W - Keyboard PME event status.
0: Keyboard has no PME event.
1: Keyboard has a PME event to assert. Write 1 to clear to be ready for next
PME event.
4 HM_PME_ST R/W - Hardware monitor PME event status.
0: Hardware monitor has no PME event.
1: Hardware monitor has a PME event to assert. Write 1 to clear to be ready for
next PME event.
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3 PRT_PME_ST R/W - Parallel port PME event status.
0: Parallel port has no PME event.
1: Parallel port has a PME event to assert. Write 1 to clear to be ready for next
PME event.
2 UR2_PME_ST R/W - UART 2 PME event status.
0: UART 2 has no PME event.
1: UART 2 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
1 UR1_PME_ST R/W - UART 1 PME event status.
0: UART 1 has no PME event.
1: UART 1 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
0 FDC_PME_ST R/W - FDC PME event status.
0: FDC has no PME event.
1: FDC has a PME event to assert. Write 1 to clear to be ready for next PME
event.
ACPI Control Register Index F4h
Bit Name R/W Default Description
7 Reserved R/W 0 Reserved
6 SPI_RST_EN R/W 0 Set one to enable the reset signal from SPI via the PWROK or PCIRST#. (SPI
as backup BIOS will assert a reset signal when FWH doesn’t response in 4
seconds)
5 KEY_SEL_ADD R/W 0 Set this bit one and KEY_SEL (CR2D[2:1]) 2’b00 will select windows 98
wakeup key as keyboard wakeup key.
4 EN_KBWAKEUP R/W 0 Set one to enable keyboard wakeup event asserted via PWSOUT#.
3 EN_MOWAKEUP R/W 0 Set one to enable mouse wakeup event asserted via PWSOUT#.
2-1 PWRCTRL R/W 11
0 VSB_PWR_LOSS R/W 0
ACPI Control Register Index F5h
Bit Name R/W Default Description
7 Reserved R/W 0 Reserved
6 Reserved R/W 0 Dummy register
5 RSTCON_EN R/W 0 0: Enable RSTCON# output via PWROK.
4-3 DELAY R/W 11
2 VINDB_EN R/W 1 Enable the PCIRSTIN_N and ATXPWGD de-bounce.
1 PCIRST_DB_EN R/W 0 Enable the LRESET_N de-bounce.
0 Reserved R/W 0
The ACPI Control the PSON_N to always on or always off or keep last state
00 : keep last state
10 : Always on
01 : Reserved (always on)
11: Always off
When VSB 3V comes, it will set to 1, and write 1 to clear it
1: Enable RSTCON# output via PCIRST#.
The PWROK delay timing from VDD3VOK by followed setting
00 : 100ms
01 : 200ms
10 : 300ms
11 : 400ms
Dummy register.
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ACPI Control Register Index F7h
Bit Name R/W Default Description
7-4 Reserved R/W 0 Reserved.
3-2 Reserved R/W 0 Dummy registers.
1 PWR_STS2_TRI R/W 0 Set this bit to one will cuase Pin55 be tri-state Status in S5 state.
0 PWR_STS_EN R/W 1
Enable power status pins. Pin77 will be S5# function. P56 will be ST1 function.
P55 will be ST2 function.
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9. Electron Characteristic
9.1 Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage -0.5 to 5.5 V
Input Voltage -0.5 to VDD+0.5 V
Operating Temperature 0 to +140 ° C
Storage Temperature -55 to 150 ° C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings
may adversely affect the life and reliability of the device
9.2 DC Characteristics
(TA = 0° C to 70° C, VDD = 3.3V ± 10%, VSS = 0V )
Parameter Conditions MIN TYP MAX Unit
Temperature Error, Remote
Diode
Supply Voltage range 3.0 3.3 3.6 V
Average operating supply current 10 mA
Standby supply current 5 uA
Resolution 1
Power on reset threshold 2.2 2.4 V
60 oC < TD < 145 oC, VCC = 3.0V to 3.6V
o
0
C <TD < 60oC 100 oC <TD < 145oC
High Level 95 uADiode source current
Low Level 10 uA
± 1
± 1
± 3
± 3
o
C
o
C
9.3 DC Characteristics Continued
(Ta = 0° C to 70° C, VDD = 3.3V ± 10%, VSS = 0V)
PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
I/OD
Input Low Voltage VIL 0.8 V
Input High Voltage VIH 2.0 V
Output Low Current IOL +12 mA VOL = 0.4V
Input High Leakage ILIH +1 µA VIN = VDD
Input Low Leakage ILIL -1 µA VIN = 0V
I/OD
Input Low Voltage VIL 0.8 V
Input High Voltage VIH 2.0 V
Output Low Current IOL +16 mA VOL = 0.4V
Input High Leakage ILIH +1 µA VIN = VDD
Input Low Leakage ILIL -1 µA VIN = 0V
I/OOD
Input Low Threshold Voltage Vt- 0.8 V VDD = 3.3 V
Input High Threshold Voltage Vt+ 2.0 V VDD = 3.3 V
Output Low Current IOL -12 -9 mA VOL = 0.4 V
-TTL level bi-directional pin with schmitt trigger, Open-drain output with12 mA sink
12ts5v
capability, 5V tolerance.
-TTL level bi-directional pin, Open-drain output with16 mA sink capability, 5V tolerance.
16t5v
-TTL level bi-directional pin, Output pin with 12mA source-sink capability, and can
12t
programming to open-drain function.
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