Fairchild Semiconductor MM74HC541WM, MM74HC541N, MM74HC541WMX, MM74HC541SJX, MM74HC541MTCX Datasheet
September 1983
Revised February 1999
MM74HC540 • MM74HC541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
© 1999 Fairchild Semiconductor Corporation DS005341.prf www.fairchildsemi.com
MM74HC540 • MM74HC541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate CMOS technology. They possess high drive current outputs which enable high speed
operation even when driving large bus capacitances.
These circuits achieve speeds comparable to low power
Schottky devices, while retaining the advantage of CMOS
circuitry, i.e., high noise im m u ni t y, and low power co ns u mp tion. Both devices have a fanout of 15 LS-TTL e quivalent
inputs.
The MM74HC540 is an inverting buffer and the
MM74HC541 is a non-inverting buffer. The 3-STATE control gate o pe r a t es a s a t w o- i n put N OR s u c h th at i f e i t he r G1
or G2 are HIGH, all eight outp uts are in the high-impedance state.
In order to enhance PC board layout, the MM74HC540 and
MM74HC541 offers a pinout having i nputs and ou tputs on
opposite sides of the package. All inputs are protected from
damage due to static discharge by diodes to V
CC
and
ground.
Features
■ Typical propagation delay: 12 ns
■ 3-STATE outputs for connection to system buses
■ Wide power supply range: 2–6V
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Output current: 6 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to t he ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HC540
Top V iew
MM74HC541
Order Number Package Number Package Description
MM74HC540WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC540SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC540MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC540N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC541WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC541N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
www.fairchildsemi.com 2
MM74HC540 • MM74HC541
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperat ure derat ing — plas tic “N” p ackage: −
12 mW/°C from 65 °C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: For a power supply of 5V ±10% the wors t case outpu t voltages (VOH, and VOL) occur for HC at 4.5 V. Thus the 4.5V values s hould b e used when
designing with this supply. Worst case V
IH
and VIL occur at V
CC
= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values s hould be used.
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
IN
) −1.5 to V
CC
+1.5V
DC Output Voltage (V
OUT
) −0.5 to V
CC
+0.5V
Clamp Diode Current (I
CD
) ±20 mA
DC Output Current, per pin (I
OUT
) ±35 mA
DC V
CC
or GND Current,
per pin (I
CC
) ±70 mA
Storage Temperature Range (T
STG
) −65°C to +150°C
Power Dissipation (P
D
)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds) 260°C
Min Max Units
Supply Voltage (V
CC
)26V
DC Input or Output Voltage
(V
IN
, V
OUT
)0V
CC
V
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise or Fall Times
(t
r
, tf) V
CC
= 2.0V 1000 ns
V
CC
= 4.5V 500 ns
V
CC
= 6.0V 400 ns
Symbol Parameter Conditions
V
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
V
IH
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum HIGH Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
V
IN
= VIH or V
IL
|I
OUT
| ≤ 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|I
OUT
| ≤ 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
V
OL
Maximum LOW Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
V
IN
= VIH or V
IL
|I
OUT
| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|I
OUT
| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
I
IN
Maximum Input V
IN
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
Current
I
OZ
Maximum 3- STATE
V
IN
= VIH or VIL, G = V
IH
6.0V ±0.5 ±5 ±10 µA
Output Leakage V
OUT
= VCC or GND
Current
I
CC
Maximum Quiescent V
IN
= VCC or GND 6.0V 8.0 80 160 µA
Supply Current I
OUT
= 0 µA
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