Fairchild Semiconductor MM74C905N, MM74C905CW Datasheet
October 1987
Revised January 1999
MM74C905 12-Bit Successive Appro ximation Register
© 1999 Fairchild Semiconductor Corporation DS005910.prf www.fairchildsemi.com
MM74C905
12-Bit Successive Approximation Register
General Description
The MM74C905 CMOS 12-bit successive approximation
register contains all the digit control and storage necessary
for successive approximation analog-to-digita l conversion.
Because of the unique capability of CMOS to switch to
each supply rail without any offset voltage, it can also be
used in digital systems as the contro l and st orage e lement
in repetitive routines.
Features
■ Wide supply voltage range: 3.0V to 15V
■ Guaranteed noise margin: 1.0V
■ High noise immunity: 0.45 V
CC
(typ)
■ Low power TTL compatibility: Fan out of 2 driving 74L
■ Provision for register extension or truncation
■ Operates in START/STOP or continuous conversion
mode
■ Drive ladder switches directly. For 10 bits or less with
50k/100k R/2R ladder network
Ordering Code:
Connection Diagram
Pin Assignments for DIP
Order Number Package Number Package Description
MM74C905N N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide
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MM74C905
Truth Table
H = HIGH Level
L = LOW Lev el
X = Don’t Care
NC = No Change
Time Inputs Outputs
t
n
DSE D0 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 CC
0 XLLX X XXXXXXXXXXXX
1D11HLX L H HHHHHHHHHHH
2D10HLD11D11L HHHHHHHHHHH
3D9HLD10D11D10LHHHHHHHHHH
4D8HLD9D11D10D9LHHHHHHHHH
5D7HLD8D11D10D9D8LHHHHHHHH
6D6HLD7D11D10D9D8D7LHHHHHHH
7D5HLD6D11D10D9D8D7D6LHHHHHH
8D4HLD5D11D10D9D8D7D6D5LHHHHH
9D3HLD4D11D10D9D8D7D6D5D4LHHHH
10 D2 H L D3 D11 D10 D9 D8 D7 D6 D5 D4 D3 L H H H
11 D1 H L D2 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 L H H
12 D0 H L D1 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 L H
13 X H L D0D11D10D9D8D7D6D5D4D3D2D1D0 L
14 X X L X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 L
X X H X H NC NCNCNCNCNCNCNCNCNCNCNC
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MM74C905
Absolute Maximum Ratings(Note 1)
Note 1: “Absolute Maximum Rat ings” are tho se values beyond which the
safety of the device cannot be guaranteed. E x c ept for “ Operating Temperature Range” they are not mea nt to imply that the devices sh ould be operated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device o peration.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Voltage at Any Pin −0.3V to VCC+0.3V
Operating Temperature Range (T
A
) −40°C to +85°C
Storage Temperature Range (T
S
) −65°C to +150°C
Power Dissipation (P
D
)
Dual-In-Line 700 mW
Small Outline 500 mW
Operating V
CC
Range 3.0V to 15V
Absolute Maximum V
CC
16V
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260°C
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
Logical “1” Input Voltage VCC = 5.0V 3.5 V
VCC = 10V 8.0 V
V
IN(0)
Logical “0” Input Voltage VCC = 5.0V 1.5 V
VCC = 10V 2.0 V
V
OUT(1)
Logical “1” Output Voltage VCC = 5.0V, IO = −10 µA4.5 V
VCC = 10V, IO = −10 µA9.0 V
V
OUT(0)
Logical “0” Output Voltage VCC = 5.0V, IO = 10 µA0.5V
VCC = 10V, IO = 10 µA1.0V
I
IN(1)
Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1.0 µA
I
IN(0)
Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA
I
CC
Supply Current VCC = 15V 0.05 300 µA
CMOS/LPTTL INTERFACE
V
IN(1)
Logical “1” Input Voltage VCC = 4.75V VCC − 1.5 V
V
IN(0)
Logical “0” Input Voltage VCC = 4.75V 0.8 V
V
OUT(1)
Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA2.4 V
V
OUT(0)
Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA0.4V
OUTPUT DRIVE (See Family Characteristics Data Sheet)
I
SOURCE
Output Source Current VCC = 5.0V, V
OUT
= 0V −1.75 −3.3 mA
(P-Channel) TA = 25°C
I
SOURCE
Output Source Current VCC = 10V, V
OUT
= 0V −8.0 −15 mA
(P-Channel) TA = 25°C
I
SINK
Output Sink Current VCC = 5.0V, V
OUT
= V
CC
1.75 3.6 mA
(N-Channel) TA = 25°C
I
SINK
Output Sink Current VCC = 10V, V
OUT
= V
CC
(N-Channel) TA = 25°C8.016mA
VCC = 10V ±5%
R
SOURCE
Q11–Q0 Outputs V
OUT
= VCC − 0.3V 150 350 Ω
TA = 25°C
R
SINK
Q11–Q0 Outputs VCC = 10V ±5%
V
OUT
= 0.3V 80 230 Ω
TA = 25°C
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