Fairchild Semiconductor MM74C86CW, MM74C86MX, MM74C86N, MM74C86M, MM74C221CW Datasheet
October 1987
Revised January 1999
MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
© 1999 Fairchild Semiconductor Corporation DS005887.prf www.fairchildsemi.com
MM74C86
Quad 2-Input EXCLUSIVE-OR Gate
General Description
The MM74C86 employs complementary MOS (CMOS)
transistors to achieve wide power supply operatin g range,
low power consumption and high noise margin these gates
provide basic functions used in the impl ementation of digital integrated circuit systems. The N- and P-channel
enhancement mode transistors pr ovide a symmetrical circuit with output swing essentially equal to the supply voltage. No DC power other than that caused by leakage
current is consumed during static condition. All inputs are
protected from damage due to static discharge by diode
clamps to V
CC
and GND.
Features
■ Wide supply voltage range: 3.0V to 15V
■ Guaranteed noise margin: 1.0V
■ High noise immunity: 0.45 V
CC
(typ.)
■ Low power: TTL compatibility:
Fan out of 2 driving 74L
■ Low power consumption: 10 nW/package (typ.)
■ The MM74C86 follows the MM74LS86 Pinout
Ordering Code:
Device also available in Tape and Reel. Specify by appendin g s uf f ix let t er “X” to the ordering co de.
Connection Diagram
Pin Assignments for DIP and SO IC
Top View
Truth Table
H = HIGH Level
L = LOW Level
Order Number Package Number Package Description
MM74C86M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C86N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Inputs Output
ABY
LLL
LHH
HLH
HHL
www.fairchildsemi.com 2
MM74C86
Absolute Maximum Ratings(Note 1)
Note 1: “Absolute Maxi mum Ratings” are those valu es beyond which the
safety of the device cannot be guaranteed. Ex ce pt for “O perating Temperature Range” they are not mean t to imply that the devices sho uld be operated at these limits. The Electrical Charac t eristics table provide s co nditions
for actual device operation.
DC Electrical Characteristics
Min/max limits apply across temperature range unless otherwise noted
AC Electrical Charac teristics (Note 2)
TA = 25°C, CL = 50 pF, unless otherwise specified
Note 2: AC Parameters are guara nt eed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: C
PD
determines t he no loa d AC power c ons um ption of a ny CM OS d evice. For com plet e expla natio n se e Family Cha ract eris tics Appl icat ion No te—
AN-90.
Voltage at any Pin (Note 1) −0.3V to VCC + 0.3V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Power Dissipation (P
D
)
Dual-In-Line Package 700 mW
Small Outline 500 mW
Operating Range (V
CC
) 3.0V to 15V
Absolute Maximum (V
CC
)18V
Lead Temperature
(Soldering, 10 seconds) 260°C
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
Logical “1” Input Voltage VCC = 5.0V 3.5 V
VCC = 10V 8.0 V
V
IN(0)
Logical “0” Input Voltage VCC = 5.0V 1.5 V
VCC = 10V 2.0 V
V
OUT(1)
Logical “1” Output Voltage VCC = 5.0V, IO = −10 µA4.5 V
VCC = 10V, IO = −10 µA9.0 V
V
OUT(0)
Logical “0” Output Voltage VCC = 5.0V, IO = +10 µA0.5V
VCC = 10V, IO = +10 µA1.0V
I
IN(1)
Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1.0 µA
I
IN(0)
Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA
I
CC
Supply Current VCC = 15V 0.01 15 µA
CMOS/LPTTL INTERFA CE
V
IN(1)
Logical “1” Input Voltage VCC = 4.75V VCC−1.5 V
V
IN(0)
Logical “0” Input Voltage VCC = 4.75V 0.8 V
V
OUT(1)
Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA2.4 V
V
OUT(0)
Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA0.4V
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
I
SOURCE
Output Source Current VCC = 5.0V, V
OUT
= 0V −1.75 −3.3 mA
(P-Channel) TA = 25°C
I
SOURCE
Output Source Current VCC = 10V, V
OUT
= 0V −8.0 −15 mA
(P-Channel) TA = 25°C
I
SINK
Output Sink Current VCC = 5.0V, V
OUT
= V
CC
1.75 3.6 mA
(N-Channel) TA = 25°C
I
SINK
Output Sink Current VCC = 10V, V
OUT
= V
CC
8.0 16 mA
(N-Channel) TA = 25°C
Symbol Parameter Conditions Min Typ Max Units
t
pd
Propagation Time to Logical VCC = 5.0V 110 185 ns
“1” or “0” VCC = 10V 50 90 ns
C
IN
Input Capacitance (Note 3) 5.0 pF
C
PD
Power Dissipation Capacitance Per Gate (Note 4) 20 pF
Loading...