Fairchild Semiconductor MM74C165N Datasheet

October 1987 Revised January 1999

MM74C165 Parallel-Load 8-Bit Shift Register

General Description

The MM74C165 func tions as an 8-bit parallel- load, serial shift register. Data is loaded into the register inde pendent of the state of the clock(s) when PARALLEL LOAD (PL

) is

low. Shifting is inhibited as long as PL

is low. Data is

sequentially shifted from com plementary outputs, Q

and

, highest-order bit (P7) first. New serial data may be

entered via the SERIAL DATA (Ds) input. Serial shifting occurs on the r ising edge of CLOC K1 or CLOCK2. Cl ock inputs may be used separately o r together for combined clocking from independent sou rces. Either clock input m ay be used also as an active-low clock enable. To prevent double-clocking when a clock in put is used as an e nable,

the enable must be changed to a hi gh level (disabled) onl y while the clock is HIGH.

Features

■ Wide supply voltage range: 3V to 15V

■ Guaranteed noise margin: 1V

■ High noise immunity: 0.45 V

(typ.)

■ Low power TTL compatibility: fan out of 2 driving 74L

■ Parallel loading independent of clock

■ Dual clock inputs

■ Fully static operation

Ordering Code:

Connection Diagram

Pin Assignments for DIP

Top View

Order Number Package Number Package Description

MM74165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2

MM74C165

Block Diagrams

*Please look into S ec t ion 8, Appendix D for availability of various package types.

Truth Table

X = Don’t Care H = V

IN(1)

L = V

IN(0)

↑ = Clock transition from V

IN(0)

to V

IN(1)

P0 thru P7 = Data present (and loaded into) parall el inputs Q0 thru Q6 = Internal flip-flop outputs

State Inputs Internal Outputs

Clock1 Clock2 Ds P0 thru P7 Q0 Q1 Q7 Q7

(as enable)

Parallel Load L X X X P0…P7P0P1P7P7 Enable H L L X X P0P1P7P7 Shift (with Ds) H ↑ L H X H P0 P6 P6 Shift (with Ds) H ↑ LLXLHP5P5 Hold (Disable) H ↑ HXXLHP5P5

+ 4 hidden pages