Fairchild Semiconductor GTLP16T1655MTDX, GTLP16T1655MTD Datasheet

© 2000 Fairchild Semiconductor Corporation DS500172 www.fairchildsemi.com

August 1998
Revised April 2000

GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver

GTLP16T1655
16-Bit LVTTL/GTLP Universal Bus Transceiver

General Description

The GTLP16T1655 is a 16-bit universal bus transceiver
that provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface
between cards operating at LVTTL logic levels and a ba ck­plane operating at GTLP logic levels. High speed back­plane operation is a direct re sult of GTLP’s reduced output
swing (<1V), reduced input threshold levels and output
edge rate control. The edge rate control minimizes bus set­tling time. GTLP is a Fair child Semico nductor der ivative of
the Gunning Transceiver Logic (GTL) JEDEC standard
JESD8-3.

Fairchild’s GTLP has intern al edge-r ate cont rol and is pro­cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GT L but with different outp ut
levels and receiver threshold. GTLP output LOW level is
typically less than 0. 5V, the output level HIGH i s 1.5V a nd
the receiver threshold is 1.0V.

Features

■ Bidirectional interface between GTLP and LVTTL logic
levels

■ Variable Edge Rate Control pin t o select desired edge
rate on the GTLP backplane (V

ERC

)

■ Partitioned as two 8-Bit transce iv ers wi th indivi du al latch
timing and output control but with a common clock.

■ Power up/down high impedance for live insertion.

■ External pin to pre-condition I/O capacitance to high

state

■ Bus-hold data inputs on the A-Port eliminates the need
for external pull-up resistors on unused inputs

■ LVTTL compatible driver and control inputs

■ Flow through pinout optimizes PCB layout

■ Open drain on GTLP to support wired-or connection

■ A Port source/sink −24 mA/+24 mA

■ B Port sink +100mA

■ D-type flip-flop, latch and transparent data paths

■ −40°C to 85°C Temperature capability

■ Available in TSSOP

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Order Number Package Number Package Description

GTLP16T1655MTD MTD64 64-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 6.1mm Wide

www.fairchildsemi.com 2

GTLP16T1655

Connection Diagram Pin Descriptions

Truth Tables

(Note 1)

Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLK.
Note 2: Output level before the indicated steady state input conditions were es ta blished, provided CLK wa s H IG H prior to LEAB going LOW.
Note 3: Output level before the indicated steady state input conditions were es ta blished.

Pin Names Description

1OEAB A-to-B Output Enable (Active LOW)
2OEAB

Byte 1 and Byte 2

1OEBA B-to-A Output Enable (Active LOW)
2OEBA

Byte 1 and Byte 2

OE Disables all I/O ports simultaneously
1LEAB A-to-B Latch Enable (Transparent HIGH)
2LEAB Byte 1 and Byte 2
1LEBA B-to-A Latch Enable (Transparent HIGH)
2LEBA Byte 1 and Byte 2
V

REF

GTLP Reference Voltage
CLK A-to-B and B-to-A Clock
1A1-1A8 A Port I/O Byte 1 and Byte 2
2A1-2A8
1B1-1B8 B Port I/O Byte 1 and Byte 2
2B1-2B8

Inputs

Output

B

Mode

CEAB LEAB CLK A

H X X X Z High Impedance
L H X L L Transparent
L H X H H Transparent
LL↑ L L Registered
LL↑ H H Registered
LLHXB

0

(Note 2) Previous State

LLLXB

0

(Note 3) Previous State

Inputs Outputs Inputs Output Edge
OE

OEAB OEBA A Port B Port

V

ERC

B Port

LLLActiveActive V

CC

Slow
L L H Z Active GND Fast
LHLActiveZ
LHHZZ
HXXZZ

3 www.fairchildsemi.com

GTLP16T1655

Functional Description

The GTLP16T1655 is a hig h drive (100 mA ) 16-bit univ er­sal bus transceiver containing D-type flip-flop, latch and
transparent modes of operation for the data path. The
device is uniquely part ition ed as two 8-bit transceivers wi th
individual latch timin g and output contro l signa ls but w ith a
common clock pin (CLK) for both transceiver words. Da ta
flow for each word i s determined by the respecti ve latch
enables (xLEAB and xLEBA), output enables (xOEAB

and

xOEBA

) and clock (CLK). The output enables (1OEAB,

1OEBA

, and 2OEAB and 2OEBA) control Byte1 and Byte2

data for the A to B and B to A directions respectively.

For A-to-B data flow, the devices operate in the transparent
mode when LEAB is HIGH. When LEAB transitions LOW,
the A data is latched indepe ndent of CLK HIGH or LO W. If
LEAB is LOW the A data is registered on the CLK LOW-to­HIGH transition. When OEAB

is LOW the outputs are

active. With OEAB

HIGH the outputs are HIGH impedance.
Data flow for the B-to-A direction is identical but uses
OEBA

, LEBA and CLK. Note that CLK is common to both

directions and both 8-bit w ords. OE

is also common and is

used to disable all I/O ports simultaneously.

Logic Diagrams

www.fairchildsemi.com 4

GTLP16T1655

Absolute Maximum Ratings (Note 4) Recommended Operating

Conditions

Note 4: The Absolute Maximum Ratings are those values beyond which

the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limit s. The parametric values defin ed in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomme nded O peratin g Cond itions ” table will defin e the condition s
for actual device operation.

Note 5: I

O

Absolute Maximum Rating must be observed.

Note 6: V

TT

and R

term

can be adjusted t o accommodate bac k plane imped-

ances other than 50Ω, within the boundaries of not exceeding the DC
Absolute I

OL

ratings (200 mA). Simila rly V

REF

can be adjusted to compen-

sate for changes in V

TT

.

Supply Voltage (VCC) −0.5V to +4.6V
DC Input Voltage (V

I

) −0.5V to +4.6V

DC Output Voltage (V

O

)
Outputs 3-STATE −0.5V to +4.6V
Outputs Active (Note 5) −0.5V to + 4.6V

DC Output Sink Current into

A Port I

OL

48 mA

DC Output Source Current from

A Port I

OH

−48 mA

DC Output Sink Current

into B Port in the LOW State, I

OL

(Note 6) 200 mA

DC Input Diode Current (I

IK

)

V

I

< 0V −50 mA

DC Output Diode Current (I

OK

)

V

O

< 0V −50 mA

V

O

> V

CC

+50 mA
ESD Rating >2000V
Storage Temperature (T

STG

) −65°C to +150°C

Supply Voltage V

CC

3.0V to 3.6V

Bus Termination Voltage (V

TT

)
GTLP 1.35V to 1.65V
GTL 1.14V to 1.26V

V

REF

GTLP 0.87V to 1.1V
GTL 0.74V to 0.87V

Input Voltage (V

I

)

on A Port and Control Pins 0.0V to V

CC

on B Port 0.0V to V

tt

HIGH Level Output Current (IOH)

A Port −24 mA

LOW Level Output Current (I

OL

)
A Port +24mA
B Port +100 mA

Operating Temperature (T

A

) −40°C to +85°C

5 www.fairchildsemi.com

GTLP16T1655

DC Electrical Characteristics

Over Recommended Operating Free-Air Temperature Range, V

REF

= 1.0V (unless otherwise noted).

Note 7: All typical values are at VCC = 3.3V, and TA = 25°C.
Note 8: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Note 9: This is specified by characterization but not tested.
Note 10: This is the increase in supply current fo r each input that is at the spe ci fie d T T L voltage level rather than V

CC

or GND.

Symbol Test Conditions Min

Typ

(Note 7)

Max Units

V

IH

B Port V

REF

+0.05 V

TT

V

Others 2.0 V

V

IL

B Port 0.0 V

REF

−0.05 V

Others 0.8 V

V

REF

GTLP 0.74 1.0 1.1 V

V

IK

VCC = 3.0V II = −18 mA −1.2 V

V

OH

A Port VCC = Min to Max (Note 8) IOH = −100 µAV

CC

−0.2

V

CC

= 3.0V IOH = −12 mA 2.4 V

I

OH

= −24 mA 2.2

V

OL

A Port VCC = Min to Max (Note 8) IOL = 100 µA0.20

VV

CC

= 3.0V IOL = 12 mA 0.40

I

OL

= 24 mA 0.50

B Port V

CC

= 3.0V IOL = 40 mA 0.20 V

IOL = 80 mA 0.40
IOL = 100 mA 0.50

I

I

A Port VCC = 3.6V VI = VCC or 0V ±10 µA
Control Pi ns VCC = 3.6V VI = VCC or 0V ±10 µA
B Port V

CC

= 3.6V VI = VTT or GND ±10 µA

I

OFF

Except VCC = 0V

I

or VO = 0 to 100

µA

V

ERC

V

CC

I

I(hold)

A Port VCC = 3.0V VI = 0.8V 75

µAVI = 2.0V −75

VCC = 3.6V VI = 0 to V

CC

±500

I

OZH

A Port VCC = 3.6V VO = V

CC

10

µA

B Port VO = 1.5V 10

I

OZL

A Port VCC = 3.6V VO = 0V −10

µA

B Port V

O

= 0.4V −10

I

OZPU

A Port VCC = 0 to 1.5V VO = 0.5 to 3V ±50 µA

(Note 9) OE = 0 or V

CC

I

OZPD

A Port VCC = 1.5 to 0V VO = 0.5 to 3V ±50 µA

(Note 9) OE

= 0 or V

CC

I

CC

A or B Ports VCC = 3.6 Outputs HIGH 55

mA(v

cc

)I

O

= 0 Outputs LOW 55

V

I

= VCC or GND Outputs Disabled 55

∆I

CC

A Port and VCC = 3.6V One Input at 0 1

mA (Note 10) Control Pins A or Control VCC–0.6

Inputs at VCC or GND

C

i

Control Pi ns VI = VCC or 0 5.8 7.0
A Port VI = VCC or 0 8.0 9.5 pF
B Port VI = VCC or 0 8.3 9.9