Fairchild Semiconductor 74ACTQ245SC, 74ACTQ245QSCX, 74ACTQ245QSC, 74ACTQ245PC, 74ACTQ245MTCX Datasheet

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© 1999 Fairchild Semiconductor Corporation DS010236 www.fairchildsemi.com
July 1989 Revised November 1999
74ACQ245 • 74ACTQ245 Quiet Series Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs
74ACQ245 74ACTQ245 Quiet Series Octal Bidirectional Transceiver
with 3-STATE Inputs/Outputs
General Description
The ACQ/ACTQ utilizes Fairchild Quiet Series technol­ogy to guarantee quiet output switching and improve dynamic threshold perf ormance. FACT Quiet Series fe a­tures GTO output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
ICC and IOZ reduced by 5 0%
Guaranteed simultaneous switching noise level and
dynamic threshold performan ce
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
3-STATE outputs drive bus lines or buffer memory
address registers
Outputs source/sink 24 mA
Faster prop delays than the standard ACT245
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
FACT, Qui et Series , FACT Quiet Series, an d GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACQ245SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Body 74ACQ245SJ M20D 20-Lead Small Outline Package (SOP) EIAJ TYPE II, 5.3mm Wide 74ACQ245PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACTQ245SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Body 74ACTQ245SJ M20D 20-Lead Small Outline Package (SOP) EIAJ TYPE II, 5.3mm Wide 74ACTQ245QSC MQA20 20-Lead Quarter Size Outline Packag e (Q SOP ), JED EC MO -13 7, 0.15 0 Wide 74ACTQ245MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ245MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACTQ245PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74ACQ245 74ACTQ245
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Descriptions
Tr uth Table
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Pin Names Description
OE Output Enable Input T/R
Transmit/Receive Input
A
0–A7
Side A 3-STATE Inputs or 3-STATE Outputs
B
0–B7
Side B 3-STATE Inputs or 3-STATE Outputs
Inputs
Outputs
OE
T/R
L L Bus B Data to Bus A L H Bus A Data to Bus B
H X HIGH-Z State
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74ACQ245 74ACTQ245
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute max imum ratings are t hose values bey ond which damage
to the device may occu r. The databook spe cificatio ns shou ld be met, wit h­out exception, to ensure that the system de sign is relia ble over its p ower supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside da t abook specifications.
DC Electrical Characteristics for ACQ
Supply Voltage (VCC) 0.5V to +7.0V DC Input Diode Current (I
IK
)
V
I
= 0.5V 20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) 0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= 0.5V 20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) 0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) 65°C to +150°C
DC Latch-Up Source or
Sink Current ±300 mA
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
) ACQ 2.0V to 6.0V ACTQ 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) 40°C to +85°C Minimum Input Edge Rate ∆V/∆t
ACQ Devices V
IN
from 30% to 70% of V
CC
VCC @ 3.0V, 4.5V, 5.5V 125 mV/ ns
Minimum Input Edge Rate ∆V/∆t
ACTQ Devices V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
TA = +25°CT
A
= 40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC 0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC 0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
= 50 µA
5.55.495.4 5.4 VIN = VIL or V
IH
3.0 2.56 2.46 IOH = 12 mA
4.5 3.86 3.76 V I
OH
= 24 mA
5.5 4.86 4.76 I
OH
= 24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
5.5 0.001 0.1 0.1 VIN = VIL or V
IH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
I
IN
Maximum Input
5.5 ±0.1 ±1.0 µAVI = VCC, GND
(Note 4) Leakage Current I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65VMax
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5 4.0 40.0 µA
VIN = V
CC
(Note 4) Supply Current or GND I
OZT
Maximum I/O VI (OE) = VIL, V
IH
Leakage Current 5.5 ±0.3 ±3.0 µAVI = VCC, GND
VO = VCC, GND
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74ACQ245 74ACTQ245
DC Electrical Characteristics for ACQ (Continued)
Note 2: All outputs loaded; thresholds on input assoc iat ed with output under tes t. Note 3: Maximum test duratio n 2. 0 ms, one output loaded at a time. Note 4: I
IN
and ICC @ 3.0V are guaranteed to be less than or equa l to th e respective limit @ 5.5V VCC.
Note 5: DIP package . Note 6: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V; one output @ GND. Note 7: Max number of Data Inputs (n) switching. (n1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (V
ILD
),
0V to threshold (V
IHD
), f = 1 MHz.
DC Electrical Characteristics for ACTQ
Note 8: All outputs loaded; thresholds on input assoc iat ed with output under tes t. Note 9: Maximum test duratio n 2. 0 ms, one output loaded at a time. Note 10: DIP package. Note 11: Max number of outputs defined as (n). n1 Data Inputs are driven 0V to 3V; one outp ut @ GND. Note 12: Max number of Data Inputs (n) switching. (n1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V
ILD
),
0V to threshold (V
IHD
) f = 1 MHz.
Symbol Parameter
V
CC
TA = +25°CT
A
= 40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
OLP
Quiet Output
5.0 1.1 1.5 V
Figure 1, Figure 2
Maximum Dynamic V
OL
(Note 5)(Note 6)
V
OLV
Quiet Output
5.0 0.6 1.2 V
Figure 1, Figure 2
Minimum Dynamic V
OL
(Note 5)(Note 6)
V
IHD
Minimum HIGH Level
5.0 3.1 3.5 V (Note 5)(Note 7)
Dynamic Input Voltage
V
ILD
Maximum LOW Level
5.0 1.9 1.5 V (Note 5)(Note 7)
Dynamic Input Voltage
Symbol Parameter
V
CC
TA = +25°CTA = 40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 4.5 1.5 2.0 2.0
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or V
CC
0.1V
V
IL
Maximum LOW Level 4.5 1.5 0.8 0.8
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or V
CC
0.1V
V
OH
Minimum HIGH Level 4.5 4.49 4.4 4.4
VI
OUT
= 50 µA
Output Voltage 5.5 5.49 5.4 5.4
VIN = VIL or V
IH
4.5 3.86 3.76 V
IOH = 24 mA
5.5 4.86 4.76 IOH = 24 mA (Note 8)
V
OL
Maximum LOW Level 4.5 0.001 0.1 0.1
VI
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
VIN = VIL or V
IH
4.5 0.36 0.44 V
IOL = 24 mA
5.5 0.36 0.44 I
OL
= 24 mA (Note 8)
I
IN
Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAVI = VCC, GND
I
OZT
Maximum 3-STATE
5.5 ±0.3 ±3.0 µA
VI = VIL, V
IH
Leakage Current VO = VCC, GND
I
CCT
Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC 2.1V
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 9) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND
V
OLP
Quiet Output
5.0 1.1 1.5 V
Figure 1, Figure 2
Maximum Dynamic V
OL
(Note 10)(Note 11)
V
OLV
Quiet Output
5.0 0.6 1.2 V
Figure 1, Figure 2
Minimum Dynamic V
OL
(Note 10)(Note 11)
V
IHD
Minimum HIGH Level Dynamic Input Voltage 5.0 1.9 2.2 V (Note 10)(Note 12)
V
ILD
Maximum LOW Level Dynamic Input Voltage 5.0 1.2 0.8 V (Note 10)(Note 12)
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