Fairchild Semiconductor 74ACT16543SSCX, 74ACT16543SSC, 74ACT16543MTDX, 74ACT16543MTD Datasheet
© 1999 Fairchild Semiconductor Corporation DS500301 www.fairchildsemi.com
August 1999
Revised October 1999
74ACT16543 16-Bit Registered Transceiver with 3-STATE Outputs
74ACT16543
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ACT16543 cont ain s si xte en non -i nv ert in g t ran sceiv e rs
containing two sets of D-type registe rs for temporary storage of data flowing in either dir ecti o n. Each byte ha s sep arate control inputs wh ich can be shorted together for full
16-bit operation. Separate Latch Enable and Output
Enable inputs are provided for each register to permit independent input and o utput contr ol in either directio n of data
flow.
Features
■ Independent registers for A and B buses
■ Separate controls for data flow in each direction
■ Back-to-back registers for storage
Multiplexed real-time and stored data transfers
■ Separate control logic for each byte
■ Outputs source/sink 24 mA
■ TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
FACT is a trade m ark of F airchild Semicondu ctor Corporation.
Order Number Package Number Package Description
74ACT16543SSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACT16543MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Descriptions
OEAB
n
A-to-B Output Enable Input (Active LOW)
OEBA
n
B-to-A Output Enable Input (Active LOW)
CEAB
n
A-to-B Enable Input (Active LOW)
CEBA
n
B-to-A Enable Input (Active LOW)
LEAB
n
A-to-B Latch Enable Input (Active LOW)
LEBA
n
B-to-A Latch Enable Input (Active LOW)
A
0–A15
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B
0–B15
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
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74ACT16543
Functional Description
The ACT16543 contains sixtee n non-inve rting tran sceivers
with 3-STAT E outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. The control pins may be shorted together to obta in
full 16-bit operat ion. The following description applies to
each byte. For data flow from A to B, for example, the A-toB Enable (CEAB
n
) input must be LOW in or der to enter
data from A
0–A15
or take data from B0–B15, as indicated in
the Data I/O Control Table. With CEAB
n
LOW, a LOW sig-
nal on the A-to-B Latch Enable (LEAB
n
) input makes the A-
to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB
n
signal puts the A latche s i n the sto rage
mode and their outputs no longer change with the A inputs.
With CEAB
n
and OEABn both LOW, the 3-STATE B output
buffers are active and reflect the da ta p rese nt a t the output
of the A latches. Control of data flow from B to A is similar,
but using the CEBA
n
, LEBAn and OEBAn inputs.
Data I/O Control Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow show n; B-to-A flow control
is the same, except using CEBA
n
, LEBAn and OEBA
n
Logic Diagrams
Byte 1
(0:7)
Byte 2
(8:15)
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.
Inputs Latch Status
(Byte n)
Output
Buffers
(Byte n)
CEAB
n
LEABnOEAB
n
H X X Latched High Z
X H X Latched —
L L X Transparent —
X X H — High Z
L X L — Driving
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