Fairchild Semiconductor 74ACT163SJX, 74ACT163SJ, 74ACT163SCX, 74ACT163SC, 74ACT163PC Datasheet
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© 2000 Fairchild Semiconductor Corporation DS009932 www.fairchildsemi.com
November 1988
Revised February 2000
74AC163 • 74ACT163 Synchronous Presettable Binary Counter
74AC163 • 74ACT163
Synchronous Presettable Binary Counter
General Description
The AC/ACT163 ar e high-speed synchronous modulo-16
binary counters. They are synchronously presettable for
application in prog rammable dividers and h ave two types
of Count Enable inputs plus a Terminal Count output for
versatility in forming synchronous multistage counters. The
AC/ACT163 has a Synchro nous Rese t input tha t overr ides
counting and parallel loading and all ows the outputs to be
simultaneously reset on the rising edge of the clock.
Features
■ ICC reduced by 50%
■ Synchronous counting and loading
■ High-speed synchronous expan sion
■ Typical count rate of 125 MHz
■ Outputs source/sink 24 mA
■ ACT163 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Connection Diagram Pin Descriptions
Order Number Package Number Package Description
74AC163SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC163SJ M16D 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide
74AC163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC163PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT163SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT163SJ M16D 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT163PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock Pulse Input
SR
Synchronous Reset Input
P
0–P3
Parallel Data Inputs
PE
Parallel Enable Input
Q
0–Q3
Flip-Flop Outputs
TC Terminal Count Output
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74AC163 • 74ACT163
Logic Symbols
IEEE/IEC
Mode Select Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Functional Description
The AC/ACT163 counts in modulo-16 binary sequence.
From state 15 (HHHH) it increments to state 0 (LLLL). The
clock inputs of all flip-flo ps are driven in pa rallel throug h a
clock buffer. Thus all changes of th e Q outpu ts occur a s a
result of, and synchronou s with, the LOW-to-HIGH transition of the CP inp ut signal. The circuits ha ve four fundamental modes of operation, in order of precedence:
synchronous reset, parallel load , count-up and hold. Four
control inputs—Synchronous Re set (SR
), Parallel Enable
(PE
), Count Enable Parallel (CEP) and Count Enable
Trickle (CET)—determine the mode of operation, as shown
in the Mode Select Table. A LOW signal on SR
overrides
counting and parallel loading and allows all outputs to go
LOW on the next rising edge of CP. A LOW signal on PE
overrides counting an d allows information on th e Parallel
Data (P
n
) inputs to be loaded into the flip-f lops on the n ext
rising edge of CP. With PE
and SR HIGH, CEP and CET
permit counting when both are HIGH. Conversely, a LOW
signal on either CEP or CET inhibits counting.
The AC/ACT163 uses D-type edge-triggered flip-flops and
changing the SR
, PE, CEP and CET inputs when the CP is
in either state does not cause er ror s, pr ovi de d tha t the recommended setup and hold time s, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15 . To implement synchronous multistage counters, the TC outputs can be used with
the CEP and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup time
sets the upper limit o n clock frequency. For faster clock
rates, the carry lookahead connecti ons shown in Figure 2
are recommended. In this sch eme the ripple del ay through
the intermediate stages commences with the same clock
that causes the first stage to tick over from m ax to min in
the Up mode, or m in to m ax in th e Dow n mo de, to start its
final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress
through the intermediate stages. The critical timing that limits the clock period is th e CP to TC
delay of the first stage
plus the CEP
to CP setup time of the last stage. The TC
output is subject t o decoding spikes due to intern al race
conditions and is th erefore not recommen ded for u se as a
clock or asynchronous reset for flip-flops, registers or
counters.
Logic Equations: Count Enable = CEP • CET • PE
TC = Q0 • Q1 • Q2 • Q3 • CET
SR
PE CET CEP Action on the Rising
Clock Edge (
)
L X X X Reset (Clear)
H L X X Load (P
n
→ Qn)
H H H H Count (Increment)
H H L X No Change (Hold)
H H X L No Change (Hold)
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74AC163 • 74ACT163
State Diagram
FIGURE 1.
FIGURE 2.
Block Diagram
Please note that this diagram is provided on ly fo r t he understanding of logic operations and shou ld not be used to estimate propagation delays.
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74AC163 • 74ACT163
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its pow er
supply, temperature, and ou tput/inp ut loadi ng varia bles. Fairchild does no t
recommend operat ion of circuits outside d at abook specifications.
DC Electrical Characteristics for AC
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum te st duration 2.0 ms, one ou t put loaded at a time.
Note 4: I
IN
and ICC @ 3.0V are guaranteed to be less than or equa l to th e respective limit @ 5.5V VCC.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
Input Voltage (V
I
) 0V to V
CC
Output Voltage (VO) 0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)
AC Devices
V
IN
from 30% to 70% of V
CC
VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
TA = +25°C TA = −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
= −50 µA
5.5 5.49 5.4 5.4
VIN = VIL or V
IH
3.0 2.56 2.46 IOH = −12 mA
4.5 3.86 3.76 V IOH = −24 mA
5.5 4.86 4.76 IOH = −24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
5.5 0.001 0.1 0.1
VIN = VILor V
IH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
IIN (Note 4) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent 5.5 4.0 40.0 µAVIN = V
CC
(Note 4) Supply Current or GND
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