Fairchild Semiconductor 74ABT16646CSSCX, 74ABT16646CSSC, 74ABT16646CMTDX, 74ABT16646CMTD Datasheet
© 1999 Fairchild Semiconductor Corporation DS011644 www.fairchildsemi.com
October 1993
Revised November 1999
74ABT16646 16-Bit Transceivers and Registers with 3-STATE Outputs
74ABT16646
16-Bit Transceivers and Registers with 3-STATE Outputs
General Description
The ABT16646 consists o f bus transceiver circ uits with 3STATE, D-type flip-flo ps, and c ontrol circui try arranged for
multiplexed transmission of da ta directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control OE
and direction pins are pr ovided to control the tr ansceiver function. In the tran sceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE
is Active
LOW. In the isolation mode (control OE
HIGH), A data may
be stored in the B register a nd/or B data may be stored in
the A regis ter.
Features
■ Independent registers for A and B buses
■ Multiplexed real-time and stored data
■ A and B output sink capability of 64 mA, source
capability of 32 mA
■ Guarante ed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Nondestructive hot insertion capability
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
Order Number Package Number Package Description
74ABT16646CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16646CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
A
0–A15
Data Register A Inputs/
3-STATE Outputs
B
0–B15
Data Register B Inputs/
3-STATE Outputs
CPAB
n
, CPBAn Clock Pulse Inputs
SAB
n
, SBA
n
Select Inputs
OE
n
Output Enable Input
DIR Direction Control Input
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74ABT16646
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various s ignals at the OE
and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15)
and #2 control pins.
Real Time Transfer
A-Bus to B-Bus
FIGURE 1.
Real Time Transfer
B-Bus to A-Bus
FIGURE 2.
Storage from
Bus to Register
FIGURE 3.
Transfer from
Register to Bus
FIGURE 4.
Inputs Data I/O (Note 1) Output Operation Mode
OE
1
DIR1CPAB1CPBA1SAB1SBA1A
0–7
B
0–7
H X H or L H or L X X Isolatio n
H X
X X X Input Input Clock An Data into A Register
H X X
X X Clock Bn Data Into B Register
L H X X L X An to Bn—Real Time (Transparent Mode)
L H
X L X Input Output Clock An Data to A Register
L H H or L X H X A Register to Bn (Stored Mode)
L H
X H X Clock An Data into A Register and Output to Bn
L L X X X L Bn to An—Real Time (Transparent Mode)
L L X
X L Output Input Clock Bn Data into B Register
L L X H or L X H B Register to An (Stored Mode)
L L X
X H Clock Bn into B Register and Output to An
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74ABT16646
Logic Diagram
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