Fairchild Semiconductor 100370QIX, 100370QI, 100370QCX, 100370QC, 100370PC Datasheet
© 2000 Fairchild Semiconductor Corporation DS010649 www.fairchildsemi.com
February 1990
Revised August 2000
100370 Low Power Universal Demultiplexer/Decoder
100370
Low Power Universal Demultiplexer/Decoder
General Description
The 100370 univers al demultiplexer/dec oder functions as
either a dual 1-of-4 decoder or as a single 1-o f-8 decoder,
depending on the sign al applied to the Mode Control (M)
input. In the dual mode, each half has a pair of active-LOW
Enable ( E
) inputs. Pin assignments for the E inputs are
such that in the 1-of-8 mode they can easily be tied
together in pairs to provide two active-LOW enables (E
1a
to
E
1b
, E2a to E2b). Signals applied to auxiliary inputs Ha, H
b
and Hc determine whether the outputs are active HIGH or
active LOW. In the dual 1-of-4 mode the Address inputs are
A
0a
, A1a and A0b, A1b with A2a unused (i.e., left open, t ied
to V
EE
or with LOW signal applied). In the 1-of- 8 mode , the
Address inputs are A
0a
, A1a, A2a with A0b and A1b LOW or
OPEN. All inputs have 50 k
Ω pull-down resistors.
Features
■ 35% power reduction of the 100170
■ 2000V ESD protection
■ Pin/function compatible with 100170
■ Voltage compensated operating range
= −4.2V to −5.7V
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagrams
24-Pin DIP 28-Pin PLCC
Order Number Package Number Package Description
100370PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100370QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100370QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
−40°C to +85°C)
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100370
Logic Symbols
Single 1-of 8 Application
Dual 1-of-4 Application-
Pin Descriptions
Truth Tables
Dual 1-of-4 Mode (M = A2a = Hc = LOW)
Single 1-of-8 Mode (M
= HIGH; A
0b
= A1b = Ha = Hb = LOW)
H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care E1 = E1a and E1b wired; E2 = E22a and E2b wired
Note 1: for H
c
= LOW, output s t ates are complemented
Pin Names Description
A
na
, A
nb
Address Inputs
E
na
, E
nb
Enable Inputs
M Mode Control Input
H
a
Z0–Z3 (Z0a–Z3a) Polarity Select Input
H
b
Z4–Z7 (Z0b–Z3b) Polarity Select Input
H
c
Common Polarity Select Input
Z
0–Z7
Single 1-of-8 Data Outputs
Z
na
, Z
nb
Dual 1-of-4 Data Outputs
Inputs Active HIGH Outputs Active LOW Outputs
(H
a
and Hb Inputs HIGH) (Ha and Hb Inputs LOW)
E
1aE2aA1aA0aZ0aZ1aZ2aZ3aZ0aZ1aZ2aZ3a
E1bE2bA1bA0bZ0bZ1bZ2bZ3bZ0bZ1bZ2bZ
3b
HXXXLLLLHHHH
XHXXLLLLHHHH
LLLLHLLLLHHH
LLLHLHLLHLHH
LLHLLLHLHHLH
LLHHLL LHHHHL
Inputs Active HIGH Outputs (Note 1)
(H
c
Input HIGH)
E
1E2A2aA1aA0aZ0Z1Z2Z3Z4Z5Z6Z7
HXXXXLLLLLLLL
XHXXXLLLLLLLL
LLL LLHLLLLLLL
LLL LHLHLLLLLL
LLLHLLLHLLLLL
LLLHHLLLHLLLL
LLHLLLLLLHLLL
LLHLHLLLLLHLL
LLHHLLLLLLLHL
LLHHHLLLLLLLH
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100370
Logic Diagram
(Zn) for 1-of-4 applicati ons .
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