2.1.1 Interface (LVDS) data assignment.......................................................................................................................5
2.1.3 Data and Color arrangement ...............................................................................................................................6
2.1.4 Data and Display Position....................................................................................................................................6
3. ABSOLUTE MAXIMUM RATINGS ......................................................................................................7
3.1 ELECTRICAL ABSOLUTE MAXIMUM RATINGS ........................................................................................... 7
3.2 ENVIRONMENTAL ABSOLUTE MAXIMUM RATINGS................................................................................... 7
6.1QUALITY STANDARD .................................................................................................................................17
6.1.2 Lot .....................................................................................................................................................................17
6.1.4 Treatment of defective products ........................................................................................................................17
6.1.5 Treatment of defective products in the acceptance inspection ..........................................................................17
6.1.6 Treatment of other problems .............................................................................................................................18
6.1.8 Applicable period of repair .................................................................................................................................18
6.1.3 Label position ....................................................................................................................................................22
8.2 DESIGN OF APPLICATION ...........................................................................................................................27
8.5 OTHER PRECAUTIONS.................................................................................................................................30
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Product NumberL5S30348P01Revision Number00
1.BASIC SPECIFICATIONS
1.1 STRUCTURES
No. PARAMETER SPECIFICATIONS UNIT
1 LCD structure
2 Outward
3 Weight 465 Typ. g
4 Active area [Screen dimension]
5 Bezel opening area
6 Number of dots
7 Dot pitch
8 Dot layout Vertical stripe -
9 Viewing direction 6 o’clock 10 Liquid crystal mode TN, Normally white, Transmissive type 11 Polarization plate Non-glare -
*1) See attached drawing for details.
Dot pitch
Dot
Pixel
G B
Dot
Dot pitch
TFT LCD -
284.0(W) x 215.6(H) x 6.8 Max. (T) mm
270.336(W) x 202.752(H) [13.3 inch] mm
273.6(W) x 206.0(H)
1024 x R·G·B(W) x 768(H) -
0.088(W) x 0.264(H) mm
Page 2/30
mm
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Product NumberL5S30348P01Revision Number00
1.2 BLOCK DIAGRAM
CN1
VDD
VSS
FLCN 1
NOTE 1) This model is not equipped with an inverter circuit.
ASIC
TFT
Timing
Controller
(LVDS-Receiver)
DC/DC
Converter
DATA
Vcom
Gate Driver
768
Page 3/30
Source Driver
1024u(RGB)
TFT Panel
Back Light
CFL
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Product NumberL5S30348P01Revision Number00
1.3 I/O PINS
LCM㧦CN1
PIN NO.SYMBOLFUNCTION
1 VDD Power Supply ( 3.3V +/- 0.3V)
2 VDD Power Supply ( 3.3V +/- 0.3V)
3 VSS Ground
4 VSS Ground
5 Rin0- LVDS Differential data input (-)
6 Rin0+ LVDS Differential data input (+)
7 VSS Ground
8 Rin1- LVDS Differential data input (-)
9 Rin1+ LVDS Differential data input (+)
10 VSS Ground
11 Rin2- LVDS Differential data input (-)
12 Rin2+ LVDS Differential data input (+)
13 VSS Ground
14 RCLK- LVDS Differential Clock input (-)
15 RCLK+ LVDS Differential Clock input (+)
16 VSS Ground
17 NC No Connection䋨Should be opened during operation䋩
18 NC No Connection䋨Should be opened during operation䋩
19 VSS Ground
20 VSS Ground
Page 4/30
I/O REMARKS
P
P
P
P
I
I
P
I
I
P
I
I
P
I
I
P
-
P
P
CN1: DF19KR-20P-1H (HIROSE)
Suitable mating connector : DF19G-20S-1C (HIROSE) Wire type
㧦DF19G-20S-1F (HIROSE) FPC type
I/O : Input / Output terminal, I : Input terminal, O : Output terminal, P : Power line terminal
NOTE 1) Internal termination resistors of LVDS input lines are 100 ohms.
NOTE 2)
Valid synchronous signals are DCLK and DE. HSYNC and VSYNC are not used.
Backlight : FLCN1
PIN NO.SYMBOLFUNCTION
1 H.V High voltage for CFL
2 LGND Low voltage for CFL
I/O REMARKS
P
P
FLCN1 : BHSR-02VS-1 (JST)
Suitable mating connector: SM02B–BHSS-1-TB (JST)
NOTE 1) I/O : Input / Output terminal, I : Input terminal, O : Output terminal, P : Power line terminal
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R
4
R
3
R
2
R
0
0 (
5
(
)
0
4
9
3
2
8
7
6
5
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Product NumberL5S30348P01Revision Number00
2. FUNCTIONS
2.1OVERVIEW
2.1.1 Interface (LVDS) data assignment
Rin0 +/-
Rin1 +/-
Rin2 +/-
RCLK +/-
Rxout 6
G0 (LSB)
Rxout 13
B1
Rxout 20
DE
R5(MSB)
Rxout 12
B
Rxout 19
VSYNC
Rxout 5
LSB)
xout
R4
Rxout 11
G
MSB
Rxout 1
HSYNC
xout
R3
Rxout 1
G
Rxout 1
B5(MSB)
xout
R2
Rxout
G
Rxout 1
B4
xout 1
R1
Rxout 8
G
Rxout 1
B3
Rxout
R0 (LSB)
Rxout 7
G1
Rxout 14
B2
Page 5/30
2.1.2 Internal signals
SYMBOL FUNCTION
DCLK Data Clock
HSYNC Horizontal Sync. (This signal is invalid.)
VSYNC Vertical Sync. (This signal is invalid.)
DE Data Enable (positive)
R0 Red Data (LSB)
R1 Red Data
R2 Red Data
R3 Red Data
R4
R5
Red Data
Red Data (MSB)
G0 Green Data (LSB)
G1 Green Data
G2 Green Data
G3 Green Data
G4 Green Data
G5 Green Data(MSB)
B0 Blue Data (LSB)
B1 Blue Data
B2 Blue Data
B3 Blue Data
B4
B5
Blue Data
Blue Data (MSB)
NOTE 1) “DE mode “ only.
The valid synchronous signals are DCLK and DE. HSYNC and VSYNC are invalid.
NOTE 2) INTERNAL SIGNALS are loaded from LVDS - Receiver to TFT Timing controller
with LVDS sequence. (See BLOCK DIAGRAM.)
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Product NumberL5S30348P01Revision Number00
2.1.3 Data and Color arrangement
INPUT DATA
DISPLAY
COLOR
BLACK L L L L L LL L L L L L L L L L L L
RED H H H H H H L LLLLLL L L LLL
GREEN L L L L L LHHHHHH L L L L L L
BASIC
COLOR
BLUE L L L L L L L L L L L L H H H HHH
CYAN L L L L L LH HHH HHH H H HHH
MAGENTA H H H H H HL LLLLL H H H H H H
YELLOW H H H H H H HH H H H HL L L LLL
WHITE
BLACK L L L L L LL L L L L L L L L L L L
RED(1) L L L L LHL L L L L L L L L L L L
RED(2) L L L LHL L L L L L L L L L L L L
RED
: :::
: :::
RED(61) H H H H䌌HLLLLLLL L L LLL
RED(62) H H H H H䌌LLLLLLL L L LLL
RED(63)
BLACK L L L LLLLLLLLLL L L LLL
GREEN(1) L L L LLLLLLLLHL L L LLL
GREEN(2) L L L LLLLLLL䌈䌌L L L LLL
GREEN
: :::
: :::
GREEN(61)L L L L L L HHH䌈䌌HL L L LLL
GREEN(62)L L L L L LHHHHH䌌L L L L LL
GREEN(63)
BLACK L L L LLLLLLLLLL L L LLL
BLUE(1)L L L LLLLLLLLLL L L LLH
BLUE(2)L L L LLLLLLLLLL L L LHL
BLUE
: :::
: :::
BLUE(61) L L L LLLLLLLLLH H H H䌌䌈
BLUE(62)L L L LLLLLLLLLH H H HH䌌
BLUE(63)
NOTE 1) Chromaticity (n) --- "n" indicates grayscale's number.
2.1.4 Data and Display Position
1㨯1 1㨯2
2㨯1
.
.
.
.
767㨯1
768㨯1 768㨯2
VpHp R G B
. . . . . . . .
. . . . . . . . .
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1㨯1023 1㨯1024
2㨯1024
.
.
.
.
767㨯1024
768㨯1023768㨯1024
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Page 7/30
3. ABSOLUTE MAXIMUM RATINGS
3.1 ELECTRICAL ABSOLUTE MAXIMUM RATINGS
Ta= 25 deg C
PARAMETER SYMBOL RATINGS UNIT REMARKS
Power supply voltage VDD-VSS 4.0 V
LVDS Input voltage VIN
CFL current IL 7.0 mA
VHV 2000 Vrms CFL supply voltage
V
LGND 100 Vrms
NOTE 1)㩷 VIN: Rin0-/+, Rin1-/+, Rin2-/+, RCLK-/+
3.2 ENVIRONMENTAL ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL CONDITIONS
TST Storage -20 60 Ambient
temperature
OP Operation 0 50
T
Humidity - Ta=40 deg C
max.
Vibration - Storage - 1.5 G NOTE 3)
Shock - Storage - 50 G XYZ 6ms / direction
VSS – 0.3 㨪 VDD + 0.3
RATINGS
MIN MAX
- 85 %RH No condensation
V NOTE 1)
Ta= 25 deg C
UNIT REMARKS
deg.C NOTE 1)
NOTE 2)
NOTE 1) Care should be taken so that the LCD module may not be subjected to the temperature
beyond this specification
NOTE 2) Ta> 40 deg. C : Absolute humidity must be less than 85% RH/40 deg.C
NOTE 3) 10-200Hz, 30min/cycle, X/Y/Z each one cycle and except for resonant frequency.
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Product NumberL5S30348P01Revision Number00
4. ELECTRICAL SPECIFICATIONS
4.1 ELECTRICAL CHARACTERISTICS
VDD =3.3V , fCLK = 65MHZ, fH = 48.4kHz, fV = 60Hz, Ta = 25 deg C
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
Power supply voltage VDD-VSS
LVDS input Threshold
voltage
Common mode voltage
of LVDS input
VTH
VTL
CM
V
High level - - +100
Low level -100 - -
1.125 1.25 1.375 V
Power supply current IDD NOTE 1) - 250 - mA
NOTE 1) Display pattern of Typ. value is 64 grayscales.
NOTE 2) V
CM : Common mode voltage of LVDS input.
< 64 grayscales >
RATINGS
3.0 3.3 3.6 V
Page 8/30
Unit REMARKS
Terminal
Post
CM=1.25V
mV
V
NOTE 2)
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Page 9/30
4.2 BACKLIGHT CHARACTERISTICS
Ta= 25 deg.C
PARAMETER
SYMBOL CONDITIONS
MIN TYP MAXUNIT REMARKS
CFL voltage VL- 630 - Vrms at IL=6.0mArms
CFL current IL3.0 - 6.5 mArms
Driving frequency fL40 - 65 kHz
Discharge starting
voltage
CFL lifetime
S- - 1350Vrms at Ta=0 degC
V
tOL
20000
- - Hours
at I
L=6.0 mArms
continuous
operating
NOTE 5)
NOTE 1) There may be a display flickering by interaction of the backlight driving conditions
(especially for the Inverter frequency f
L) and the module's horizontal frequency fH.
Therefore, sufficient confirmation should be made when using inverter.
NOTE 2) The open circuit voltage of the Inverter should be designed higher than the discharge
starting voltage recorded in this table, and also should be applied more than 1 second. If
not applied as mentioned above, the backlight may not start properly.
NOTE 3) Asymmetrical waveform will cause a degradation of lifetime by unevenness of mercury.
Therefore, the current waveform should have an unbalancing-ratio of less than 10%, and
an amplitude-ratio of less than 2 ±10%. The current waveform should be measured by
actual final product.
Ip
-p
I
Current Waveform
Unbalance rate = | Ip - I-p | / IL x 100 (%)
Wave-height rate = I
p (or I-p) / IL
p:High peak
I
-p :Low peak
I
L:RMS
I
NOTE 4) Be sure to use a Ground Referenced type for the Inverter. Don't use a Ground Floating
type.
NOTE 5) The value that corresponds to the items written below is the definition of CFL life (when the
CFL is lit at Ta= 25, IL= 6.0mA):
1) when the brightness of the CFL falls to 50% or less of its initial value,
2) when the lighting start voltage does not fulfill the value written above
NOTE 6) The regulation of the CFL life is when the direction of the CFL tube axis (longer length of the
LCD module) is installed horizontally in the module. The life of the CFL may shorten when
the LCD module is used vertically due to mercury migration within the CFL tube.
NOTE 7) The CFL life will differ depending on the environmental temperature the LCD module is
used in. If the CFL is used in a cold/ hot environment for a long period of time, the
brightness will decrease drastically which may lead to a shorter CFL life.
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Product NumberL5S30348P01Revision Number00
4.3TIMINGS
4.3.1 Interface ( LVDS ) signal timing parameteres
VDD = 3.3V , fCLK = 65MHz , Ta = 25 deg.C
PARAMETER SYMBOL
Data setup time tsu 420 - - ps
Data hold time thd
CONDITION MIN TYP MAX UNIT
t
CLK=15.4ns
420 - - ps
The timing waveform in Figure 1 indicates the ideal strobe point of the LVDS input data:
n · tCLK
n : odd number
14
t
CLK : LVDS input clock period
The data setup time is "tsu" and the data hold time is "thd".
14
tCLK
7 tCLK
14
9 tCLK
14
11 tCLK
14
13 tCLK
RCLK +/-
Rin x +/-
㩷 tsu
thd
1 tCLK
14
Figure 1. LVDS data-input-timing waveform diagram
3 tCLK
14
5 tCLK
Page 10/30
14
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