Epson E0C6001 Technical Manual
MF943-02
CMOS 4-BIT SINGLE CHIP MICROCOMPUTER
E0C6001 T
ECHNICAL
M
ANUAL
E0C6001 Technical Hardware
E0C6001 Technical Software
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material
or due to its application or use in any product or circuit and, further, there is no representation that this material
is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any
intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that
anything made in accordance with this material will be free from any patent or copyright infringement of a third
party. This material or portions thereof may contain technology or the subject relating to strategic products under
the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license
from the Ministry of International Trade and Industry or other approval from another government agency. Please
note that "E0C" is the new name for the old product "SMC". If "SMC" appears in other manuals understand that
it now reads "E0C".
© SEIKO EPSON CORPORATION 1998 All rights reserved.
PREFACE
This manual is individualy described about the hardware and the software
of the E0C6001.
I. E0C6001 Technical Hardware
This part explains the function of the E0C6001, the circuit configurations, and details the controlling method.
II. E0C6001 Technical Software
This part explains the programming method of the E0C6001.
Hardware
Software
Hardware
E0C6001
I.
Technical Hardware
Hardware
CONTENTS
CHAPTER 1 INTRODUCTION............................................................... I-1
1.1 Configuration ................................................................... I-1
1.2 Features .......................................................................... I-2
1.3 Block Diagram ................................................................. I-3
1.4 Pin Layout Diagram......................................................... I-4
1.5 Pin Description ................................................................ I-5
CHAPTER 2 POWER SUPPLY AND INITIAL RESET ................................ I-6
2.1 Power Supply .................................................................. I-6
2.2 Initial Reset...................................................................... I-8
Oscillation detection circuit...................................... I-9
Reset pin (RESET) .................................................... I-9
Simultaneous high input to input ports (K00–K03) ... I-9
Internal register following initialization.................... I-10
2.3 Test Pin (TEST).............................................................. I-10
CHAPTER 3 CPU, ROM, RAM ............................................................ I-11
3.1 CPU................................................................................ I-11
3.2 ROM ............................................................................... I-12
3.3 RAM ............................................................................... I-12
CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ...................... I-13
4.1 Memory Map .................................................................. I-13
4.2 Oscillation Circuit............................................................ I-18
Crystal oscillation circuit......................................... I-18
CR oscillation circuit ............................................... I-19
4.3 Input Port (K00–K03)...................................................... I-20
Configuration of input port...................................... I-20
Interrupt function ................................................... I-20
Mask option ............................................................ I-22
Control of input port ............................................... I-23
4.4 Output Port (R00, R01) .................................................. I-25
Configuration of output port.................................... I-25
Mask option ............................................................ I-26
Control of output port ............................................. I-28
4.5 I/O Port (P00–P03)......................................................... I-31
Configuration of I/O port ........................................ I-31
I/O control register and I/O mode........................... I-32
Mask option ............................................................ I-32
Control of I/O port .................................................. I-33
4.6 LCD Driver (COM0–COM3, SEG0–SEG19) .................. I-35
Configuration of LCD driver..................................... I-35
Cadence adjustment of oscillation frequency ........... I-41
Mask option (segment allocation)............................. I-42
Control of LCD driver .............................................. I-44
4.7 Clock Timer .................................................................... I-45
Configuration of clock timer .................................... I-45
Interrupt function ................................................... I-46
Control of clock timer.............................................. I-47
4.8 Heavy Load Protection Function .................................... I-49
Operation of heavy load protection function ............ I-49
Control of heavy load protection function ................ I-50
Hardware
4.9 Interrupt and HALT......................................................... I-51
Interrupt factors...................................................... I-53
Specific masks and factor flags for interrupt............ I-54
Interrupt vectors ..................................................... I-54
Control of interrupt ................................................. I-55
CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM.............................I-56
CHAPTER 6 ELECTRICAL CHARACTERISTICS .................................... I-58
6.1 Absolute Maximum Rating ............................................. I-58
6.2 Recommended Operating Conditions ............................ I-59
6.3 DC Characteristics ......................................................... I-60
6.4 Analog Circuit Characteristics
and Power Current Consumption ...................................
I-62
6.5 Oscillation Characteristics .............................................. I-66
CHAPTER 7 PACKAGE ...................................................................... I-68
7.1 Plastic Package.............................................................. I-68
7.2 Ceramic Package for Test Samples............................... I-69
CHAPTER 8 PAD LAYOUT .................................................................. I-70
8.1 Diagram of Pad Layout................................................... I-70
8.2 Pad Coordinates............................................................. I-71
CHAPTER 1: INTRODUCTION
I-1
INTRODUCTION
Each member of the E0C6001 Series of single chip microcomputers feature a 4-bit E0C6200B core CPU, 1,024 words
of ROM (12 bits per word), 80 words of RAM (4 bits per
word), an LCD driver, 4 bits for input ports (K00–K03), 2
bits for output ports (R00, R01), one 4-bit I/O port (P00–
P03) and one timer (clock timer).
Because of their low voltage operation and low power consumption, the E0C6001 Series are ideal for a wide range of
applications.
Configuration
The E0C6001 Series are configured as follows, depending on
the supply voltage.
CHAPTER 1
1.1
Table 1.1.1
Configuration of the
E0C6001 Series
Model Supply Voltage Oscillation Circuits
3.0 V
1.5 V
E0C6001
E0C60L01
Crystal or CR
Crystal or CR
Supply Voltage Range
1.8–3.6 V
1.2–2.0 V
E0C6001 TECHNICAL HARDWARE
I-2
Features
Crystal or CR oscillation circuit, 32.768 kHz (typ.)
100 instructions
1,024 words ×12 bits
80 words × 4 bits
4 bits (Supplementary pull-down resistors may be used )
2 bits (Piezo buzzer and programmable frequency output
can be driven directry by mask option)
4 bits
20 segments × 4, 3 or 2 common duty
1 system: clock timer
Input port interrupt 1 system
Timer interrupt 1 system
1.5 V (1.2–2.0 V) E0C60L01
3.0 V (1.8–3.6 V) E0C6001
1.0 µA
(Crystal oscillation CLK = 32.768 kHz, when halted)
2.5 µA
(Crystal oscillation CLK = 32.768 kHz, when executing)
QFP12-48pin (plastic) or chip
1.2
Built-in oscillation circuit
Instruction set
ROM capacity
RAM capacity (data RAM)
Input port
Output port
Input/output port
LCD driver
Timer
Interrupts:
External interrupt
Internal interrupt
Supply voltage
Current consumption (typ.)
Supply form
CHAPTER 1: INTRODUCTION
I-3
1.3
Fig. 1.3.1
Block diagram
Power
Controller
LCD
Driver
RAM
80
× 4
Interrupt
Generator
I Port
Test Port
I/O Port
O Port
Timer
Core CPU E0C6200B
ROM
1,024 × 12
OSC
System
Reset
Control
RESET
OSC1
COM0
|
COM3
SEG0
|
SEG19
VDD
VL1
|
VL3
CA
CB
VS1
VSS
K00~K03
TEST
P00~P03
R00, R01
OSC2
FOUT
&
BUZZER
(FOUT/BUZZER)
(BUZZER)
Block Diagram
E0C6001 TECHNICAL HARDWARE
I-4
1.4
N.C. = No Connection
1
2
3
4
5
6
7
8
9
10
11
12
OSC2
V
S1
N.C.
P00
P01
P02
P03
K00
K01
K02
K03
N.C.
13
14
15
16
17
18
19
20
21
22
23
24
R01
R00
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
25
26
27
28
29
30
31
32
33
34
35
36
TEST
RESET
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
37
38
39
40
41
42
43
44
45
46
47
48
COM0
COM1
COM2
COM3
V
L3
VL2
VL1
CA
CB
V
SS
VDD
OSC1
Pin No Pin Name Pin No Pin Name Pin No Pin No Pin NamePin Name
Fig. 1.4.1
Pin assignment
QFP12-48pin
2536
13
24
INDEX
121
48
37
Pin Layout Diagram
CHAPTER 1: INTRODUCTION
I-5
1.5
Table 1.5.1 Pin description
Terminal Name
V
DD
V
SS
V
S1
V
L1
V
L2
V
L3
CA, CB
OSC1
OSC2
K00–K03
P00–P03
R00, R01
SEG0–19
COM0–3
RESET
TEST
Pin No.
47
46
2
43
42
41
44, 45
48
1
8–11
4–7
14, 13
36–27
24–15
37–40
26
25
Input/Output
(I)
(I)
O
O
O
O
–
I
O
I
I/O
O
O
O
I
I
Function
Power source (+) terminal
Power source (-) terminal
Oscillation and internal logic system regulated
voltage output terminal
LCD system reducer output terminal (V
L2
× 1/2)
/ LCD system reducer output terminal (V
L3
× 1/3)
LCD system booster output terminal (V
L1
× 2)
/ LCD system reducer output terminal (V
L3
× 2/3)
LCD system booster output terminal (V
L1
× 3)
/ LCD system booster output terminal (V
L2
× 3/2)
Booster capacitor connecting terminal
Crystal or CR oscillation input terminal
Crystal or CR oscillation output terminal
Input terminal
I/O terminal
Output terminal
LCD segment output terminal
(convertible to DC output terminal by mask option)
LCD common output terminal
Initial setting input terminal
Test input terminal
Pin Description
E0C6001 TECHNICAL HARDWARE
I-6
POWER SUPPLY AND INITIAL RESETCHAPTER 2
2.1
Power Supply
With a single external power supply (*1) supplied to VDD
through VSS, the E0C6001 Series generate the necessary
internal voltages with the regulated voltage circuit (<VS1> for
oscillators and internal circuit) and the voltage booster/
reducer (<VL2, VL3 or VL1, VL3> for LCDs).
When the E0C6001 LCD power is selected for 4.5 V LCD
panel by mask option, the E0C6001 short-circuits between
<VL2> and <VSS> in internally, and the voltage booster/
reducer generates <VL1> and <VL3>. When 3.0 V LCD panel
is selected, the E0C6001 short-circuits between <VL3> and
<VSS>, and the voltage reducer generates <VL1> and <VL2>.
The E0C60L01 short-circuits between <VL1> and <VSS>, and
the voltage booster generates <VL2> and <VL3>.
The voltage <VS1> for the internal circuit that is generated
by the regulated voltage circuit is -1.2 V (VDD standard).
Figure 2.1.1 shows the power supply configuration of the
E0C6001 Series in each condition.
*1 Supply voltage: E0C6001 ...... 3.0 V
E0C60L01 .... 1.5 V
- External loads cannot be driven by the output voltage of the
regulated voltage circuit and the voltage booster/reducer.
- See Chapter 6, "ELECTRICAL CHARACTERISTICS", for
voltage values.
Note
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
I-7
• E0C6001
4.5 V LCD panel
1/4, 1/3, 1/2 duty, 1/3 bias
Note: VL2 is shorted to VSS inside the IC.
3 V LCD panel 3 V LCD panel
1/4, 1/3, 1/2 duty, 1/3 bias 1/4, 1/3, 1/2 duty, 1/2 bias
• E0C60L01
4.5 V LCD panel 3 V LCD panel
1/4, 1/3, 1/2 duty, 1/3 bias 1/4, 1/3, 1/2 duty, 1/2 bias
Note: VL1 is shorted to VSS inside the IC.
Fig. 2.1.1 External element configuration of power system
Note: VL3 is shorted to VSS inside the IC.
V
DD
V
S1
V
L1
V
L2
V
L3
CA
CB
V
SS
3 V
V
DD
V
S1
V
L1
V
L2
V
L3
CA
CB
V
SS
3 V
V
DD
V
S1
V
L1
V
L2
V
L3
CA
CB
V
SS
3 V
V
DD
V
S1
V
L1
V
L2
V
L3
CA
CB
V
SS
1.5 V
V
DD
V
S1
V
L1
V
L2
V
L3
CA
CB
V
SS
1.5 V
E0C6001 TECHNICAL HARDWARE
I-8
Initial Reset
To initialize the E0C6001 Series circuits, an initial reset
must be executed. There are three ways of doing this.
(1)Initial reset by the oscillation detection circuit (Note)
(2)External initial reset via the RESET pin
(3)External initial reset by simultaneous high input to pins
K00–K03 (depending on mask option)
Figure 2.2.1 shows the configuration of the initial reset
circuit.
Fig. 2.2.1
Configuration of
initial reset circuit
2.2
Vss
RESET
K03
K02
K01
K00
OSC2
OSC1
OSC1
Oscillation
circuit
Vss
Oscillation
detection
circuit
Noise
rejection
circuit
Initial
reset
Noise
rejection
circuit
Note Be sure to use reset function (2) or (3) at power-on because the
initial reset function by the oscillation detection circuit (1) may not
operate normally depending on the power-on procedure.
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
I-9
The oscillation detection circuit outputs the initial reset
signal at power-on until the crystal oscillation circuit starts
oscillating, or when the crystal oscillation circuit stops
oscillating for some reason.
However, use the following reset functions at power-on
because the initial reset function by the oscillation detection
circuit may not operate normally depending on the power-on
procedure.
An initial reset can be invoked externally by making the
reset pin high. This high level must be maintained for at
least 5 ms (when oscillating frequency, fosc = 32 kHz),
because the initial reset circuit contains a noise rejection
circuit. When the reset pin goes low the CPU begins to
operate.
Another way of invoking an initial reset externally is to input
a high signal simultaneously to the input ports (K00–K03)
selected with the mask option. The specified input port pins
must be kept high for at least 4 sec (when oscillating frequency fosc = 32 kHz), because of the noise rejection circuit.
Table 2.2.1 shows the combinations of input ports (K00–
K03) that can be selected with the mask option.
A Not used
B K00*K01
C K00*K01*K02
D K00*K01*K02*K03
When, for instance, mask option D (K00*K01*K02*K03) is
selected, an initial reset is executed when the signals input
to the four ports K00–K03 are all high at the same time.
If you use this function, make sure that the specified ports
do not go high at the same time during normal operation.
Oscillation detection
circuit
Reset pin (RESET)
Simultaneous high
input to input ports
(K00–K03)
Table 2.2.1
Input port combinations
E0C6001 TECHNICAL HARDWARE
I-10
Internal register following initialization
Table 2.2.2
Initial values
2.3
An initial reset initializes the CPU as shown in the table
below.
CPU Core
Name
Program counter step
Program counter page
New page pointer
Stack pointer
Index register X
Index register Y
Register pointer
General register A
General register B
Interrupt flag
Decimal flag
Zero flag
Carry flag
Signal
PCS
PCP
NPP
SP
X
Y
RP
A
B
I
D
Z
C
Number of Bits
8
4
4
8
8
8
4
4
4
1
1
1
1
Setting Value
00H
1H
1H
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
0
Undefined
Undefined
Peripheral Circuits
Name
RAM
Display memory
Other peripheral circuit
Number of Bits
80 × 4
20 × 4
–
Setting Value
Undefined
Undefined
*1
*1: See section 4.1, "Memory Map"
Test Pin (TEST)
This pin is used when IC is inspected for shipment.
During normal operation connect it to VSS.
I-11
CHAPTER 3: CPU, ROM, RAM
CPU, ROM, RAM
CPU
The E0C6001 Series employs the E0C6200B core CPU, so
that register configuration, instructions, and so forth are
virtually identical to those in other processors in the family
using the E0C6200B. Refer to the "E0C6200/6200A Core
CPU Manual" for details of the E0C6200B.
Note the following points with regard to the E0C6001 Series:
(1)The SLEEP operation is not provided, so the SLP instruc-
tion cannot be used.
(2)Because the ROM capacity is 1,024 words, 12 bits per
word, bank bits are unnecessary, and PCB and NBP are
not used.
(3)The RAM page is set to 0 only, so the page part (XP, YP)
of the index register that specifies addresses is invalid.
PUSH XP PUSH YP
POP XP POP YP
LD XP,r LD YP,r
LD r,XP LD r,YP
CHAPTER 3
3.1
E0C6001 TECHNICAL HARDWARE
I-12
3.2 ROM
The built-in ROM, a mask ROM for the program, has a
capacity of 1,024 × 12-bit steps. The program area is 4
pages (0–3), each consisting of 256 steps (00H–FFH). After
an initial reset, the program start address is page 1, step
00H. The interrupt vector is allocated to page l, steps 01H–
07H.
3.3
Fig. 3.2.1
ROM configuration
RAM
The RAM, a data memory for storing a variety of data, has a
capacity of 80 words, 4-bit words. When programming,
keep the following points in mind:
(1)Part of the data memory is used as stack area when
saving subroutine return addresses and registers, so be
careful not to overlap the data area and stack area.
(2)Subroutine calls and interrupts take up three words on
the stack.
(3)Data memory 000H–00FH is the memory area pointed by
the register pointer (RP).
00H step
07H step
08H step
FFH step
12 bits
Program start address
Interrupt vector area
Bank 0
Program area
0 page
1 page
2 page
3 page
01H step
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
I-13
PERIPHERAL CIRCUITS
AND OPERATION
Peripheral circuits (timer, I/O, and so on) of the E0C6001
Series are memory mapped. Thus, all the peripheral circuits
can be controlled by using memory operations to access the
I/O memory. The following sections describe how the peripheral circuits operate.
CHAPTER 4
Memory Map
The data memory of the E0C6001 Series has an address
space of 113 words, of which 32 words are allocated to
display memory and 13 words, to I/O memory. Figure 4.1.1
show the overall memory map for the E0C6001 Series, and
Tables 4.1.1(a)–(d), the memory maps for the peripheral
circuits (I/O space).
4.1
Unused area
Fig. 4.1.1
Memory map
Note Memory is not mounted in unused area within the memory map
and in memory area not indicated in this chapter. For this reason,
normal operation cannot be assured for programs that have been
prepared with access to these areas.
Address
Page High
Low
0123456789ABCDE
F
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF
3
0
1
2
4
5
6
7
8
9
A
B
C
D
E
F
0
RAM area (000H–04FH)
80 words x 4 bits (R/W)
Display memory area (090H–0AFH)
32 words x 4 bits (Write only)
I/O memory area Tables 4.1.1(a)–(d)
E0C6001 TECHNICAL HARDWARE
I-14
Table 4.1.1(a) I/O memory map
* 1 Initial value following initial reset
* 2 Not set in the circuit
* 3 Undefined
* 4 Reset (0) immediately after being read
* 5 Constantly 0 when being read
* 6 Refer to main manual
Address Comment
Register
D3 D2 D1 D0 Name SR
*1
10
0E0H
0E4H
0E8H
K03 K02 K01 K00
TM3 TM2 TM1 TM0
EIK03 EIK02 EIK01 EIK00
R/W
R
R
K03
K02
K01
K00
–
–
–
–
TM3
TM2
TM1
TM0
–
–
–
–
EIK03
EIK02
EIK01
EIK00
0
0
0
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Timer data (clock timer 2 Hz)
Timer data (clock timer 4 Hz)
Timer data (clock timer 8 Hz)
Timer data (clock timer 16 Hz)
Input port (K00–K03)
High
High
High
High
Low
Low
Low
Low
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
High
High
High
High
Low
Low
Low
Low
*2
*2
*2
*2
0 EIT2 EIT8 EIT32 0
EIT2
EIT8
EIT32
0
0
0
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
Enable
Enable
Enable
Mask
Mask
Mask
0EBH
R R/W
*5
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
I-15
Table 4.1.1(b) I/O memory map
* 1 Initial value following initial reset
* 2 Not set in the circuit
* 3 Undefined
* 4 Reset (0) immediately after being read
* 5 Constantly 0 when being read
* 6 Refer to main manual
Address Comment
Register
D3 D2 D1 D0 Name SR
*1
10
0EDH
0EFH
0 0 0 IK0
0 IT2 IT8 IT32
0
0
0
IK0
0
0
IT2
IT8
IT32
0
0
0
Yes
Yes
Yes
Interrupt factor flag (K00–K03)
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
Yes No
R
R
*5
*5
*5
*4
0F6H
P03 P02 P01 P00
P03
P02
P01
P00
–
–
–
–
I/O port (P00–P03)
High
High
High
High
Low
Low
Low
Low
*2
*2
*2
*2
R/W
*5
*4
*4
*4
*5
*5
No
No
No
0F3H
00
R01 R00
0
0
R01
BUZZER
R00
FOUT
0
0
0
0
High
ON
High
ON
Low
OFF
Low
OFF
R01 output port data
Buzzer ON/OFF control register
R00 output port data
Frequency output ON/OFF control register
R/WR
BUZZER FOUT
E0C6001 TECHNICAL HARDWARE
I-16
Table 4.1.1(c) I/O memory map
* 1 Initial value following initial reset
* 2 Not set in the circuit
* 3 Undefined
* 4 Reset (0) immediately after being read
* 5 Constantly 0 when being read
* 6 Refer to main manual
Address Comment
Register
D3 D2 D1 D0 Name SR
*1
10
0F9H
0FAH
0 TMRST 0 0
HLMOD 0 0 0
W
0
TMRST
0
0
Reset
HLMOD
0
0
0
0
Clock timer reset
Heavy load protection mode register
Reset –
R
RR
R/W
Heavy
load
Normal
load
*5
*5
*5
0FBH
0FCH
CSDC 0 0 0
0 0 0 IOC
R
R
0
0
0
0
IOC
0
I/O port P00–P03 Input/Output
LCD drive switch
Static Dynamic
Output Input
*5
*5
*5
*5
*5
*5
R/W
R/W
CSDC
0
0
0
*5
*5
*5
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
I-17
Table 4.1.1(d) I/O memory map
* 1 Initial value following initial reset
* 2 Not set in the circuit
* 3 Undefined
* 4 Reset (0) immediately after being read
* 5 Constantly 0 when being read
* 6 Refer to main manual
Address Comment
Register
D3 D2 D1 D0 Name SR
*1
10
0FDH
XBZR 0 XFOUT1 XFOUT0RXBZR
0
XFOUT1
XFOUT0
0
0
0
Buzzer frequency control
2 kHz
High
High
4 kHz
Low
Low
R/WR/W
*5
FOUT frequency control:
XFOUT1(0), XFOUT0(0) -> F1
XFOUT1(0), XFOUT0(1) -> F2
XFOUT1(1), XFOUT0(0) -> F3
XFOUT1(1), XFOUT0(1) -> F4
E0C6001 TECHNICAL HARDWARE
I-18
Oscillation Circuit
The E0C6001 Series have a built-in crystal oscillation
circuit. This circuit generates the operating clock for the
CPU and peripheral circuit on connection to an external
crystal oscillator (typ. 32.768 kHz) and trimmer capacitor
(5–25 pF).
Figure 4.2.1 is the block diagram of the crystal oscillation
circuit.
4.2
Fig. 4.2.1
Crystal oscillation circuit
Crystal oscillation
circuit
As Figure 4.2.1 indicates, the crystal oscillation circuit can
be configured simply by connecting the crystal oscillator
(X'tal) between the OSC1 and OSC2 pins and the trimmer
capacitor (CG) between the OSC1 and VDD pins.
C
G
X'tal
OSC2
OSC1
To CPU and
peripheral circuits
The E0C6001 Series
V
DD
Rf
R
D
C
D
V
DD
Note
The OSC1 and OSC2 terminals on the board should be shielded
with the VDD (+ side)
.
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
I-19
CR oscillation circuit
For the E0C6001 Series, CR oscillation circuit (typ. 65 kHz)
may also be selected by a mask option. Figure 4.2.2 is the
block diagram of the CR oscillation circuit.
Fig. 4.2.2
CR oscillation circuit
As Figure 4.2.2 indicates, the CR oscillation circuit can be
configured simply by connecting the register (R) between
pins OSC1 and OSC2 since capacity (C) is built-in.
See Chapter 6, "ELECTRICAL CHARACTERISTICS" for R
value.
OSC2
OSC1
C
To CPU and
peripheral circuits
The E0C6001 Series
R
E0C6001 TECHNICAL HARDWARE
I-20
Input Port (K00–K03)
The E0C6001 Series have a 4-bit general-purpose input
port. Each of the input port pins (K00–K03) has an internal
pull-down resistance. The pull-down resistance can be
selected for each bit with the mask option.
Figure 4.3.1 shows the configuration of input port.
Selecting "pull-down resistance enabled" with the mask
option allows input from a push button, key matrix, and so
forth. When "pull-down resistance disabled" is selected, the
port can be used for slide switch input and interfacing with
other LSIs.
4.3
Configuration of
input port
Fig. 4.3.1
Configuration of input port
All four input port bits (K00–K03) provide the interrupt
function. The conditions for issuing an interrupt can be set
by the software for the four bits. Also, whether to mask the
interrupt function can be selected individually for all four
bits by the software. Figure 4.3.2 shows the configuration of
K00–K03.
Interrupt function
Kxx
V
SS
Mask option
Address
V
DD
Interrupt
request
Data bus
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Port)
I-21
Fig. 4.3.3
Input interrupt timing
Input interrupt programing related precautions
When the content of the mask register is rewritten, while
the port K input is in the active status. The input interrupt
factor flag is set at ➀.
The interrupt mask registers (EIK00–EIK03) enable the
interrupt mask to be selected individually for K00–K03. An
interrupt occurs when the input value which are not
masked change and the interrupt factor flag (IK0) is set to 1.
Fig. 4.3.2
Input interrupt circuit
configuration
(K00–K03)
When using an input interrupt, if you rewrite the content of
the mask register, when the value of the input terminal
which becomes the interrupt input is in the active status
(input terminal = high status), the factor flag for input
interrupt may be set.
For example, a factor flag is set with the timing of ➀ shown
in Figure 4.3.3. However, when clearing the content of the
mask register with the input terminal kept in the high
status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set.
Data bus
Address
Interrupt mask
register (EIK)
Kxx
Mask option
(K00–K03)
Noise
rejector
One for each pin series
Interrupt factor
flag (IK)
Interrupt
request
Address
Address
Port K input
Factor flag set Not set
Mask register
Active status
➀
E0C6001 TECHNICAL HARDWARE
I-22
Consequently, when the input terminal is in the active
status (high status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will
only set at the rising edge in this case. When clearing, then
setting the mask register, set the mask register, when the
input terminal is not in the active status (low status).
The contents that can be selected with the input port mask
option are as follows:
(1) An internal pull-down resistance can be selected for each
of the four bits of the input ports (K00–K03). Having
selected "pull-down resistance disabled", take care that
the input does not float. Select "pull-down resistance
enabled" for input ports that are not being used.
(2) The input interrupt circuit contains a noise rejection
circuit to prevent interrupts form occurring through
noise. The mask option enables selection of the noise
rejection circuit for each separate pin series. When "use"
is selected, a maximum delay of 0.5 ms (fosc = 32 kHz)
occurs from the time an interrupt condition is established
until the interrupt factor flag (IK) is set to 1.
Mask option
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Port)
I-23
Table 4.3.1 list the input port control bits and their addresses.
Table 4.3.1 Input port control bits
Control of input port
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0E0H
K03 K02 K01 K00
R
K03
K02
K01
K00
–
–
–
–
Input port (K00–K03)
High
High
High
High
Low
Low
Low
Low
0E8H
EIK03 EIK02 EIK01 EIK00
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
0EDH
0 0 IK0
R
0
0
0
IK0
0
Interrupt factor flag (K00–K03)
Yes No
0
K00–K03 Input port data (0E0H)
The input data of the input port pins can be read with these
registers.
When 1 is read: High level
When 0 is read: Low level
Writing: Invalid
The value read is 1 when the pin voltage of the four bits of
the input port (K00–K03) goes high (VDD), and 0 when the
voltage goes low (VSS). These bits are reading, so writing
cannot be done.
Loading...