Dell LATITUDE E5410,LATITUDE E5510 Schematics

5

4

www.rosefix.com

3

2

1

D D

Fonseca UMA Schematics Document

rPGA988A Mobile Arrandale

Intel Ibex Peak-M

C C

2009-11-03

REV : X01

B B

DY : Nopop Component B_TPM:Use Lom TPM C_TPM:Use China TPM

A A

http://sualaptop365.edu.vn

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

Fonseca UMA

1

1 82Tuesday, November 03, 2009

X01

5

www.rosefix.com

Fonseca UMA Block Diagram

4

3

2

1

DF3-14 DF3

Project code

PCB P/N Revision

91.4GN01.001

91.4EQ01.001

48.?????.0SB 48.?????.0SB 09276 - SB 09226 - SB

D D

Clock Generator

SLG8SP585VTR

7

Thermal & Fan

EMC4022

BTO(1)

39

Smart CARD Socket

BTO(2)

C C

PC CARD Socket

1394 Connector

67

72

71

DDR III DIMM1 1067Mhz

DDR III

DIMM2

1067Mhz

O2

OZ77CR6

Ricoh

R5U242

Channel A

18

Channel B

19

34

USB2.0

X1

PCIE

SD/SDHC/MMC Socket

BTO(3)

Power SW(NewCard)

TPS2231MRGPR

B B

HDD CONN

ODD CONN

USB Port x 2

71

INT2

New Card Connector

Free Fall Sensor

72

DE351DL

SATA SATA

59

SATA

59

X2

63

TCM (Option) ZTE

WLAN Switch

A A

64

32

72

PCIE

SMBus

40

INT1

USB2.0

36

LPC

BC

Int KB

KSI/KSO ECE1077

68

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5

PS2

Intel Mobile CPU

Arrandale

rPGA988A

DMIx4

Intel PCH

Ibex Peak-M

HM55

12 USB 2.0/1.1 ports

10/100/1000Mb ETHERNET

High Definition Audio

4 SATA ports

6 PCIE ports

ACPI 1.1

LPC I/F

PCI/PCI BRIDGE

LPC

SPI FLASH 64Mb

FLASH 8Mb

ECTouchPad

MEC 5045

4

BC

37 38

8~14

FDI

20~28

SPI

SIO Expander

eDP

CRT

Display Port (B) Display Port (C) USB2.0 SATA PCIE

HD AUDIO

62

35

LPC

ECE 5028

eDP-LCD Panel

BL Converter

Digital MIC

Module

73

Azalia CODEC

IDT 92HD81

OP AMP

30

MDC (Option)

Module

IO Board

76

LOM

ESW

BCM5761E

3

54

VSW

MAX4885EETG+

TLV320AIC3004

RJ11

IO Board

RJ45

IO Board

35

Serial Port

IO Board

MIC Jack

HP Jack

2CH SPEAKER (1W/1W)

76

CRT CONN

CPU DC/DC

ISL62883

INPUTS

+PWR_SRC

55

OUTPUTS

+VCC_CORE

SYSTEM DC/DC

TPS51125

47

46

OUTPUTSINPUTS

75

+PWR_SRC

SYSTEM DC/DC

X2

Docking

E/Family

75

TPS51116

INPUTS OUTPUTS

+PWR_SRC

SYSTEM DC/DC

TPS51218

+3.3V_ALW

+5V_ALW

50

+1.5V_SUS

+0.75V_DDR_VTT

52

INPUTS OUTPUTS

74

Bluetooth (Option)

Module

73

Camera (Option)

60

Module

USB Port x 2

IO Board

X2

73

76

+PWR_SRC +1.05V_VTT

SYSTEM LDO

RT9035

INPUTS OUTPUTS

+3.3V_SUS

+1.8V_RUN

SYSTEM DC/DC

ADP3211

INPUTS OUTPUTS

+PWR_SRC

+CPU_GFXCORE

51

53

1/2 Mini-Card

WLAN Module

64

Mini-Card

WWAN Module

76IO Board

Finger Printer

AES2880 (Option)

FP Board

2

78

Title

Size Document Number Rev

Custom

Date: Sheet of

BATTERY CHARGER

TI BQ24745

(AC, Battery Existence)

INPUTS OUTPUTS

+DC_IN_SS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Fonseca UMA

+PBATT

2 82Thursday, October 29, 2009

1

45

X01

5

4

3

2

1

www.rosefix.com

ADAPTER

D D

ADP3211

MAX17036

53

47 47

+CPU_GFXCORE

+VCC_CORE

53

Regulator

LDO

Switch

BATTERY

CHARGER BQ24745

C C

+PWR_SRC

TPS51125

+3V_ALW_2

46

+5V_ALW_2

46

TPS51218

52

+1.05V_VTT

TPS51116

52

+1.5V_SUS

SI4800BDY

50

+0.75V_DDR_VTT

42

5050

+5V_ALW

B B

SI34800BDV

42

+5V_MOD

A A

42

5

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SI4800BDY

+5V_RUN

+5V_HDD

46

FD38880

+3.3V_RUN

42

+3.3V_LAN

42

+15V_ALW

46

35

NJT4030PT1G

42

+CAMERA_VDD

4

73

+3.3V_HDD

42

+1.2V_LOM

+3.3V_ALW

SI3456BDV

3

46

35

SI3456BDV

42

+3.3V_SUS

RT9018

+1.8V_RUN

42

51

SI3456BDV

42

+3.3V_ALW_PCH

2

+1.5V_RUN

42

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, T aiwan, R.O.C.

Taipei Hsien 221, T aiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Power Diagram

Taipei Hsien 221, T aiwan, R.O.C.

Fonseca UMA

1

3 82Thursday, October 29, 200 9

X01

5

2.2K

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H14

PCH_SMB_CLK

C8

PCH_SMB_DATA

D D

C C

PCH

ibex Peak-M

C6 G8

E10G12

A5

B6

A50 B53

PCH_SML0CLK PCH_SML0DATA

KBC_SCL1 KBC_SDA1

LAN_SMBCLK LAN_SMBDAT

2.2K

+3.3V_ALW_PCH

2N7002 2N7002

+3.3V_ALW_PCH

+3.3V_ALW

EC

MEC5045

A7

CKG_SMBCLK

B7

CKG_SMBDAT

A2

DOCK_SMB_ALERT#

B4

DOCK_SMB_CLK

A3

DOCK_SMB_DAT

B B

A A

B5

LCD_SMBCLK

A4

LCD_SMBDAT

A56

PBAT_SMBCLK

B59

PBAT_SMBDAT

B50

CHARGER_SMBCLK

A47

CHARGER_SMBDAT

B49

AUD_DOCK_SMBCLK

B48

AUD_DOCK_SMBDAT

A49

CARD_SMBCLK

B52

CARD_SMBDAT

5

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2.2K

+3.3V_ALW

4

2.2K

2N7002 2N7002

4

+3.3V_RUN

10K

100 ohm

2.2K

+3.3V_ALW

2.2K

A3 SMB Addr=[XX] A4

32 31

133

127 129

13 12

3 4

10 9

8 9

20 19

3

+3.3V_LAN

LOM

BCM5761E

+3.3V_RUN

CLK Gen

SLG8SP585VTR

Docking

+LCDVDD

LCD Panel

(eDP Type)

Battery

connector

Charger

BQ24745RHDR

+3.3V_RUN

ADC/DAC

TLV320AIC3004

ExpressCard

connector

3

Dummy Dummy

SMB Addr=[D2]

SMB Addr=[C4/72/70/48]

SMB Addr=[58]

SMB Addr=[16]

SMB Addr=[12]

SMB Addr=[30]

2

DIMMA(DM1)

202 200

DIMMB(DM2)

202 200

53

XDP1

51

53

XDP2

51

FFSensor

14

DE351DL

13

2

Dummy

SMB Addr=[A0]

SMB Addr=[A4]

SMB Addr=[3A]

1

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin T ai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

SMBus Diagram

Fonseca UMA

1

4 82Tuesday, Novem ber 03, 2009

X01

5

4

3

2

1

www.rosefix.com

Thermal Block Diagram

D D

Audio Block Diagram

HP0_PORT_A_L

HP0_PORT_A_R

DP1

SC2200P50V2KX-2 GP

DN1

DP2/DN4

C C

DN2/DP4

SC2200P50V2KX-2 GP

Thermal

EMC4022

DP3/DN5

SC2200P50V2KX-2 GP

Q3902

MMBT3904-7-F-GP

Q3901

MMBT3904-7-F-GP

SYSTEM

Q3905

MMBT3904-7-F-GP

DIMM

Q3903

MMBT3904-7-F-GP

CPU

VREFOUT_A_OR_F

HP1_PORT_B_L

HP1_PORT_B_R

PORT_C_L

PORT_C_R

VREFOUT_C

Codec

92HD81

SPKR_PORT_D_L+

SPKR_PORT_D_L-

SPKR_PORT_D_R-

SPKR_PORT_D_R+

AUD_EXT_MIC_L

AUD_EXT_MIC_R

AUD_VREFOUT_B

AUD_HP_OUT_L

AUD_HP_OUT_R

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R+

AUD_SPK_R-

0R3-0-U-V-GP

AUD_SPK_L+_R

AUD_SPK_L-_R

AUD_SPK_R+_R

AUD_SPK_R-_R

MIC

Hear Phone

SPEAKER

60

WLANDN3/DP5

B B

THERMTRIP2#

CPU_ThermalTrip

PORT_E_L

PORT_E_R

PORT_F_L

PORT_F_R

SCD47U25V3KX-1G P

AUD_DOCK_MIC_IN _L

AUD_DOCK_MIC_IN _R

AUD_DOCK_HP_OUT _L_C

AUD_DOCK_HP_OUT _R_C

SC1U16V3KX-2GP

DOCKING

DAI_BCLK#

DAI_LRCK#

DAI_DO#

DAI_DI

TLV320AIC3004

75

DOCK HP

DOCK MIC

74

PCH_ThermalTrip

THERMTRIP3#

A A

5

http://sualaptop365.edu.vn

+3.3V_SUS

4

3

DMIC_CLK/GPIO1

DMIC0/GPIO2

0R2J-2-GP

AUD_DMIC_CLK AUD_DMIC_CLK_G_ C

AUD_DMIC_IN0

33R2J-2-GP

2

AUD_DMIC_IN0_C

Title

AUDIO/THERMAL Diagram

Size Document N umber Rev

Date: Sheet of

AUDIO/THERMAL Diagram

A3

Digital MIC

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

5 82Thursday, October 2 9, 2009

1

50

X01

5

4

3

2

1

PCH Strapping

Name Schematics Notes

SPKR

D D

INIT3_3V# Internal pull-up. Leave as "No Connect"

GNT3#/ GPIO55

INTVRMEN

GNT0#, GNT1#

GNT2#/ GPIO53

C C

B B

A A

SPI_MOSI

NV_ALE

NV_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.

HDA_DOCK_EN# /GPIO[33]

HDA_SDO

HDA_SYNC

GPIO15

GPIO8

GPIO27

www.rosefix.com

Calpella Schematic Checklist Rev: 1.6

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Connect to Vcc3_3 with 8.2-k

No Reboot Mode with TCO Disabled:

pull-up resistor.

Internal pull-up.

Default Mode: Low (0) = Top Block Swap Mode

Connect to ground with 4.7-kΩ weak pull-down resistor.

Note:

CRB uses a 1 kΩ ; do not stuff resistor

High (1) = Integrated VRM is enabled Low (0) = Integrated VRM is disabled Note:

CRB uses a 330-k resistor.

Leave both GNT0# and GNT1# floating. No pull up required

Default (SPI):

Connect GNT1# to ground with 1-kΩ pull-down resistor.

Boot from PCI:

Leave GNT0# Floating.

Connect both GNT0# and GNT1# to ground with 1-kΩ pull-down

Boot from LPC:

resistor.

Default -

= Configures DMI for ESI compatible operation (for servers only.

Low (0)

Not for mobile/desktops).

Connect to Vcc3_3 with 8.2-kΩ weak pull-up

Enable Intel Anti-Theft Technology:

resistor.

Disable Intel Anti-Theft Technology:

Left floating, no pull-down required.

Connect to +NVRAM_VCCQ with 8.2-kΩ weak

Enable Intel Anti-Theft Technology:

pull-up resistor [CRB has it pulled up with 1-kΩ no-stuff resistor] Leave floating (internal pull-down).

Disable Intel Anti-Theft Technology:

Flash Descriptor Security will be overridden.

Low (0):

Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features.

High (1):

Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently.

Note:

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

Low (1) - Intel ME Crypto Transport Layer Security TLS) cipher suite with no confidentiality. High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality. Note: This is an unmuxed signal. This signal has a weak internal pull-down of 20KΩ which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1K pull-up on this signal to +3.3VA rail.

Weak internal pull-up. Do not pull low. Sampled at rising edge of RSMRST#.

Do not connect (floating). Internal pull-up.

Default =

High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.

5

Internal pull-up.

CRB recommends 1-kΩ pull-down for FD Override. There is an internal pull-up of 20 kΩ for HDA_DOCK_EN# which is only enabled at boot/reset for strapping functions.

http://sualaptop365.edu.vn

4

Ω ~ 10-kΩ weak

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[4] Disabled - No Physical Display Port attached to

CFG[3]

CFG[0]

DisplayPort Presence

PCI-Express Static Lane Reversal

PCI-Express Configuration Select1:0:

1 unless specified otherwise)

1:Embedded

Embedded DisplayPort.

Enabled - An external Display Port device is

0:

connected to the Embedded Display Port.

Normal Operation.

1:

Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Single PCI-Express Graphics Bifurcation enabled

PCIE Routing

LANE1

LANE2

LANE3

LANE4

LANE5

LANE6

LANE7

LANE8

3

WWAN

WLAN

PCMCIA

Express Card

None

10M/100M/1G LAN

Not available for HM55

Calpella Schematic Checklist Rev: 1.6

USB Routing

Pair

0

1

2

3

4

5

6

7

8

9

10

11

12

13

Title

Table of Content

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

Table of Content

Default Value

1

USB

Device

USB0 @ MB

USB1 @ MB

USB2 @ IO Board

USB3 @ IO Board

WLAN

Bluetooth

Not available for HM55

DOCKING PORT1

DOCKING PORT2

Finger Printer

Camera

PCCard / SmartCard

WWAN

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

6 82Thursday, October 2 9, 2009

1

X01

5

4

3

2

1

SSID = CLOCK

+3.3V_RU N +3.3V_RU N_CLKGEN

D D

+1.05V_R UN

C C

CLKIN_DMI#23

CLK_PCIE_ SATA#23

CLK_PCIE_ SATA23

CLK_CPU _BCLK#23

CLK_CPU _BCLK23

B B

L702

1 2

BLM21PG 300SN1-GP

12

C702

SC1U10V2KX-1GP

L701

1 2

BLM21PG 300SN1-GP

12

C710

SC1U10V2KX-1GP

DREFCLK #23

DREFCLK23

CLKIN_DMI23

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12

C703

SC10U10V5ZY-1GP

12

C711

SC10U10V5ZY-1GP

12

C704

C705

SCD1U16V2ZY-2GP

12

C713

C712

SCD1U16V2ZY-2GP

2 3 1

RN701 SRN0J-6-G PRN701 SRN0J-6-G P

2 3 1

RN703 SRN0J-6-G PRN703 SRN0J-6-G P

2 3 1

RN704 SRN0J-6-G PRN704 SRN0J-6-G P

1 2 3

RN705 SRN0J-6-G PRN705 SRN0J-6-G P

12

C706

SCD1U16V2ZY-2GP

X01-43

4

12

C707

SCD1U16V2ZY-2GP

12

C709

C708

SCD1U16V2ZY-2GP

+1.05V_R UN_CLKGEN_IO

SCD1U16V2ZY-2GP

CLK_PCH _DREFCLK1# CLK_PCH _DREFCLK1

CLK_IN_DM I# CLK_IN_DM I

CLK_PCIE_ SATA1# CLK_PCIE_ SATA1

CLK_CPU _BCLK1# CLK_CPU _BCLK1

U701

4

DOT_96#

3

DOT_96

14

SRC_2#

13

SRC_2

11

SRC_1/SATA#

10

SRC_1/SATA

22

CPU_0#

23

CPU_0

19

CPU_1#

20

CPU_1

CKG_SMB DAT37

CKG_SMB CLK37

+3.3V_RU N_CLKGEN +1.05V_RUN_ CLKGEN_IO

1

5

17

24

29

VDD_SRC

VDD_CPU

SLG8SP585VTR-GP

VSS_REF

GND

21

26

33

15

18

VDD_27

VDD_REF

VDD_DOT

VDD_SRC_IO

VDD_CPU_IO

27MHZ_SS

CPU_STOP#

CKPWRGD/PD#

REF_0/CPU_SEL

XTAL_IN

XTAL_OUT

VSS_DOT

VSS_278VSS_SATA

VSS_SRC

VSS_CPU

2

9

12

Main Source: 71.08585.003 (SLG8SP585VTR) 2nd Source: 71.93197.003 (ICS9LRS3197AKLFT) 3rd Source: 71.28748.A03 (SL28748ELCT)

27MHZ

SDA SCL

6 7

16 25 30

28 27

31 32

CPU_STO P# CK_PW RGD FSC

CLK_XTA L_IN CLK_XTA L_OUT

CLK_SDA TA CLK_SCL K

+3.3V_RU N

Q701

34

2

5

1

6

DMN66D0 LDW-7-GP

+3.3V_RU N

1

23

RN702

RN702 SRN2K2J -1-GP

SRN2K2J -1-GP

4

12

R704 10KR2J-3 -GPR704 10KR2J-3 -GP

CLK_SCL K

CLK_SDA TA

1 2

DY

R708 0R2J-2-GP

1 2

DY

R709 0R2J-2-GP

+3.3V_RU N

R705

1 2

33R2J-2-G P

R706

R706 10KR2J-3 -GP

10KR2J-3 -GP

CK_PW RGD

CLK_SCL K_HDDFALL 40

CLK_SDA TA_HDDFALL 40

12

C714

DY

SC4D7P5 0V2CN-1GP

For EMI

+3.3V_RU N_CLKGEN

1 2

CLK_PCH _14M 23

Q702

+1.05V_V TT

12

R701

R701 4K7R2J-2 -GP

4K7R2J-2 -GP

DY

CLK_XTA L_IN CLK_XTA L_OUT

R707

R707 10KR2J-3 -GP

10KR2J-3 -GP

FSC

FSC 0 1

SPEED

5

133MHz

(Default)

http://sualaptop365.edu.vn

100MHz

4

C715

SC15P50V2JN-2-GP

A A

12

1 2

X-14D318 18M-37GP

12

X01.09/0918

X701

C701

12

SC15P50V2JN-2-GP

3

2

Title

Clock Generator - SLG8SP585

Size Document N umber Rev

A3

Date: Sheet of

Q702

2N7002A -7-GP

G

S D

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

1

7 82Thursday, October 2 9, 2009

VR_CLKE N# 47

X01

SSID = CPU

5

4

www.rosefix.com

3

2

1

D D

DMI_PTX_C RXN022 DMI_PTX_C RXN122 DMI_PTX_C RXN222 DMI_PTX_C RXN322

DMI_PTX_C RXP022 DMI_PTX_C RXP122 DMI_PTX_C RXP222 DMI_PTX_C RXP322

DMI_CTX_P RXN022 DMI_CTX_P RXN122 DMI_CTX_P RXN222 DMI_CTX_P RXN322

DMI_CTX_P RXP022 DMI_CTX_P RXP122 DMI_CTX_P RXP222 DMI_CTX_P RXP322

FDI_TXN022 FDI_TXN122

C C

FDI_TXN222 FDI_TXN322 FDI_TXN422 FDI_TXN522 FDI_TXN622 FDI_TXN722

FDI_TXP022 FDI_TXP122 FDI_TXP222 FDI_TXP322 FDI_TXP422 FDI_TXP522 FDI_TXP622 FDI_TXP722

FDI_FSYNC022 FDI_FSYNC122

FDI_INT22

FDI_LSYNC022 FDI_LSYNC122

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

G24

G23

G21

G18

G22

G19

A24 C23 B22 A21

B24 D23 B23 A22

D24

F23 H23

D25 F24 E23

E22 D21 D19 D18

E19 F21

D22 C21 D20 C18

E20 F20

F17 E17

C17

F18 D17

CPU1A

DMI_RX0# DMI_RX1# DMI_RX2# DMI_RX3#

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX0# DMI_TX1# DMI_TX2# DMI_TX3#

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI_TX0# FDI_TX1# FDI_TX2# FDI_TX3# FDI_TX4# FDI_TX5# FDI_TX6# FDI_TX7#

FDI_TX0 FDI_TX1 FDI_TX2 FDI_TX3 FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

AUBURNDALE

B B

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

PEG_RX0# PEG_RX1# PEG_RX2#

DMI

PEG_RX3# PEG_RX4# PEG_RX5# PEG_RX6# PEG_RX7# PEG_RX8#

PEG_RX9# PEG_RX10# PEG_RX11# PEG_RX12# PEG_RX13# PEG_RX14# PEG_RX15#

PEG_RX10

PEG_RX11

PEG_RX12

PEG_RX13

PEG_RX14

PEG_RX15

PEG_TX10# PEG_TX11# PEG_TX12# PEG_TX13# PEG_TX14# PEG_TX15#

PCI EXPRESS -- GRAPHICS

1 OF 9

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5

Intel(R) FDI

PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9

PEG_TX0# PEG_TX1# PEG_TX2# PEG_TX3# PEG_TX4# PEG_TX5# PEG_TX6# PEG_TX7# PEG_TX8# PEG_TX9#

PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

R801

PEG_IRCOM P_R

B26 A26 B27

EXP_RBIAS

A25

K35 J34 J33

(1) If PCIe Graphics is not implemented,

G35

TX/RX pairs can be left as No Connect.

G32

(2) PEG I or R COMP or RBIAS always keep whether PEG used or not.

F34 F31 D35 E33 C33 D32 B32 C31

eDP_AUX# _C

B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32

eDP_HPD#

C30

eDP_AUX_ C

A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29

eDP_CTX_ LRX_C_N1

D27

eDP_CTX_ LRX_C_N0

C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28

eDP_CTX_ LRX_C_P1

C27

eDP_CTX_ LRX_C_P0

C25

R801

1 2

R802

1 2

1 2 1 2

49D9R2F -GP

750R2F-G P

C802 SCD1 U10V2KX-4GPC802 SCD1 U10V2KX-4GP

C803 SCD1 U10V2KX-4GPC803 SCD1 U10V2KX-4GP

C804 SCD1 U10V2KX-4GPC804 SCD1 U10V2KX-4GP C805 SCD1 U10V2KX-4GPC805 SCD1 U10V2KX-4GP

C801 SCD1 U10V2KX-4GPC801 SCD1 U10V2KX-4GP C806 SCD1 U10V2KX-4GPC806 SCD1 U10V2KX-4GP

eDP_AUX# 54

eDP_AUX 54

eDP_CTX_ LRX_N1 eDP_CTX_ LRX_N0

eDP_CTX_ LRX_P1 eDP_CTX_ LRX_P0

+1.05V_V TT

12

R803

R803 7K5R2F-1 -GP

7K5R2F-1 -GP

Q801

Q801 2N7002A -7-GP

2N7002A -7-GP

eDP_LCD_ HPD

G

12

R804

S D

R804 110KR2F -GP

110KR2F -GP

R804 close to eDP Panel Connector

eDP_CTX_ LRX_N1 54 eDP_CTX_ LRX_N0 54

eDP_CTX_ LRX_P1 54 eDP_CTX_ LRX_P0 54

eDP_LCD_ HPD 54

CAPs close to eDP Panel Connector

A A

http://sualaptop365.edu.vn

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU - PCIE/DMI/FDI (1/7)

Size Document N umber Rev

A3

Date: Sheet of

CPU - PCIE/DMI/FDI (1/7)

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

8 82Thursday, October 2 9, 2009

X01

SSID = CPU

www.rosefix.com

+1.05V_V TT

D D

Place near U380 1

C C

Processor Pullups

1 2

R903 49D9R2F -GPR903 49D9R2F -GP

1 2

R906 49D9R2F -GPR906 49D9R2F -GP

1 2

DY

R908 68R2-GP

+3.3V_RU N

12

R912

8K2R2J-3 -GP

CPU_CAT ERR#38

12

H_CATER R#

H_PROCH OT#

H_CPURS T#

+1.05V_V TT

12

R913

R913 2K2R2J-2 -GP

2K2R2J-2 -GP

1.05V_VT T_Q901

Q901

H_CATER R#

312

MMBT390 4-7-F-GP

C901

C901 SCD1U10 V2KX-4GP

SCD1U10 V2KX-4GP

H_PW RGD25,5 8

DRAM_PW ROK22

H_VTTPW RGD52

PLTRST1 #21,58

Processor Compensation Signals

1 2

R902 20R2F-GPR902 20R2F-GP

1 2

R904 20R2F-GPR904 20R2F-GP

1 2

R905 49D9R2F -GPR905 49D9R2F -GP

1 2

R907 49D9R2F -GPR907 49D9R2F -GP

X01.09/0819

1 2

R917

R917 0R2J-2-GP

0R2J-2-GP

H_SKTOC C#37

H_PECI2 5

H_PROCH OT#47

H_THERM TRIP#25,39

H_CPURS T#58

H_PM_SYNC22

1 2

R919 0R2J-2-GPR919 0R2J-2 -GP

1 2

R921

R921 1K5R2F-2 -GP

1K5R2F-2 -GP

5

12

R924

R924 750R2F-G P

750R2F-G P

4

H_COMP3

H_COMP2

H_COMP1

H_COMP0

H_SKTOC C#

H_CATER R#

H_PECI

H_PROCH OT#

H_THERM TRIP#

H_CPURS T#

VCCPW RGOOD

VCCPW RGOOD_0

DRAM_PW ROK

H_VTTPW RGD

H_PW RGD_XDP

PLT_RST #_R

AT23

AT24

G16

AT26

AH24

AK14

AT15

AN26

AK15

AP26

AL15

AN14

AN27

AK13

AM15

AM26

AL14

CPU1B

COMP3

COMP2

COMP1

COMP0

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#

PM_SYNC

VCCPWRGOOD_1

VCCPWRGOOD_0

SM_DRAMPWROK

VTTPWRGOOD

TAPPWRGOOD

RSTIN#

3

2 OF 9

BCLK_CP U_P_R

A16

BCLK

MISC

CLOCKS

AUBURNDALE

THERMAL PWR MANAGEMENT

DDR3

MISC

DDR3

MISC

JTAG & BPM

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

PM_EXT_TS0# PM_EXT_TS1#

PRDY#

PREQ#

TCK TMS

TRST#

TDO

TDI_M

TDO_M

DBR#

BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# BPM6# BPM7#

TDI

B16

AR30 AT30

E16 D16

A18 A17

F6

AL1 AM1 AN1

AN15 AP15

AT28 AP27

AN28 AP28 AT27

AT29 AR27 AR29 AP29

AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

BCLK_CP U_N_R

BCLK_ITP_ P_R BCLK_ITP_ N_R

PEG_CLK _R PEG_CLK #_R

DPLL_RE F_SSCLK_R DPLL_RE F_SSCLK#_R

SM_DRAM RST#

SM_RCOM P_0 SM_RCOM P_1 SM_RCOM P_2

PM_EXT_ TS#

XDP_PRD Y# XDP_PRE Q#

XDP_TCL K XDP_TMS XDP_TRS T#

XDP_TDI_R XDP_TDO _R XDP_TDI_M XDP_TDO _M

H_DBR#_ R

XDP_OBS 0 XDP_OBS 1 XDP_OBS 2 XDP_OBS 3 XDP_OBS 4 XDP_OBS 5 XDP_OBS 6 XDP_OBS 7

RN903

1 2 3

SRN0J-6-G P

XDP_PRD Y# 5 8 XDP_PRE Q# 58

XDP_TCL K 5 8 XDP_TMS 58 XDP_TRS T# 5 8

XDP_OBS 0 58 XDP_OBS 1 58 XDP_OBS 2 58 XDP_OBS 3 58 XDP_OBS 4 58 XDP_OBS 5 58 XDP_OBS 6 58 XDP_OBS 7 58H_PW RGD_XDP58

2

X01-43

4

+1.05V_V TT

R914 10KR2J-3 -GPR914 10KR2J-3 -GP

R918 0R2J-2-GPR918 0R2J-2-GP

12

1 2

BCLK_CP U_P_R 25 BCLK_CP U_N_R 25

BCLK_ITP_ P 58 BCLK_ITP_ N 5 8

PEG_CLK _R 23 PEG_CLK #_R 2 3

DPLL_RE F_SSCLK_R 2 3 DPLL_RE F_SSCLK#_R 23

S D

12

R939

R939 100KR2J -1-GP

100KR2J -1-GP

DY

XDP_DBR ESET# 22,38 ,58

DDR_HVR EF_RST_GATE 37

G

R934 1KR2J-1-G PR934 1KR2J-1-G P

Q902

Q902 2N7002A -7-GP

2N7002A -7-GP

1 2

DY

R935 0R2J-2-GP

DDR3 Compensation Signals

SM_RCOM P_0

SM_RCOM P_1

SM_RCOM P_2

XDP_TMS

XDP_TDI_R

XDP_PRE Q#

XDP_TCL K

1

+1.5V_SU S

12

DDR3_DR AMRST# 18,19

X01.09/0917

1 2

R909 100R2F-L 1-GP-UR9 09 100R2F-L 1-GP-U

1 2

R910 24D9R2F -L-GPR910 24D9R2F -L-GP

1 2

R911 130R2F-1 -GPR911 130R2F-1 -GP

+1.05V_V TT

1 2

DY

R922 51R2J-2-G P

1 2

DY

R923 51R2J-2-G P

1 2

DY

R925 51R2J-2-G P

1 2

DY

R926 51R2J-2-G P

B B

+3.3V_SU S

VCC

5

4

Y

+3.3V_AL W_PCH

DRAM_PW ROK_R

R938

0R2J-2-GP

12

DY

R936

R936 1K5R2F-2 -GP

1K5R2F-2 -GP

1 2

12

R937

R937 750R2F-G P

750R2F-G P

DRAM_PW ROK

X01.09/0917

X01-4

U901

SIO_SLP_S 3#22,35,38,5 0

RUNPW ROK37,38,58

1 2

R915 0R2J-2-GPR915 0R2J-2-GP

1 2

R920 0R2J-2-GPR920 0R2J-2-GP

RUNPW ROK_C

A A

1

B

2

A

3

GND

74LVC1G 08GW-1-GP

http://sualaptop365.edu.vn

JTAG MAPPING

XDP_TDI_R

XDP_TDO _M

XDP_TDI_M

XDP_TDO _R

Scan Chain (Default)

12

CPU Only

GMCH Only

1 2

R929 0R2J-2-GPR929 0R2J-2-GP

1 2

DY

R930 0R2J-2-GP

R901

R901 0R2J-2-GP

0R2J-2-GP

1 2

DY

R931 0R2J-2-GP

1 2

R932 0R2J-2-GPR932 0R2J-2-GP

Stuff --> R929, R901, R932 No Stuff --> R930, R931 Stuff --> R929, R930 No Stuff --> R901, R931, R932 Stuff --> R931, R932 No Stuff --> R929, R930, R901

Title

CPU Thermal/Clock/PM (2/7)

Size Document N umber Rev

A3

Date: Sheet of

CPU Thermal/Clock/PM (2/7)

XDP_TDI

XDP_TDO

Fonseca UMA

XDP_TDI 58

XDP_TDO 58

XDP_TRS T#

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

9 82Thursday, October 2 9, 2009

12

R933

R933 51R2J-2-G P

51R2J-2-G P

X01

5

SSID = CPU

4

3 OF 9

www.rosefix.com

CPU1C

3 OF 9

3

CPU1D

2

4 OF 9

1

W8

SB_CK0

AA6

SA_CK0

AA7

SA_CK0#

M_A_DQ[6 3..0]18

D D

C C

B B

M_A_BS018 M_A_BS118 M_A_BS218

M_A_CAS #18 M_A_RAS #18 M_A_W E#18

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ1 0 M_A_DQ1 1 M_A_DQ1 2 M_A_DQ1 3 M_A_DQ1 4 M_A_DQ1 5 M_A_DQ1 6 M_A_DQ1 7 M_A_DQ1 8 M_A_DQ1 9 M_A_DQ2 0 M_A_DQ2 1 M_A_DQ2 2 M_A_DQ2 3 M_A_DQ2 4 M_A_DQ2 5 M_A_DQ2 6 M_A_DQ2 7 M_A_DQ2 8 M_A_DQ2 9 M_A_DQ3 0 M_A_DQ3 1 M_A_DQ3 2 M_A_DQ3 3 M_A_DQ3 4 M_A_DQ3 5 M_A_DQ3 6 M_A_DQ3 7 M_A_DQ3 8 M_A_DQ3 9 M_A_DQ4 0 M_A_DQ4 1 M_A_DQ4 2 M_A_DQ4 3 M_A_DQ4 4 M_A_DQ4 5 M_A_DQ4 6 M_A_DQ4 7 M_A_DQ4 8 M_A_DQ4 9 M_A_DQ5 0 M_A_DQ5 1 M_A_DQ5 2 M_A_DQ5 3 M_A_DQ5 4 M_A_DQ5 5 M_A_DQ5 6 M_A_DQ5 7 M_A_DQ5 8 M_A_DQ5 9 M_A_DQ6 0 M_A_DQ6 1 M_A_DQ6 2 M_A_DQ6 3

A10

C10

B10

D10

E10

F10

H10

G10

AH5 AF5 AK6 AK7 AF6 AG5

AJ7 AJ6

AJ10

AJ9

AL10

AK12

AK8

AL7

AK11

AL8

AN8 AM10 AR11

AL11

AM9

AN9

AT11 AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14 AP14

AC3 AB2

AE1 AB3 AE9

SA_DQ0 SA_DQ1

C7

SA_DQ2

A7

SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6

A8

SA_DQ7

D8

SA_DQ8 SA_DQ9

E6

SA_DQ10

F7

SA_DQ11

E9

SA_DQ12

B7

SA_DQ13

E7

SA_DQ14

C6

SA_DQ15 SA_DQ16

G8

SA_DQ17

K7

SA_DQ18

J8

SA_DQ19

G7

SA_DQ20 SA_DQ21

J7

SA_DQ22

J10

SA_DQ23

L7

SA_DQ24

M6

SA_DQ25

M8

SA_DQ26

L9

SA_DQ27

L6

SA_DQ28

K8

SA_DQ29

N8

SA_DQ30

P9

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1

U7

SA_BS2

SA_CAS# SA_RAS# SA_WE#

AUBURNDALE

DDR SYSTEM MEMORY A

SA_CKE0

SA_CK1 SA_CK1# SA_CKE1

SA_CS0# SA_CS1#

SA_ODT0 SA_ODT1

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS #0M_A _DQS#0 M_A_DQS #1 M_A_DQS #2 M_A_DQS #3 M_A_DQS #4 M_A_DQS #5 M_A_DQS #6 M_A_DQS #7

M_A_DQS 0 M_A_DQS 1 M_A_DQS 2 M_A_DQS 3 M_A_DQS 4 M_A_DQS 5 M_A_DQS 6 M_A_DQS 7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_CLK_D DR0 18 M_CLK_D DR#0 18 M_CKE0 18

M_CLK_D DR1 18 M_CLK_D DR#1 18 M_CKE1 18

M_CS#0 18 M_CS#1 18

M_ODT0 1 8 M_ODT1 1 8

M_A_DM[7 ..0] 18

M_A_DQS #[7..0] 18

M_A_DQS [7..0] 18

M_A_A[15 ..0] 18

M_B_DQ[6 3..0]19

M_B_BS019 M_B_BS119 M_B_BS219

M_B_CAS #19 M_B_RAS #19 M_B_W E#19

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ1 0 M_B_DQ1 1 M_B_DQ1 2 M_B_DQ1 3 M_B_DQ1 4 M_B_DQ1 5 M_B_DQ1 6 M_B_DQ1 7 M_B_DQ1 8 M_B_DQ1 9 M_B_DQ2 0 M_B_DQ2 1 M_B_DQ2 2 M_B_DQ2 3 M_B_DQ2 4 M_B_DQ2 5 M_B_DQ2 6 M_B_DQ2 7 M_B_DQ2 8 M_B_DQ2 9 M_B_DQ3 0 M_B_DQ3 1 M_B_DQ3 2 M_B_DQ3 3 M_B_DQ3 4 M_B_DQ3 5 M_B_DQ3 6 M_B_DQ3 7 M_B_DQ3 8 M_B_DQ3 9 M_B_DQ4 0 M_B_DQ4 1 M_B_DQ4 2 M_B_DQ4 3 M_B_DQ4 4 M_B_DQ4 5 M_B_DQ4 6 M_B_DQ4 7 M_B_DQ4 8 M_B_DQ4 9 M_B_DQ5 0 M_B_DQ5 1 M_B_DQ5 2 M_B_DQ5 3 M_B_DQ5 4 M_B_DQ5 5 M_B_DQ5 6 M_B_DQ5 7 M_B_DQ5 8 M_B_DQ5 9 M_B_DQ6 0 M_B_DQ6 1 M_B_DQ6 2 M_B_DQ6 3

AF3 AG1

AK1 AG4 AG3

AH4 AK3

AK4 AM6 AN2

AK5

AK2 AM4 AM3

AP3 AN5

AT4 AN6 AN4 AN3

AT5

AT6 AN7

AP6

AP8

AT9

AT7

AP9

AR10

AT10

AB1

AC5

AC6

B5

SB_DQ0

A5

SB_DQ1

C3

SB_DQ2

B3

SB_DQ3

E4

SB_DQ4

A6

SB_DQ5

A4

SB_DQ6

C4

SB_DQ7

D1

SB_DQ8

D2

SB_DQ9

F2

SB_DQ10

F1

SB_DQ11

C2

SB_DQ12

F5

SB_DQ13

F3

SB_DQ14

G4

SB_DQ15

H6

SB_DQ16

G2

SB_DQ17

J6

SB_DQ18

J3

SB_DQ19

G1

SB_DQ20

G5

SB_DQ21

J2

SB_DQ22

J1

SB_DQ23

J5

SB_DQ24

K2

SB_DQ25

L3

SB_DQ26

M1

SB_DQ27

K5

SB_DQ28

K4

SB_DQ29

M4

SB_DQ30

N5

SB_DQ31 SB_DQ32 SB_DQ33

AJ3

SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37

AJ4

SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0

W5

SB_BS1

R7

SB_BS2

SB_CAS#

Y7

SB_RAS# SB_WE#

AUBURNDALE

DDR SYSTEM MEMORY - B

SB_CK0# SB_CKE0

SB_CK1 SB_CK1# SB_CKE1

SB_CS0# SB_CS1#

SB_ODT0 SB_ODT1

SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7

SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0

SB_MA1

SB_MA2

SB_MA3

SB_MA4

SB_MA5

SB_MA6

SB_MA7

SB_MA8

SB_MA9

SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS #0 M_B_DQS #1 M_B_DQS #2 M_B_DQS #3 M_B_DQS #4 M_B_DQS #5 M_B_DQS #6 M_B_DQS #7

M_B_DQS 0 M_B_DQS 1 M_B_DQS 2 M_B_DQS 3 M_B_DQS 4 M_B_DQS 5 M_B_DQS 6 M_B_DQS 7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8

M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_CLK_D DR2 19 M_CLK_D DR#2 19 M_CKE2 19

M_CLK_D DR3 19 M_CLK_D DR#3 19 M_CKE3 19

M_CS#2 19 M_CS#3 19

M_ODT2 1 9 M_ODT3 1 9

M_B_DM[7 ..0] 19

M_B_DQS #[7..0] 19

M_B_DQS [7..0] 19

M_B_A[15 ..0] 19

A A

5

http://sualaptop365.edu.vn

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU - DDR (3/7)

Size Document N umber Rev

A3

Date: Sheet of

CPU - DDR (3/7)

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

1

10 82Thursday, October 2 9, 2009

X01

5

4

3

2

1

SSID = CPU

D D

C C

CFG0

DY

CFG3

B B

CFG4

DY

X01-47

www.rosefix.com

SO-DIMM VREFDQ (M3) Circuit for Clarksfield Processor

12

R1102

R1102 3K01R2F-3-GP

3K01R2F-3-GP

12

R1105

R1105 3K01R2F-3-GP

3K01R2F-3-GP

12

R1109

R1109 3K3R2J-3-GP

3K3R2J-3-GP

PCI-Express Configuration Select

1:Single PEG

CFG0

0:Bifurcation enabled (Clarkfiled only)

CFG3 - PCI-Express Static Lane Reversal

1 :Normal Operation

CFG3

0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

CFG4 - Display Port Presence

1:Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port

TP1115TP1115 TP1116TP1116

TP1101TP1101 TP1102TP1102

TP1103TP1103 TP1104TP1104

TP1105TP1105 TP1106TP1106 TP1107TP1107 TP1108TP1108 TP1109TP1109 TP1110TP1110 TP1111TP1111 TP1112TP1112 TP1113TP1113 TP1114TP1114

VREF_CH_A_DIMM

1

VREF_CH_B_DIMM

1

1 1

1 1 1 1 1 1 1 1 1 1

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

AP25

AL25 AL24 AL22 AJ33

AG9 M27

G25 G17

AM30 AM28 AP31

AL32

AL30 AM31 AN29 AM32 AK32 AK31 AK28

AJ28 AN30 AN32

AJ32

AJ29

AJ30 AK30

AC9 AB9

L28 J17

H17

E31 E30

H16

B19 A19

A20 B20

U9 T9

J29 J28

CPU1E

RSVD#AP25 RSVD#AL25 RSVD#AL24 RSVD#AL22 RSVD#AJ33 RSVD#AG9 RSVD#M27 RSVD#L28 SA_DIMM_VREF# SB_DIMM_VREF# RSVD#G25 RSVD#G17 RSVD#E31 RSVD#E30

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 RSVD_TP#H16

RSVD#B19 RSVD#A19

RSVD#A20 RSVD#B20

RSVD#U9 RSVD#T9

RSVD#AC9 RSVD#AB9

RSVD#J29 RSVD#J28

AUBURNDALE

RESERVED

5 OF 9

RSVD#AJ13 RSVD#AJ12

RSVD#AH25 RSVD#AK26

RSVD#AL26

RSVD_NCTF#AR2

RSVD#AJ26 RSVD#AJ27

RSVD#AL28 RSVD#AL29 RSVD#AP30 RSVD#AP32 RSVD#AL27 RSVD#AT31 RSVD#AT32 RSVD#AP33 RSVD#AR33

RSVD#AR32

RSVD_TP#E15 RSVD_TP#F15

RSVD#D15

RSVD#C15 RSVD#AJ15 RSVD#AH15

RSVD_TP#AA5 RSVD_TP#AA4

RSVD_TP#R8 RSVD_TP#AD3 RSVD_TP#AD2 RSVD_TP#AA2 RSVD_TP#AA1

RSVD_TP#R9 RSVD_TP#AG7 RSVD_TP#AE3

RSVD_TP#V4

RSVD_TP#V5

RSVD_TP#N2 RSVD_TP#AD5 RSVD_TP#AD7

RSVD_TP#W3 RSVD_TP#W2

RSVD_TP#N3 RSVD_TP#AE5 RSVD_TP#AD9

CPU Piin AJ13 and AJ12: Core voltage sense line. Via from PGA pad to the back of the MB and provide test point.

H_RSVD32

AJ13

H_RSVD33

AJ12

AH25

H_RSVD35

AK26

H_RSVD36

AL26 AR2

AJ26 AJ27

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33

AR32

E15 F15 A2

KEY

D15 C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

RSVD_VSS

AP34

VSS

1 1

1

VSS (AP34) can be left NC is CRB implementation; EDS/DG recommendation to GND.

1 2

R1117 0R2J-2-GPR1117 0R2J-2-GP

Do not route any additional trace.

TP1118TP1118 TP1117TP1117

TP1119TP1119

TP1120TP1120

CFG7

A A

12

DY

R1103

R1103 3K01R2F-3-GP

3K01R2F-3-GP

5

CFG7(Reserved) - Temporarily used for early Clarksfield sampl es.

CFG7 Clarksfield (only for early samples pre-ES1) -

Connect to GND with 3.01K Ohm/5% resistor.

Note: Only temporary for early CFD sample (rPGA/BGA) [For details please refer to the WW33 MoW and sightin g report]. For a common M/B design (for AUB and CFD), the pull-down resistor shouble be used. Does not impact AUB functionality.

http://sualaptop365.edu.vn

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

3

2

Date: Sheet of

CPU - Reserve (4/7)

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

1

X01

11 8 2Thursday, October 29, 2009

X01

5

SSID = CPU

www.rosefix.com

PROCESSOR CORE POWER

+VCC_CORE

D D

C1210

12

SC22U6D3V5MX-2GP

C1212

C1211

12

SC22U6D3V5MX-2GP

C1213

12

SC22U6D3V5MX-2GP

X01-37

C1221

C1222

C1220

12

SC22U6D3V5MX-2GP

C1222

C1223

12

SC22U6D3V5MX-2GP

14ONLY

C1223

12

SC22U6D3V5MX-2GP

X01-37

C1227

C1226

12

C C

SC10U6D3V5MX-3GP

SC10U10V5KX-2GP

DY

C1229

C1228

12

SC10U10V5KX-2GP

X01-37

C1236

C1237

12

C1201

SC10U10V5KX-2GP

C1243

12

SC22U6D3V5MX-2GP

DY

B B

12

C1238

SC10U10V5KX-2GP

C1244

12

SC22U6D3V5MX-2GP

DY

C1238

SC10U10V5KX-2GP

C1246

C1245

12

SC22U6D3V5MX-2GP

DY

SC22U6D3V5MX-2GP

SC10U10V5KX-2GP

SC22U6D3V5MX-2GP

C1214

12

C1224

12

SC22U6D3V5MX-2GP

15ONLY

C1230

12

14/15

12

C1239

X01-37

12

C1215

SC22U6D3V5MX-2GP

SC10U10V5KX-2GP

C1225

12

14ONLY

SC10U10V5KX-2GP

C1231

12

SC10U6D3V5MX-3GP

SC10U10V5KX-2GP

C1240

12

SC10U10V5KX-2GP

14/15

SC22U6D3V5MX-2GP

C1232

12

SC10U10V5KX-2GP

C1241

12

SC10U6D3V5MX-3GP

14ONLY

DY

C1233

C1242

4

CPU1F

+VCC_CORE

AG35

VCC

AG34

VCC

AG33

48A

SC10U10V5KX-2GP

AG32 AG31 AG30 AG29 AG28 AG27 AG26

AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27

AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

POWER

AUBURNDALE

1.1V RAIL POWER

CPU CORE SUPPLY

CPU VIDS

SENSE LINES

3

6 OF 9

VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0

VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0

PSI#

VID0 VID1 VID2 VID3 VID4 VID5 VID6

PROC_DPRSLPVR

VTT_SELECT

ISENSE

VCC_SENSE VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

X01-37

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

G15

Arrandale drives this pin High for 1.05V Clarksfield drives this pin Low for 1.1V

AN35

AJ34 AJ35

B15 A15

SC10U10V5KX-2GP

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6

H_VTTVID1

CPU_IMON_R

VCC_SENSE_R VSS_SENSE_R

VTT_SENSE_R TP_VSS_SENSE_VTT

14/15

15ONLY

12

C1203

C1202

SC10U10V5KX-3GP

X01-37

PSI# 47

H_VID[6..0] 47

PM_DPRSLPVR 47

1

TP1201TP1201

R1205 0R2J-2-GPR1205 0R2J-2-GP

R1206

0R2J-2-GP

1 2

DY

1

12

C1234

TP1202TP1202

C1204

1 2

15ONLY

12

C1205

SC10U10V5KX-3GP

14/15

12

C1235

C1235 SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

VTT_SENSE 52

X01-24

SC22U6D3V5MX-2GP

12

C1217

12

2

C1206

SC10U10V5KX-2GP

12

SC10U10V5KX-3GP

14ONLY

12

C1218

SC10U10V5KX-2GP

CPU_IMON 39,47

12

R1207

DY

14/15

C1216

SC10U10V5KX-3GP

12

C1219

+1.05V_VTT

DY

27D4R2F-L1-GP

X01-37

12

C1207

SC10U10V5KX-2GP

12

R1208

27D4R2F-L1-GP

14/15

12

SC10U10V5KX-3GP

+1.05V_VTT

C1209

C1208

SC10U10V5KX-3GP

The decoupling capacitors, filter recommendations and sense resistors on the CPU/PCH Rails are specific to the CRB Implementation. Customers need to follow the recommendations in the Calpella Platform Design Guide.

Please note that The VTT Rail values are Arrandale for VTT=1.05V Clarksfield for VTT=1.1V

+VCC_CORE

12

R1202

R1202 100R2F-L1-GP-U

100R2F-L1-GP-U

R1203 0R2J-2-GPR1203 0R2J-2-GP R1201 0R2J-2-GPR1201 0R2J-2-GP

Place near PU4701

12

R1204

R1204 100R2F-L1-GP-U

100R2F-L1-GP-U

DY

12

SC10U10V5KX-3GP

X01-16

1 2 1 2

+1.05V_VTT

1

VCC_SENSE 47 VSS_SENSE 4 7

VSS_SENSE_R 47

A A

5

http://sualaptop365.edu.vn

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Custom

Date: Sheet of

CPU - VCC_CORE (5/7)

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

1

12 82Thursday, October 29, 2009

X01

5

SSID = CPU

4

www.rosefix.com

3

2

1

+CPU_GF XCORE

D D

C C

15A

C1302

DY

C1305

C1304

C1303

12

SC22U6D3V5MX-2GP

DY

12

SC22U6D3V5MX-2GP

DY

C1306

C1307

12

SC22U6D3V5MX-2GP

DY

C1307

12

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

C1301

C1308

12

SC10U6D3V3MX-GP

X01-37

+1.05V_V TT

14/15

12

C1317

C1316

SC10U10 V5KX-2GP

+1.05V_V TT

B B

C1320

18A

SC22U6D3V5MX-2GP

14/15

C1322

C1321

12

SC10U10V5KX-2GP

C1317 SC22U6D 3V5MX-2GP

SC22U6D 3V5MX-2GP

X01-37

14/15

C1323

12

SC10U10V5KX-2GP

AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16

AL21 AL19 AL18

AL16 AK21 AK19 AK18 AK16

AJ21

AJ19

AJ18

AJ16 AH21 AH19 AH18 AH16

J24 J23

H25

K26

J27 J26

J25 H27 G28 G27 G26 F26 E26 E25

CPU1G

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36

VTT1 VTT1 VTT1

VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1

SENSE

AUBURNDALE

GRAPHICS

GRAPHICS VIDs

FDI PEG & DMI

POWER

VAXG_SENSE

VSSAXG_SENSE

LINES

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

DDR3 - 1.5V RAILS

1.1V1.8V

VCCPLL VCCPLL VCCPLL

7 OF 9

GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID5 GFX_VID6

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VTT1 VTT1 VTT1 VTT1

VTT1 VTT1 VTT1 VTT1 VTT1 VTT1

VTT1 VTT1 VTT1

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

AR25 AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID5 GFX_VID6

GFX_DPR SLPVR

12

C1309

SC1U10V2KX-1GP

C1318

SC22U6D 3V5MX-2GP

SC10U10 V5KX-2GP

C1318

1.35A

VCC_AXG _SENSE 53 VSS_AXG _SENSE 53

GFX_VID0 53 GFX_VID1 53 GFX_VID2 53 GFX_VID3 53 GFX_VID4 53 GFX_VID5 53 GFX_VID6 53

GFX_VR_ EN 53

1

TP1301TP1301

GFX_IMON 53

X01-37

+1.5V_RU N

3A

12

C1310

C1311

SC1U10V2KX-1GP

12

C1319

C1319 SC22U6D 3V5MX-2GP

SC22U6D 3V5MX-2GP

C1325

C1324

12

SC10U10 V5KX-2GP

12

C1312

SC1U10V2KX-1GP

12

C1313

C1314

SC1U10V2KX-1GP

SC10U10V5KX-2GP

+1.05V_V TT

12

C1315

SC22U6D3V5MX-2GP

TC1304

TC1304 SE330U2 VDM-L-GP

SE330U2 VDM-L-GP

X01-37

+1.8V_RU N

12

C1326

12

C1327

SC1U25V5KX-1GP

12

C1328

C1329

SC1U25V5KX-1GP

C1329

SC4D7U6D3V3KX-GP

SC2D2U10V5KX-2GP

12

C1330

C1330 SC22U6D 3V5MX-2GP

SC22U6D 3V5MX-2GP

Please note that the VTT Rail Values Arrandale for VTT=1.05V Clarksfield for VTT=1.1V

A A

5

http://sualaptop365.edu.vn

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU - GFXCORE (6/7)

Size Document N umber Rev

A3

Date: Sheet of

CPU - GFXCORE (6/7)

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

1

13 82Thursday, October 2 9, 2009

X01

5

4

3

2

1

SSID = CPU

D D

C C

B B

www.rosefix.com

AT20

AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12

AR9 AR6

AR3 AP20 AP17 AP13 AP10

AP7

AP4

AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AM8 AM5

AM2 AL34 AL31 AL23 AL20 AL17 AL12

AK29 AK27 AK25 AK20 AK17

AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AH9 AH6 AH3

AG10

AF8 AF4 AF2

AE35

AL9 AL6 AL3

AJ8 AJ5 AJ2

CPU1H

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

AUBURNDALE

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

K27

H35 H32 H28 H26 H24 H22 H18 H15 H13 H11

G34 G31 G20

F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11

D33 D30 D26

C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11

A29 A27 A23

9 OF 9

CPU1I

VSS

K9

VSS

K6

VSS

K3

VSS

J32

VSS

J30

VSS

J21

VSS

J19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H8

VSS

H5

VSS

H2

VSS VSS VSS VSS

G9

VSS

G6

VSS

G3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E8

VSS

E5

VSS

E2

VSS VSS VSS VSS

D9

VSS

D6

VSS

D3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

B8

VSS

B6

VSS

B4

VSS VSS VSS VSS

A9

VSS

NCTF TEST PIN:

A35,AT1,AT35,B1,A3,A33,A34,AP1,AP35,

NCTF TEST PIN:

A35,AT1,AT35,B1,A3,A33,A34,AP1,AP35,

AUBURNDALE

VSS

AR1,AR35,AT2,AT3,AT33,AT34,B35,C1,C35

9 OF 9

VSS_NCTF#AR34

VSS_NCTF#B34

VSS_NCTF#B2

VSS_NCTF#B1 VSS_NCTF#A35 VSS_NCTF#AT1

VSS_NCTF#AT35 RSVD_NCTF#AT33 RSVD_NCTF#AT34 RSVD_NCTF#AP35 RSVD_NCTF#AR35

RSVD_NCTF#AT3 RSVD_NCTF#AR1 RSVD_NCTF#AP1 RSVD_NCTF#AT2

RSVD_NCTF#C1

RSVD_NCTF#A3

RSVD_NCTF#C35

RSVD_NCTF#B35 RSVD_NCTF#A34 RSVD_NCTF#A33

AR34 B34 B2

B1 A35 AT1 AT35 AT33 AT34 AP35 AR35 AT3 AR1 AP1 AT2 C1 A3 C35 B35 A34 A33

A35

B35AT35 AR35

AT34

A34

2X3X

NCTF

CPU1, Board Top View

4X

AT2

AT1

AR1

TP_MCP_ VSS_NCTF11 TP_MCP_ VSS_NCTF21 TP_MCP_ VSS_NCTF41 TP_MCP_ VSS_NCTF31

TP_MCP_ VSS_NCTF33

TP_MCP_ VSS_NCTF32

TP_MCP_ VSS_NCTF43

TP_MCP_ VSS_NCTF42 TP_MCP_ VSS_NCTF12 TP_MCP_ VSS_NCTF13

TP_MCP_ VSS_NCTF23 TP_MCP_ VSS_NCTF22

All NCTF pins should be Test Points and should be routed as trace.

1X

C1 B1

1 1 1 1

1

1 1 1

1 1

TP1401TP1401 TP1404TP1404 TP1410TP1410 TP1407TP1407

TP1409TP1409

TP1408TP1408

TP1412TP1412

TP1411TP1411 TP1402TP1402 TP1403TP1403

TP1406TP1406 TP1405TP1405

A3

A A

5

http://sualaptop365.edu.vn

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU - VSS (7/7)

Size Document N umber Rev

A3

Date: Sheet of

CPU - VSS (7/7)

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

1

14 82Thursday, October 2 9, 2009

X01

5

4

3

2

1

www.rosefix.com

D D

C C

(Blank)

B B

A A

http://sualaptop365.edu.vn

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserve

Fonseca UMA

1

15 82Thursday, October 29, 2009

X01

5

4

3

2

1

www.rosefix.com

D D

C C

(Blank)

B B

A A

http://sualaptop365.edu.vn

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserve

Fonseca UMA

1

16 82Thursday, October 29, 2009

X01

5

4

3

2

1

www.rosefix.com

D D

C C

(Blank)

B B

A A

http://sualaptop365.edu.vn

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserve

Fonseca UMA

1

17 82Thursday, October 29, 2009

X01

5

4

3

2

1

SSID = Memory

www.rosefix.com

SO-DIMMA

DM1

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6

M_VREF_CA_DIMM1 M_VREF_DQ_DIMM1

MA_VTT

4

M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

D D

M_A_BS210

M_A_BS010 M_A_BS110

C C

+V_DDR_MCH_REF

1 2

R1807

R1807 0R3J-0-U-GP

0R3J-0-U-GP

B B

A A

+V_DDR_MCH_REF

Place these caps close to VTT1 and VTT2.

R1808

R1808 0R3J-0-U-GP

0R3J-0-U-GP

C1811

SCD1U10V2KX-5GP

1 2

C1820

SCD1U10V2KX-5GP

+0.75V_DDR_VTT

12

R1809

R1809 0R3J-0-U-GP

0R3J-0-U-GP

12

C1823

C1824

SC1U10V2KX-1GP

5

http://sualaptop365.edu.vn

12

C1825

12

MA_VTT

SC1U10V2KX-1GP

12

C1826

M_VREF_CA_DIMM1

12

C1812

SC2D2U16V3KX-GP

M_VREF_DQ_DIMM1

12

C1821

C1821 SC2D2U16V3KX-GP

SC2D2U16V3KX-GP

Place between DM1 and DM2.

+0.75V_DDR_VTT

12

SC1U10V2KX-1GP

M_A_DQ[63..0]10

12

C1822

C1822 SC10U10V5KX-2GP

SC10U10V5KX-2GP

M_ODT010 M_ODT110

DDR3_DRAMRST#9,19

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

Reverse Type

DDR3-204P-42-GP

62.10017.N61

H = 9.2mm

RAS#

CAS#

CKE0 CKE1

EVENT#

VDDSPD

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1 NP2

WE#

CS0# CS1#

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

SCL

SA0 SA1

NC#1 NC#2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

M_A_DM0

11

M_A_DM1

28

M_A_DM2

46

M_A_DM3

63

M_A_DM4

136

M_A_DM5

153

M_A_DM6

170

M_A_DM7

187

SODIMM1_1_SMB_DATA_R

200

SODIMM1_1_SMB_CLK_R

202

198

199

SA0_DIMM1

197

SA1_DIMM1

201

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

M_A_RAS# 10 M_A_WE# 10 M_A_CAS# 10

M_CS#0 10 M_CS#1 10

M_CKE0 10 M_CKE1 10

M_CLK_DDR0 10 M_CLK_DDR#0 10

M_CLK_DDR1 10 M_CLK_DDR#1 10

R1804 0R2J-2-GPR1804 0R2J-2-GP R1805 0R2J-2-GPR1805 0R2J-2-GP

12

C1802

C1803

SC2D2U16V3KX-GP

SCD1U10V2KX-5GP

+1.5V_SUS

3

M_A_DM[7..0] 10

M_A_DQS#[7..0] 10

M_A_DQS[7..0] 10

M_A_A[15..0] 10

1 2 1 2

+3.3V_RUN

+1.5V_SUS

Layout Note: Place these Caps near SO-DIMMA.

2

X01-37

Near Memory +1.5V_SUS Plane

SA0_DIMM1

SA1_DIMM1

12

R1803

R1803 0R2J-2-GP

0R2J-2-GP

PCH_SMBDATA_MEM 19,23,40,58 PCH_SMBCLK_MEM 19,23,40,5 8

SODIMM A DECOUPLING

C1804

TC1801

14ONLY

C1805

SC10U6D3V3MX-GP

SE330U2D5VDM-2GP

12

C1813

SC10U6D3V3MX-GP

12

C1814

SCD1U16V2KX-3GP

1 2

C1827

1 2

C1828

1 2

C1829

1 2

C1830

Title

Size Document Number Rev

Date: Sheet of

+3.3V_RUN

12

R1802

R1802 10KR2J-3-GP

10KR2J-3-GP

DY

12

R1801

R1801 0R2J-2-GP

0R2J-2-GP

X01-37

C1807

C1806

SC10U6D3V3MX-GP

12

14/15

12

C1816

C1815

SCD1U16V2KX-3GP

SCD1U16V2ZY-2GP

Custom

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 0, SA1_DIM0 = 1 SO-DIMMA SPD Address is 0xA4 SO-DIMMA TS Address is 0x34

C1808

C1801

C1809

SC10U6D3V3MX-GP

C1817

SCD1U16V2KX-3GP

SC10U6D3V3MX-GP

12

SC1U10V2KX-1GP

+1.5V_RUN+1.5V_SUS

DDR III Socket - DM1

12

14/15

C1818

12

Near CPU +1.5V_RUN Plane

Fonseca UMA

DY

C1819

SC1U10V2KX-1GP

12

15ONLY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

12

C1810

SC10U6D3V3MX-GP

12

DY

X01-37

18 8 2Thursday, October 29, 2009

X01

5

SSID = Memory

www.rosefix.com

D D

M_B_BS210

M_B_BS010 M_B_BS110

C C

+V_DDR_MCH_REF

1 2

R1907

R1907 0R3J-0-U-GP

0R3J-0-U-GP

B B

A A

+V_DDR_MCH_REF

R1908

R1908 0R3J-0-U-GP

0R3J-0-U-GP

Place these caps close to VTT1 and VTT2.

5

1 2

http://sualaptop365.edu.vn

C1904

SCD1U10V2KX-5GP

C1913

SCD1U10V2KX-5GP

12

C1923

C1922

SC1U10V2KX-1GP

12

C1924

0R3J-0-U-GP

M_VREF_CA_DIMM2

12

C1905

C1905 SC2D2U16V3KX-GP

SC2D2U16V3KX-GP

M_VREF_DQ_DIMM2

12

C1914

C1914 SC2D2U16V3KX-GP

SC2D2U16V3KX-GP

+0.75V_DDR_VTT

R1909

12

C1925

SC1U10V2KX-1GP

12

DDR3_DRAMRST#9, 18

12

4

SO-DIMMB

DM2

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ[63..0]10

M_ODT210 M_ODT310

4

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_VREF_CA_DIMM2 M_VREF_DQ_DIMM2

MB_VTT

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

Reverse Type

DDR3-204P-48-GP

62.10017.P41

H = 5.2mm

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

WE#

NP1 NP2

CK0

CK1

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA SCL

SA0 SA1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

3

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

M_B_DM0

11

M_B_DM1

28

M_B_DM2

46

M_B_DM3

63

M_B_DM4

136

M_B_DM5

153

M_B_DM6

170

M_B_DM7

187

SODIMM2_1_SMB_DATA_R

200

SODIMM2_1_SMB_CLK_R

202

198

199

SA0_DIMM2

197

SA1_DIMM2

201

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

3

+1.5V_SUS

M_B_RAS# 10 M_B_WE# 10 M_B_CAS# 10

M_CS#2 10 M_CS#3 10

M_CKE2 10 M_CKE3 10

M_CLK_DDR2 10 M_CLK_DDR#2 10

M_CLK_DDR3 10 M_CLK_DDR#3 10

12

C1903

C1902

SCD1U10V2KX-5GP

R1905 0R2J-2-GPR1905 0R2J-2-GP

1 2

R1906 0R2J-2-GPR1906 0R2J-2-GP

1 2

SC2D2U16V3KX-GP

Layout Note: Place these Caps near SO-DIMMB.

X01-37

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

SO-DIMMB is placed farther from the Processor than SO-DIMMA

2

M_B_DM[7..0] 10

M_B_DQS#[7..0] 10

M_B_DQS[7..0] 10

M_B_A[15..0] 10

+3.3V_RUN

+1.5V_SUS

2

PCH_SMBDATA_MEM 18,23,40,58 PCH_SMBCLK_MEM 18,23,40,5 8

SODIMM B DECOUPLING

C1901

C1907

SC10U6D3V3MX-GP

12

C1917

C1918

SCD1U16V2KX-3GP

C1915

C1906

12

C1916

SCD1U16V2KX-3GP

1

+3.3V_RUN

12

R1902

R1902 10KR2J-3-GP

10KR2J-3-GP

SA1_DIMM2

SA0_DIMM2

12

R1903

R1903 0R2J-2-GP

0R2J-2-GP

C1908

C1909

SC10U6D3V3MX-GP

12

C1919

SC1U10V2KX-1GP

12

SCD1U16V2KX-3GP

Title

Size Document Number Rev

Custom

Date: Sheet of

12

R1904

R1904 0R2J-2-GP

0R2J-2-GP

DY

C1911

C1912

C1910

SC10U6D3V3MX-GP

12

DY

C1920

SC1U10V2KX-1GP

12

DDR III Socket - DM2

C1912

SC10U6D3V3MX-GP

DY

C1921

SC10U6D3V3MX-GP

12

SC1U10V2KX-1GP

12

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

1

12

19 8 2Thursday, October 29, 2009

X01

5

4

3

2

1

SSID = PCH

www.rosefix.com

4 OF 10

PCH1D

PANEL_B KEN_PCH38,54

D D

+3.3V_RU N

RN2002

1

4

2 3

SRN10KJ -5-GP

C C

B B

SRN10KJ -5-GP

RN2001

1 2 3

SRN2K2J -1-GP

M_BLUE75 M_GREEN75 M_RED75

4

ENVDD_P CH38,5 4

LCTLB_D ATA LCTLA_C LK

DDC1_DA TA DDC1_CL K

12

R2002

R2003

150R2F-1-GP

Place near PCH

R2001

R2001 100KR2J -1-GP

100KR2J -1-GP

12

R2004

150R2F-1-GP

LBKLT_C TL_PCH54

0.5% 1K ohm

TP2002TP2002 TP2003TP2003

TP2004TP2004 TP2001TP2001

TP2005TP2005

DDC1_CL K75 DDC1_DA TA7 5

PCH_HSYNC75 PCH_VSYNC75

12

R2005

LDDC_DA TA_PCH

1

LCTLA_C LK LCTLB_D ATA

LVDS_IBG

1

LVDS_VB G

1

LVD_VRE F

1

CRT_IREF

1KR2D-1-GP

LDDC_CL K_PCH

1

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CLK

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK-M-G P-NF

LVDS

Digital Display Interface

CRT

4 OF 10

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

BJ46 BG46

BJ48

No Connect if register is configured to disable DisplayPort*

BG48

BF45 BH45

DVI_B_DDC _CLK

T51

DVI_B_DDC _DATA

T53

DPB_DOC K_AUX#

BG44

DPB_DOC K_AUX

BJ44

DPB_DOC K_HPD_PCH

AU38

BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

Y49 AB49

BE44 BD44 AV40

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

U50 U52

BC46 BD46 AT38

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

DPB_LAN E_0N DPB_LAN E_0P DPB_LAN E_1N DPB_LAN E_1P DPB_LAN E_2N DPB_LAN E_2P DPB_LAN E_3N DPB_LAN E_3P

DVI_C_DDC _CLK DVI_C_DDC _DATA

DPC_DOC K_AUX# DPC_DOC K_AUX DPC_DOC K_HPD_PCH

DPC_LAN E_0N DPC_LAN E_0P DPC_LAN E_1N DPC_LAN E_1P DPC_LAN E_2N DPC_LAN E_2P DPC_LAN E_3N DPC_LAN E_3P

X01-15

Cap. place near docking connector

DPB_DOC K_HPD_PCH

DPC_DOC K_HPD_PCH

C2002 S CD1U10V2KX-4G PC2002 S CD1U10V2KX-4G P

1 2

C2003 S CD1U10V2KX-4G PC2003 S CD1U10V2KX-4G P

1 2

C2004 S CD1U10V2KX-4G PC2004 S CD1U10V2KX-4G P

1 2

C2005 S CD1U10V2KX-4G PC2005 S CD1U10V2KX-4G P

1 2

C2006 S CD1U10V2KX-4G PC2006 S CD1U10V2KX-4G P

1 2

C2007 S CD1U10V2KX-4G PC2007 S CD1U10V2KX-4G P

1 2

C2008 S CD1U10V2KX-4G PC2008 S CD1U10V2KX-4G P

1 2

C2009 S CD1U10V2KX-4G PC2009 S CD1U10V2KX-4G P

1 2

C2010 S CD1U10V2KX-4G PC2010 S CD1U10V2KX-4G P

1 2

C2011 S CD1U10V2KX-4G PC2011 S CD1U10V2KX-4G P

1 2

C2001 S CD1U10V2KX-4G PC2001 S CD1U10V2KX-4G P

1 2

C2012 S CD1U10V2KX-4G PC2012 S CD1U10V2KX-4G P

1 2

C2013 S CD1U10V2KX-4G PC2013 S CD1U10V2KX-4G P

1 2

C2014 S CD1U10V2KX-4G PC2014 S CD1U10V2KX-4G P

1 2

C2015 S CD1U10V2KX-4G PC2015 S CD1U10V2KX-4G P

1 2

C2016 S CD1U10V2KX-4G PC2016 S CD1U10V2KX-4G P

1 2

S D

12

R2006

R2006 110KR2F -GP

110KR2F -GP

S D

12

R2007

R2007 110KR2F -GP

110KR2F -GP

+5V_RUN

Q2001

G

2N7002A -7-GP

Q2002

G

2N7002A -7-GP

DVI_B_DDC _CLK 7 4 DVI_B_DDC _DATA 74

DPB_DOC K_AUX# 74 DPB_DOC K_AUX 74

DPB_LAN E_0N_C 74 DPB_LAN E_0P_C 74 DPB_LAN E_1N_C 74 DPB_LAN E_1P_C 74 DPB_LAN E_2N_C 74 DPB_LAN E_2P_C 74 DPB_LAN E_3N_C 74 DPB_LAN E_3P_C 74

DVI_C_DDC _CLK 74 DVI_C_DDC _DATA 74

DPC_DOC K_AUX# 74 DPC_DOC K_AUX 74

DPC_LAN E_0N_C 74 DPC_LAN E_0P_C 74 DPC_LAN E_1N_C 74 DPC_LAN E_1P_C 74 DPC_LAN E_2N_C 74 DPC_LAN E_2P_C 74 DPC_LAN E_3N_C 74 DPC_LAN E_3P_C 74

DPB_DOC K_HPD 74

DPC_DOC K_HPD 7 4

A A

5

http://sualaptop365.edu.vn

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH - LVDS/CRT/DDI (1/9)

Size Document N umber Rev

Date: Sheet of

PCH - LVDS/CRT/DDI (1/9)

A3

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

1

20 82Thursday, October 2 9, 2009

X01

5

SSID = PCH

RN2102

INT_PIRQB# PCI_PLOCK #

+3.3V_RU N

D D

PCI_PERR# PCI_REQ1# PCI_STOP#

+3.3V_RU N

C C

B B

A A

R2108 100 KR2J-1-GPR2108 100 KR2J-1-GP

R2124 100 KR2J-1-GPR2124 100 KR2J-1-GP

R2123 8K2 R2J-3-GPR21 23 8K 2R2J-3-GP

12

R2120

DY

1 2 3 4 5 6

RN2103

2 3 1

SRN8K2J -3-GP

1 2

12

R2121

1KR2J-1-GP

DY

RN2102

SRN8K2J -2-GP-U

RN2101

SRN8K2J -2-GP-U

PCI_GNT0#

PCI_GNT1#

1KR2J-1-GP

www.rosefix.com

+3.3V_RU N

10

INT_PIRQC#

9

PCI_IRDY#PCI_SERR#

8

INT_PIRQD#PCI_TRDY#

7

PCI_FRAME #

+3.3V_RU N

10

PCI_REQ0#

9

PCH_PIRQF #

8

PCI_DEVSE L#

7

INT_PIRQA#

PCI_GNT#1

01

11

PCI_PLTRS T#

BOOT BIOS Locat ion

PCI

SPI(Default)

LVDS_CB L_DET# PCIE_MCAR D2_DET#

4

BT_DET#

CAM_MIC_C BL_DET#

FFS_PCH _INT

BOOT BIOS Strap

PCI_GNT#0

0 0 LPC

0 1 Reserved (NAND)

PCI_GNT[3:0]#: Internal pull hi gh during Strap

5

http://sualaptop365.edu.vn

4

+3.3V_AL W_PCH

147

U2101A

1

2

TSLVC08 APW-1-GP

147

U2101B

4

5

TSLVC08 APW-1-GP

147

U2101C

9

10

TSLVC08 APW-1-GP

147

U2101D

12

13

TSLVC08 APW-1-GP

LVDS_CB L_DET#54

CAM_MIC_C BL_DET#73

CLK_PCI_5 02838 CLK_PCI_E C37 CLK_PCI_D OCK74

CLK_PCI_L OOPBACK23

4

3

5 OF 10

PCH1E

H40

AD0

N34

AD1

C44

AD2

A38

Consider layout routing

R2104

R2104 33R2J-2-G P

33R2J-2-G P

3

6

8

11

FFS_INT137 ,40

12

R2102

R2102 33R2J-2-G P

33R2J-2-G P

12

R2107

R2107 33R2J-2-G P

33R2J-2-G P

12

R2109

R2109 33R2J-2-G P

33R2J-2-G P

12

PCIE_MCAR D2_DET#76

1 2

R2110

R2110 0R2J-2-GP

0R2J-2-GP

1 2

R2116 22R2J-2-GPR2116 22R2J-2-GP

1 2

R2118 22R2J-2-GPR2118 22R2J-2-GP

1 2

R2117 22R2J-2-GPR2117 22R2J-2-GP

1 2

R2115 22R2J-2-GPR2115 22R2J-2-GP

PCI_GNT3#

1 2

DY

R2122 4K7R2J-2 -GP

PLTRST1 # 9,58

PLTRST2 # 58,72

PLTRST3 # 37,38,70,7 6

PLTRST4 # 32,34,35,6 4

BT_DET#73

TP2102TP2102

TP2104TP2104

TP2105TP2105

PCIE_MCAR D2_DET#

1

CLK_PCI_L OOPBACK_R

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

PCI_REQ0# PCI_REQ1#

BT_DET#

PCI_GNT0# PCI_GNT1# PCI_GNT2# PCI_GNT3#

LVDS_CB L_DET#

PCH_PIRQF #

CAM_MIC_C BL_DET#

FFS_PCH _INT

PCIRST#

PCI_SERR# PCI_PERR#

PCI_IRDY#

PCI_DEVSE L# PCI_FRAME #

PCI_PLOCK #

PCI_STOP# PCI_TRDY#

PCH_PME #

PCI_PLTRS T#

CLK_PCI_5 028_R CLK_PCI_E C_R CLK_PCI_D OCK_R

3

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1#/GPIO50

B45

REQ2#/GPIO52

M53

REQ3#/GPIO54

F48

GNT0#

K45

GNT1#/GPIO51

F36

GNT2#/GPIO53

H53

GNT3#/GPIO55

B41

PIRQE#/GPIO2

K53

PIRQF#/GPIO3

A36

PIRQG#/GPIO4

A48

PIRQH#/GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M-G P-NF

A16 swap overri de Strap/Top-Blo ck Swap Override j umper

PCI_GNT#3 Low = A16 swap

override/Top-Bl ock Swap Override e nabled High = Default

PCI

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_DQ0/NV_IO0 NV_DQ1/NV_IO1 NV_DQ2/NV_IO2 NV_DQ3/NV_IO3 NV_DQ4/NV_IO4 NV_DQ5/NV_IO5 NV_DQ6/NV_IO6 NV_DQ7/NV_IO7 NV_DQ8/NV_IO8

NV_DQ9/NV_IO9 NV_DQ10/NV_IO10 NV_DQ11/NV_IO11

NVRAM

NV_DQ12/NV_IO12 NV_DQ13/NV_IO13 NV_DQ14/NV_IO14 NV_DQ15/NV_IO15

NV_RCOMP

NV_WR#0_RE# NV_WR#1_RE#

NV_WE#_CK0 NV_WE#_CK1

USB

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

5 OF 10

NV_ALE NV_CLE

NV_RB#

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

AY9 BD1 AP15 BD8

AV9 BG8

AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6

BD3 AY6

AU2

AV7

AY8 AY5

AV11 BF5

H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24

B25

D25

N16 J16 F16 L16 E14 G16 F12 T15

2

USB_RBIAS _PN

2

NV_ALE NV_CLE

USBP6USBP6+ USBP7USBP7+

USB_OC# 0_1_R USB_OC# 2_3_R USB_OC# 4_5 USB_OC# 6_7 USB_OC# 8_9 USB_OC# 10_11 USB_OC# 12_13 PCH_OC7 #

1

+V_NVRA M_VCCQ

DMI Termination Voltage

NV_CLE Set to Vss whe n low.

Set to Vcc when high.

Danbury Technol ogy: Disabled when L ow. Enable when Hig h.

NV_CLE

NV_ALE

12

R2103

R2103 1KR2J-1-G P

1KR2J-1-G P

DY

+V_NVRA M_VCCQ

12

R2105

R2105 1KR2J-1-G P

1KR2J-1-G P

DY

USB

Pair

USBP0- 63 USBP0+ 63 USBP1- 63 USBP1+ 63 USBP2- 76 USBP2+ 76 USBP3- 76 USBP3+ 76 USBP4- 64 USBP4+ 64 USBP5- 73 USBP5+ 73

1

TP2110TP2110

1

TP2109TP2109

1

TP2101TP2101

1

TP2103TP2103

USBP8- 74 USBP8+ 74 USBP9- 74 USBP9+ 74 USBP10- 78 USBP10+ 78 USBP11- 73 USBP11+ 73 USBP12- 32,3 4,72 USBP12+ 32,34 ,72 USBP13- 76 USBP13+ 76

1 2

R2112

R2112 22D6R2F -L1-GP

22D6R2F -L1-GP

R2113 0R2J-2-GPR2113 0R2J-2-GP

1 2

R2114 0R2J-2-GPR2114 0R2J-2-GP

1 2

USB_OC# 8_9 USB_OC# 6_7 PCH_OC7 # USB_OC# 12_13

+3.3V_AL W_PCH

Title

PCH - PCI/USB/NVRAM (2/9)

Size Document N umber Rev

A3

Date: Sheet of

Device

USB0 @ MB (Charger)

0

USB1 @ MB

1

USB2 @ IO Board

2

USB3 @ IO Board

3

WLAN

4

Bluetooth

5

Not available for HM55

6

Not available for HM55

7

DOCK1

8

DOCK2

9

Finger Printer

10

Camera

11

PCCard / SmartCard

12

WWAN

13

USB_OC# 0_1 63 USB_OC# 2_3 76

USB_OC# 0_1_R 58 USB_OC# 2_3_R 58 USB_OC# 4_5 5 8 USB_OC# 6_7 5 8 USB_OC# 8_9 5 8 USB_OC# 10_11 58 USB_OC# 12_13 58 PCH_OC7 # 5 8

RN2104

1 2 3 4 5 6

SRN10KJ -L3-GP

Fonseca UMA

10

USB_OC# 0_1_R

9

USB_OC# 2_3_R

8

USB_OC# 4_5

7

USB_OC# 10_11

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

21 82Thursday, October 2 9, 2009

1

+3.3V_AL W_PCH

X01

5

4

3

2

1

SSID = PCH

D D

C C

ME_SUS_ PWR_ACK37

B B

www.rosefix.com

DMI_CTX_P RXN08 DMI_CTX_P RXN18 DMI_CTX_P RXN28 DMI_CTX_P RXN38

DMI_CTX_P RXP08 DMI_CTX_P RXP18 DMI_CTX_P RXP28 DMI_CTX_P RXP38

DMI_PTX_C RXN08 DMI_PTX_C RXN18 DMI_PTX_C RXN28 DMI_PTX_C RXN38

DMI_PTX_C RXP08 DMI_PTX_C RXP18 DMI_PTX_C RXP28 DMI_PTX_C RXP38

+1.05V_R UN

1 2

R2203 49D9R2F-GPR2 203 49D9 R2F-GP

XDP_DBR ESET#9,38,58

12

R2208

R2208 8K2R2J-3 -GP

8K2R2J-3 -GP

DRAM_PW ROK9

PCH_RSM RST#37 SIO_SLP_S 4# 38,50 ,72

PM_PW RBTN#_R58

SIO_PW RBTN#37

AC_PRES ENT37

+3.3V_AL W_PCH

DMI_IRCOMP_R

1 2

R2201 0R2 J-2-GPR2201 0R2J -2-GP

1 2

R2207 0R2 J-2-GPR2207 0R2J -2-GP

1 2

R2209 0R2 J-2-GPR2209 0R2J -2-GP

1 2

R2210 0R2 J-2-GPR2210 0R2J -2-GP

1 2

R2213 10K R2J-3-GPR22 13 10 KR2J-3-GP

1 2

R2215 0R2J-2-GPR2215 0R2J-2 -GP

1 2

R2217 0R2J-2-GPR2217 0R2J-2 -GP

1 2

R2219 0R2J-2-GPR2219 0R2J-2 -GP

1 2

R2221 0R2J-2-GPR2221 0R2J-2 -GP

1 2

R2222 8K2R2J-3 -GPR2222 8K2R2J-3 -GP

1 2

R2223 10KR2J-3 -GPR2223 10KR2J-3 -GP

+3.3V_RU N

12

R2204

R2204 1KR2J-1-G P

1KR2J-1-G P

PM_SYSRST #_R

PM_PW ROKRESET_O UT#_R

PWRO K

ME_PW ROK

PCH_LAN _RST#

DRAM_PW ROK

PCH_RSM RST#_R

ME_SUS_ PWR_ACK_R

PM_PW RBTN#_R

AC_PRESENT_R

PCH_BAT LOW#

PCH_RI#

PCH1C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK/GPIO30

P5

PWRBTN#

P7

ACPRESENT/GPIO31

A6

BATLOW#/GPIO72

F14

RI#

IBEXPEAK-M-G P-NF

DMI

System Power Management

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

WAKE#

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

SLP_LAN#/GPIO29

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12

BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12

BJ14

BF13

BH13

BJ12

BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

PCH_PCIE_ WAKE#

CLKRUN#

PM_SUS_ STAT#

PCH_SUS CLK

PCH_SLP _S5#

PM_SLP_ S4#_R

PM_SLP_ S3#_R

SIO_SLP_M #_R

PM_SLP_ DSW#

H_PM_SYNC

SIO_SLP_L AN#_R

1 2

R2205 10K R2J-3-GPR22 05 10 KR2J-3-GP

1

TP2202TP2202

1

TP2201TP2201

1 2

R2214 0R2J-2 -GPR2 214 0R2J-2-GP

1 2

R2216 0R2J-2 -GPR2 216 0R2J-2-GP

1 2

R2218 0R2J-2 -GPR2 218 0R2J-2-GP

1 2

R2220 0R2J-2 -GPR2 220 0R2J-2-GP

1

TP2203TP2203

1 2

R2224 0R2J-2 -GP

DY

FDI_TXN0 8 FDI_TXN1 8 FDI_TXN2 8 FDI_TXN3 8 FDI_TXN4 8 FDI_TXN5 8 FDI_TXN6 8 FDI_TXN7 8

FDI_TXP0 8 FDI_TXP1 8 FDI_TXP2 8 FDI_TXP3 8 FDI_TXP4 8 FDI_TXP5 8 FDI_TXP6 8 FDI_TXP7 8

FDI_INT 8

FDI_FSYNC0 8

FDI_FSYNC1 8

FDI_LSYNC0 8

FDI_LSYNC1 8

+3.3V_AL W_PCH

X01-47

PCH_PCIE_ WAKE# 38

SIO_SLP_S 5# 37

SIO_SLP_S 3# 9,35,3 8,50

SIO_SLP_M # 38

H_PM_SYNC 9

SIO_SLP_L AN# 38

R2206

R2206 8K2R2J-3 -GP

8K2R2J-3 -GP

R2211

R2211 10KR2J-3 -GP

10KR2J-3 -GP

+3.3V_RU N

12

Option to " Disable "

12

clkrun. Pulling it down

DY

will keep the clks running.

CLKRUN# 3 6,37,38

+3.3V_AL W_PCH

1 2

R2225

R2225 0R2J-2-GP

0R2J-2-GP

U2201

RESET_O UT#37

SIO_SLP_S 3#

A A

1 2

DY

R2227

R2227 0R2J-2-GP

0R2J-2-GP

5

http://sualaptop365.edu.vn

RESET_O UT#

SIO_SLP_S 3#_R

U2201

1

B

2

A

3

GND

74LVC1G 08GW-1-GP

X01.09/0917

DY

VCC

Y

+3.3V_AL W

5

4

RESET_O UT#_R

4

1 2

R2226 10KR2 J-3-GPR2226 10K R2J-3-GP

1 2

DY

R2228 10KR2J-3-GP

R2229 10KR2J-3-GPR2229 10KR2J-3-GP

R2231 10KR2J-3-GPR2231 10KR2J-3-GP

DY

1 2

3

ME_SUS_ PWR_ACK_R

AC_PRES ENT_R

PCH_RSM RST#_R

Type: PP Just Pull down

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH - DMI/FDI/PM (3/9)

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

PCH - DMI/FDI/PM (3/9)

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

1

X01

22 82Thursday, October 2 9, 2009

X01

5

4

3

2

1

SSID = PCH

PCIE_PRX_ WWANT X_N17 6 PCIE_PRX_ WWANT X_P176

PCIE_PTX_ WWANR X_N1_C76

D D

C C

B B

PCIE_PTX_ WWANR X_P1_C76

PCIE_PTX_ R5U241RX_N3_ C32 PCIE_PTX_ R5U241RX_P3_ C32

PCIE_PRX_ WLANTX_N264

PCIE_PRX_ WLANTX_P264 PCIE_PTX_ WLANRX_N2 _C64 PCIE_PTX_ WLANRX_P2 _C64

PCIE_PRX_ R5U241TX_N332 PCIE_PRX_ R5U241TX_P332

PCIE_PRX_ EXPTX_N47 2

PCIE_PRX_ EXPTX_P472 PCIE_PTX_ EXPRX_N4_C72 PCIE_PTX_ EXPRX_P4_C72

PCIE_PRX_ GLANTX_N635

PCIE_PRX_ GLANTX_P635 PCIE_PTX_ GLANRX_N6_C35 PCIE_PTX_ GLANRX_P6_C35

CLK_PCIE_ LOM#35 CLK_PCIE_ LOM35

CLK_PCIE_ R5U241#32 CLK_PCIE_ R5U24132

CLK_PCIE_ MINI1#64 CLK_PCIE_ MINI164

CLK_PCIE_ MINI2#76 CLK_PCIE_ MINI276

+3.3V_AL W_PCH

LOM_CLK REQ#35

PCMCLK_ REQ#32,58

+3.3V_RU N

+3.3V_AL W_PCH

CLK_PCIE_ EXP#72 CLK_PCIE_ EXP72

www.rosefix.com

PCH1B

BG30

PERN1

BJ30 1 2 1 2

SCD1U10 V2KX-4GP

1 2 1 2

SCD1U10 V2KX-4GP

1 2 1 2

SCD1U10 V2KX-4GP

1 2

EXP

1 2

EXP

SCD1U10 V2KX-4GP

1 2 1 2

SCD1U10 V2KX-4GP

1 2

DY

RN2306

2 3 1

RN2307

2 3 1

1 2

RN2311

1

EXP

2 3

SRN0J-6-G P

RN2308

1 2 3

RN2301

2 3 1

SRN0J-6-G P

PCIE_PTX_ WWANR X_N1 PCIE_PTX_ WWANR X_P1

PCIE_PTX_ WLANRX_N2 PCIE_PTX_ WLANRX_P2

PCIE_PTX_ R5U241RX_N3 PCIE_PTX_ R5U241RX_P3

PCIE_PTX_ EXPRX_N4 PCIE_PTX_ EXPRX_P4

PCIE_PTX_ GLANRX_N6 PCIE_PTX_ GLANRX_P6

PCIE_CLK_ RQ0#

CLK_PCIE_ LOM_N CLK_PCIE_ LOM_P

4

LOM_CLK REQ#

CLK_PCIE_ R5U241_N CLK_PCIE_ R5U241_P

4

PCMCLK_ REQ#

PCIE_CLK_ RQ3#

CLK_PCIE_ EXP_N

4

CLK_PCIE_ EXP_P

EXPCLK_ REQ#_PCH

CLK_PCIE_ MINI1_N

4

CLK_PCIE_ MINI1_P

MINI1CLK_REQ #_PCH

CLK_PCIE_ MINI2_N CLK_PCIE_ MINI2_P

4

MINI2CLK_REQ #_PCH

C2301

C2301 C2302

C2302

C2305

C2305 C2306

C2306

C2307

C2307 C2304

C2304

C2312

C2312 C2311

C2311

C2303

C2303 C2308

C2308

PCIe port 7 and 8 may not be available for all Ibex Peak SKUs.

R2307 10KR2J-3-GP

SRN0J-10 -GP-U

R2319 10KR2J-3-GPR2319 10KR2J-3-GP

R2308 10KR2J-3-GPR2308 10KR2J-3-GP

X01-43

SRN0J-10 -GP-U

X01-41

14ONLY

PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +V3.3A. PCIECLKRQ{1,2} should have a 10K pull-up to +3.3S

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0#/GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1#/GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2#/GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4#/GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5#/GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ#/GPIO56

IBEXPEAK-M-G P-NF

WWAN

WLAN

PCMCIA

Express Card

WPAN

LAN

SMBus

PCI-E*

Link

Controller

PEG

CLKOUT_DP_N/CLKOUT_BCLK1_N

CLKOUT_DP_P/CLKOUT_BCLK1_P

LAN

From CLK BUFFER

PCMCIA

WPAN

Express Card

WLAN

WWAN

Clock Flex

2 OF 10

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1ALERT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N/CKSSCD_N CLKIN_SATA_P/CKSSCD_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

PCH_GPIO1 1

B9

PCH_SMB _CLK

H14

PCH_SMB _DATA

C8

PCH_GPIO6 0

J14

PCH_SML 0CLK

C6

PCH_SML 0DATA

G8

PCH_GPIO7 4

M14

KBC_SCL 1

E10

KBC_SDA 1

G12

CL_CLK

T13

CL_DATA

T11

CL_RST#

T9

PCH_GPIO4 7

H1

AD43 AD45

CLK_EXP _N

AN4

CLK_EXP _P

AN2

CLK_DP_ N

AT1

CLK_DP_ P

AT3

CLKIN_DMI#

AW24

CLKIN_DMI

BA24

CLK_CPU _BCLK#

AP3

CLK_CPU _BCLK

AP1

DREFCLK #

F18

DREFCLK

E18

CLK_PCIE_ SATA#

AH13

CLK_PCIE_ SATA

AH12

CLK_PCH _14M

P41

CLK_PCI_L OOPBACK

J42

AH51

XTAL25_ OUT

AH53

XCLK_RC OMP

AF38

CLK_SIO_1 4M_R

T45

CLK_PCI_T PM_CHA_R

P43

CLK_PCI_T PM_R

T42

CLK48_P CH

N50

1

4

RN2312

SRN0J-10 -GP-U

4

RN2313

SRN0J-10 -GP-U

R2317 90D9R 2F-1-GPR2317 90D 9R2F-1-GP

R2314 22R2J -2-GPR2314 22R2 J-2-GP R2315 22R2J -2-GP

R2315 22R2J -2-GP

R2309 22R2J-2-GP

R2313 22R2J-2-GP

R2311 22R2J -2-GPR2311 22R2 J-2-GP

R2312 22R2J -2-GPR2312 22R2 J-2-GP

SC22P50 V2JN-4GP

PCH_SMB _CLK 37

PCH_SMB _DATA 3 7

TP2301TP2301

TP2302TP2302

TP2303TP2303

23

PEG_CLK #_R 9

1

PEG_CLK _R 9

1

DPLL_RE F_SSCLK#_R 9

23

DPLL_RE F_SSCLK_R 9

CLKIN_DMI# 7 CLKIN_DMI 7

CLK_CPU _BCLK# 7 CLK_CPU _BCLK 7

DREFCLK # 7 DREFCLK 7

CLK_PCIE_ SATA# 7 CLK_PCIE_ SATA 7

CLK_PCH _14M 7

CLK_PCI_L OOPBACK 21

1 2

1 2 1 2

J

1 2

C_TPM

1 2

B_TPM

1 2

EC2301

DY

12

+1.05V_R UN

12

EC2302

DY

SC22P50 V2JN-4GP

+3.3V_AL W_PCH

1

23

RN2309

RN2309 SRN2K2J -1-GP

SRN2K2J -1-GP

4

PCH_SMB CLK_MEM18,19,40,58

PCH_SMB DATA_MEM18,19,40,58

CLK_SIO_1 4M 38 CLK_JET WAY_14M 3 6

CLK_PCI_T PM_CHA 36

CLK_PCI_T PM 35,7 0

CLK_SC_ 48M 34

CLK_FD_ 48M 7 5

X01-33

1 2

DY

1 2

DY

1 2

1

23

RN2305

RN2305 SRN2K2J -1-GP

SRN2K2J -1-GP

4

PCH_SMB _CLK

PCH_SMB _DATA

+3.3V_AL W_PCH

1

23

RN2303

RN2303 SRN2K2J -1-GP

SRN2K2J -1-GP

4

+3.3V_RU N

1

23

RN2310

RN2310 SRN2K2J -1-GP

SRN2K2J -1-GP

4

PCH_GPIO1 1

PCH_GPIO6 0

PCH_GPIO7 4

PCH_GPIO4 7

KBC_SCL 1 37

KBC_SDA 1 37

+3.3V_RU N

U2301

1

2

3 4

DMN66D0 LDW-7-GP

R2302 10KR2J-3 -GPR2302 10KR2J-3 -GP

R2303 10KR2J-3 -GP

R2301 10KR2J-3 -GP

R2304 10KR2J-3 -GPR2304 10KR2J-3 -GP

+3.3V_AL W_PCH

6

5

X01.09/0825

X01.09/0918

XTAL25_ INXTAL25_ IN

12

R2316

R2316 1MR2J-1-G P

1MR2J-1-G P

XTAL25_ OUT

From Intel DG 1 .6 CLKOUTFLEX{3:0} RS on PCI/NonPC I Routing (for s ingle / double- load) => 22 ohm serie s resistor

1 2

C2310

C2310 SC12P50 V2JN-3GP

SC12P50 V2JN-3GP

12

X2301

X2301 XTAL-25M HZ-96GP

XTAL-25M HZ-96GP

1 2

C2309

C2309 SC12P50 V2JN-3GP

SC12P50 V2JN-3GP

15ONLY

A A

X01-41

MINI2CLK_REQ #76

+3.3V_RU N +3.3 V_ALW_PC H +3.3V_AL W_PCH+3.3V_R UN

12

R2306

Q2303

G

2N7002A -7-GP

14ONLY

S D

5

http://sualaptop365.edu.vn

R2306 10KR2J-3 -GP

10KR2J-3 -GP

MINI2CLK_REQ #_PCH

EXPCLK_ REQ#72

4

Q2304

G

2N7002A -7-GP

EXP

S D

12

R2310

R2310 10KR2J-3 -GP

10KR2J-3 -GP

EXPCLK_ REQ#_PCH MINI1CLK_REQ #_PCH

MINI1CLK_REQ #58,64

3

+3.3V_RU N +3.3 V_ALW_PC H

12

Q2302

G

2N7002A -7-GP

S D

R2305

R2305 10KR2J-3 -GP

10KR2J-3 -GP

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH - PCIE/SMBUS/CLOCK/CL (4/9)

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

1

X01

23 82Thursday, October 2 9, 2009

X01

5

SSID = PCH

R2404 10MR2J-L -GPR2404 10MR2J-L -GP

D D

C2403

SC15P50V2JN-2-GP

12

1

2 3

X-32D768 KHZ-46GP

www.rosefix.com

PCH_RTC X1

1 2

X2401

4

PCH_RTC X2

C2405

12

SC12P50V2JN-3GP

+RTC_CE LL +RTC_CE LL

R2406

R2406 20KR2J-L 2-GP

20KR2J-L 2-GP

+RTC_CE LL

R2403

R2403 20KR2J-L 2-GP

20KR2J-L 2-GP

X01.09/0918

PCH_AZ_ MDC_BITCLK76 PCH_AZ_ CODEC_BITCLK3 0

PCH_AZ_ MDC_SYNC76 PCH_AZ_ CODEC_SYNC30

PCH_AZ_ MDC_RST#76 PCH_AZ_ CODEC_RST#30,75

PCH_MDC _SDOUT76

ACZ_BIT_C LK

12

EC2401

DY

SC33P50 V2JN-3GP

PCH_COD EC_SDOUT30

C C

1 2

R2423 33R2J-2-GPR2423 33R2J-2-GP

1 2

R2424 33R2J-2-GPR2424 33R2J-2-GP

1 2

R2425 33R2J-2-GPR2425 33R2J-2-GP

1 2

R2426 33R2J-2-GPR2426 33R2J-2-GP

1

4

2 3

RN2403 SRN33 J-5-GP-URN2403 SRN33J-5-G P-U

1 2

R2427 33R2J-2-GPR2427 33R2J-2-GP

1 2

R2428 33R2J-2-GPR2428 33R2J-2-GP

For EMI, RF Cap.

+3.3V_RU N

1 2

DY

R2410 1KR2J-1-GP

B B

Place near PCH side

PCH_JTA G_RST#

A A

+3.3V_RU N

R2421 8K2 R2J-3-GP

NO REBOOT STRAP

+3.3V_SU S

1 2

DY

12

R2416

R2416 20KR2F-L -GP

20KR2F-L -GP

DY

12

R2401

R2401 10KR2J-3 -GP

10KR2J-3 -GP

DY

PCH_SPI_D O

ACZ_SPK R

No Reboot Strap R23

HDA_SPKR

Form DG1.5 TRST# on PCH does not belong to JTAG interface. For ES1 silicon, an ext. pull up 3.3-V Sus is required for bias internal state. A 20-K/10-K voltage divider to this signal to 1.1 V. However, from ES2 silicon onward, this signal is a No Connect regardless if JTAG interface on PCH is enabled or not.

Low = Default High = No Reboot

Pull up +3.3V_M enable iAMT(DY disable)

5

http://sualaptop365.edu.vn

4

1 2

C2404

SC1U10V 3KX-3GP

1 2

C2402

SC1U10V 3KX-3GP

+3.3V_AL W_PCH

4

21

12

G2401

G2401 GAP-OPEN

GAP-OPEN

12

SRTCRST# new signal Pin

PCH_COD EC_SDIN030

PCH_MDC _SDIN176

ACZ_SDA TAOUT_R

1 2

R2408 8K2 R2J-3-GPR24 08 8K 2R2J-3-GP

PCH_SPI_D IN62

Internal pull-up of 20K for HDA_DOCK_EN#,

PCH_JTA G_TCK58

PCH_JTA G_TMS58

PCH_JTA G_TDI58

PCH_JTA G_TDO58

PCH_JTA G_RST#58

PCH_SPI_C LK62

PCH_SPI_C S0#6 2

PCH_SPI_C S1#6 2

PCH_SPI_D O62

1 2

R2402

R2402 1MR2J-1-G P

1MR2J-1-G P

1 2

R2405

R2405 330KR2F -L-GP

330KR2F -L-GP

ACZ_SPK R30

TP2401TP2401

TP2402TP2402

ME_FW P38

1 2

ME_FW P

3

SM_INTRUD ER#

PCH_INTVR MEN

PCH_RTC X1 PCH_RTC X2

PCH_RTC RST#

SRTCRST #

SM_INTRUD ER#

PCH_INTVR MEN

ACZ_BIT_C LK

ACZ_SYNC_ R

ACZ_SPK R SAT A_PTX_HRX0+_ C

ACZ_RST #_R

PCH_COD EC_SDIN0

PCH_MDC _SDIN1

HDA_SDIN2

1

HDA_SDIN3

1

ME_FW P

PCH_GPIO1 3

PCH_JTA G_TCK

PCH_JTA G_TMS

PCH_JTA G_TDI

PCH_JTA G_TDO

PCH_JTA G_RST#

PCH_SPI_C LK

PCH_SPI_C S0#

PCH_SPI_C S1#

PCH_SPI_D O

PCH_SPI_D IN_R

33R2J-2-G PR24 15 33 R2J-2-GPR2415

12

R2422

R2422 1KR2J-1-G P

1KR2J-1-G P

DY

INTVRMEN- Integrated SUS

1.1V VRM Enable High - Enable internal VRs

PCH1A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN#/GPIO33

J30

HDA_DOCK_RST#/GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M-G P-NF

+RTC_CE LL

R2418 0R2J-2-GPR2418 0R2J-2 -GP

W=20mils

12

C2401

SC1U10V 3KX-3GP

integrated VccS us1_05,VccSus1_5 ,VccCL1_5

INTVRMEN

FWH4/LFRAME#

LDRQ1#/GPIO23

LPC

RTCIHDA

SATA

SATAICOMPO

SATAICOMPI

SATA0GP/GPIO21

SATA1GP/GPIO19

SPI JTAG

W=20mils

RTC_PW R_L

1 2

High=Enable Low=Disable

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATALED#

2

D33 B33 C32 A32

C34

A34 F34

AB9

AK7 AK6 AK11 AK9

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF16

AF15

T3

Y9

V1

D2401

3

BAT54CW -1-GP

LPC_LAD 0 LPC_LAD 1 LPC_LAD 2 LPC_LAD 3

integrated VccL an1_05VccCL1_05

LAN100_SLP

3

High=Enable Low=Disable

2

LPC_LAD [0..3]

LPC_LFR AME# 35,36,37,38 ,70

LPC_LDR Q0# 38 LPC_LDR Q1# 38

SATA_PT X_HRX0-_C

SATA_PT X_ORX1-_C SATA_PT X_ORX1+_C

SATA port 2 and 3 may not be available for all Ibex Peak SKUs.

SATA_PT X_DRX_N5_C SATA_PT X_DRX_P5_C

SATAICOMP

HDD_DET #_R

PCH_GPIO1 9

C2410 SCD01U5 0V2KX-1GPC2410 SCD01U5 0V2KX-1GP C2411 SCD01U5 0V2KX-1GPC2411 SCD01U5 0V2KX-1GP

1 2

R2409 37D4R2F -GPR2409 37D4R2F -GP

R2414

PCH_GPIO1 9 58

LPC_LAD [0..3] 35,36,3 7,38,70

+3.3V_RU N

12

R2407

R2407 8K2R2J-3 -GP

8K2R2J-3 -GP

C2406 SCD01U5 0V2KX-1GPC2406 SCD01U5 0V2KX-1GP

1 2

C2407 SCD01U5 0V2KX-1GPC2407 SCD01U5 0V2KX-1GP

1 2

C2408 SCD01U5 0V2KX-1GPC2408 SCD01U5 0V2KX-1GP

1 2

C2409 SCD01U5 0V2KX-1GPC2409 SCD01U5 0V2KX-1GP

1 2

1 2 1 2

+1.05V_R UN

HDD_DET #_R PCH_GPIO1 9

SATA_AC T#_R 66

1 2

0R2J-2-GP

HDD_DET #_R 58 HDD_DET # 59

X01-30

1 2 3

X01-48

+3.3V_RT C_LDO

1

+COIN_CEL LL_R

2

R2419 1KR 2J-1-GPR241 9 1KR 2J-1-GP

Title

Size Document N umber Rev

A3

Date: Sheet of

+COIN_CEL L

12

RTC_BAT _DET#25

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH - SPI/RTC/LPC/SATA/IHDA (5/9)

Fonseca UMA

1

X01-47

IRQ_SERIRQ 35,36 ,37,38

HDD

SATA_PR X_HTX0- 59 SATA_PR X_HTX0+ 59 SATA_PT X_HRX0- 59 SATA_PT X_HRX0+ 59

ODD

SATA_PR X_OTX1- 59 SATA_PR X_OTX1+ 59 SATA_PT X_ORX1- 59 SATA_PT X_ORX1+ 59

DOCKING eSATA

SATA_PR X_DTX_5- 74 SATA_PR X_DTX_5+ 74

SATA_PT X_DRX_5- 74

SATA_PT X_DRX_5+ 74

RN2401

SRN10KJ -5-GP

MLX-CON3 -10-GP-U

1

+3.3V_RU N

4

RTC1

4

1

2 3

5

20.F1000.003

24 82Thursday, October 2 9, 2009

X01

5

4

3

2

1

SSID = PCH

D D

SIO_EXT_W AKE#38

USB_MCA RD1_DET#64

SC47P50 V2JN-3GP

1 2

DY

SC47P50 V2JN-3GP

+3.3V_RU N

C C

B B

A A

R2508 10KR2J-3 -GPR2508 10KR2J-3 -GP

R2509 10KR2J-3 -GPR2509 10KR2J-3 -GP

R2510 10K R2J-3-GPR25 10 10 KR2J-3-GP

R2511 10K R2J-3-GPR25 11 10 KR2J-3-GP

R2501 10K R2J-3-GPR25 01 10 KR2J-3-GP

R2512 10K R2J-3-GPR25 12 10 KR2J-3-GP

R2513 100 KR2J-1-GPR2513 100 KR2J-1-GP

R2514 100 KR2J-1-GPR2514 100 KR2J-1-GP

R2515 8K2 R2J-3-GPR25 15 8K 2R2J-3-GP

R2517 10K R2J-3-GPR25 17 10 KR2J-3-GP

R2535 10K R2J-3-GPR25 35 10 KR2J-3-GP

+3.3V_AL W_PCH

R2534 10K R2J-3-GPR25 34 10 KR2J-3-GP

R2518 10K R2J-3-GPR25 18 10 KR2J-3-GP

R2520 100 KR2J-1-GPR2520 100 KR2J-1-GP

R2521 100 KR2J-1-GPR2521 100 KR2J-1-GP

R2522 1KR 2J-1-GPR252 2 1KR 2J-1-GP

R2523 100 KR2J-1-GPR2523 100 KR2J-1-GP

R2524 10K R2J-3-GPR25 24 10 KR2J-3-GP

R2525 10K R2J-3-GPR25 25 10 KR2J-3-GP

R2528 8K2 R2J-3-GP

Internal pull up GPIO27 to enable VccVRM

www.rosefix.com

C2501

SC47P50 V2JN-3GP

C2501

C2502

PCH_GPIO2 2

PCH_GPIO1

PCH_GPIO6

PCH_GPIO7

SIO_EXT_S CI#_R

PCH_GPIO1 6

SPEAKER _DET#

USB_MCA RD1_DET#

STP_PCI#

PCH_GPIO3 7

RTC_BAT _DET#_R

USB_MCA RD2_DET#

PCH_GPIO4 6

BIO_DET#

LED_BD_ DET#_R

SIO_EXT_W AKE#

PCIE_MCAR D1_DET#

PCH_GPIO1 2

SIO_EXT_S MI#

TP_ONDIE_ PLL_VR

SIO_EXT_S CI#_R58

SIO_EXT_S CI#37

12

DY

12

USB_MCA RD2_DET#76

LED_BD_ DET#77 LED_BD_ DET#_R58

RTC_BAT _DET#24

RTC_BAT _DET#_R58

PCH_GPIO3 758

C2503

DY

SC47P50V2JN-3GP

from Checklist 1.5 VSS_NCTF Pins can be con nected to GND or left as NC ( floating).

When tied to GN D they should be routed as trace and not as a GN D plane.

Note: CRB has s ome NCTF pins tied to GND and some left float ing.

BJ52

PCH1, Board Top View

R2502 0R2J-2-GPR2502 0R2J-2-GP

SIO_EXT_S MI#37

PCH_GPIO1 658

SPEAKER _DET#60

PCIE_MCAR D1_DET#64

R2506

R2506 0R2J-2-GP

0R2J-2-GP

1 2

R2532

R2532 0R2J-2-GP

0R2J-2-GP

12

FFS_INT2_ R40

TEMP_AL ERT#38,58

BIO_DET#7 8

1 2

NCTF

4X

BJ2

BJ1

BH1

5

http://sualaptop365.edu.vn

TP2510TP2510

TP2512TP2512 TP2511TP2511 TP2508TP2508

TP2513TP2513

TP2519TP2519

TP2515TP2515 TP2517TP2517 TP2518TP2518

TP2516TP2516 TP2514TP2514 TP2509TP2509

B53BJ53 BH53

2X3X

1X

D1

4

B2

SIO_EXT_S CI#_R

PCH_GPIO1

PCH_GPIO6

PCH_GPIO7

SIO_EXT_S MI#

PCH_GPIO1 2

SIO_EXT_W AKE#

PCH_GPIO1 6

SPEAKER _DET#

PCH_GPIO2 2

PCIE_MCAR D1_DET#

TP_ONDIE_ PLL_VR

STP_PCI#

USB_MCA RD1_DET#

RTC_BAT _DET#_R

PCH_GPIO3 7

TPM_ID0

TPM_ID1

USB_MCA RD2_DET#

PCH_GPIO4 6

FFS_INT2_ R

TEMP_AL ERT#

BIO_DET#

TP_VSS_ NCTF13

1

TP_VSS_ NCTF22

1

TP_VSS_ NCTF21

1

TP_VSS_ NCTF11

1

TP_VSS_ NCTF23

1

TP_VSS_ NCTF43

1

TP_VSS_ NCTF32

1

TP_VSS_ NCTF41

1

TP_VSS_ NCTF42

1

TP_VSS_ NCTF33

1

TP_VSS_ NCTF31

1

TP_VSS_ NCTF12

1

A53

A52

A4

Y3

C38

D37

J32

F10

K9

T7

AA2

F38

Y7

H10

AB12

V13

M11

V6

AB7

AB13

V3

P3

H3

F1

AB6

AA4

F8

A4

A49

A5 A50 A52 A53

B2

B4 B52 B53

BE1

BE53

BF1

BF53

BH1

BH2 BH52 BH53

BJ1 BJ2 BJ4

BJ49

BJ5 BJ50 BJ52 BJ53

D1 D2

D53

E1

E53

TPM ID

ID1=0

ID1=1

PCH1F

BMBUSY#/GPIO0

TACH1/GPIO1

TACH2/GPIO6

TACH3/GPIO7

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

SATA4GP/GPIO16

TACH0/GPIO17

SCLOCK/GPIO22

GPIO24

GPIO27

GPIO28

STP_PCI#/GPIO34

SATACLKREQ#/GPIO35

SATA2GP/GPIO36

SATA3GP/GPIO37

SLOAD/GPIO38

SDATAOUT0/GPIO39

PCIECLKRQ6#/GPIO45

PCIECLKRQ7#/GPIO46

SDATAOUT1/GPIO48

SATA5GP/GPIO49

GPIO57

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31

IBEXPEAK-M-G P-NF

GPIO

NCTF

ID0=0

C_TPM RSVD

CLKOUT_PCIE6N

CLKOUT_PCIE6P

CLKOUT_PCIE7N

MISC

CLKOUT_BCLK0_N/CLKOUT_PCIE8N

CLKOUT_BCLK0_P/CLKOUT_PCIE8P

CPU

RSVD

CLKOUT_PCIE7P

ID0=1

B_TPMNONE

3

6 OF 10

PCH_SRC 6_XDP_N

AH45

PCH_SRC 6_XDP_P

AH46

PCH_SRC 7_DMI_LAI_N

AF48

PCH_SRC 7_DMI_LAI_P

AF47

U2

A20GATE

BCLK_CP U_N

AM3

BCLK_CP U_P

AM1

BG10

PECI

T1

RCIN#

PROCPWRGD

THRMTRIP#

100KR2J -1-GP

BE10

PCH_THE RMTRIP_RLED_BD_ DET#_R

BD10

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18

TP10

AJ24

TP11

AK41

TP12

AK42

TP13

M32

TP14

N32

TP15

M30

TP16

N30

TP17

H12

TP18

AA23

TP19

AB45

NC_1

AB38

NC_2

AB42

NC_3

AB41

NC_4

T39

NC_5

INIT3_3V#

P6

INIT3_3V#

C10

TP24

+3.3V_RU N +3.3V_RU N

12

B_TPM

R2516

R2526

12

CTPM and DisableBTPM

1

TP2502TP2502

1

TP2503TP2503

1

TP2501TP2501

1

TP2504TP2504

SIO_A20GA TE 37

RN2501

1

4

23

SRN0J-10 -GP-U

H_PECI 9

SIO_RCIN# 37

H_PW RGD 9,58

1

TP2506TP2506

X01.09/0825

B_TPM and DisableBTPM

12

C_TPM

R2527

R2527 100KR2J -1-GP

100KR2J -1-GP

TPM_ID1TPM_ID0

R2529

R2529 100KR2J -1-GP

100KR2J -1-GP

2

+3.3V_RU N

RN2502

SIO_A20GA TE SIO_RCIN#

RN2502

1 2 3

SRN10KJ -5-GP

4

X01-30

BCLK_CP U_N_R 9 BCLK_CP U_P_R 9

+1.05V_R UN

R2505

R2505 56R2J-4-G P

1 2

R2507 56R2J-4-GPR2507 56R2J-4-GP

56R2J-4-G P

Place 2 R close to PCH

Title

PCH - GPIO/CPU/MISC (6/9)

Size Document N umber Rev

Date: Sheet of

PCH - GPIO/CPU/MISC (6/9)

A3

12

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Fonseca UMA

25 82Thursday, October 2 9, 2009

1

H_THERM TRIP# 9,39

X01

Dell LATITUDE E5410,LATITUDE E5510 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual