PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
4
3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
2
Date :Sheeto f
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-G871P
LA-G871P
LA-G871P
1109Tuesday, March 05, 2 019
1109Tuesday, March 05, 2 019
1109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 2
5
4
3
2
1
Merion14 AR Block Diagram
Memory BUS (DDR4)
DDR4 2400MHz for WHL-U
DD
2-Lane eDP1.3
P38
PCIE[5][6][7][8]
HDMI 1.4
CONN
EDP CONN
HDMI
P40
AR-SP
P42-4 3
SMBus
SATA[1]/PC IE[12]
M.2,2230 Key E
P52
WLAN+BT/CNVi
USB2.0[7]USB2.0[10]
PCIE[10]
P52
Left side TypeC
USB2.0
USB2.0[1] from PCH
CC
SMBus
P45
PD Solut i on
TPS65982DD
TBT
P44,50
PCIE[9]
Card reader
RTS524 2
SD4.0
Micro SIM
P70
P70
P52
M.2,3042 Key B
WWAN/LTE/HCA
PCIex2 for 2nd SSD and
Optane
CNVi
EDP
DDI[1]
DDI[2]
INTEL
WHL-U 42 MCP
PAGE 6~19
USB/PCIE MUX
PCIE[11]
HD3SS3212
P54
USB3.0[4]
SPI
SATA[2]/PCIE[16][15] [14][13]
Pop option
GD25B256 DYIG
BB
vPro use
256Mb 4K sector WSON8
P8
GD25B64CYIGR
P8
P8
P63
P63
Smart Card
USH board
TDA8034HN
RFID/NFC
Fingerprint
CONN
Fingerprint
MOCV
Non-vPro use
64Mb 4K sector WSO N8
GD25B127D SIGR
USB2.0[8]
SPI
USH TPM1.2
BCM58202
SPI
FP-USB2.0
P66
ESPI
SMSC KBC
MEC510 5
P58-5 9
Non-vPro use
128Mb 4K sector SOP8
TPM2.0
ST-ST33HTPH 2032AHC 1
BC link
KB/TP CONN
PWM
FAN CONN
Up to 2x16GB Modules
USB
I2C
P66
USB2.0[2]
SLGC55544BVTR
USB POWER SHARE
HD Audio I/F
Reverse Type
DDR4-SO-DIMM X2
BANK 0, 1, 2, 3
P23~24
I2C[0]
USB2.0[6]
USB2.0[2]_PS
P71
USB3.0[2]
USB2.0[3]
USB3.0[3]
I2C[3]
HDA Codec
ALC3254
M.2 2280
SSD Conn
P56
P68
LCD Touch
USB3.0 Conn
PS(Ext Port 1)
USB3.0 Conn
(Ext Port 2)
ActiveSteeringAntenna(MB
)
INT.Speaker
Universal Jack
Dig. MIC
Camera
P38
P38
P71
P72
P56
P56
P38
Trough eDP Cable
Trough eDP Cable
Right side
Left side
P9
LED/B
Bettery LED
Breath LED
LID SWITCH
USH CONN
CPU&PCH XDP Port
AUTOMATIC POWER
SWITCH(APS)
DC/DC Interface
POWER ON/OFF SW
P64
P64
P66
P79
P79
P78
P77
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
2
Title
Size
Size
Size
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
Document Num berRe v
Document Num berRe v
Document Num berRe v
LA-G871P
LA-G871P
LA-G871P
1
2109Tuesday, March 05, 2019
2109Tuesday, March 05, 2019
2109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 3
5
JUSB2-->Lef t
4
POWER STATES
Signal
State
S0 (Full ON) / M0
DD
S3 (Suspend to RAM) / M3LOW
S4 (Suspend to DISK) / M3
S5 (SOFT OFF) / M3
S3 (Suspend to RAM) / M-OFF
SLP
S3#
HIGH
LOW
LOW
SLP
SLP
S5#
S4#
HIGH HIGH
HIGH HIGH
HIGH HIGH
LOW
LOW
LOW
HIGH HIGH
SLP
A#
HIGH
HIGH
HIGH
LOW
ALW AYS
PLANE
ON
ONONON
ONON
ONON
ONON
M
PLANE
ON
OFFOFFOFF
SUS
PLANE
RUN
PLAN E
ONONON
OFF
OFF
OFF
OFF
OFFLOW
CLOCKS
OFF
OFF
OFF
3
USB3.0
USB3.0-1
USB3.0-2
USB3.0-3
USB3.0-4
USB3.0-5
USB3.0-6
SSIC
PCIE
PCIE-1
PCIE-2
PCIE-3
PCIE-4
PCIE-5
PCIE-6
PCIE-7
PCIE-8
SATA
PCIE-9
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
CC
LOWLOWLOW
LOWLOWLOWLOW
HIGH
ON
ON
OFFOFFOFFOFF
OFFOFFOFFOFF
PCIE-10M.2 2230(BT)
PCIE-11
PCIE-12
SATA-0
SATA-1
PCIE-13
PCIE-14
PCIE-15
PCIE-16
SATA-1*
SATA-2
2
N/A
JUSB1-->Right
M.2 3042(LTE)
Alpine Ridge - SP
Card Reader
M.2 2230(WLAN)
M.2 3042(LTE)
M.2 2280 SSD
(PCIex4 or SATA)
USB PORT#DESTINATION
1
2
3
4
5
6
7
8
9
10
1
DESTINATION
Type C
JUSB1-->Right
JUSB2-->Left
N/A
N/A
Camera
M2 3042(WWAN)
USH
Reserve for FPR in PB
PM TABLE
+5V_ALW
+3.3V_ALW
BB
State
S0
S5 S4/AC
S5 S4/AC doesn't existOFFOFFOFF
AA
power
plane
5
+3.3V_ALW_DSW
+3.3V_ALW_PCH
+RTC_CELL
+1.8V_PRIM
+5V_ALW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_PRIM
ON
ON
+1.2V_MEM
+2.5V_MEM
+1.0V_VCCSTG
ONON
OFFOFF
+5V_RUN
+3.3V_RUN
+0.6V_DDR_VTT
+1.8V_RUN
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-G871P
LA-G871P
LA-G871P
3109Tuesday, March 05, 2 019
3109Tuesday, March 05, 2 019
3109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 4
5
Barrel
ADAPT ER
DD
Type-C
ADAPTER
CHARGER
ISL9538
(PU700)
+13.5VB
4
SY8210A
(PU200)
SY8286R
(PU301)
SYV828C
(PU102)
SIO_SLP_S4#
0.6V_DDR_ VTT_ON
PCH_P RIM_EN
ALWO N
+1.2V_MEM
+0.6V_DDR_VTT
+1.0V_PRIM
+5V_ALW
+5V_ALW2
3
TPS22961
(UZ27)
VCCSTG_ EN
SY8057BQ
(PU401)
SY8057CQ
(PU402)
EM5209
(UZ47)
+VCCPLL_OC
RUN_ ON
PCH_P RIM_EN
RUN_ ON
+1.0VS_VCCIO
+1.0V_PRIM_CORE
BATTERY
SY8288B
CC
(PU100)
ALWO N
+3.3V_RTC_LDO
+3.3V_ALW2
SLGC55544C
(UI3)
SY6288
(UI1)
USB_PW R_SHR_ VBUS_EN
USB_PW R_EN1#
2
TPS22961
(UZ19)
TPS22961
(UZ21)
+5V_RUN
+5V_USB_CHG_PWR
+USB_EX2_PWR
VCCSTG_ EN
RUN_ ON
+1.0V_VCCSTG
+1.0V_VCCST
Merion 14 Touch PWR is +5V
PJV1701
(QV8)
EM5209
(@UZ5)
3.3V_TS_EN
AUD_PW R_EN
1
CPU PWR
PCH PWR
Peripheral Device PWR
TYPE-C Power
+TS_PWR
+5V_RUN_AUDIO
+3.3V_ALW
RT8097A
FDMF3035
ISL95808
(PU614)
BB
IMVP_V R_ON
FDMF3035
(PU612)
IMVP_V R_ON
+VCC_GT+VCC_SA
+5V_ALW
(PU610)
FDMF303 5
(PU613)
IMVP_V R_ON
+VCC_CORE
TPS65982DD
(UT5)
AO6405
(QV1)
EN_IN VPWR
+BL_PWR_SRC
+20V_TBTA_VBUS_1(5V~20V)
TYPE-C
+20V_TBTA_VBUS_1(5V~20V)
AA
AP2204
(UT8)
+5V_ALW
+5V_TBT_VBUS
AP2112 K
(UT7)
+3.3V_VDD_PIC
Reserved
5
4
3
(PU501)
EM5209
(UZ47)
EM5209
(UZ3)
EM5209
(UZ4)
G527ATP1U
(UV24)
AP7361C
(PU503)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.
PROPRIETARY NOTE: THIS SHEET O F ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFO RMATION OF DELL INC. ("DELL ") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLO SED TO ANY THIRD
PARTY WITHOUT D ELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document NumberRe v
Size Document NumberRe v
Size Document NumberRe v
Date :Sheetof
Date :Sheetof
Date :Sheetof
Power Sequence
Power Sequence
Power Sequence
LA-G871P
LA-G871P
LA-G871P
1
5109Tuesday, March 05 , 2019
5109Tuesday, March 05 , 2019
5109Tuesday, March 05 , 2019
1.0
1.0
1.0
Page 6
5
4
3
2
1
For 2LANE EDP
+3.3V_RUN
DD
CC
CPU_DP1_CTRL_CLK
2
1
RC5032.2K_0402_5%
CPU_DP1_CTRL_DATA
2
1
RC1782.2K_0402_5%
CPU_DP2_CTRL_CLK
12
RC1762.2K_0402_5%
CPU_DP2_CTRL_DATA
12
RC5022.2K_0402_5%
All VREF traces should
have 10 mil trace width
AR
+1.0VS_VCCIO
COMPENSATION PU FOR eDP
CAD Note:
Trace width=5 mils
Isolation Spacing=25mil,
Max length=100 mils.
This strap should sample HIGH.
There should NOT be any on-board device
CPU@
UC1I
CR30
CNV_WR_D0N
CP30
CNV_WR_D0P
CM30
CNV_WR_D1N
CN30
CNV_WR_D1P
CN32
CNV_WT_D0N
CM32
CNV_WT_D0P
CP33
CNV_WT_D1N
CN33
CNV_WT_D1P
CN31
CNV_WR_CLKN
CP31
CNV_WR_CLKP
CP34
CNV_WT_CLKN
CN34
CNV_WT_CLKP
CP32
CNV_WT_RCOMP_0
CR32
CNV_WT_RCOMP_1
CP20
GPP_F0/CNV_PA_BLANKING
CK19
GPP_F1
CG17
GPP_F2
CR14
GPP_C8/UART0_RXD
CP14
GPP_C9/UART0_TXD
CN14
GPP_C10/UART0_RTS#
CM14
GPP_C11/UART0_CTS#
CJ17
GPP_F8/CNV_MFUART2_RXD
CH17
GPP_F9/CNV_MFUART2_TXD
CF17
GPP_F23/A4WP_PRESENT
WHL-U42_BGA1528
CNVio
9 of 20
3
GPP_H18/CPU_C10_GATE#
GPP_H19/TIMESYNC_0
GPP_H21/XTAL_FREQ_SELECT
GPP_D4/IMGCLKOUT0/BK4/SBK4
GPP_H20/IMGCLKOUT_1
GPP_F12/EMMC_DATA0
GPP_F13/EMMC_DATA1
GPP_F14/EMMC_DATA2
EMMC
GPP_F15/EMMC_DATA3
GPP_F16/EMMC_DATA4
GPP_F17/EMMC_DATA5
GPP_F18/EMMC_DATA6
GPP_F19/EMMC_DATA7
GPP_F20/EMMC_RCLK
GPP_F21/EMMC_CLK
GPP_F11/EMMC_CMD
GPP_F22/EMMC_RESET#
EMMC_RCOMP
GPP_H22
GPP_H23
GPP_F10
GPD7
GPP_F3
1
CNV_COEX3<52>
SBIOS_TX<79>
CNV_COEX2<52>
CNV_COEX1<52>
CNV_PRX_DTX_N0
CNV_PRX_DTX_P0
CNV_PRX_DTX_N1
CNV_PRX_DTX_P1
CNV_PTX_DRX_N0
CNV_PTX_DRX_P0
CNV_PTX_DRX_N1
CNV_PTX_DRX_P1
CLK_CNV_PRX_DTX_N
CLK_CNV_PRX_DTX_P
CLK_CNV_PTX_DRX_N
CLK_CNV_PTX_DRX_P
CNV_WT_RCOMP
2
RC448150_0402_1%
CNV_COEX3
PCH_TBT_PERST#
SBIOS_TX
TYPEC_CON_SEL1
TYPEC_CON_SEL2
CNV_COEX2
CNV_COEX1
CNV_PRX_DTX_N0<52>
CNV_PRX_DTX_P0<52>
CNV_PRX_DTX_N1<52>
CNV_PRX_DTX_P1<52>
CNV_PTX_DRX_N0<52>
CNV_PTX_DRX_P0<52>
CNV_PTX_DRX_N1<52>
BB
+3.3V_ALW_PCH
1
1
PCH_TBT_PERST#
PCH_TBT_PERST#
2
RC55710K_0402_5%RTD3@
2
RC75410K_0402_5%@
CNV_PTX_DRX_P1<52>
CLK_CNV_PRX_DTX_N<52>
CLK_CNV_PRX_DTX_P<52>
CLK_CNV_PTX_DRX_N<52>
CLK_CNV_PTX_DRX_P<52>
PCH_TBT_PERST#<42>
Reserve
+3.3V_ALW_PCH+3.3V_ALW_PCH
RC744
@
10K_0402_5%
12
TYPEC_CON_SEL2TYPEC_CON_SEL1
12
RC745
@
10K_0402_5%
AA
VendorTBDTBDFOXCONJAE
TYPEC_CON_SEL 1
TYPEC_CON_SEL 2
5
LOW
LOW
LOW
HIGH
@
10K_0402_5%
12
12
@
10K_0402_5%
LOW
RC743
RC63
HIGHHIGH
HIGH
4
driving it to opposite direction during strap sampling.
CPU_C10_GATE#
CN27
CM27
GPP_H21
CF25
RTD3_CIO_PWR_EN
CN26
GPP_H23
CM26
CK17
TBT_RTD3_WAKE#
BV35
CN20
TBT_FORCE_PWR
CG25
CH25
MEM_CONFIG0
CR20
MEM_CONFIG1
CM20
MEM_CONFIG2
CN19
MEM_CONFIG3
CM19
MEM_CONFIG4
CN18
CR18
CP18
CM18
CM16
CP16
CR16
CN16
EMMC_RCOMP
CK15
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXP RESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
12
RC5121_040 2_1%
12
RC50480.6_0402_ 1%
12
RC7100_040 2_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PLACE RC62 AND RC515 CLOS
TO THE SPI SIGNAL TO AVOID STUB
Disa bled
Enabled
3
MEM_SMBCLK
CK14
MEM_SMBDATA
CH15
GPP_C2
CJ15
SML0_SMBCLK
CH14
SML0_SMBDATA
CF15
GPP_C5
CG15
SML1_SMBCLK
CN15
SML1_SMBDATA
CM15
GPP_B23
CC34
ESPI_IO0_R
CA29
ESPI_IO1_R
BY29
ESPI_IO2_R
BY27
ESPI_IO3_R
BV27
CA28
CA27
ESPI_CLK
BV32
BV30
GPP_A8
BY30
566439_CNL_PCH_UY_EDS_Vol_1_Rev_1. 1.pdf
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V. This strap should sample HIGH.
There should NOT be any on-board device driving it to opposite direction
during strap sampling.
Merion no RJ45 LAN p ort
SML1_SMBCLK <58>
SML1_SMBDATA <58>
12
RC36615_0402_5%
12
RC36715_0402_5%
12
RC36815_0402_5%
12
RC36915_0402_5%
ESPI_CS# <58,79>
ESPI_RESET# <58,79>
12
RC1933 _0402_5% EMI@
+3.3V_ALW _PCH
12
RC61
100K_0402_ 5%
PCH_SPI_D2
12
RC519
@
4.7K_0402_ 5%
PLACE RC61 AND RC519 CLOS
CONSENT STRAP
HIGH
LOW
TO THE SPI SIGNAL TO AVOID STUB
Disa bled
Enabled
ESPI_IO0 <58,79>
ESPI_IO1 <58,79>
ESPI_IO2 <58,79>
ESPI_IO3 <58,79>
RVP 15 ohm
575962_WHL-U_DDR4_RVP_Sch_Rev0p5.pd f
ESPI_CLK_5105 <58,79>
2
ESPI_CLK_51 05
SML0_SMB CLK
SML1_SMB CLK
MEM_SMB CLK
RF Request
1 2
CC316@RF@33P_0402_50V8J
1 2
CC318@RF@33P_0402_50V8J
1 2
CC319@RF@33P_0402_50V8J
1 2
CC320@RF@33P_0402_50V8J
Place close CPU side
Merion Limit height
QC2 change to SB000014O00 H=0.6mm(MAX)
+3.3V_RUN
1
QC2
S1
2
G1
MEM_SMBCLK
6
D1
4
S2
5
G2
MEM_SMBDATA
D2
PJX138K_ SOT563-6
3
1219 Change
1
DDR_XDP_WAN_SMBCLK <23,24,79>
DDR_XDP_WAN_SMBDAT <23,24,79>
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
RTC_DET#
RC3182.2K_0402_5%
RC3192.2K_0402_5%
GPP_A8
12
12
12
RC8498.2K_04 02_5%@
12
RC121 K_0402_5%
12
RC141 K_0402_5%
12
RC151 K_0402_5%
12
RC5071K_040 2_5%
12
RC347499_040 2_1%@
12
RC348499_040 2_1%@
12
RC86610K_02 01_5%
1031 change
+3.3V_RUN
+3.3V_ALW_PCH
Follow RVP pull up change to 4.7K
BB
PCH_SPI_D1_ R1<66>
PCH_SPI_D0_ R1<66>
PCH_SPI_CLK _R1<6 6>
Pop optio n at P.102
For vPro
256Mb WSON8 Flash ROM
For Non-vPro
PCH_SPI_CLK_1_RPCH_SPI_CLK_0_R
33_0402_5%
@EMI@
12
RC289
AA
33P_0402_50V8J
12
CC1452
5
33_0402_5%
@EMI@
12
RC299
33P_0402_50V8J
@EMI@
@EMI@
12
CC1453
PCH_SPI_CS#0_R1
PCH_SPI_D2_R1
PCH_SPI_CS#1_R1PCH_SPI_CS#1_R2
PCH_SPI_D2_R1
12
RC320_0201_5%@
12
RC3349.9_0201_1%
VPRO@
NVPRO@
12
RC3020_0201_5%
12
RC3533 _0201_1%
NVPRO@
4
PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R
64Mb WSON8 Flash ROM
UC5VPRO@
1
CS#
2
SO(IO1)
3
IO2
4
VSS
ThemalPad
GD25B256DYIG_W SON8_8X6
For Non-vPro
128Mb SOP8 Flash ROM
UC6NVPRO@
1
CS#
2
DO(IO1)
3
IO2
4
GND
DI(IO0)
GD25B127DS IGR_SO8
SOFTWARE TAA
VPRO PDG P.296 R1 50 ohm
PCH_SPI_D1_R1
RC73449.9_0201_ 1%VPRO@
PCH_SPI_D0_R1
RC57049.9_0201_ 1%VPRO@
PCH_SPI_CLK_R1
RC57149.9_0201_ 1%VPRO@
PCH_SPI_D3_R1
RC57249.9_0201_ 1%VPRO@
NVPRO follow PDG P.298 R1 33 ohm
PCH_SPI_D1_R1
RC57333_0201_1%NVPRO@
PCH_SPI_D0_R1
RC57433_0201_1%NVPRO@
PCH_SPI_CLK_R1
RC57533_0201_1%NVPRO@
PCH_SPI_D3_R1
RC57633_0201_1%NVPRO@
PDG SPI0 2 resistor 50ohm, SPI0 3 resistor 33ohm
CLOSEED TO ROM
Please place close for future replace to RP
+3.3V_SPI
8
VCC
PCH_SPI_D3_0_R
7
IO3
PCH_SPI_CLK_0_R
6
SCLK
PCH_SPI_D0_0_R
5
SI(IO0)
9
+3.3V_SPI
8
PCH_SPI_D3_1_R
VCC
7
IO
PCH_SPI_CLK_1_R
6
CLK
PCH_SPI_D0_1_R
5
3
12
12
12
12
12
12
12
12
CC9
1 2
0.1U_0201_1 0V6K
NVPRO@
CC10
1 2
0.1U_0201_1 0V6K
PCH_SPI_D1_0_R
PCH_SPI_D0_0_R
PCH_SPI_CLK_0_R
PCH_SPI_D3_0_R
PCH_SPI_D1_1_R
PCH_SPI_D0_1_R
PCH_SPI_CLK_1_R
PCH_SPI_D3_1_R
Pop optio n at P.102
Pop optio n at P.102
VPRO PDG P.296 R2 5 ohm
NVPRO PDG P.298 R2 10 ohm
12
RC240_ 0201_5%NVPRO@
12
RC254. 99_0201_1%
VPRO@
12
RC264. 99_0201_1%
VPRO@
12
RC274. 99_0201_1%
VPRO@
12
RC280_ 0201_5%@
12
RC294. 99_0201_1%
VPRO@
12
RC304. 99_0201_1%
VPRO@
+3.3V_SPI
+3.3V_ALW _PCH
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
PROM_BIOS_R<63 >
12
RC310_ 0201_5%@
DC4
RB521CM-30T2R _SOD923-2
PCH_SPI_CS# 1_R1
PCH_SPI_D0_ R1
PCH_SPI_D1_ R1
PCH_SPI_CLK _R1
PCH_SPI_CS# 0_R1
PCH_SPI_D2_ R1
PCH_SPI_D3_ R1
21
PCH_SPI_CS# 1
PCH_SPI_D0
PCH_SPI_D1
PCH_SPI_CLK
PCH_SPI_CS# 0
PCH_SPI_D2
PCH_SPI_D3
JSPI1
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
GND1
22
GND2
ACES_5050 6-02041-P01
2
DELL CONFIDENTIAL/PROPRIETARY
GPP_C2
RC2664.7K _0402_5%
TLS CONFIDENTIALITY
HIGH
LOW(DEFAULT)
GPP_C5
RC2774.7K _0402_5%
GPP_C5
@
RC39720K _0402_5%
EC interface
HIGH
LOW (DEFAULT)
GPP_B23
RC317150K_0402_5%
for DCI-OOB
EXI BOOT STALL BYPASS
HIGH
LOW(DEFAULT)
WEAK INTERNAL PD
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
CPU(3/14)SPI,ESPI,SMB,LPC
CPU(3/14)SPI,ESPI,SMB,LPC
CPU(3/14)SPI,ESPI,SMB,LPC
Document Num berRe v
Document Num berRe v
Document Num berRe v
LA-G871P
LA-G871P
LA-G871P
1
12
ENABLE
DISABLE
12
12
ESPI
LPC
12
ENABLED
DIABLED
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
8109Tuesd ay, March 05, 2 019
8109Tuesd ay, March 05, 2 019
8109Tuesd ay, March 05, 2 019
1.0
1.0
1.0
Page 9
BOOT BIOS Dest i nat i on(Bi t 6)
+3.3V_ALW_PCH
1 2
Place close CPU side
12
12
12
12
12
12
12
12
1
@
RC400
10K_0402_5 %
10K_0402_5 %
RC401
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_RUN
TBT_DET#
HIG HNON AR
LOWAR
5
@
T12
PAD~D
TPM_PIRQ#< 66>
PCH_3.3V_TS_EN<38>
RC710,RC711 change to 33oh m from 75ohm,
DD
PU OPTION TO AVOID RSP SIGNALS
+1.8V_PRIM
CC
+3.3V_RUN
BB
FROM FLOATING IN CASE INTERNAL PUS NOT ENABLED IN A0
I2C3_A NT for ACTIVE S TEERING ANT for MERIO N
+3.3V_ALW_PC H
12
RC8314.7K_0402_5 %
12
12
12
12
12
12
NRB_BIT
RC72420K _0402_5%@
RC73320K _0402_5%@
RC747100K_0402_ 5%@
RC84110K_0402_5 %@
RC5122.2K_ 0201_5%
RC5132.2K_ 0201_5%
CNV_BRI_PRX_DTX<52>
CNV_RGI_PTX_DRX_R<52>
CNV_BRI_PTX_DRX_R<52>
CNV_RGI_PRX_DTX<52>
CNV_BRI_PRX_DTX
CNV_RGI_PRX_DTX
PCH_3.3V_TS_ EN
GPP_A7
I2C3_ANT_SDA
I2C3_ANT_SCL
M.2 CNVI MODES
0 = Integrated CNVi enable.
1 = Integrated CNVi disable. (Disable CNVi for bring up)
WEAK INTERNAL PU
follow Intel MOW WW32
12
RC71033_0402_5 %
12
RC71133_0402_5 %
RC710,RC711 place d closer to PCH.
3MM_CAM_DET #<38>
P_SENSOR_PWR_SAVE#<38>
SMART_SPK_DET1#<56>
TS_INT#<38>
TS
TP
Follow RVP,PDG pull up change to 20K
+1.8V_PRIM
TS_I2C_SDA<38 >
TS_I2C_SCL<38>
I2C1_SDA_TP<63>
I2C1_SCK_TP<63>
@
T388
PAD~D
@
T389
PAD~D
566439_CNL_PCH_LP__EDS_Rev1p2
P.119 Primary Well Group H (Per-pad 1.8 V or 3.3 V)
Please setting 3.3V
add I2C3 TP for for sensor IC(Reserved)
add I2C3_ANT TP for ACTIVE STEERING ANT for MERION
20K_0402_5%
RC842
12
CNV_RGI_PTX_DRX_R
12
4.7K_0402_5%
@
RC832
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
Weak IPD
No REBOOT
REBOOT ENABLE
4
PRIM_CORE_OPT_ DIS
GPP_A7
ONE_DIMM#
NRB_BIT
1
PME#
TPM_PIRQ#
PCH_3.3V_TS_ EN
GPP_B22
CNV_BRI_PRX_DTX
CNV_RGI_PTX_DRX
CNV_BRI_PTX_DRX
CNV_RGI_PRX_DTX
3MM_CAM_DET #
P_SENSOR_PW R_SAVE#
SMART_SPK_DET 1#
TS_INT#
I2C2_SDA_ALS
1
I2C2_SCL_ALS
1
I2C3_ANT_SDA
I2C3_ANT_SCL
CPU@
UC1F
CC27
GPP_B15/GSPI0_CS0#
CC32
GPP_A7/PIRQA#/GSPI0_CS1#
CE28
GPP_B16/GSPI0_CLK
CE27
GPP_B17/GSPI0_MISO
CE29
GPP_B18/GSPI0_MOSI
CA31
GPP_B19/GSPI1_CS0#
CA32
GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#
CC29
GPP_B20/GSPI1_CLK
CC30
GPP_B21/GSPI1_MISO
CA30
GPP_B22/GSPI1_MOSI
CK20
GPP_F5/CNV_BRI_RSP
CG19
GPP_F6/CNV_RGI_DT
CJ20
GPP_F4/CNV_BRI_DT
CH19
GPP_F7/CNV_RGI_RSP
CR12
GPP_C20/UART2_RXD
CP12
GPP_C21/UART2_TXD
CN12
GPP_C22/UART2_RTS#
CM12
GPP_C23/UART2_CTS#
CM11
GPP_C16/I2C0_SDA
CN11
GPP_C17/I2C0_SCL
CK12
GPP_C18/I2C1_SDA
CJ12
GPP_C19/I2C1_SCL
CF27
GPP_H4/I2C2_SDA
CF29
GPP_H5/I2C2_SCL
CH27
GPP_H6/I2C3_SDA
CH28
GPP_H7/I2C3_SCL
CJ30
GPP_H8/I2C4_SDA
CJ31
GPP_H9/I2C4_SCL
WHL-U42 _BGA1528
I2C , UART
1031 change,RC435 reserve for FUSE location
+3.3V_RUN
I2C3_ANT_SCL
I2C3_ANT_SDA
RF Request
+3.3V_RUN_R
100P_0201_50V8J
@RF@
1
CC1466
2
place as close as JASA1
Reserved for wake on voice
SIO_SLP_S0#<11,17,66,79,87>
1218 add RC867 reserve for BITS3921 23
Active Steering Antenna circuit
12
RC4350_0603_5%
12
RC5490_0201_5%@
12
RC5480_0201_5%@
PRIM_CORE_OPT_ DIS
SIO_SLP_S0#
3
GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
GPP_D10/ISH_SPI_CLK/GSPI2_CLK
ISH
6 of 20
GPP_D11/ISH_SPI_MISO/GSPI2_MISO
GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
GPP_H10/I2C5_SDA/ISH_I2C2_SDA
GPP_H11/I2C5_SCL/ISH_I2C2_SCL
GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#
+3.3V_RUN_R
I2C3_ANT_SCL_R
I2C3_ANT_SDA_R
+3.3V_ALW_PCH
5
UC9
@
1
MC74VHC1G32D FT2G_SC70-5~D
P
INB
4
O
2
INA
G
3
12
RC8670_0201_5%@
12
RC6600_0201_5%@
IR_CAM_DET#
CN22
DGPU_HOLD_R ST#
CR22
TBT_DET#
CM22
GPP_D12
CP22
ISH_I2C0_ACC_SDA
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_D13/ISH_UART0_RXD
GPP_D14/ISH_UART0_TXD
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
CK22
CH20
CH22
CJ22
CJ27
CJ29
CM24
CN23
CM23
CR24
CG12
CH12
CF12
CG14
BW35
BW34
CA37
CA36
CA35
CA34
BW37
CONN@
JASA1
4
4
G2
3
G1
3
2
2
1
1
CVILU_CI1804M1HR G-NH
ISH_I2C0_ACC_SCL
ISH_I2C1_ALS_SDA
ISH_I2C1_ALS_SCL
ISH_I2C2_SDA
ISH_I2C2_SCL
SML0B_SMBDATA
SML0B_SMBCLK
WWAN_FULL_PWR _EN
SIO_EXT_WAKE#
LCD_CBL_D ET#
PCH_HDD_E N
ISH_ACC1
ISH_ACC2
ISH_TABLE_MODE#
ISH_ALS_INT#
ISH_NB_MODE
ISH_LID_CL#_NB
ISH_LID_CL#_TAB
NB_MODE for NB13/Bandon
LID_CL#_NB for NB13/Bandon
LID_CL#_TAB for NB13/Bandon
ISH_ALS_INT# for Merion
6
5
Link CI1804M1HRG-NH done 0212
VR_LPM_R# <87>
2
IR_CAM_DET# <38>
1
@
T420
PAD~D
1
@
T415
PAD~D
1
@
T416
PAD~D
ISH_I2C1_ALS_SDA <38>
ISH_I2C1_ALS_SCL <38>
ISH_I2C2_SDA <52>
ISH_I2C2_SCL <52>
Reserve
WWAN_FULL_PWR _EN <52>
SIO_EXT_WAKE# <5 8>
LCD_CBL_DET# < 38>
1
@
T421
PAD~D
1
@
T395
PAD~D
1
@
T396
PAD~D
1
@
T397
PAD~D
ISH_ALS_INT# <38>
1
@
T375
PAD~D
1
@
T376
PAD~D
1
@
T377
PAD~D
TBT_DET#
RF Request
SML0B_SMBCL K
PRIM_CORE_OPT_ DIS
SIO_EXT_WAKE#
SML0B_SMBCLK
SML0B_SMBDATA
GPP_D12
LCD_CBL_D ET#
IR_CAM_DET#
ISH_I2C2_SDA
ISH_I2C2_SCL
CC1476@RF@33P _0402_50V8J
RC85410K_04 02_5%@
RC74810K_04 02_5%
RC8291K_040 2_5%@
RC8301K_040 2_5%@
RC847100K_0 402_5%
12
RC749100K_0 402_5%
RC345100K_0 402_5%
12
RC3631K_040 2_5%
12
RC3621K_040 2_5%
+3.3V_ALW_PC H
AA
12
2.2K_0402_5 %
RC46
@
GPP_B22
HIGH
LOW(DEFAULT)
LPC
SPI
5
10K_0402_5%
12
DIMM Detect
HIGH
LOW
RC53
ONE_DIMM#
1 DIMM
2 DIMM
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.
4
3
2
Title
Size Document N umberRe v
Size Document N umberRe v
Size Document N umberRe v
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
CPU(4/14)GSPI,I2C,UART,ISH
CPU(4/14)GSPI,I2C,UART,ISH
CPU(4/14)GSPI,I2C,UART,ISH
LA-G871P
LA-G871P
LA-G871P
1
9109Tuesday, March 05, 201 9
9109Tuesday, March 05, 201 9
9109Tuesday, March 05, 201 9
1.0
1.0
1.0
Page 10
5
4
3
2
1
For Merion AR (follow WHL 180416a port map)
CPU@
UC1H
DD
AR(PCIE5~8) --->
Card Reader RTS5242----->
M.2 2230(WLAN) --->
CC
M.2 3042(LTE/SATA Cache)--->
M2 2280 SSD (4 Lane) --->
BB
AA
PCIE_PRX_DTX_N5<42>
PCIE_PRX_DTX_P5<42>
PCIE_PTX_DRX_N5<42>
PCIE_PTX_DRX_P5<42>
PCIE_PRX_DTX_N6<42>
PCIE_PRX_DTX_P6<42>
PCIE_PTX_DRX_N6<42>
PCIE_PTX_DRX_P6<42>
PCIE_PRX_DTX_N7<42>
PCIE_PRX_DTX_P7<42>
PCIE_PTX_DRX_N7<42>
PCIE_PTX_DRX_P7<42>
PCIE_PRX_DTX_N8<42>
PCIE_PRX_DTX_P8<42>
PCIE_PTX_DRX_N8<42>
PCIE_PTX_DRX_P8<42>
PCIE_PRX_DTX_N9<70>
PCIE_PRX_DTX_P9<70>
PCIE_PTX_DRX_N9<70>
PCIE_PTX_DRX_P9<70>
PCIE_PRX_DTX_N10<52>
PCIE_PRX_DTX_P10<52>
PCIE_PTX_DRX_N10<52>
PCIE_PTX_DRX_P10<52>
PCIE_PRX_DTX_N11<54>
PCIE_PRX_DTX_P11<54>
PCIE_PTX_DRX_N11<54>
PCIE_PTX_DRX_P11<54>
PCIE_PRX_DTX_N12<52>
PCIE_PRX_DTX_P12<52>
PCIE_PTX_DRX_N12<52>
PCIE_PTX_DRX_P12<52>
PCIE_PRX_DTX_N13<68>
PCIE_PRX_DTX_P13<68>
PCIE_PTX_DRX_N13<68>
PCIE_PTX_DRX_P13<68>
PCIE_PRX_DTX_N14<68>
PCIE_PRX_DTX_P14<68>
PCIE_PTX_DRX_N14<68>
PCIE_PTX_DRX_P14<68>
PCIE_PRX_DTX_N15<68>
PCIE_PRX_DTX_P15<68>
PCIE_PTX_DRX_N15<68>
PCIE_PTX_DRX_P15<68>
PCIE_PRX_DTX_N16<68>
PCIE_PRX_DTX_P16<68>
PCIE_PTX_DRX_N16<68>
PCIE_PTX_DRX_P16<68>
2
1
RC50100_0402_1%
Jony _12/21: Refer RVP keep it setting
570990_CF L_U_DD R4_RV P_CRB_ Sch_Re v0p8. pdf
PCIE_RCOMPN
PCIE_RCOMPP
BW9
PCIE5_RXN/USB31_5_RXN
BW8
PCIE5_RXP/USB31_5_RXP
BW4
PCIE5_TXN/USB31_5_TXN
BW3
PCIE5_TXP/USB31_5_TXP
BU6
PCIE6_RXN/USB31_6_RXN
BU5
PCIE6_RXP/USB31_6_RXP
BU4
PCIE6_TXN/USB31_6_TXN
BU3
PCIE6_TXP/USB31_6_TXP
BT7
PCIE7_RXN
BT6
PCIE7_RXP
BU2
PCIE7_TXN
BU1
PCIE7_TXP
BU9
PCIE8_RXN
BU8
PCIE8_RXP
BT4
PCIE8_TXN
BT3
PCIE8_TXP
BP5
PCIE9_RXN
BP6
PCIE9_RXP
BR2
PCIE9_TXN
BR1
PCIE9_TXP
BN6
PCIE10_RXN
BN5
PCIE10_RXP
BR4
PCIE10_TXN
BR3
PCIE10_TXP
BN10
PCIE11_RXN/SATA0_RXN
BN8
PCIE11_RXP/SATA0_RXP
BN4
PCIE11_TXN/SATA0_TXN
BN3
PCIE11_TXP/SATA0_TXP
BL6
PCIE12_RXN/SATA1A_RXN
BL5
PCIE12_RXP/SATA1A_RXP
BN2
PCIE12_TXN/SATA1A_TXN
BN1
PCIE12_TXP/SATA1A_TXP
BK6
PCIE13_RXN
BK5
PCIE13_RXP
BM4
PCIE13_TXN
BM3
PCIE13_TXP
BJ6
PCIE14_RXN
BJ5
PCIE14_RXP
BL2
PCIE14_TXN
BL1
PCIE14_TXP
BG5
PCIE15_RXN/SATA1B_RXN
BG6
PCIE15_RXP/SATA1B_RXP
BL4
PCIE15_TXN/SATA1B_TXN
BL3
PCIE15_TXP/SATA1B_TXP
BE5
PCIE16_RXN/SATA2_RXN
BE6
PCIE16_RXP/SATA2_RXP
BJ4
PCIE16_TXN/SATA2_TXN
BJ3
PCIE16_TXP/SATA2_TXP
CE6
PCIE_RCOMP_N
CE5
PCIE_RCOMP_P
CR28
GPP_H12/M2_SKT2_CFG_0
CP28
GPP_H13/M2_SKT2_CFG_1
CN28
GPP_H14/M2_SKT2_CFG_2
CM28
GPP_H15/M2_SKT2_CFG_3
WHL-U42_BGA1528
USB_OC3#
USB_OC0#
USB_OC1#
USB_OC2#
PCIE / USB3.1 / SATA
8 of 20
RC75720K_0402_5%@
RC75820K_0402_5%@
RC75920K_0402_5%@
RC76020K_0402_5%@
PCIE1_RXN/USB31_1_RXN
PCIE1_RXP/USB31_1_RXP
PCIE1_TXN/USB31_1_TXN
PCIE1_TXP/USB31_1_TXP
PCIE2_RXN/USB31_2_RXN/SSIC_1_R XN
PCIE2_RXP/USB31_2_RXP/SSIC_1_RX P
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date:Sheeto f
Date:Sheeto f
Date:Sheet
Compal Electronics, Inc.
CPU(5/14)PCIE,USB,SATA
CPU(5/14)PCIE,USB,SATA
CPU(5/14)PCIE,USB,SATA
LA-G871P
LA-G871P
LA-G871P
10109Tuesday, March 05, 2019
10109Tuesday, March 05, 2019
10109Tuesday, March 05, 2019
1
1.0
1.0
1.0
of
Page 11
1
CC21
1 2
15P_0402_5 0V8J
4
3
YC1
24MHZ_12PF_ 8Y24000034
2
1
CC22
1 2
15P_0402_5 0V8J
CC23
1 2
15P_0402_5 0V8J
RC66
10M_0402_5 %
12
RC75110K_0402_5%
12
RC481 K_0402_5%@
12
RC834100K_0402_5%
RC7210K _0402_5%
RC55510K_0402 _5%
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU(6/14)CLK,PM,RTC
CPU(6/14)CLK,PM,RTC
CPU(6/14)CLK,PM,RTC
Document Num berRe v
Document Num berRe v
Document Num berRe v
12
YC2
32.768KHZ_1 2.5PF_9H03200 042
ESR MAX=50k ohm
PCH_RTCX2_R
15P_0402_5 0V8J
12
PCH_PRIM_EN <78,87>
12
12
+RTC_CELL_PCH
12
RC691M_0402_5%
RC7310K _0402_5%
RC34410K_0402 _5%@
RC6810K _0402_5%@
12
12
12
LA-G871P
LA-G871P
LA-G871P
1
+3.3V_ALW_PCH
CC26
1 2
+3.3V_ALW_PCH
+3.3V_ALW_DSW
+3.3V_ALW
11109Tuesday, Marc h 05, 2019
11109Tuesday, Marc h 05, 2019
11109Tuesday, Marc h 05, 2019
1.0
1.0
1.0
RC4450_0201_5%@
REFCLK_CNV
4.7P_0402_50V8C
ESD@
1
CC1477
2
12
20K_0402_5 %
4.7K_0402_ 5%
2
XTAL24_IN_CPU
XTAL24_OUT_CPU
PCH_RTCX1
PCH_RTCX2
RC451
@
RC452
2
+3.3V_ALW_PCH
12
RC7280_0402_5%E MI@
12
RC7290_0402_5%E MI@
DC1
NDS3@
21
RB751S-40_ SOD523-2
DC2
NDS3@
21
RB751S-40_ SOD523-2
For deglitch,
refer to 575412_WHL_U_PDG rev0p8
0 = 3.3V supply is 3.3V +/- 5% (3.3V for bring up)
1 = 3.3V supply is 3.0V +/- 5%
12
INPUT3VSEL
12
Jony_1221: Refer RVP is 200 K ohm
570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.p df
XTAL24_IN
XTAL24_OUT
REFCLK_CNV
SUSCLK
SIO_SLP_SUS #
VCCDSW _EN_Q
12
RC4410_0201_5%DS3@
@NDS3@
12
RC442
8/21 can change to 10 K for merge to RP
DELL CONFIDENTIAL/PROPRIETARY
200K_0402_1%
RC59
12
12
RC5320_0402_5%@
0_0201_5%
3.3V_CAM_ EN#
PCH_BATLOW #
AC_PRESE NT
INTRUDER#
VRALERT#
SIO_SLP_LAN #
Title
Title
Title
Size
Size
Size
Date :Sheetof
Date :Sheetof
Date :Sheetof
3
CLK_ITPXDP_N
CLK_ITPXDP_P
@
RC530
RC298
SUSCLK
XTAL24_IN_CPU
XTAL24_OUT_CPU
XCLK_BIASR EF
REFCLK_CNV
PCH_RTCX1
PCH_RTCX2
SRTCRST#
PCH_RTCRST#
@
RC60
RC7380_0201_5%@
RC40260.4_0402_ 1%
LC5BL M15BD121SN1 D_2P~DESD@
LC5 place near CPU side
PCH_RTCRST# <58,79>
CMOS1 DVT1.0 footprint change to SHORTPADS-NPM
CMOS1 must take care short & touch risk on layout placement
1211 change
Follow NB14 UU AR, Intel CNVi recommendation RC237 pop,
But measure cold reset and Global reset sequence timing fail, So depop RC237
SIO_SLP_S0#
12
RC763100K_0402_ 5%
VCCST_PW RGD
100P_0402_50V8J
12
CC301ESD@
5
S4 power side PD need @,need check
RC215
POP
NO Support Deep sleep
DE-POP
Support Deep sleep
PCH_DPW ROK
12
@NDS3@
RC215
100K_0402_1%
0.01UF_0402_25V7K
12
1
@
CC266
2
0_0201_5%
RC220
@
T355
PCH_RSMRS T#_AND
10K_0402_5%
12
PAD~D
RC75
VCCST_PWRGD<59,79>
PCH_RSMRST#_AND<63,79>
1
RC771K _0402_5%@
RC7862 _0402_5%
ME_SUS_PWR_ACK is for LPC use only
SUSACK# is for LPC use only
PCH_PLTRST#_A ND
.047U_0402_16V7K
12
CC196ESD@
For E SD solution
4
SYS_RESET#<79>
12
12
Follow PDG P.251
PCH_PCIE_WAKE#<42,58,59>
LAN_WAKE#<58>
@
T422
PCH_DPWROK<58>
PAD~D
CPU@
PCH_PLTRST#
SYS_RESET#
PCH_RSMRS T#_AND
H_CPUPW RGDH_ CPUPWRG D_R
VCCST_PW RGD_CPU
SYS_PW ROK<58,79>
PCH_PWROK<88>
T380
T381
@
PAD~D
@
PAD~D
1
1
LAN_W AKE#
PM_LANPH Y_ENABLE
1
XDP_DBRESET#<79>
GPP_A13
GPP_A15
UC1K
BJ35
GPP_B13/PLTRST#
CN10
SYS_RESET#
BR36
RSMRST#
AR2
PROCPWRGD
BJ2
VCCST_PWRGOOD
CR10
SYS_PWROK
BP31
PCH_PWROK
BP30
DSW_PWROK
BV34
GPP_A13/SUSWARN#/SUSPWRDACK
BY32
GPP_A15/SUSACK#
BU30
WAKE#
BU32
GPD2/LAN_WAKE#
BU34
GPD11/LANPHYPC
WHL-U42 _BGA1528
+3.3V_ALW_PCH
RC248
@
2.2K_0402_ 5%
12
1
CC78
0.1U_0402_2 5V6
2
Follow ICL_2/23 CKT
RC2430_0201_5%@
12
SYSTEM POWER MANAGE MENT
11 of 20
SYS_RESET#
3
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SPL_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
INTRUDER#
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
INPUT3VSEL
ESD Request:place near CPU sideESD Request:place near CPU side
SIO_SLP_S0#
BJ37
BU36
BU27
SIO_SLP_S5#
BT29
BU29
SIO_SLP_LAN #
BT31
BT30
SIO_SLP_A#
BU37
BU28
BU35
PCH_BATLOW #
BV36
BR35
INTRUDER#
3.3V_CAM_ EN#
CC37
CC36
VRALERT#
BT27
INPUT3VSEL
SYS_RESET#
0.1U_0402_25V6
@ESD@
12
CC302
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
1218
Follow NB14 UU AR
Add 'CNVI_EN#' net connection to GPP_H3
CNV_RF_RESET#<52>
CLKREQ_CNV#<52>
CNVI_EN#<52>
T404 PAD~D@
T405 PAD~D@
T419 PAD~D@
1
1
KB_DET#<63>
1
SPKR<56>
1
+3.3V_ALW_PCH
2
1
ENABLE
DISAB LE
HDA_SDOUT
1
DISABLE
ENABLE
SPKR
+3.3V_RUN
CONTACTLESS_DET#
2
12
1
1
12
AUD_PWR_EN
12
HOST_SD_WP#
12
1
CLKREQ_CNV#
CNV_RF_RESET#
2
CNVI_EN#
2
KB_DET#
BB
AA
RC27810K_0402_5%
RC27910K_0402_5%
RC29210K_0402_5%
+3.3V_ALW_PCH
RC28810K_0402_5%
1206 change
Follow NB14 UU AR
'CNV_RF_RESET#' change to 75K PD from 71.5K
'CLKREQ_CNV#' change to 71.5K PD from 75K
RC75271.5K_04 02_1%
RC64075K_0402_5%
RC86875K_0402_5%
1218
Follow NB14 UU AR
Add 75K PD for 'CNVI_EN#'
RC1832.2K_0402_5%@
TOP SWAP STRAP
HIGH
LOW(DEFAULT)
Internal 20k PD
+3.3V_ALW_PCH
2
RC1874.7K_0402_5%@
Flash Descriptor Security override
HIGH
LOW(DEFAULT)
RF Request. Place near CPU side (Intel MOW)
1
2
HDA_RST#
CC331
2.2P_0402_50V8C
@RF@
HDA_SDIN0
1
2
CC332
@RF@
2.2P_0402_50V8C
1
2
HDA_SDOUT
CC333
2.2P_0402_50V8C
@RF@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date:Sheetof
Date:Sheetof
Date:Sheetof
Compal Electronics, Inc.
CPU(7/14)MISC,JTAG,HDA,SDIO
CPU(7/14)MISC,JTAG,HDA,SDIO
CPU(7/14)MISC,JTAG,HDA,SDIO
LA-G871P
LA-G871P
LA-G871P
12109Tuesday, March 05, 2019
12109Tuesday, March 05, 2019
12109Tuesday, March 05, 2019
1
1.0
1.0
1.0
Page 13
5
2
1
RC1201K_0201_1%@
CFG0
1
RC4111K_0201_1%@
4
2
CFG7
3
2
1
EAR-STALL/NOT STALL RESET
SEQUENCE AFTER PCU PLL IS LOCKED
CFG0
DD
RC4051K_0201_1%@
PCH/ PCH LESS MODE SELECTION
CFG1
RC4061K_0201_1%@
PCI EXPRESS STATIC LANE REVERSAL
FOR ALL PEG PORTS
CFG2
CC
RC4071K_0201_1%@
PCH/ PCH LESS MODE SELECTION
CFG3
RC7231K_0201_1%
0: AN EXTERNAL DISPLAY PORT DEVICE PORT IS CONNECTED TO THE EMBEDDED PORT
1: NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT
DMI AC COUPLING - JUST A PLA CE HOLDER.
NOT APPLICABLE FOR ULX-ULT
CFG11
RC4161K_0201_1%@
PM SYNC LEGACY
CFG12
RC4171K_0201_1%@
1: (DEFAULT) PEG TRAIN IMMEDIATELY
FOLLOWING XXRESETB DE ASSERTION
0: PEG WAIT FOR BIOS FOR TRAINING
2
1
1: DISABLED(DEFAULT); IN THIS CASE, CFG WILL BE
DISABLED IN LOCKED UNITS AND ENABLED IN UN-LOCKED UNITS AND
0: EENABLED; CFG WILL BE
AVAILABLE REGARDLESS OF THE LOCKING OF THE UNIT
12
1
12
1:(DEFULT)
DMI WILL BE CONFIGURED AS HALF S WING DC COUPLED
0:DMI WILL BE CONFIGURED AS FULL SWING A C COUPLED
12
1
CFG8
CFG9
1:VRS SUPPORTING SVID PROTOCOL ARE PRESENT
0: NO VR SUPPORTING SVID
2
CFG10
1: POWER FEATURES ACTIVATED DURING RESET
0: POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT ACTIVATED
CFG11
CFG12
1: (DEFAULT) PMSYNC 2.0
0 : LEGACY
2
CFG13
Refer RVP CFG_RCOMP Keep 49.9 ohm to GND
570990_CF L_U_DD R4_RV P_CRB_ Sch_Re v0p8. pdf
+1.0V_PRIM_XDP
Refer RVP CFG_RCOMP Keep 1.5K to 1.0 VA
570990_CF L_U_DD R4_RV P_CRB_ Sch_Re v0p8. pdf
CFG[0..19]<79>
RC62449.9_0201_1%
RC1251.5K_0201_5%
ITP_PMODE<79>
need check
12
12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
CFG_RCOMP
ITP_PMODE
CPU@
UC1Q
T4
CFG_0
R4
CFG_1
T3
CFG_2
R3
CFG_3
J4
CFG_4
M4
CFG_5
J3
CFG_6
M3
CFG_7
R2
CFG_8
N2
CFG_9
R1
CFG_10
N1
CFG_11
J2
CFG_12
L2
CFG_13
J1
CFG_14
L1
CFG_15
L3
CFG_16
N3
CFG_18
L4
CFG_17
N4
CFG_19
AB5
CFG_RCOMP
W4
ITP_PMODE
CG2
RSVD25
CG1
RSVD24
H4
RSVD34
H3
RSVD33
BV24
RSVD22
BV25
RSVD23
G3
RSVD66
G4
RSVD67
BK36
RSVD17
BK35
RSVD16
W3
RSVD35
AM4
RSVD7
AM3
RSVD6
A35
RSVD1
D34
RSVD30
G2
RSVD32
G1
RSVD31
WHL-U42_BGA1528
RESERVED SIGNALS
20 of 20
RSVD_TP5
RSVD_TP4
IST_TRIG
RSVD_TP3
RSVD15
RSVD14
TP_1
TP_2
RSVD21
RSVD20
RSVD18
RSVD19
RSVD29
RSVD26
RSVD27
VSS_434
RSVD12
RSVD13
RSVD8
RSVD9
RSVD11
RSVD10
RSVD72
RSVD73
RSVD74
RSVD75
TP_4
TP_3
RSVD68
RSVD_TP1
RSVD_TP2
RSVD28
RSVD36
RSVD37
SKTOCC#
F37
F34
CP36
CN36
BJ36
BJ34
BK34
BR18
BT9
BT8
BP8
BP9
CR4
CP3
CR3
BP36
AT3
AU3
AN1
AN2
AN4
AN3
AL2
AL1
AL4
AL3
BP34
BP35
C34
A34
B35
CR35
AH26
AJ27
E1
RC8480_0201_5%@
RC420
@
RC5630_0201_5%
@
RC5640_0201_5%
@
SKTOCC#
RC5650_0201_5%
@
1206 change
Follow NB14 UU AR
Add T423 for CNVi Intel request
1
1
1
1
1
1
1
1
1
2
1
1
1
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
12
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
12
12
12
@
T16
@
T17
@
T18
@
T19
@
T20
@
T21
@
T360
@
T361
@
T363
0_0201_5%
1
@
T364
@
T365
@
T423
+1.0V_VCCSTG
1
2
RC436
@
100_0201_1%
CFG5,6
PCH/ PCH LESS MODE SELECTION
01: DEVICE1 FUNTION 1, DISABLED, DEVICE 1 FUNCTION2 ENABLED
00: DEVICE 1 FUNCTION 1 ENABLED, DEVICE 1 FUNCTION 2 ENABLED
PMSYNC AYNC MODE- PM SYNC
1: (DEFAULT)SYNCHCRONOUS (1 24 MHZ CYCLE PER BIT)
CFG13
0: ASYNC - 4-24MHZ CYCLES PER BIT
2
1
AA
RC4181K_0201_1%@
CFG14
RC4191K_0201_1%@
12
CFG15
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
CFG14CFG15
5
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date:Sheetof
Date:Sheetof
Date:Sheet
Compal Electronics, Inc.
CPU(8/14)CFG,RSVD
CPU(8/14)CFG,RSVD
CPU(8/14)CFG,RSVD
LA-G871P
LA-G871P
LA-G871P
13109Tuesday, March 05, 2019
13109Tuesday, March 05, 2019
13109Tuesday, March 05, 2019
1
1.0
1.0
1.0
of
Page 14
2
2
+1.0V_VCC STG
TOUCH_SCREE N_PD#
Merion Limit height
QC4 change to SB000014O00 H=0.6mm(MAX)
TOUCH_SCREEN_PD# don't move to RPC,
TOUCH_SCREE N_PD#
TOUCH_SCREE N_PD
1219 Change
QC4
@
2
5
12
RC5660 _0201_5%@
1
S1
G1
D1
S2
G2
D2
PJX138K _SOT563-6
3
TOUCH_SCREE N_PD
6
4
Reserve for Panel side TS PH voltage problem
MEM_INTERLE AVED
PROCHOT#
TOUCH_SCREEN_DET#<38>
TOUCHPAD_INTR#<58,63>
4
2
1
RC84499 _0402_1%
2
1
RC5590_0201_5%@
XDP_OBS0_R<79 >
XDP_OBS1_R<79 >
@
T366
PAD~D
@
T367
PAD~D
1
1
RC106
2
2
49.9_0201_1%
H_CATERR#
PROCHOT#_R
H_THERMTRIP#_ R
XDP_OBS 2_R
1
XDP_OBS 3_R
1
MEM_INTERLE AVED
TOUCH_SCREE N_PD#
TOUCHPAD_INTR#
CPU_POPI RCOMP
PCH_POPI RCOMP
EDRAM_OP IO_RCOMP
EOPIO_RC OMP
12
1
RC107
RC109
RC108
49.9_0201_1%
@
@
2
49.9_0201_1%
49.9_0201_1%
need check
RC108,RC109
This is applicable only for CFL U43e. These pins are
RSVD in WHL and hence can be left unconnected
CB34
CC35
BP27
BW25
AA4
AR1
Y4
BJ1
U1
U2
U3
U4
CE9
CN3
L5
N5
CPU@
UC1D
CATERR#
PECI
PROCHOT#
THRMTRIP#
BPM#_0
BPM#_1
BPM#_2
BPM#_3
GPP_E3/ CPU_GP0
GPP_E7/ CPU_GP1
GPP_B3/ CPU_GP2
GPP_B4/ CPU_GP3
PROC_POP IRCOMP
PCH_OPIRC OMP
RSVD70
RSVD71
WHL-U42 _BGA1528
5
+1.0V_VCC ST
2
H_THERMTRIP#_ R
H_CATERR#
PROCHOT#
TOUCH_SCREE N_PD#
TOUCHPAD_INTR#
PECI_EC<58>
PROCHOT#<58, 84,88>
H_THERMTRIP#<23,24 ,59>
RC2181K_0201 _1%
12
2
1
RC21949.9_020 1_1%@
+1.0V_VCC STG
RC5581K_0201 _1%
1
DD
+3.3V_RUN
2
1
RC8210K _0201_5%@
2
1
RC56710K_020 1_5%
CC
CPU MISC
3
PROC_TCK
JTAG
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_TRST#
PCH_JTAGX
PROC_PRE Q#
PROC_PRDY#
4 of 20
PCH_JTAG_TDOPCH_JTAG_TDI
@ESD@
0.1U_0201_25V6K
1
CC303
2
T6
U6
PROC_TDI
Y5
T5
AB6
W6
PCH_TCK
U5
PCH_TDI
W5
PCH_TDO
P5
PCH_TMS
Y6
P6
W2
W1
ESD request,Place near CPU side.
CPU_XDP_TRST#
XDP_JTAGX
@ESD@
0.1U_0201_25V6K
1
CC304
2
CPU_XDP_TCLK <79>
CPU_XDP_TDI <79>
CPU_XDP_TDO <79>
CPU_XDP_TMS <79>
RC8651_0201_5%@
PCH_JTAG_TCK <79>
PCH_JTAG_TDI <79>
PCH_JTAG_TDO <79>
PCH_JTAG_TMS <79>
CPU_XDP_TRST# <79 >
XDP_JTAGX <79>
1
RC871K_ 0201_5%@
CPU_XDP_PREQ# <79>
CPU_XDP_PRDY# <79>
XDP_JTAGX
@ESD@
0.1U_0201_25V6K
1
CC305
2
1
2
1
TOUCH_SCREEN_PD#_R
+3.3V_RUN
12
RC104
@
10K_020 1_5%
TOUCH_SCREEN_PD#_R <38>
+3.3V_ALW_PCH
@
RC843
10K_020 1_5%
12
12
RC844
10K_020 1_5%
DIMM TYPE
HIGHInterlea ve
Non-In terleave
LOW
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DIS CLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size
Size
Size
Date:Sheeto f
Date:Sheeto f
Date:Sheeto f
Compal Electronics, Inc.
CPU(9/14)XDP
CPU(9/14)XDP
CPU(9/14)XDP
Document NumberRe v
Document NumberRe v
Document NumberRe v
LA-G871P
LA-G871P
LA-G871P
1
14109Tuesday, March 05, 2019
14109Tuesday, March 05, 2019
14109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 15
+VCC_CORE
2
2
1
1
2
1
2
1
Close C PU
RC150
100_0402_1%
RC151
100_0402_1%
1V@0 .0 5A
VCC_SENSE_IA <88>
VSS_SENSE_IA <88>
+1.0V_VCCSTG
2
VCCCORE35
VCCCORE36
VCCCORE37
VCCCORE38
VCCCORE44
VCCCORE45
VCCCORE48
VCCCORE49
VCCCORE50
VCCCORE46
VCCCORE47
VCCCORE51
VCCCORE52
VCCCORE56
VCCCORE57
VCCCORE58
VCCCORE59
VCCCORE53
VCCCORE54
VCCCORE55
VCCCORE63
VCCCORE64
VCCCORE60
VCCCORE61
VCCCORE62
VCCCORE69
VCCCORE65
VCCCORE66
VCCCORE67
VCCCORE68
VCCCORE70
VCCCORE73
VCCCORE71
VCCCORE72
VCCCORE74
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
RSVD5
VCCSTG1
AW24
AW25
AW26
AW27
AY24
AY26
BA5
BA7
BA8
BA25
BA27
BB2
BB26
BC5
BC6
BC7
BC9
BC10
BC26
BC27
BD5
BD8
BD10
BD25
BD27
BE9
BE24
BE25
BE26
BE27
BF2
BF9
BF24
BF26
BG27
AN6
AN5
AA3
AA1
AA2
Y3
BG3
+VCC_CORE
VCCSENSE_R
VSSSENSE_R
H_CPU_SVIDALRT#
VIDSCLK_R
VIDSOUT_R
+1.0V_VCCSTG_R
RC430
@
0_0201_5%
1
1
0_0201_5%
RC429
@
2
RC1530_0603_5%@
+VCC_CORE_G0
+VCC_CORE_G1
+VCC_CORE_G2
+VCC_CORE_G3
3
+VCC_CORE
CPU@
UC1L
AN9
VCCCORE5
AN10
VCCCORE1
AN24
VCCCORE2
AN26
VCCCORE3
AN27
VCCCORE4
AP2
VCCCORE6
AP9
VCCCORE9
AP24
VCCCORE7
AP26
VCCCORE8
AR5
VCCCORE13
AR6
VCCCORE14
AR7
VCCCORE15
AR8
VCCCORE16
AR10
VCCCORE10
AR25
VCCCORE11
AR27
VCCCORE12
AT9
VCCCORE19
AT24
VCCCORE17
AT26
VCCCORE18
AU5
VCCCORE24
AU6
VCCCORE25
AU7
VCCCORE26
AU8
VCCCORE27
AU9
VCCCORE28
AU24
VCCCORE20
AU25
VCCCORE21
AU26
VCCCORE22
AU27
VCCCORE23
AV2
VCCCORE30
AV5
VCCCORE32
AV7
VCCCORE33
AV10
VCCCORE29
AV27
VCCCORE31
AW5
VCCCORE39
AW6
VCCCORE40
AW7
VCCCORE41
AW8
VCCCORE42
AW9
VCCCORE43
AW10
VCCCORE34
BB9
RSVD3
BC24
RSVD4
AY9
RSVD1
BB24
RSVD2
WHL-U42_BGA1528
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache)
CPU POWER 1 OF 4
12 of 20
5
PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package
CAD Note: Place the PU resistors close to CPU
RC154 close to CPU 1000 - 1500mils
2
H_CPU_SVIDALRT#
1
RC155220_0402_5%
CAD Note: Place the PU resistors close to CPU
RC156close to CPU 1000 - 1500mils
VIDSOUT_R
12
RC1570_0201_5%@
CAD Note: Place the PU resistors close to CPU
RC158close to CPU 1000 - 1500mils
12
VIDSCLK_R
RC1590_0201_5%@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date:Sheetof
Date:Sheetof
Date:Sheetof
Compal Electronics, Inc.
CPU(10/14)PWR-VCC CORE
CPU(10/14)PWR-VCC CORE
CPU(10/14)PWR-VCC CORE
LA-G871P
LA-G871P
LA-G871P
15109Tuesday, March 05, 2019
15109Tuesday, March 05, 2019
15109Tuesday, March 05, 2019
1
1.0
1.0
1.0
Page 16
5
4
3
2
1
THE BALLOUT ONLY FOR WHL ES2 CPU
DD
+VCCGT: 0.55~1.5V, 54A
+VCCGTX : 0.55~1.5V, 7A
+VCC_GT+VCC_CORE
CPU@
UC1M
A5
A6
A8
A11
A12
A14
A15
A17
A18
A20
AA9
AB2
AB8
AB9
AB10
AC8
AD9
AE8
CC
BB
AE10
AF10
AJ10
AL10
AM8
AE9
AF2
AF8
AG8
AG9
AH9
AJ8
AK2
AK9
AL8
AL9
Y10
B11
B14
B17
B20
C11
C12
C14
C15
C17
C18
C20
D11
D12
D14
V2
Y8
B3
B4
B6
B8
C2
C3
C6
C7
C8
D4
D7
CPU POWER 2 OF 4
VCCGT8
VCCGT9
VCCGT10
VCCGT1
VCCGT2
VCCGT3
VCCGT4
VCCGT5
VCCGT6
VCCGT7
ES1/ES2
VCCGT11/VCCCORE75
VCCGT13/VCCCORE76
VCCGT14/VCCCORE77
VCCGT15/VCCCORE78
VCCGT12/VCCCORE79
VCCGT16/VCCCORE80
VCCGT17/VCCCORE81
VCCGT19/VCCCORE82
VCCGT20/VCCCORE83
VCCGT18/VCCCORE84
VCCGT22/VCCCORE85
VCCGT23/VCCCORE86
VCCGT21/VCCCORE87
VCCGT24/VCCCORE88
VCCGT25/VCCCORE89
VCCGT26/VCCCORE90
VCCGT28/VCCCORE91
VCCGT27/VCCCORE92
VCCGT29//VCCCORE93
VCCGT30/VCCCORE94
VCCGT32/VCCCORE95
VCCGT33/VCCCORE96
VCCGT31/VCCCORE97
VCCGT34/VCCCORE98
VCCGT115/VCCCORE99
VCCGT119/VCCCORE100
VCCGT120/VCCCORE101
VCCGT39
VCCGT40
VCCGT41
VCCGT42
VCCGT35
VCCGT36
VCCGT37
VCCGT38
VCCGT49
VCCGT51
VCCGT52
VCCGT53
VCCGT54
VCCGT43
VCCGT44
VCCGT45
VCCGT46
VCCGT47
VCCGT48
VCCGT50
VCCGT62
VCCGT63
VCCGT55
VCCGT56
VCCGT57
WHL-U42_BGA1528
13 of 20
1.5V@54A
VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT64
VCCGT69
VCCGT70
VCCGT71
VCCGT72
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT73
VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT87
VCCGT88
VCCGT89
VCCGT90
VCCGT80
VCCGT81
VCCGT82
VCCGT83
VCCGT84
VCCGT85
VCCGT86
VCCGT95
VCCGT96
VCCGT91
VCCGT92
VCCGT93
VCCGT94
VCCGT98
VCCGT97
VCCGT100
VCCGT101
VCCGT99
VCCGT102
VCCGT104
VCCGT105
VCCGT106
VCCGT103
VCCGT107
VCCGT108
VCCGT109
VCCGT111
VCCGT112
VCCGT110
VCCGT114
VCCGT113
VCCGT116
VCCGT117
VCCGT118
VCCGT_SENSE
VSSGT_SENSE
D15
D17
D18
D20
E4
F5
F6
F7
F8
F11
F14
F17
F20
G11
G12
G14
G15
G17
G18
G20
H5
H6
H7
H8
H11
H12
H14
H15
H17
H18
H20
J7
J8
J11
J14
J17
J20
K2
K11
L7
L8
L10
M9
N7
N8
N9
N10
P2
P8
R9
T8
T9
T10
U8
U10
V9
W8
W9
E3
D2
+VCC_GT
VCCGT_SENSE_R
VSSGT_SENSE_R
+VCC_GT
1
Close C PU
RC160
100_0402_1%
2
1
RC6320_0201_5%@
12
RC6310_0201_5%@
2
VCC_SENSE_GT <88 >
VSS_SENSE_GT <88>
12
RC161
100_0402_1%
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
Follow 575962 RVP V0P7,VCCSFR_OC enable gated by VCCSTG_EN
+1.0V_VCCSTG source
+1.0V_PRIM
+3.3V_RUN
RZ1422
12
12
RZ1420
CPU_C10_GATE#<6,87>
BB
@
0_0201_5%
RUN_ON<17,58,59,78,87>
MC74VHC1G0 8DFT2G_SC70-5
12
RZ3200_020 1_5%@
CZ105 1U_ 0201_6.3V6M
100K_0402_5%
+3.3V_ALW
1
B
2
A
UZ35
+5V_ALW
5
P
G
3
12
O
4
VCCSTG_EN
UZ19
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
EM5201V_D FN8_3X3
4.4moh m/6A
TR=12.5us@Vin=1.05V
+1.0V_VCCSTG+1.0V_V CCST
12
JUMP@
PJP2
PAD-OPEN1x1m
+1.0V_VCC STG_C
6
VOUT
5
GND
Follow 575962 RVP V0P7,VCCSTG RAIL design
+1.0V_VCCST source
+1.0V_PRIM
UZ21
VCCST_EN
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
EM5201V_D FN8_3X3
4.4moh m/6A
TR=12.5us@Vin=1.05V
VOUT
+1.0V_VCC ST_C
6
5
GND
12
CZ1001U_ 0201_6.3V6M
SIO_SLP_S3#<11,17,42,59,79>
SIO_SLP_S4#<11,79,86,87>
AA
RUN_ON<17,58,59,78,87>
Follow 575962 V0p7 PDG page519,Premium design Vccst gated by RUN_ON
RZ14160_0201_5%@
RZ14170_0201_5%@
RZ14230_0201_5%@
+5V_ALW
12
12
12
RC864
@
0_0603_5%
12
JUMP@
PJP1
12
PAD-OPEN1x1m
1 2
CZ101 0.1 U_0201_10V6K
12
RZ1510_ 0603_5%@
pop option with UZ19
1 2
CZ106
0.1U_0201_1 0V6K
RC864 Co-lay
with PJP1
+1.0V_VCCST
RF Request
+1.2V_MEM
place as close as CPU
RF@
RF@
680P_0402_50V7K
1200P_0402_50V7K
1
1
CC1479
CC1478
2
2
+1.0V_VCCST
PSC
PDG0.8 P.479 0402
close to package
1
2
+1.0V_VCCSTG
+1.0V_VCCSTG
0801 Confirmed with
Intel can change to 0201
CC28
1U_0201_6.3V6M
1V@0 .12 A
1V@0 .04 A
1
0801 Confirmed with
PDG0.8 P.479 0402
+1.2V_MEM
Primary Side
Secondary Side
Intel can change to 0201
CC29
2
1U_0201_6.3V6M
+VCCPLL_OC
PSC
1.2V @0.2 6A
close to package
Follow RVP rev1.0
1
PDG0.8 P.479 0402
0801 Confirmed with
Intel can change to 0201
WHL_U PDG rev0. 8 P.479
VDDQ:
Primary Side cap
1x 22uF 0603 + 6x 10uF 0402
Secondary Side cap
4x 1uF 0402/0201 + 3x 10uF 0402
PDG P.479 22U 0603,10U 0402
1
1
CC32
2
2
22U_0603_6.3V6M
PDG P.479 1U 0402/0201,10U 0402
1
1
CC1454
2
2
10U_0402_6.3V6M
1
CC430
2
2
1U_0201_6.3V6M
1
1
1
CC35
CC34
CC33
2
10U_0402_6.3V6M
1
CC45
2
10U_0402_6.3V6M
CC36
2
2
10U_0402_6.3V6M
10U_0402_6.3V6M
1
1
CC46
CC195
CC1455
2
2
1U_0201_6.3V6M
10U_0402_6.3V6M
+1.2V_MEM
1.2V @3.5 A
1V@0 .12 A
PDG0.8 P.479
0805 Reserve
MOW WW30
1
1x22U/47U 0805
CC1480
0.1U_0201_10V6K
1
CC37
2
10U_0402_6.3V6M
1
CC1456
2
1U_0201_6.3V6M
CC96
2
22U_0603_6.3V6M
PDG0.8 P.479 0402
0801 Confirmed with
Intel can change to 0201
CC96 follow Intel MOW WW30 change to pop
but 22U_0805 shortage,so use 22U_060 3.
1
CC38
2
10U_0402_6.3V6M
10U_0402_6.3V6M
1
CC1457
2
1U_0201_6.3V6M
1U_0201_6.3V6M
CPU@
UC1N
AD36
VDDQ1
AH32
VDDQ2
AH36
VDDQ3
AM36
VDDQ4
AN32
VDDQ5
AW32
VDDQ6
AY36
VDDQ7
BE32
VDDQ8
BH36
VDDQ9
R32
VDDQ10
Y36
VDDQ11
BC28
RSVD1
BP11
VCCST1
BP2
VCCST2
BG1
VCCSTG1
BG2
VCCSTG2
BL27
VCCPLL_OC1
BM26
VCCPLL_OC2
BR11
VCCPLL1
BT11
VCCPLL2
WHL-U42 _BGA1528
PSC
close to package
1
CC31
2
1U_0201_6.3V6M
1
PDG0.8 P.479 0201
CC1462
2
0.1U_0201_10V6K
CPU POWER 3 OF 4
14 of 20
+1.0V_VCCST
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCSA2
VCCSA1
VCCSA3
VCCSA5
VCCSA6
VCCSA4
VCCSA9
VCCSA7
VCCSA8
VCCSA13
VCCSA14
VCCSA10
VCCSA11
VCCSA12
VCCSA15
VCCSA16
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
+VCC_SA
+1.0VS_VCCIO
+1.0VS_VCCIO
AK24
0.95 V@3. 1A
AK26
AL24
AL25
AL26
AL27
AM25
AM27
BH24
BH25
BH26
BH27
BJ24
BJ26
BP16
BP18
BG8
BG10
BH9
BJ8
BJ9
BJ10
BK8
BK25
BK27
BL8
BL9
BL10
BL24
BL26
BM24
BN25
BP28
BP29
BE7
BG7
RC166100_0402_1%
Primary Side
12
RC4250_0201_5%@
12
RC4260_0201_5%@
12
1
CC1458
2
1.15 V@5. 1A
VCCIO_SENSE
VSSIO_SENSE
PDG P.479 0201
1
CC1459
2
1U_0201_6.3V6M
Primary or Secondary Side
1
1
CC235
CC234
2
2
10U_0402_6.3V6M
PDG P.479 0402
Placeholder
1
1
CC40
CC39
2
2
@
@
10U_0402_6.3V6M
+VCC_SA
+1.0VS_VCCIO
Close CPU
12
RC163
100_0402_1 %
VCCIO_SENSE <87>
VSSIO_SENSE <87>
12
12
RC165
@
0_0201_5%
RC164
100_0402_1%
VSS_SENSE_SA <88>
VCC_SENSE_SA <88>
WHL_U PDG rev0. 8 P.479
VCCIO:
Primary Side cap
4x 1uF 0201
Primary or Secondary Side
6x 10uF 0402
Placeholder Only
4x 10uF 0402
1
1
CC1460
CC1461
2
2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
PDG P.479 0402
1
1
1
CC236
2
10U_0402_6.3V6M
10U_0402_6.3V6M
1
CC41
2
@
10U_0402_6.3V6M
10U_0402_6.3V6M
1
CC51
CC52
CC237
2
2
2
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1
CC42
2
@
10U_0402_6.3V6M
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
2
Title
Size
Size
Size
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
CPU(12/14)PWR-VCCIO,MEM
CPU(12/14)PWR-VCCIO,MEM
CPU(12/14)PWR-VCCIO,MEM
Document Num berRe v
Document Num berRe v
Document Num berRe v
LA-G871P
LA-G871P
LA-G871P
1
17109Tuesday, Marc h 05, 2019
17109Tuesday, Marc h 05, 2019
17109Tuesday, Marc h 05, 2019
1.0
1.0
1.0
Page 18
5
4
3
2
1
close UC1 <100mil
12
LC1LQM18PN2R2NC0L_2P~D
RC422
@
0.01_0603_1%
12
DD
0809 BSOD
Pop LC2 INDUCTOR,CC100 22U_0603
+1.0V_PRIM+1.0V_CLK
depop RC175
Add CC103 22U_0603
12
LC2LQM18PN2R2NC0L_2P~D
RC175
@
0.01_0603_1%
12
CC100/CC103 one is close to the
CPU and the other is far fr om the CPU.
PDG rev0.8 P.509
Place an 22uF edge cap not more t han
12 mm away measuring from package edge.
+1.0V_AMPHYPLL+1.0V_MPHYGT
1
1
CC69
CC80
2
2
1U_0201_6.3V6M
1U_0201_6.3V6M
PDG0.8 P.505 0402
0801 Confirmed with
Intel can change to 0201
+3.3V_ALW_PCH
PDG P.505 no decoup.PDG P.505 no decoup.
12
1
2
CC98 close to CP17
PCH Internal VRM
close to BT24
+1.0V_MPHYGT
LC4
BLM18EG221TN1D_2P~D
12
RC845
@RF@
0_0201_5%
CC77
RF@
2.2P_0201_25V
+1.8V_PRIM
1.8V @0. 696 A
1
CC98
2
+VCCPDSW_1P05
PDG0.8 P.505 0402
1.05 V@3 .10 8A
1
2
2
RF@
2.2P_0201_25V
1
1U_0201_6.3V6M
PDG0.8 P.504 0402 reserve
0801 Confirmed with
Intel can change to 0201
1.05 V@0 .02 4A
1
CC65
2
1U_0201_6.3V6M
PDG P.504 0603
CC71
22U_0603_6.3V6M
CC95
+1.0V_MPHYGT
+1.0V_PRIM
CC67/CC68 close t o BP20
1
CC68
2
PDG0.8 P.504 0402
0801 Confirmed with
Intel can change to 0201*2
+3.3V_ALW_PCH
+1.0V_PRIM_CORE
0801 Confirmed with
Intel can change to 0201
VCCHDA
+1.0V_AMPHYPLL
+1.0V_APLL
+1.0V_PRIM
+3.3V_ALW_DSW
1031 change
+3.3V_ALW_PCH
+1.0V_PRIM
+1.0V_PRIM
+1.0V_APLL
1.05 V@1 .62 5A
1
CC67
2
1U_0201_6.3V6M
1U_0201_6.3V6M
3.3V @0. 199 A
1.05 V@4 .26 A
CC66 close to BV18
1
CC66
2
@
1U_0201_6.3V6M
1.05 V@0 .10 2A
1.05 V@0 .15 2A
1.05 V@0 .10 2A
1.05 V@0 .12 9A
3.3V @0. 001 A
3.3V @0. 006 A
3.3V @0. 002 A
CPU@
UC1P
BP20
VCCPRIM_1P05_1
BW16
VCCPRIM_1P05_9
BW18
VCCPRIM_1P05_10
BW19
VCCPRIM_1P05_11
BY16
VCCPRIM_1P05_12
CA14
VCCPRIM_1P05_14
CC15
VCCPRIM_1P8_1
CD15
VCCPRIM_1P8_4
CD16
VCCPRIM_1P8_5
CP17
VCCPRIM_1P8_8
CB22
VCCPRIM_3P3_4
CB23
VCCPRIM_3P3_5
CC22
VCCPRIM_3P3_6
CC23
VCCPRIM_3P3_7
CD22
VCCPRIM_3P3_8
CD23
VCCPRIM_3P3_9
CP29
VCCPRIM_3P3_10
BU15
VCCPRIM_CORE1
BU22
VCCPRIM_CORE2
BV15
VCCPRIM_CORE3
BV16
VCCPRIM_CORE4
BV18
VCCPRIM_CORE5
BV19
VCCPRIM_CORE6
BV20
VCCPRIM_CORE7
BV22
VCCPRIM_CORE8
BW20
VCCPRIM_CORE9
BW22
VCCPRIM_CORE10
CA12
VCCPRIM_CORE11
CA16
VCCPRIM_CORE12
CA18
VCCPRIM_CORE13
CA19
VCCPRIM_CORE14
CA20
VCCPRIM_CORE15
CB12
VCCPRIM_CORE16
CB14
VCCPRIM_CORE17
CB15
VCCPRIM_CORE18
BT24
VCCDSW_1P05
BU14
VCCAPLL_1P05_4
BV12
VCCPRIM_MPHY_1P05_1
BW12
VCCPRIM_MPHY_1P05_3
BW14
VCCPRIM_MPHY_1P05_4
BY12
VCCPRIM_MPHY_1P05_5
BY14
VCCPRIM_MPHY_1P05_6
BV2
VCCAMPHYPLL_1P05
BR15
VCCAPLL_1P05_2
CC12
VCCDUSB_1P05
BR24
VCCDSW_3P3_1
BT20
VCCHDA
BV23
VCCSPI
BT18
VCCPRIM_1P05_4
BT19
VCCPRIM_1P05_5
BU18
VCCPRIM_1P05_7
BU19
VCCPRIM_1P05_8
BT22
VCCPRIM_1P05_6
BP22
VCCPRIM_1P05_2
BV14
VCCPRIM_MPHY_1P05_2
WHL-U42_BGA1528
CPU POWER 4 OF 4
16 of 20
VCCPRIM_3P3_3
VCCRTC
VCCPRIM_1P05_13
DCPRTC
VCCPRIM_1P05_3
VCCAPLL_1P05_3
VCCA_BCLK_1P05
VCCAPLL_1P05_1
VCCA_SRC_1P05
VCCA_XTAL_1P05
VCCDPHY_1P24_2
VCCDPHY_1P24_4
VCCDPHY_1P24_1
VCCDPHY_1P24_3
VCCDPHY_1P24_5
VCCDSW_3P3_2
VCCA_19P2_1P05
VCCPRIM_1P8_2
VCCPRIM_1P8_3
VCCPRIM_1P8_6
VCCPRIM_1P8_7
VCCPRIM_1P8_9
VCCPRIM_3P3_2
VCCPRIM_3P3_1
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
CB16
BR23
BY20
BP24
BR20
BT12
BP14
BR14
BU12
CP5
BY24
CA24
BY23
CA23
CP25
BT23
BR12
CC18
CC19
CD18
CD19
CP23
BW23
BP23
CB36
CB35
3.3V @0. 199 A
PDG0.8 P.505
0402 reserve
1.05 V@0 .00 9A
1.05 V@0 .10 2A
1.05 V@0 .03 4A
1.05 V@0 .03 4A
1.24 V@0 .61 A
PCH Internal VRM
1.05 V@0 .02 7A
3.3V @0. 199 A
3.3V @0. 199 A
+3.3V_ALW_PCH
1
CC75
2
@
1U_0201_6.3V6M
+1.0V_PRIM
PDG P.505 0201 reserve
+1.0V_PRIM
+1.0V_APLL
+1.0V_PRIM
+1.0V_APLL
+1.0V_PRIM
+1.0V_CLK
+VCCLDOSRAM_1P24
+1.0V_PRIM
+3.3V_ALW_PCH
+3.3V_ALW_PCH
CORE_VID0 <87>
CORE_VID1 <87>
CC75 close to CP29
0801 Confirmed with
Intel can change to 0201,
Follow MOW Delete CC74
DCPRTC
1
2
PCH Internal VRM
close to BP24
CAD NOTE: CAPs
1.8V @0. 696 A
3.0V @0. 002 A
CC76
@
1U_0201_6.3V6M
+VCCDPHY_1P24
+1.8V_PRIM
+RTC_CELL_PCH
1
1
CC72
CC73
2
2
1U_0201_6.3V6M
0.1U_0201_6.3V6K
PDG0.8 P.505 0402
0801 Confirmed with
Intel can change to 0201
PCH Internal VRM
1
close to CP25
PDG P.505 0402
CC84
2
4.7U_0402_6.3V6M
+3.3V_ALW_DSW
3.3V @0. 199 A
1
CC1464 close to CP23
PDG0.8 P.505 0402 reserve
CC1464
2
0801 Confirmed with
Intel can change to 0201
@
1U_0201_6.3V6M
CC72/CC73 close to BR23
1
CC1463 close to BR24
CC1463
2
PDG0.8 P.505 0402 reserve
0801 Confirmed with
@
Intel can change to 0201
1U_0201_6.3V6M
+3.3V_ALW_DSW+3.3V_ALW_PCH
12
RC4400_0402_5%@NDS3@
12
RC2140_0201_5%@
+3.3V_ALW_DSW_R
12
RC4390_0402_5%DS3@
22U_0402_6.3V6M
22U_0402_6.3V6M
@
@
1
1
CC280
CC279
2
2
RC439
RC440RE53 6RC215R C441RC44 2
AA
Support DS3
No Support DS3
VVV
X
VVV
XX
X
X
'V' mean POP, 'X' mean DE-POP
5
QC7 c hange to SB00000SS00
For Merion layout l imit height
QC7
DS3@
NTK3139PT1G_SOT723-3
13
D
2
0.1U_0402_25V6K
12
12
@
CC340
X
L2N7002WT1G_SC-70-3
13
D
DS3@
S
QC6
+3.3V_ALW
S
499K_0402_1%
DS3@
12
G
RC432
49.9K_0402_1%
DS3@
RC433
2
G
100K_0402_5%
RC431
12
VCCDSW_EN_GPIO <11>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF E NGINEERING DRAWING A ND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT M AY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size
Size
Size
Date:Sheetof
Date:Sheetof
Date:Sheetof
Compal Electronics, Inc.
CPU(13/14)PCH PWR
CPU(13/14)PCH PWR
CPU(13/14)PCH PWR
Document NumberRe v
Document NumberRe v
Document NumberRe v
LA-G871P
LA-G871P
LA-G871P
1
18109Tuesday, March 05, 2019
18109Tuesday, March 05, 2019
18109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 19
5
4
3
2
1
CPU@
DD
CC
BB
CR34
VSS_1
BT5
VSS_2
BY5
VSS_3
CP35
VSS_4
CM37
VSS_5
CK37
VSS_6
AW1
VSS_7
CM1
VSS_8
BD6
VSS_9
AY4
VSS_10
B34
VSS_11
E35
VSS_12
A4
VSS_13
AE24
VSS_14
AE26
VSS_15
AF25
VSS_16
AG24
VSS_17
AG26
VSS_18
AH24
VSS_19
AH25
VSS_20
B2
VSS_21
B36
VSS_22
C36
VSS_23
C37
VSS_24
CN1
VSS_25
CN2
VSS_26
CN37
VSS_27
CP2
VSS_28
D1
VSS_29
A32
VSS_30
F33
VSS_31
A3
VSS_32
BJ7
VSS_33
CJ36
VSS_34
A36
VSS_35
BK10
VSS_36
CJ4
VSS_37
AB27
VSS_38
BK2
VSS_39
CK1
VSS_40
AB3
VSS_41
BK28
VSS_42
AB30
VSS_43
BK3
VSS_44
CK4
VSS_45
AB33
VSS_46
BK33
VSS_47
CK7
VSS_48
AB36
VSS_49
BK4
VSS_50
CL2
VSS_51
AB4
VSS_52
BK7
VSS_53
CM13
VSS_54
AB7
VSS_55
BL25
VSS_56
CM17
VSS_57
AC10
VSS_58
BL28
VSS_59
CM21
VSS_60
AC27
VSS_61
BL29
VSS_62
CM25
VSS_63
AC30
VSS_64
BL30
VSS_65
CM29
VSS_66
BL31
VSS_67
CM31
VSS_68
AD33
VSS_69
BL32
VSS_70
CM33
VSS_71
AD35
VSS_72
WHL -U42_BGA1528
UC1R
GND 1 OF 3
17 of 20
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
BL7
AE25
BM33
CM5
AE27
BM35
CM9
AE30
BM36
CN13
AE7
BM9
CN17
AF27
BN30
CN21
AF3
BN7
CN25
AF30
CN29
AF33
BP15
AF36
AF4
CN5
AF7
BP25
CN9
AG10
BP3
CP1
BP32
CP11
AH27
BP33
CP13
AH28
BP4
CP15
AH29
BP7
CP19
AH30
CP21
AH31
BR19
CP27
AH33
BR25
AH35
CP37
AJ25
BT15
AJ28
BT16
CP9
AJ7
CR2
AK3
CR36
AK33
D21
AK36
BT25
D25
AK4
BT28
AL28
BT33
D5
AL29
BT35
D6
AL32
BT36
D8
AL7
D9
AM10
BU11
E23
AM28
E27
AM33
BU23
E29
AM35
BU24
E31
BU25
E33
AN25
BU7
E9
AN28
BV11
F12
AN29
F15
AN30
F18
AN31
BV3
F2
AN7
BV31
F21
AN8
BV33
F24
BV4
F3
AP3
BW11
F4
AP33
BW15
G21
AP36
G27
AP4
G33
AR28
G35
G36
AT33
BW24
G9
AT35
H21
AT36
BW7
H27
AT4
BY11
AU10
BY15
H9
AU28
BY22
J12
AU29
J15
WHL -U42_BGA1528
CPU@
UC1S
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
GND 2 OF 3
18 of 20
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
BY25
J18
AU32
BY28
J21
AV25
BY33
J24
AV28
BY35
J33
AV3
BY36
J36
AV33
J6
AV36
C1
K21
AV4
C21
K22
AV6
C25
K24
AV8
C29
K25
AW28
C33
K27
AW29
C4
K28
AW3
C9
K29
AW30
CA11
K3
AW31
CA15
K30
AY33
CA22
K31
AY35
K32
B12
K4
B15
CA25
K9
B18
CB11
L27
B21
L33
B23
L35
B25
CB18
L36
B27
CB19
L6
B29
CB2
N25
B31
CB20
N27
CB25
CPU@
UC1T
N6
VSS_290
B37
VSS_291
CB3
VSS_292
P10
VSS_293
B5
VSS_294
CB33
VSS_295
P3
VSS_296
B7
VSS_297
CB4
VSS_298
P33
VSS_299
B9
VSS_300
CB7
VSS_301
P36
VSS_302
BA10
VSS_303
CC11
VSS_304
P4
VSS_305
BA28
VSS_306
P7
VSS_307
BA3
VSS_308
CC20
VSS_309
R27
VSS_310
BB3
VSS_311
CC25
VSS_312
R28
VSS_313
BB33
VSS_314
CC28
VSS_315
R29
VSS_316
BB36
VSS_317
CC31
VSS_318
R30
VSS_319
BB4
VSS_320
CC7
VSS_321
R31
VSS_322
BC25
VSS_323
CD11
VSS_324
T27
VSS_325
CD12
VSS_326
T30
VSS_327
BC29
VSS_328
CD14
VSS_329
T33
VSS_330
T35
VSS_331
BC32
VSS_332
CD24
VSS_333
T36
VSS_334
CD25
VSS_335
T7
VSS_336
BC8
VSS_337
CE33
VSS_338
U26
VSS_339
BD28
VSS_340
CE35
VSS_341
U7
VSS_342
BD33
VSS_343
CE36
VSS_344
V26
VSS_345
BD35
VSS_346
CE7
VSS_347
V27
VSS_348
BD36
VSS_349
CF11
VSS_350
V3
VSS_351
BE10
VSS_352
CF14
VSS_353
V30
VSS_354
BE28
VSS_355
CF19
VSS_356
V33
VSS_357
BE29
VSS_358
CF2
VSS_359
V36
VSS_360
BE3
VSS_361
WHL -U42_BGA1528
GND 3 OF 3
19 of 20
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
VSS_396
VSS_397
VSS_398
VSS_399
VSS_400
VSS_401
VSS_402
VSS_403
VSS_404
VSS_405
VSS_406
VSS_407
VSS_408
VSS_409
VSS_410
VSS_411
VSS_412
VSS_413
VSS_414
VSS_415
VSS_416
VSS_417
VSS_418
VSS_419
VSS_420
VSS_421
VSS_422
VSS_423
VSS_424
VSS_425
VSS_426
VSS_427
VSS_428
VSS_429
VSS_430
VSS_431
VSS_432
VSS_433
CF23
V4
BE30
CF28
W10
BE31
CF3
W27
CF4
W30
BF3
CG33
W7
BF33
CG7
BF36
Y26
BF4
CH31
Y27
BG25
Y30
BG28
CJ11
Y33
CJ14
Y35
BH28
CJ19
Y7
BH29
CJ23
BH32
CJ28
BH33
CJ33
BH35
CJ35
BP19
BR16
BY18
BY19
CC16
BU16
CC14
BR22
BU20
CD20
BT14
BP12
CB24
CC24
J5
U24
BD7
AR4
AU4
AW4
BA6
BC4
BE4
BE8
BA4
BD4
BG4
CJ2
CJ3
AM5
CM4
AC5
AG5
CR6
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
MCP(14/14)VSS
MCP(14/14)VSS
MCP(14/14)VSS
LA-G871P
LA-G871P
LA-G871P
19109Tuesday, March 05, 2 019
19109Tuesday, March 05, 2 019
19109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 20
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
SOC or PCH / FCH
SOC or PCH / FCH
SOC or PCH / FCH
LA-G871P
LA-G871P
LA-G871P
20109Tuesday, March 05, 2 019
20109Tuesday, March 05, 2 019
20109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 21
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
SOC or PCH / FCH
SOC or PCH / FCH
SOC or PCH / FCH
LA-G871P
LA-G871P
LA-G871P
21109Tuesday, March 05, 2 019
21109Tuesday, March 05, 2 019
21109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 22
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
SOC or PCH / FCH
SOC or PCH / FCH
SOC or PCH / FCH
LA-G871P
LA-G871P
LA-G871P
22109Tuesday, March 05, 2 019
22109Tuesday, March 05, 2 019
22109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 23
1
+0.6V_DDR_ VTT
+2.5V_MEM
H_THERMTRIP# <14,24,59>
+DDR_VREF_CA
0.022U_0402_16V7K
CD31
For DDR4
12
2
+3.3V_RUN_ DIMM1
+DDR_VREF _A_CA
0.6V_DDR_VTT_ON <8 6>
+1.2V_MEM
+3.3V_RUN
CONN@
JDIMM1B
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
255
VDDSPD
164
VREFCA
1
VSS1
2
VSS2
5
VSS3
6
VSS4
9
VSS5
10
VSS6
14
VSS7
15
VSS8
18
VSS9
19
VSS10
22
VSS11
23
VSS12
26
VSS13
27
VSS14
30
VSS15
31
VSS16
35
VSS17
36
VSS18
39
VSS19
40
VSS20
43
VSS21
44
VSS22
47
VSS23
48
VSS24
51
VSS25
52
VSS26
56
VSS27
57
VSS28
60
VSS29
61
VSS30
64
VSS31
65
VSS32
68
VSS33
69
VSS34
72
VSS35
73
VSS36
77
VSS37
78
VSS38
81
VSS39
82
VSS40
85
VSS41
86
VSS42
89
VSS43
90
VSS44
93
VSS45
94
VSS46
98
VSS47
262
GND1
264
NPTH2
LOTES_ADDR02 06-P001A
JDIMM1_EVE NT#
+DDR_VREF_A_CA
REVERSE
RD141K _0402_5%@
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VPP1
VPP2
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
GND2
NPTH1
12
+1.2V_MEM
1K_0402_1%
12
1K_0402_1%
12
+1.2V_MEM
141
142
147
148
153
154
159
160
163
258
VTT
257
259
99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252
261
263
RD15
12
RD172_ 0402_1%
RD16
12
24.9_0402_1%
12
RD18
5
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..16]<7>
Layout Note:
Place near JDIMM1
DD
CC
+1.2V_MEM
12
+1.2V_MEM
1
2
10U_0603_10V6M
CD1
12
1U_0201_6.3V6M
1
CD9
2
10U_0603_10V6M
10U_0603_10V6M
CD3
CD2
12
12
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
CD11
CD10
2
2
0801 Confirmed with
Intel 1U can change to 0201
Layout Note:
Place near
JDIMM1.258
Refence WHL R VP rev0 .7
10U_0603_10V6M
10U_0603_10V6M
CD4
CD5
12
12
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
CD13
CD12
2
2
10U_0603_10V6M
1U_0201_6.3V6M
Refence WHL R VP rev0 .7
+0.6V_DDR_VTT
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0603_10V6M
@
12
12
CD63
BB
DIMM Select
SA01SA1
0
DIMM1
*
DIMM2
1
0
DIMM3
1
DIMM4
AA
1U_0201_6.3V6M
10U_0603_10V6M
1
1
CD23
CD24
CD22
2
2
0801 Confirmed with
Intel 1U can change to 0201
SA2
0
0
0
0
0
0
1
1
CD69
2
+3.3V_RUN
12
12
Merion Limit height
CD17 change to SGA0000AM00 H=1.0mm(MAX)
WHL_U PDG rev0.8 P.92
VDDQ:
4 near each side of the DIMM
10U_0603_10V6M
10U_0603_10V6M
220U_D7_2VM_R4.5M
connector close to VDD pins
16x 10uF 0603
@
1
16x 1uF 0402
CD8
CD7
CD6
12
CD14
1
2
RD4
@
0_0201_5%
RD5
@
0_0201_5%
1U_0201_6.3V6M
1
2
1U_0201_6.3V6M
CD70
CD17
12
+
Placehold er
1x 330uF 7343
2
VPP :
DIMM pin side, 1 p er DIMM
2x 10uF 0603
2x 1uF 0402
+2.5V_MEM
1U_0201_6.3V6M
1
CD15
CD16
2
WHL_U PDG rev0.8 P.92
VTT:
Place on VTT plane close to SODIMM
2x 10uF 0603(1 cap stuffed, 1 placeholder)
4x 1uF 0402
VDD SP D:
Place close to DIMM
2x 0.1uF 0402
2x 2.2uF 0402
+3.3V_RUN+3.3V_ RUN
12
RD6
@
0_0201_5%
12
RD7
@
0_0201_5%
1U_0201_6.3V6M
1
2
0801 Confirmed with
Intel 1U can change to 0201
+3.3V_RUN
12
RD10
@
0_0603_5%
+3.3V_RUN_ DIMM1
2.2U_0402_6.3V6M
1
1
CD27
2
2
12
RD8
@
0_0201_5%
DIMM1_SA0
DIMM1_SA1
DIMM1_SA2
12
RD9
@
0_0201_5%
CD18
0.1U_0201_10V6K
CD28
1U_0201_6.3V6M
1
CD19
2
+DDR_VREF _A_CA
1
2
4
DDR_A_CLK 0<7>
DDR_A_CLK #0<7>
DDR_A_CLK 1<7>
DDR_A_CLK #1<7>
DDR_A_CKE 0<7>
DDR_A_CKE 1<7>
DDR_A_CS# 0<7>
DDR_A_CS# 1<7>
DDR_A_ODT0<7>
DDR_A_ODT1<7>
DDR_A_BG0<7>
10U_0603_10V6M
10U_0603_10V6M
1
CD21
CD20
2
1
CD29
@
1
2
0.1U_0201_6.3V6K
CD25
0.1U_0402_2 5V6
1
2
2
2.2U_0402_6.3V6M
CD26
12
RD120_ 0201_5%@
DDR_A_BG1<7>
DDR_A_ACT#< 7>
DDR_A_PAR ITY<7>
DDR_A_ALE RT#<7>
DDR_XDP_W AN_SMB DAT<8 ,24,79>
DDR_XDP_W AN_SMB CLK<8 ,24,79>
+1.2V_MEM
DDR_A_CLK 0
DDR_A_CLK #0
DDR_A_CLK 1
DDR_A_CLK #1
DDR_A_CKE 0
DDR_A_CKE1
DDR_A_CS# 0
DDR_A_CS# 1
1
T50PA D~D @
1
T51PA D~D @
DDR_A_ODT0
DDR_A_ODT1
DDR_A_BG0
DDR_A_BG1
DDR_A_BA0
DDR_A_BA0<7>
DDR_A_BA1
DDR_A_BA1<7>
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA1 0
DDR_A_MA1 1
DDR_A_MA1 2
DDR_A_MA1 3
DDR_A_MA1 4
DDR_A_MA1 5
DDR_A_MA1 6
DDR_A_ACT#
DDR_A_PAR ITY
DDR_A_ALE RT#
JDIMM1_EVE NT#
DDR_DRAMRS T#_R
DIMM1_SA2
DIMM1_SA1
DIMM1_SA0
+1.2V_MEM
470_0402_1%
12
RD11
DDR_DRAMRS T#
DDR_DRAMRST# <7>DDR_DRAMRST#_R<24>
3
Link LOTES_ADDR0206-P001A02 done 0410
CONN@
JDIMM1A
137
CK0(T)
139
CK0#(C)
138
CK1(T)
140
CK1#(C)
109
CKE0
110
CKE1
149
S0#
157
S1#
162
S2#/C0
165
S3#/C1
155
ODT0
161
ODT1
115
BG0
113
BG1
150
BA0
145
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_AP
120
A11
119
A12
158
A13
151
A14_WE#
156
A15_CAS#
152
A16_RAS#
114
ACT#
143
PARITY
116
ALERT#
134
EVENT#
108
RESET#
254
SDA
253
SCL
166
SA2
260
SA1
256
SA0
92
CB0_NC
91
CB1_NC
101
CB2_NC
105
CB3_NC
88
CB4_NC
87
CB5_NC
100
CB6_NC
104
CB7_NC
97
DQS8(T)
95
DQS8#(C)
12
DM0#/DBI0#
33
DM1#/DBI1#
54
DM2#/DBI2#
75
DM3#/DBI3#
178
DM4#/DBI4#
199
DM5#/DBI5#
220
DM6#/DBI6#
241
DM7#/DBI7#
96
DM8#/DBI8#
LOTES_ADDR02 06-P001A
REVERSE
DQS0(T)
DQS0#(C)
DQS1(T)
DQS1#(C)
DQS2(T)
DQS2#(C)
DQS3(T)
DQS3#(C)
DQS4(T)
DQS4#(C)
DQS5(T)
DQS5#(C)
DQS6(T)
DQS6#(C)
DQS7(T)
DQS7#(C)
DDR_VTT_CTRL<7>
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
8
DQ0
7
DQ1
20
DQ2
21
DQ3
4
DQ4
3
DQ5
16
DQ6
17
DQ7
13
11
28
DQ8
29
DQ9
41
42
24
25
38
37
34
32
50
49
62
63
46
45
58
59
55
53
70
71
83
84
66
67
79
80
76
74
174
173
187
186
170
169
183
182
179
177
195
194
207
208
191
190
203
204
200
198
216
215
228
229
211
212
224
225
221
219
237
236
249
250
232
233
245
246
242
240
DDR_A_D2
DDR_A_D5
DDR_A_D1
DDR_A_D7
DDR_A_D0
DDR_A_D4
DDR_A_D6
DDR_A_D3
DDR_A_DQS0
DDR_A_DQS# 0
DDR_A_D8
DDR_A_D13
DDR_A_D15
DDR_A_D11
DDR_A_D12
DDR_A_D10
DDR_A_D9
DDR_A_D14
DDR_A_DQS1
DDR_A_DQS# 1
DDR_A_D32
DDR_A_D36
DDR_A_D34
DDR_A_D35
DDR_A_D37
DDR_A_D33
DDR_A_D39
DDR_A_D38
DDR_A_DQS4
DDR_A_DQS# 4
DDR_A_D41
DDR_A_D45
DDR_A_D46
DDR_A_D43
DDR_A_D40
DDR_A_D44
DDR_A_D42
DDR_A_D47
DDR_A_DQS5
DDR_A_DQS# 5
DDR_A_D29
DDR_A_D25
DDR_A_D30
DDR_A_D26
DDR_A_D28
DDR_A_D24
DDR_A_D27
DDR_A_D31
DDR_A_DQS3
DDR_A_DQS# 3
DDR_A_D23
DDR_A_D16
DDR_A_D22
DDR_A_D20
DDR_A_D18
DDR_A_D19
DDR_A_D17
DDR_A_D21
DDR_A_DQS2
DDR_A_DQS# 2
DDR_A_D52
DDR_A_D49
DDR_A_D55
DDR_A_D51
DDR_A_D48
DDR_A_D53
DDR_A_D54
DDR_A_D50
DDR_A_DQS6
DDR_A_DQS# 6
DDR_A_D57
DDR_A_D60
DDR_A_D62
DDR_A_D59
DDR_A_D61
DDR_A_D56
DDR_A_D63
DDR_A_D58
DDR_A_DQS7
DDR_A_DQS# 7
1
NC
2
A
3
GND
74AUP1G07S E-7_TSSOP5
+DDR_VREF _A_CA
+1.2V_MEM
UD1
5
4
Y
1 2
CD32@0.1U_0201_10V6K
RD19100K_0402_5%
VCC
6/8 Change to SA00007WE00 DII
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
2
Title
Size
Size
Size
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
DDR4 DIMMA
DDR4 DIMMA
DDR4 DIMMA
Document Num berRe v
Document Num berRe v
Document Num berRe v
LA-G871P
LA-G871P
LA-G871P
1
23109Tuesday, Marc h 05, 2019
23109Tuesday, Marc h 05, 2019
23109Tuesday, Marc h 05, 2019
1.0
1.0
1.0
Page 24
5
DDR_B_DQS#[0..7]<7>
DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>
DDR_B_MA[0..16]<7>
4
3
2
1
For DDR4
Link LOTES_ADDR0206-P001A02 done 0410
CONN@
JDIMM2A
REVERSE
137
CK0(T)
139
CK0#(C)
138
CK1(T)
140
CK1#(C)
109
CKE0
110
CKE1
149
S0#
157
S1#
162
1
1
S2#/C0
165
S3#/C1
155
ODT0
161
ODT1
115
BG0
113
BG1
150
BA0
145
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_AP
120
A11
119
A12
158
A13
151
A14_WE#
156
A15_CAS#
152
A16_RAS#
114
ACT#
143
PARITY
116
ALERT#
134
EVENT#
108
RESET#
254
SDA
253
SCL
166
SA2
260
SA1
256
SA0
92
CB0_NC
91
CB1_NC
101
CB2_NC
105
CB3_NC
88
CB4_NC
87
CB5_NC
100
CB6_NC
104
CB7_NC
97
DQS8(T)
95
DQS8#(C)
12
DM0#/DBI0#
33
DM1#/DBI1#
54
DM2#/DBI2#
75
DM3#/DBI3#
178
DM4#/DBI4#
199
DM5#/DBI5#
220
DM6#/DBI6#
241
DM7#/DBI7#
96
DM8#/DBI8#
LOTES_ADDR02 06-P001A
8
DQ0
7
DQ1
20
DQ2
21
DQ3
4
DQ4
3
DQ5
16
DQ6
17
DQ7
13
DQS0(T)
11
DQS0#(C)
28
DQ8
29
DQ9
41
DQ10
42
DQ11
24
DQ12
25
DQ13
38
DQ14
37
DQ15
34
DQS1(T)
32
DQS1#(C)
50
DQ16
49
DQ17
62
DQ18
63
DQ19
46
DQ20
45
DQ21
58
DQ22
59
DQ23
55
DQS2(T)
53
DQS2#(C)
70
DQ24
71
DQ25
83
DQ26
84
DQ27
66
DQ28
67
DQ29
79
DQ30
80
DQ31
76
DQS3(T)
74
DQS3#(C)
174
DQ32
173
DQ33
187
DQ34
186
DQ35
170
DQ36
169
DQ37
183
DQ38
182
DQ39
179
DQS4(T)
177
DQS4#(C)
195
DQ40
194
DQ41
207
DQ42
208
DQ43
191
DQ44
190
DQ45
203
DQ46
204
DQ47
200
DQS5(T)
198
DQS5#(C)
216
DQ48
215
DQ49
228
DQ50
229
DQ51
211
DQ52
212
DQ53
224
DQ54
225
DQ55
221
DQS6(T)
219
DQS6#(C)
237
DQ56
236
DQ57
249
DQ58
250
DQ59
232
DQ60
233
DQ61
245
DQ62
246
DQ63
242
DQS7(T)
240
DQS7#(C)
H_THERMTRIP# <14,23,5 9>
DDR_B_D1
DDR_B_D4
DDR_B_D6
DDR_B_D7
DDR_B_D0
DDR_B_D5
DDR_B_D3
DDR_B_D2
DDR_B_DQS0
DDR_B_DQS# 0
DDR_B_D13
DDR_B_D11
DDR_B_D14
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D12
DDR_B_D15
DDR_B_DQS1
DDR_B_DQS# 1
DDR_B_D32
DDR_B_D37
DDR_B_D38
DDR_B_D35
DDR_B_D36
DDR_B_D33
DDR_B_D34
DDR_B_D39
DDR_B_DQS4
DDR_B_DQS# 4
DDR_B_D41
DDR_B_D47
DDR_B_D43
DDR_B_D42
DDR_B_D45
DDR_B_D46
DDR_B_D40
DDR_B_D44
DDR_B_DQS5
DDR_B_DQS# 5
DDR_B_D17
DDR_B_D20
DDR_B_D22
DDR_B_D19
DDR_B_D16
DDR_B_D21
DDR_B_D23
DDR_B_D18
DDR_B_DQS2
DDR_B_DQS# 2
DDR_B_D25
DDR_B_D29
DDR_B_D27
DDR_B_D30
DDR_B_D24
DDR_B_D28
DDR_B_D26
DDR_B_D31
DDR_B_DQS3
DDR_B_DQS# 3
DDR_B_D48
DDR_B_D49
DDR_B_D51
DDR_B_D54
DDR_B_D52
DDR_B_D53
DDR_B_D50
DDR_B_D55
DDR_B_DQS6
DDR_B_DQS# 6
DDR_B_D57
DDR_B_D60
DDR_B_D59
DDR_B_D63
DDR_B_D61
DDR_B_D56
DDR_B_D58
DDR_B_D62
DDR_B_DQS7
DDR_B_DQS# 7
+DDR_VREF _B_CA
+3.3V_RUN_ DIMM2
+DDR_VREF _B_CA
+1.2V_MEM
+DDR_VREF_B_CA
CONN@
JDIMM2B
REVERSE
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
255
VDDSPD
164
VREFCA
1
VSS1
2
VSS2
5
VSS3
6
VSS4
9
VSS5
10
VSS6
14
VSS7
15
VSS8
18
VSS9
19
VSS10
22
VSS11
23
VSS12
26
VSS13
27
VSS14
30
VSS15
31
VSS16
35
VSS17
36
VSS18
39
VSS19
40
VSS20
43
VSS21
44
VSS22
47
VSS23
48
VSS24
51
VSS25
52
VSS26
56
VSS27
57
VSS28
60
VSS29
61
VSS30
64
VSS31
65
VSS32
68
VSS33
69
VSS34
72
VSS35
73
VSS36
77
VSS37
78
VSS38
81
VSS39
82
VSS40
85
VSS41
86
VSS42
89
VSS43
90
VSS44
93
VSS45
94
VSS46
98
VSS47
262
GND1
264
NPTH2
LOTES_ADDR02 06-P001A
+1.2V_MEM
1K_0402_1%
12
RD28
RD302_ 0402_1%
1K_0402_1%
12
RD29
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VTT
VPP1
VPP2
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
GND2
NPTH1
12
+1.2V_MEM
141
142
147
148
153
154
159
160
163
258
257
259
99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252
261
263
12
24.9_0402_1%
12
RD31
+DDR_VREF_B_DQ
0.022U_0402_16V7K
CD62
+0.6V_DDR_ VTT
+2.5V_MEM
DDR_DRAMRS T#_R
+1.2V_MEM
JDIMM2_EVE NT#
DDR_B_CLK 0
DDR_B_CLK #0
DDR_B_CLK 1
DDR_B_CLK #1
DDR_B_CKE 0
DDR_B_CKE 1
DDR_B_CS# 0
DDR_B_CS# 1
T54PA D~D @
T55PA D~D @
DDR_B_ODT0
DDR_B_ODT1
DDR_B_BG0
DDR_B_BG1
DDR_B_BA0
DDR_B_BA1
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA1 0
DDR_B_MA1 1
DDR_B_MA1 2
DDR_B_MA1 3
DDR_B_MA1 4
DDR_B_MA1 5
DDR_B_MA1 6
DDR_B_ACT#
DDR_B_PAR ITY
DDR_B_ALE RT#
JDIMM2_EVE NT#
DIMM2_SA2
DIMM2_SA1
DIMM2_SA0
12
RD271K _0402_5%@
Layout Note:
DD
+1.2V_MEM
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
CD35
CD33
CD34
CD36
12
12
12
12
+1.2V_MEM
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
CD41
2
2
CC
+0.6V_DDR_VTT
10U_0603_10V6M
@
12
CD66
BB
1U_0201_6.3V6M
1
1
CD43
CD42
CD44
2
2
0801 Confirmed with
Intel 1U can change to 0201
Layout Note:
Place near
JDIMM2.258
Refence WHL R VP rev0 .7
1U_0201_6.3V6M
10U_0603_10V6M
1
1
12
CD55
CD54
2
2
0801 Confirmed with
Intel 1U can change to 0201
DIMM Select
SA2
SA01SA1
DIMM1
DIMM2
DIMM3
*
DIMM4
0
0
0
0
0
1
0
0
0
1
1
Place near JDIMM2
Refence WHL R VP rev0 .7
10U_0603_10V6M
10U_0603_10V6M
CD37
CD38
12
12
12
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
1
CD46
CD45
2
2
2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
CD71
CD56
2
2
+3.3V_RUN
12
RD20
@
0_0201_5%
12
RD21
@
0_0201_5%
Merion Limit height
CD49 change to SGA0000AM00 H=1.0mm(MAX)
WHL_U PDG rev0.8 P.92
VDDQ:
4 near each side of the DIMM
10U_0603_10V6M
220U_D7_2VM_R4.5M
10U_0603_10V6M
CD39
12
1U_0201_6.3V6M
CD47
WHL_U PDG rev0.8 P.92
VTT:
Place on VTT plane close to SODIMM
2x 10uF 0603(1 cap stuffed, 1 placeholder)
4x 1uF 0402
VDD SP D:
Place close to DIMM
2x 0.1uF 0402
2x 2.2uF 0402
CD72
12
RD22
@
0_0201_5%
12
RD23
@
0_0201_5%
connector close to VDD pins
16x 10uF 0603(2 DIMMS TOTAL)
@
1
CD40
CD49
16x 1uF 0402(2 DIMMS TOTAL)
+
Placehold er
1x 330uF 7343
2
VPP :
DIMM pin side, 1 p er DIMM
2x 10uF 0603
2x 1uF 0402
+2.5V_MEM
1U_0201_6.3V6M
1
CD48
2
0801 Confirmed with
Intel 1U can change to 0201
+3.3V_RUN+3.3V_ RUN
12
RD24
@
0_0201_5%
DIMM2_SA0
DIMM2_SA1
DIMM2_SA2
12
RD25
@
0_0201_5%
1U_0201_6.3V6M
1
2
+3.3V_RUN
CD50
1U_0201_6.3V6M
1
CD51
2
12
RD26
@
0_0603_5%
+3.3V_RUN_DIMM2
2.2U_0402_6.3V6M
1
12
CD59
2
+DDR_VREF _B_CA
10U_0603_10V6M
10U_0603_10V6M
1
1
CD53
CD52
2
2
DDR_DRAMRS T#_R<23>
0.1U_0402_2 5V6
0.1U_0201_10V6K
CD60
2.2U_0402_6.3V6M
0.1U_0201_6.3V6K
1
1
CD58
CD57
2
2
CD61
@
DDR_DRAMRS T#_R
3
2
CEST523NC5VB_SOT-523-3
ESD@
DD1
1
1206 change
DD1 close to CD61
0821 ESD team request to add DD1.
1
2
DDR_B_CLK 0<7>
DDR_B_CLK #0<7>
DDR_B_CLK 1<7>
DDR_B_CLK #1<7>
DDR_B_CKE 0<7>
DDR_B_CKE 1<7>
DDR_B_CS# 0<7>
DDR_B_CS# 1<7>
DDR_B_ODT0<7>
DDR_B_ODT1<7>
DDR_B_BG0<7>
DDR_B_BG1<7>
DDR_B_BA0<7>
DDR_B_BA1<7>
DDR_B_ACT#< 7>
DDR_B_PAR ITY<7>
DDR_B_ALE RT#<7>
DDR_XDP_W AN_SMB DAT<8,23 ,79>
DDR_XDP_W AN_SMB CLK<8 ,23,79>
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
2
Title
Size
Size
Size
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
DDR4 DIMMB
DDR4 DIMMB
DDR4 DIMMB
Document Num berRe v
Document Num berRe v
Document Num berRe v
LA-G871P
LA-G871P
LA-G871P
1
24109Tuesday, Marc h 05, 2019
24109Tuesday, Marc h 05, 2019
24109Tuesday, Marc h 05, 2019
1.0
1.0
1.0
Page 25
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
DDR_2
DDR_2
DDR_2
LA-G871P
LA-G871P
LA-G871P
25109Tuesday, March 05, 2 019
25109Tuesday, March 05, 2 019
25109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 26
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
DDR_3
DDR_3
DDR_3
LA-G871P
LA-G871P
LA-G871P
26109Tuesday, March 05, 2 019
26109Tuesday, March 05, 2 019
26109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 27
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
DGPU
DGPU
DGPU
LA-G871P
LA-G871P
LA-G871P
27109Tuesday, March 05, 2 019
27109Tuesday, March 05, 2 019
27109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 28
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
DGPU
DGPU
DGPU
LA-G871P
LA-G871P
LA-G871P
28109Tuesday, March 05, 2 019
28109Tuesday, March 05, 2 019
28109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 29
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
DGPU
DGPU
DGPU
LA-G871P
LA-G871P
LA-G871P
29109Tuesday, March 05, 2 019
29109Tuesday, March 05, 2 019
29109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 30
5
DD
CC
4
3
2
1
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BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
DGPU
DGPU
DGPU
LA-G871P
LA-G871P
LA-G871P
30109Tuesday, March 05, 2 019
30109Tuesday, March 05, 2 019
30109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 31
5
DD
CC
4
3
2
1
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BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
DGPU
DGPU
DGPU
LA-G871P
LA-G871P
LA-G871P
31109Tuesday, March 05, 2 019
31109Tuesday, March 05, 2 019
31109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 32
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
DGPU
DGPU
DGPU
LA-G871P
LA-G871P
LA-G871P
32109Tuesday, March 05, 2 019
32109Tuesday, March 05, 2 019
32109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 33
5
DD
CC
4
3
2
1
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BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
DGPU
DGPU
DGPU
LA-G871P
LA-G871P
LA-G871P
33109Tuesday, March 05, 2 019
33109Tuesday, March 05, 2 019
33109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 34
5
DD
CC
4
3
2
1
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AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
DGPU
DGPU
DGPU
LA-G871P
LA-G871P
LA-G871P
34109Tuesday, March 05, 2 019
34109Tuesday, March 05, 2 019
34109Tuesday, March 05, 2 019
1
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1.0
1.0
Page 35
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DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
VRAM
VRAM
VRAM
LA-G871P
LA-G871P
LA-G871P
35109Tuesday, March 05, 2 019
35109Tuesday, March 05, 2 019
35109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 36
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DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
VRAM
VRAM
VRAM
LA-G871P
LA-G871P
LA-G871P
36109Tuesday, March 05, 2 019
36109Tuesday, March 05, 2 019
36109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 37
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CC
4
3
2
1
Reserve
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AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
DGPU_DC/DC Interface
DGPU_DC/DC Interface
DGPU_DC/DC Interface
LA-G871P
LA-G871P
LA-G871P
37109Tuesday, March 05, 2 019
37109Tuesday, March 05, 2 019
37109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 38
ISH_I2C1_ALS_ SDA
ISH_I2C1_ALS_ SCL
ISH_ALS_INT#
DV3
P2
1
N
P1
BAT54CTB_SOT-523
2
3
12
RV7330_0603_ 5%@
12
RV7320 _0603_5%@
1
RV7402.2K_020 1_5%
RV7412.2K_020 1_5%
RV7422.2K_020 1_5%
@
RV74310K_0201 _5%
@
RV74410K_0201 _5%
3
LCD_VCC_TEST_EN <58 >
2
ENVDD_PCH <6>
USB20_N6_R
2
USB20_P6_R
3
Merion14
Touchscreen power
+5V
Depop RV732,Pop RV733
12
12
12
12
12
+3.3V_RUN
+3.3V_RUN
+5V_RUN
+3.3V_RUN
3
PCH_PLTRST#_AND <11 ,42,52,68,70>
TS_INT# <9>
TS_I2C_SDA <9>
TS_I2C_SCL <9>
IR_CAM_DET# <9>
3MM_CAM_DET# <9>
TOUCH_SCREEN_PD#_R <14>
ISH_I2C1_ALS_SDA <9>
ISH_I2C1_ALS_SCL <9>
ISH_ALS_INT# <9>
P_SENSOR_PWR_SAVE# <9>
ISH_P_SENSOR_INT# <12>
+3.3V_ALS_PWR
FZ2
+13.5VB
+BL_PWR_SRC
1A_65V_T0603FF1000TM
1031 change
21
FV1
0.1U_0402_25V6
1
CV15
2
S
G
2
0212 change
QV2 change from SB00000NK00
to SB00000SI00
For parts shortage problem
TS_I2C_SCL
TS_I2C_SDA
3
2
CEST523NC5VB_SOT-523-3
ESD@
DZ10
1
ISH_I2C1_ALS_ SCL
ISH_I2C1_ALS_ SDA
3
2
CEST523NC5VB_SOT-523-3
ESD@
DZ21
1
+3.3V_ALS_PWR
1031 change,RZ1476 reserve for FUSE l ocation
+3.3V_RUN
12
RZ14760_0603_5%
WebCAM
3.3V_CAM_EN#<11>
For Touchscreen
3.3V_TS_EN<58>
PCH_3.3V_TS_EN<9>
For 2 LANE EDP & 5V_TSP
TS_I2C_SDA
TS_I2C_SCL
TS_INT#
TS_INT#
RF Request
TS_I2C_SDA
TS_I2C_SCL
LCDVDD POWER
+LCDVDD+EDP_VDD
PAD-OPEN1x1m
1
@
10U_0402_10 V6M
2
+3.3V_CAM
12
RZ3880_0201 _5%@
0212 change
QV7 change from SB00000NK00
to SB00000SI00
For parts shortage problem
12
RV3230 _0201_5%@
12
@
RV3240 _0201_5%
CA6RF@
82P_0402_50V8J
1
2
0.1U_0201_10V6K
1
@
2
DMIC0 <56>
DMIC_CLK0 <56>
120P_0402_50V8J
RF@
RF@
1
CV754
CV19
2
CA7
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
4
+LCDVDD
Reserve for EA
10K_0402_5%
RV8
12
10K_0402_5%
RV325
12
10K_0402_5%
RV734
12
Need change SP01001SS10
TOUCH SCREEN & IR CAMERA connector
CONN@
JIRTS1
1
1
2
2
TS_I2C_SDA
3
3
TS_I2C_SCL
4
4
5
5
6
6
7
7
8
8
9
9
ISH_I2C1_ALS_ SDA
10
ISH_I2C1_ALS_ SCL
10
11
11
ISH_ALS_INT#
12
12
P_SENSOR_ PWR_SA VE#
13
13
ISH_P_SENS OR_INT#
14
14
15
15
16
16
17
17
+13.5VB_IR
18
18
19
G1
20
G2
ACES_5020 8-0180N-P01
Link ACES_50208-0180N-P01 done 0323
0824 change footprint to ACES_50208-0180N-P01_18P-T-S
Backlight POWER
+13.5VB
1000P_0402_50V7K
270K_0402_5%
CV13
RV4
1 2
12
BL_PWR_SRC_ON
0.01U_0402_50V7K
1
2
Merion Limit height
DV13,DV14,DZ10,DZ21 change to H=0.9mm(MAX)
12
CV14
RV547K_0402_5%
EN_INVPW R<5 8>
DMIC_CLK0
DMIC0
3
2
CEST523NC5VB_SOT-523-3
ESD@
DV13
1
1206 change1206 ch ange
USB20_P6_ R
USB20_N6_ R
3
2
CEST523NC5VB_SOT-523-3
ESD@
DV14
1
1206 change1206 ch ange
1A_65V_T0603 FF1000TM
QV1
S
45
G
AO6405_TSOP6
3
21
1031 change
D
+BL_PW R_SRC_P
6
2
1
QV2
2N7002KTB_S OT523-3
13
D
CONN@
JEDP1
41
GND_1
42
GND_2
43
GND_3
44
GND_4
45
GND_5
46
GND_6
47
GND_7
48
GND_8
49
GND_9
50
GND_10
51
GND_11
52
GND_12
53
GND_13
54
GND_14
55
GND_15
56
GND_16
57
GND_17
58
DD
GND_18
59
GND_19
60
GND_20
61
GND_21
62
GND_22
63
GND_23
64
GND_24
65
GND_25
66
GND_26
67
GND_27
68
GND_28
69
GND_29
70
GND_30
71
GND_31
72
GND_32
73
GND_33
74
GND_34
I-PEX_20879-0 40E-01
5
+TS_PWR
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
USB20_N6_R
USB20_P6_R
12
RZ14700_0201_5%@ RF@
Pin15: LOOP_BACK
+BL_PWR_SRC
12
LV1
EMI@
DISP_ON
+LCDVDD
TOUCH_SCREEN _DET#
EDP_AUXN_C
EDP_AUXP_C
EDP_TXP0_C
EDP_TXN0_C
EDP_TXP1_C
EDP_TXN1_C
PRIVACY_ENABLE <58>
+3.3V_RUN_F
+3.3V_CAM
EDP_HPD <6>
LCD_TST <58>
LCD_CBL_DET# <9>
Due to SB12/14 Mic. rec eive path is different between Touch and
Non-Touch Panel, so add TOUCH_SCREEN_DET# pin for different verb
table
2.7MM_CAM_DET# <12>
82P_0402_50V8J
100P_0402_50V8J
12
CAM_MIC_CBL_DET# <12>
BIA_PWM
BLM15PX2 21SN1D_2P
12
CV10.1U_0402_25 V6
12
CV20.1U_0402_25 V6
12
CV30.1U_0402_25 V6
12
CV40.1U_0402_25 V6
12
CV50.1U_0402_25 V6
12
CV60.1U_0402_25 V6
12
RF Request
EDP_HPD
RV71 00K_0402_5%@
TOUCH_SCREEN_DET# <14>
EDP_AUXN <6>
EDP_AUXP < 6>
EDP_TXP0 <6>
EDP_TXN0 <6>
EDP_TXP1 <6>
EDP_TXN1 <6>
CA5RF@
12
Relink I-PEX_20879-040E-01 done 0827
RF Request
+LCDVDD+3.3V_CAM
CC
12P_0201_50V8J
RF@
1
CV20
2
BB
AA
place as close as JEDP1
1213 change
Add CZ313 for RF request
1217
Change CZ313 to CV757
82P_0201_50V8J
RF@
100P_0201_50V8J
RF@
1
1
CV21
CV751
2
2
+BL_PWR_SRC
0.1U_0603_50V7K
12
@
CV11
BIA_PWM
4.7K_0402_5%
12
RV1
DISP_ON
4.7K_0402_5%
12
RV2
RF Request
+BL_PW R_SRC
1213 change
Add CZ314 for RF request
1217
Change CZ314 to CV758
27P_0201_25V8
RF@
82P_0402_50V8J
RF@
120P_0402_50V8J
12P_0402_50V8J
100P_0201_50V8J
1
2
RF@
RF@
1
1
1
1
CV757
CV23
CV22
CV752
2
2
2
2
82P_0402_50V8J
RF@
12P_0402_50V8J
RF@
RF@
1
CV750
2
120P_0402_50V8J
RF@
1
1
CV25
CV24
CV753
2
2
+TS_PW R
12P_0402_50V8J
27P_0402_50V8J
RF@
1
CV758
2
RF@
1
CV18
2
place as close as JEDP1
+LCDVDD
0.1U_0201_10V6K
1
@
CV12
2
DV1
1
BAT54CW _SOT323-3
DV2
1
BAT54CW _SOT323-3
EDP_BIA_PWM
3
BIA_PWM_EC
2
3
2
+3.3V_CAM
1
2
PANEL_BKLEN <6>
PANEL_BKEN_EC <58>
0.1U_0201_10V6K
@
CZ202
EDP_BIA_PWM <6>
BIA_PWM_EC <58>
+TS_PW R
+3.3V_RUN
0.1U_0201_10V6K
1
@
CZ2
2
Close to JEDP1. 10Close to JEDP1.17~19Close to JEDP1. 11Close to JEDP1.1Close to JEDP1.30~31
TOUCH_SCREEN _DET#
If touch panel, GPIO Low-> Touch Mic. EQ ;
others the GPIO is High -> Non-Touch Mic. EQ
3MM_CAM_ DET#
2.7MM_CAM _DET#
2
Touch pull up at the panel side
@
@
@
@
JUMP@
PJP12
12
@
RV101
12
0.01_1206_1 %
CV16
QZ1 change to SB00000SS00
For Merion layout limit height
12
RV982.2K_0201_5%
12
RV992.2K_0201_5%
12
RV311100K _0201_5%
12
RV3191K_0201_ 5%
1 2
CV5433P_0201_50V8J@RF@
1 2
CV5533P_0201_50V8J@RF@
Change to SA00006Y700(H=1mm)
For Merion layout placement
+3.3V_RUN_F+3.3V_RUN
QZ1
NTK3139PT1G_SOT72 3-3
13
D
S
G
2
0.1U_0402_25V6K
12
@
CZ220
+5V_RUN
47K_0402_5%
RV6
+3.3V_RUN
100K_0402_5%
12
12
RV326
13
D
2
G
S
+3.3V_RUN
RF Request
+13.5VB
UV24
1
IN
OUT
2
GND
SET
3
FLAG
EN(/EN)
G527ATP1U_TSOT23-6
FZ1
21
0.5A_65V_T06 03FF0500TM
1031 change
USB20_N6<10>
USB20_P6<10>
+TS_PWR
1031 change
FV2
21
0.5A_65V_T0603FF0500TM
+TS_PW R_QV8+3.3V_5V_RUN_QV 8
12
RV4000_0201_5%@
2N7002KTB_SOT523-3
QV7
For Merion 3mm IR CAM ALS & P-Sensor
100P_0201_50V8J
RF@
1
CZ3
2
+3.3V_ALW
CV17
@
1 2
0.01UF_0402_ 25V7K
6
UV24_SET
12
5
RV10220K_02 01_5%
EN_LCDPWR
4
100K_0402_5%
12
RV3
QV8 change to SB00000SS00
For Merion layout limit height
QV8
NTK3139PT1G_SOT72 3-3
13
D
S
G
2
0.1U_0402_25V6K
12
@
CV635
Depop RV733,Pop RV732
P_SENSOR_ PWR_SA VE#
ISH_P_SENS OR_INT#
DV3 change to SCS00008B80
For Merion layout limit height
EMI@
LZ1
1
1
4
4
DLM0NSN90 0HY2D_4P
Merion13
Touchscreen power
+3.3V
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
2
Title
Size
Size
Size
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
eDP CONN & Touch screen
eDP CONN & Touch screen
eDP CONN & Touch screen
Document Num berRe v
Document Num berRe v
Document Num berRe v
LA-G871P
LA-G871P
LA-G871P
1
38109Tuesday, Marc h 05, 2019
38109Tuesday, Marc h 05, 2019
38109Tuesday, Marc h 05, 2019
1.0
1.0
1.0
Page 39
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
DP
DP
DP
LA-G871P
LA-G871P
LA-G871P
39109Tuesday, March 05, 2 019
39109Tuesday, March 05, 2 019
39109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 40
5
AR_DP1_P0<42>
DD
CC
BB
AR_DP1_N0<42>
AR_DP1_P1<42>
AR_DP1_N1<42>
AR_DP1_P2<42>
AR_DP1_N2<42>
AR_DP1_P3<42>
AR_DP1_N3<42>
1 2
CV310.1U_0402_25V6
1 2
CV320.1U_0402_25V6
1 2
CV330.1U_0402_25V6
1 2
CV340.1U_0402_25V6
1 2
CV350.1U_0402_25V6
1 2
CV360.1U_0402_25V6
12
0.1U_0402_25 V6
CV37
12
0.1U_0402_25 V6
CV38
AR_DP1_HPD<42>
AR_DP1_CTRL_CLK<42>
AR_DP1_CTRL_DATA<42>
+3.3V_RUN
L2N7002DW 1T1G_SC88-6
4
Based on EMI & EE test resu lt
Chang e locat ion LV 31~LV38 to 5.6O hm
RV26, RV29, RV32,RV35 to 13 0Ohm
12
EMI@
RV565.6_0402_5%
HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P0
HDMI_TX_N0
HDMI_CLKP
HDMI_CLKN
1M_0402_5%
RV20
12
5
QV3B
2
1
EMI@
RV575.6_0402_5%
EMI@
RV585.6_0402_5%
2
1
EMI@
RV595.6_0402_5%
EMI@
RV605.6_0402_5%
2
1
EMI@
RV615.6_0402_5%
EMI@
RV625.6_0402_5%
2
1
EMI@
RV635.6_0402_5%
+3.3V_RUN
G
S
QV5
2N7002KTB_ SOT523-3
2
L2N7002DW 1T1G_SC88-6
6
1
34
HCM1012GH90 0BP_4P
2
1
LV3
@EMI@
12
12
HCM1012GH90 0BP_4P
2
1
LV6
@EMI@
12
12
HCM1012GH90 0BP_4P
2
1
LV9
@EMI@
12
12
HCM1012GH90 0BP_4P
2
1
LV12
@EMI@
12
2
HDMI_HPD
13
D
QV3A
HDMI_CTRL_CLK
HDMI_CTRL_DATA
HDMI_L_TX_P2
3
3
4
4
3
3
4
4
3
3
4
4
3
3
4
4
0212 change
QV5 change from SB00000NK00
to SB00000SI00
For parts shortage problem
EMI@
RV26
130_0402_5 %
12
HDMI_L_TX_N2
HDMI_L_TX_P1
EMI@
RV29
130_0402_5 %
12
HDMI_L_TX_N1
HDMI_L_TX_P0
EMI@
RV32
130_0402_5 %
12
HDMI_L_TX_N0
HDMI_L_CLKP
EMI@
RV35
130_0402_5 %
12
HDMI_L_CLKN
12
RV2120K_0402_5%
12
RV222.2K_0402_ 5%
12
RV232.2K_0402_ 5%
+VHDMI_VCC
3
+5V_RUN
0.1U_0201_10V6K
1
@
CV39
2
+3.3V_RUN
1
AP2330W-7_SC59-3
IN
UV2
OUT
GND
3
2
12
RV19@10K_0402_5 %
HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P0
HDMI_TX_N0
HDMI_CLKP
HDMI_CLKN
+3.3V_RUN
2
+VHDMI_VCC
0.1U_0201_10V6K
10U_0603_10V6M
1
1
@
CV40
CV41
2
2
HDMI connector
HDMI_HPD
HDMI_CTRL_DATA
HDMI_CTRL_CL K
HDMI_CECHDMI_CEC
HDMI_L_CLKN
HDMI_L_CLKP
HDMI_L_TX_N0
HDMI_L_TX_P0
HDMI_L_TX_N1
HDMI_L_TX_P1
HDMI_L_TX_N2
HDMI_L_TX_P2
RV10470_0402_1%
RV11470_0402_ 1%
RV12470_0402_ 1%
RV13470_0402_ 1%
RV14470_0402_ 1%
RV15470_0402_ 1%
RV16470_0402_ 1%
RV17470_0402_1%
RV1810K_0402_5%
0212 change
QV4 change from SB00000NK00
to SB00000SI00
For parts shortage problem
Link HMRBL-A41L0F done 0123
12
12
12
12
12
12
12
12
12
CONN@
JHDMI1
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Reserved
13
CEC
12
CK-
11
CK_shield
10
CK+
9
D0-
8
D0_shield
7
D0+
6
D1-
5
D1_shield
4
D1+
3
D2-
2
D2_shield
1
D2+
ACON_HMRBL-A41L0F
HDMI_OB
2
GND4
GND3
GND2
GND1
G
20
21
22
23
13
D
QV4
2N7002KTB_ SOT523-3
S
1
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document N umberRe v
Size Document N umberRe v
Size Document N umberRe v
Date :Sheetof
Date :Sheetof
Date :Sheet
Compal Electronics, Inc.
HDMI CONN
HDMI CONN
HDMI CONN
LA-G871P
LA-G871P
LA-G871P
1
40109Tuesday, March 05, 2019
40109Tuesday, March 05, 2019
40109Tuesday, March 05, 2019
1.0
1.0
1.0
of
Page 41
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
CRT
CRT
CRT
LA-G871P
LA-G871P
LA-G871P
41109Tuesday, March 05, 2 019
41109Tuesday, March 05, 2 019
41109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 42
5
4
3
2
1
+3.3V_TBT_FLAS H_R
+3.3V_TBT_FLAS H_R+3.3V_TBT_FLAS H_R
12
RT2
TBT_ROM_CS#
TBT_ROM_DO
TBT_ROM_WP #
PCIE_PTX_C_DR X_P5
PCIE_PTX_C_DR X_N5
PCIE_PTX_C_DR X_P6
PCIE_PTX_C_DR X_N6
PCIE_PTX_C_DR X_P7
PCIE_PTX_C_DR X_N7
PCIE_PTX_C_DR X_P8
PCIE_PTX_C_DR X_N8
CPU_DP1_P 0_C
CPU_DP1_N 0_C
CPU_DP1_P 1_C
CPU_DP1_N 1_C
CPU_DP1_P 2_C
CPU_DP1_N 2_C
CPU_DP1_P 3_C
CPU_DP1_N 3_C
CPU_DP1_A UXP_C
CPU_DP1_A UXN_C
CPU_DP2_P 0_C
CPU_DP2_N 0_C
CPU_DP2_P 1_C
CPU_DP2_N 1_C
CPU_DP2_P 2_C
CPU_DP2_N 2_C
CPU_DP2_P 3_C
CPU_DP2_N 3_C
CPU_DP2_A UXP_C
CPU_DP2_A UXN_C
CPU_DP2_H PD
DPSNK1_DD C_CLK
SNK0_CONFIG1
DPSNK_RB IAS
TBT_JTAG_TDI
TBT_JTAG_TMS
TBT_JTAG_TCK
TBT_JTAG_TDO
TBTA_RBIAS
TBTA_RSENSE
TBTA_USB20_P
TBTA_USB20_N
TBTA_LSTX
TBTA_LSRX
TBTA_HPD
TBTA_USB2_RB IAS
12
RT3
RT4
2.2K_0201_5%
2.2K_0201_5%
Y23
Y22
T23
T22
M23
M22
H23
H22
V19
T19
AC5
AB7
AC7
AB9
AC9
AB11
AC11
AB13
AC13
Y11
W11
AA2
Y5
R4
AB15
AC15
AB17
AC17
AB19
AC19
AB21
AC21
Y12
W12
Y6
Y8
N4
Y18
Y4
V4
T4
W4
H6
J6
A15
B15
A17
B17
A19
B19
B21
A21
Y15
W15
E20
D20
A5
A4
M4
H19
AC23
AB23
V18
AC1
L15
N15
C23
C22
1
CT1
0.1U_0201_1 0V6K
2
12
RT1
3.3K_0201_5%
TBT_ROM_HOLD#
DD
CPU
DDI1
CC
CPU
DDI2
BB
TBT_ROM_CLK
TBT_ROM_DI
PCIE_PTX_DRX _P5<10>
PCIE_PTX_DRX _N5< 10>
PCIE_PTX_DRX _P6<10>
PCIE_PTX_DRX _N6< 10>
PCIE_PTX_DRX _P7<10>
PCIE_PTX_DRX _N7< 10>
PCIE_PTX_DRX _P8<10>
PCIE_PTX_DRX _N8< 10>
CPU_DP1_P 0<6>
CPU_DP1_N 0<6>
CPU_DP1_P 1<6>
CPU_DP1_N 1<6>
CPU_DP1_P 2<6>
CPU_DP1_N 2<6>
CPU_DP1_P 3<6>
CPU_DP1_N 3<6>
CPU_DP1_AUXP<6>
CPU_DP1_AUXN<6>
CPU_DP1_CTRL_CLK<6>
CPU_DP1_CTRL_DATA<6>
CPU_DP2_P 0<6>
CPU_DP2_N 0<6>
CPU_DP2_P 1<6>
CPU_DP2_N 1<6>
CPU_DP2_P 2<6>
CPU_DP2_N 2<6>
CPU_DP2_P 3<6>
CPU_DP2_N 3<6>
CPU_DP2_AUXP<6>
CPU_DP2_AUXN<6>
Type C
AA
UT2
8
VCC
7
HOLD#(IO3)
6
CLK
5
DI(IO0)
W25Q80 DVSSIG_SO8
1 2
CT20.22U_0201_6 .3V6M
1 2
CT30.22U_0201_6 .3V6M
1 2
CT40.22U_0201_6 .3V6M
1 2
CT50.22U_0201_6 .3V6M
1 2
CT1230.22 U_0201_6.3V6 M
1 2
CT1240.22 U_0201_6.3V6 M
1 2
CT1250.22 U_0201_6.3V6 M
1 2
CT1260.22 U_0201_6.3V6 M
CLK_PCIE_P5<11>
CLK_PCIE_N5<11>
CLKREQ_PCIE #5<11>
1 2
CT100.1U_0201_10V6 K
1 2
CT110.1U_0201_10V6 K
1 2
CT120.1U_0201_10V6 K
1 2
CT130.1U_0201_10V6 K
1 2
CT140.1U_0201_10V6 K
1 2
CT150.1U_0201_10V6 K
1 2
CT160.1U_0201_10V6 K
1 2
CT170.1U_0201_10V6 K
1 2
CT180.1U_0201_10V6 K
1 2
CT190.1U_0201_10V6 K
1 2
CT1770.1U _0201_10V6K
1 2
CT1760.1U _0201_10V6K
1 2
CT1720.1U _0201_10V6K
1 2
CT1710.1U _0201_10V6K
1 2
CT1740.1U _0201_10V6K
1 2
CT1680.1U _0201_10V6K
1 2
CT1730.1U _0201_10V6K
1 2
CT1700.1U _0201_10V6K
1 2
CT1690.1U _0201_10V6K
1 2
CT1750.1U _0201_10V6K
RT3814K_0201_1%
12
RT394.75K_0402_0.5%
TBT_A_TRX_DTX_P1<45>
TBT_A_TRX_DTX_N1<4 5>
TBT_A_TTX_DRX_P1<45>
TBT_A_TTX_DRX_N1<4 5>
TBT_A_TTX_DRX_P0<45>
TBT_A_TTX_DRX_N0<4 5>
TBT_A_TRX_DTX_P0<45>
TBT_A_TRX_DTX_N0<4 5>
TBTA_USB20_P<44>
TBTA_USB20_N<44>
RT41499_0201_1%
1
CS#
2
DO(IO1)
3
WP#(IO2)
4
GND
CPU_DP1_H PD<6>
CPU_DP2_H PD<6>
12
TBTA_AUXP<44>
TBTA_AUXN<44>
TBTA_LSTX<44>
TBTA_LSRX<44>
TBTA_HPD<44>
12
+3.3V_TBT_LC
12
3.3K_0201_5%
UT1A
PCIE_RX0_P
PCIE_RX0_N
PCIE_RX1_P
PCIE_RX1_N
PCIE_RX2_P
PCIE_RX2_N
PCIE_RX3_P
PCIE_RX3_N
PCIE_REFCLK_100_IN_P
PCIE_REFCLK_100_IN_N
PCIE_CLKREQ_N
DPSNK0_ML0_P
DPSNK0_ML0_N
DPSNK0_ML1_P
DPSNK0_ML1_N
DPSNK0_ML2_P
DPSNK0_ML2_N
DPSNK0_ML3_P
DPSNK0_ML3_N
DPSNK0_AUX_P
DPSNK0_AUX_N
DPSNK0_HPD
DPSNK0_DDC_CLK
DPSNK0_DDC_DATA
DPSNK1_ML0_P
DPSNK1_ML0_N
DPSNK1_ML1_P
DPSNK1_ML1_N
DPSNK1_ML2_P
DPSNK1_ML2_N
DPSNK1_ML3_P
DPSNK1_ML3_N
DPSNK1_AUX_P
DPSNK1_AUX_N
DPSNK1_HPD
DPSNK1_DDC_CLK
DPSNK1_DDC_DATA
DPSNK_RBIAS
TDI
TMS
TCK
TDO
RBIAS
RSENSE
PA_RX1_P
PA_RX1_N
PA_TX1_P
PA_TX1_N
PA_TX0_P
PA_TX0_N
PA_RX0_P
PA_RX0_N
PA_DPSRC_AUX_P
PA_DPSRC_AUX_N
PA_USB2_D_P
PA_USB2_D_N
PA_LSTX
PA_LSRX
PA_DPSRC_HPD
PA_USB2_RBIAS
THERMDA
THERMDA
PCIE_ATEST
TEST_EDM
FUSE_VQPS_64
FUSE_VQPS_128
MONDC_CIO_0
MONDC_CIO_1
12
12
12
RT8
RT7
RT6
RT5
10K_0201_5%
POC
10K_0201_5%
10K_0201_5%
Rework Debug Pin1 +3.3V_TBTA_LC, Pin6 GND
PCIE_TX0_P
PCIE_TX0_N
PCIE_TX1_P
PCIE_TX1_N
PCIE_TX2_P
PCIE_TX2_N
PCIE_TX3_P
PCIE_TX3_N
PCIe GEN3
PCIE_RBIAS
DPSRC_ML0_P
DPSRC_ML0_N
DPSRC_ML1_P
DPSRC_ML1_N
DPSRC_ML2_P
DPSRC_ML2_N
DPSRC_ML3_P
DPSRC_ML3_N
DPSRC_AUX_P
DPSRC_AUX_N
SINK PORT 0
SOURCE PORT 0
DPSRC_HPD
DPSRC_RBIAS
LC GPIOPOC GPIO
POC_GPIO_0
POC_GPIO_1
POC_GPIO_2
POC_GPIO_3
POC_GPIO_4
POC_GPIO_5
POC_GPIO_6
SINK PORT 1
TEST_PWR_GOOD
Misc
TBT PORTS
XTAL_25_OUT
PB_DPSRC_AUX_P
PB_DPSRC_AUX_N
PORT B
PB_USB2_D_P
PB_USB2_D_N
PB_DPSRC_HPD
POC
PB_USB2_RBIAS
MONDC_SVR
USB2_ATEST
MONDC_DPSNK_0
MONDC_DPSNK_1
MONDC_DPSRC
ALPINE-RIDGE_B GA337
MISC
Port A
DEBUG
12
10K_0201_5%
TBT_JTAG_TCK
TBT_JTAG_TDO
PERST_N
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
TEST_EN
RESET_N
XTAL_25_IN
EE_DI
EE_DO
EE_CS_N
EE_CLK
PB_RX1_P
PB_RX1_N
PB_TX1_P
PB_TX1_N
PB_TX0_P
PB_TX0_N
PB_RX0_P
PB_RX0_N
PB_LSTX
PB_LSRX
ATEST_P
ATEST_N
TBT_JTAG_TDI
TBT_JTAG_TMS
V23
V22
P23
P22
K23
K22
F23
F22
L4
N16
R2
R1
N2
N1
L2
L1
J2
J1
W19
Y19
G1
N6
U1
U2
V1
V2
W1
W2
Y1
Y2
AA1
J4
E2
D4
H4
F2
D2
F1
E1
AB5
F4
D22
D23
AB3
AC4
AC3
AB4
B7
A7
A9
B9
A11
B11
A13
B13
Y16
W16
E19
D19
B4
B5
G2
F19
D6
A23
B23
E18
W13
W18
AB2
PCIE_PRX_C_ DTX_P5
PCIE_PRX_C_ DTX_N5
PCIE_PRX_C_ DTX_P6
PCIE_PRX_C_ DTX_N6
PCIE_PRX_C_ DTX_P7
PCIE_PRX_C_ DTX_N7
PCIE_PRX_C_ DTX_P8
PCIE_PRX_C_ DTX_N8
TBT_PERST#
TBT_PCIE_RBIAS
AR_DP1_P0
AR_DP1_N0
AR_DP1_P1
AR_DP1_N1
AR_DP1_P2
AR_DP1_N2
AR_DP1_P3
AR_DP1_N3
AR_DP1_HP D
TBT_DP_RBIAS
TBT_I2C_SDA
TBT_I2C_SCL
TBT_ROM_WP #
TBT_TMU_CLK_OUT
PCIE_WA KE#_AR
TBT_CIO_PLUG_EVE NT#
AR_DP1_CTRL_ DATA
AR_DP1_CTRL_ CLK
TBT_SRC_CFG1
TBTA_I2C_INT
TBTB_I2C_INT
RTD3_USB_PW R_EN
TBT_FORCE_PW R
TDOCK_BATLOW #
SIO_SLP_S3#
RTD3_CIO_PW R_EN
TEST_EN
TEST_PWRGD
TBT_RESET_N_EC
XTAL_25_IN
RT394
EMI@
XTAL_25_OUT
EMI@
TBT_ROM_DI
TBT_ROM_DO
TBT_ROM_CS#
TBT_ROM_CLK
TBTB_LSTX
TBTB_LSRX
TBTB_HPD
TBTB_USB2_RB IAS
RT42499_0201_1%
1 2
CT60.22U_0201_6 .3V6M
1 2
CT70.22U_0201_6 .3V6M
1 2
CT80.22U_0201_6 .3V6M
1 2
CT90.22U_0201_6 .3V6M
1 2
CT1270.22 U_0201_6.3V6 M
1 2
CT1280.22 U_0201_6.3V6 M
1 2
CT1290.22 U_0201_6.3V6 M
1 2
CT1300.22 U_0201_6.3V6 M
12
RT34
3.01K_0201 _1%
AR_DP1_HP D <40>
12
RT3514K_0201_1%
TBT_I2C_SDA <44>
TBT_I2C_SCL <44>
TBT_CIO_PLUG_EVE NT# <12>
AR_DP1_CTRL_DATA <40>
AR_DP1_CTRL_ CLK <40>
TBTA_I2C_INT <44>
TBT_FORCE_PW R <6>
SIO_SLP_S3# < 11,17,59,79>
12
RT36100_0201_5%
12
RT37100_0201_5%
TBT_RESET_N_EC <44,58>
12
0_0201_5%
RT40
12
0_0201_5%
12
12
RT90_ 0201_5%@
AR_DP1_P0 < 40>
AR_DP1_N0 <40>
AR_DP1_P1 < 40>
AR_DP1_N1 <40>
AR_DP1_P2 < 40>
AR_DP1_N2 <40>
AR_DP1_P3 < 40>
AR_DP1_N3 <40>
RTD3_CIO_PW R_EN <6>
XTAL_25_IN_R
XTAL_25_OUT_R
+3.3V_TBT_LC
PCIE_PRX_DTX _P5 <10>
PCIE_PRX_DTX _N5 <10>
PCIE_PRX_DTX _P6 <10>
PCIE_PRX_DTX _N6 <10>
PCIE_PRX_DTX _P7 <10>
PCIE_PRX_DTX _N7 <10>
PCIE_PRX_DTX _P8 <10>
PCIE_PRX_DTX _N8 <10>
YT1
3
OUT
4
27P_0402_50V8J
GND2
12
CT20
25MHZ 20PF F L2500123Z
AR_DP1_P0A R_DP1_N0
1 2
CT201 1P _0201_50V8C@
AR_DP1_P1
AR_DP1_P2
AR_DP1_P3
Close UT1
Intel Review request
20180518
GND1
AR_DP1_N1
1 2
CT202 1P _0201_50V8C@
AR_DP1_N2
1 2
CT203 1P _0201_50V8C@
AR_DP1_N3
1 2
CT204 1P _0201_50V8C@
1
IN
2
27P_0402_50V8J
12
CT21
TBT RTD3 Suppor t
TBT_RTD3_WAK E#<6>
PCH_PCIE_W AKE#<11,58 ,59>
PCIE_WA KE#<52,59 ,68>
For backdrive issue
PCH_PLTRST#_A ND<1 1,38,52,68,70>
PCH_TBT_PERST#<6>
TBT_RTD3_WAK E#
PCH_PCIE_W AKE#
PCIE_WA KE#
+3.3V_ALW _PCH
TBT_CIO_PLUG_EVE NT#
AR_DP1_CTRL_ DATA
AR_DP1_CTRL_ CLK
SNK0_DDC_data/c lk – connect to 2k PU only if
SRC0 is connected and suppor t HDMI (a.i H DMI
or DP++ connector). Otherwise can be 100k PD.
SNK1_DDC_data – connect to 1 00k PD. If SRC0
support HDM I, conne ct as SNK0_CFG1 to GPU
and/or appropriate A UX/DDC demux co ntrol
SNK1_DDC_clk – connect to 100k PD .
PCIE_WA KE#_AR
TBTA_I2C_INT
TBTB_I2C_INT
TBT_I2C_SDA
TBT_I2C_SCL
TDOCK_BATLOW #
TBT_SRC_CFG1
TBT_CIO_PLUG_EVE NT#
RTD3_CIO_PW R_EN
12
RT39110K_ 0402_5%
12
RT122.2K_0 201_5%
12
RT132.2K_0 201_5%
12
RT45510K_ 0402_5%RTD3@
12
RT1610K_0201_5%
12
RT1710K_0201_5%
12
RT182.2K_0201_5%
12
RT192.2K_0201_5%
12
RT2010K_0201_5%
12
RT33810K_ 0201_5%
12
@
RT37110K_ 0201_5%
RTD3@
12
RT37210K_ 0201_5%
+3.3V_TBT
+3.3V_TBT_SX
Intel review request for TBT RTD3 20170810 (KWmlk)
TBTA_LSRX
TBTA_LSTX
TBTA_HPD
CPU_DP1_H PD
RTD3_CIO_PW R_EN
RTD3_USB_PW R_EN
TBT_FORCE_PW R
TBT_TMU_CLK_OUT
CPU_DP2_H PD
TBTB_LSTX
TBTB_LSRX
TBTB_HPD
DPSNK1_DD C_CLK
SNK0_CONFIG1
+3.3V_ALW
0_0201_5%
RTD3@
1
2
UT34
RTD3@
RTD3@
UT32
1
NO
3
NC
6
IN
TS5A3159ADC KR_SC70-6
B
A
COM
GND
12
RT4920_020 1_5%@
12
RT4930_020 1_5%@
MC74VHC1G0 8DFT2G_SC70-5
12
0_0201_5%
RT456
@
12
RT4450_0201_5%@RTD3@
12
RT448
@
RTD3_SELECT<58>
12
RT447
10K_0201_5 %
RT211M_0201_5%
RT221M_0201_5%
RT23100K_0201_5%
RT24100K_0201_5%
NRTD3@
RT25100K_0402_5%
RT26100K_0201_5%
RT2710K_0201_5%
RT28100K_0201_5%
RT29100K_0201_5%
RT31100K_0201_5%
RT32100K_0201_5%
RT33100K_0201_5%
RT128100K _0201_5%
RT129100K _0201_5%
RTD3@
CT360
0.1U_0201_1 0V6K
1 2
RT4960_02 01_5%NRTD3@
5
P
TBT_PERST#_R
4
O
G
3
+3.3V_ALW
0.1U_0201_1 0V6K
5
V+
PCIE_WA KE#_AR_R
4
2
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
RT494
12
RTD3@
RTD3@
CT237
1 2
RT4950_0201 _5%@
100K_0201_5%
@
@RTD3@
1M_0201_5%
12
12
RT441
RT440
12
IN
TBT_PERST#
PCIE_WA KE#_AR
0_0201_5%
NC NO
COMXX
HLCOM
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
2
Title
Size
Size
Size
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
TBT-AR-SP(1/2) DP,PCIE
TBT-AR-SP(1/2) DP,PCIE
TBT-AR-SP(1/2) DP,PCIE
Document Num berRe v
Document Num berRe v
Document Num berRe v
LA-G871P
LA-G871P
LA-G871P
1
42109Tuesday, Marc h 05, 2019
42109Tuesday, Marc h 05, 2019
42109Tuesday, Marc h 05, 2019
1.0
1.0
1.0
Page 43
2
+3.3V_AL W
1
1
CT44
2
10U_0402_6.3V6M
1
CT48
CT49
2
1U_0201_6.3V6M
1U_0201_6.3V6M
1
LT10.6UH_ MND-04ABIR60 M-XGL_20%
CT59
10U_0402_6.3V6M
1
CT45
CT46
2
2
10U_0402_6.3V6M
10U_0402_6.3V6M
1
1
CT51
CT50
2
2
1U_0201_6.3V6M
1U_0201_6.3V6M
2
1
1
CT60
CT61
2
2
1U_0201_6.3V6M
10U_0402_6.3V6M
+3.3V_TBT
VCC3P3_SVR:3.3V @ 0.6A max
1
CT47
2
10U_0402_6.3V6M
1
2
+0.9V_TBT_L VR_OUT
1
2
VCC0P9_SVR:0.9V @ 1.8A max
Minimum of 4vias must be used
1
1
CT53
CT52
2
2
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
CT55
CT56
2
2
47U_0603_6.3V6M
47U_0603_6.3V6M
1
CT62
2
1U_0201_6.3V6M
+0.9V_TBT_S VR
1
CT54
2
1U_0201_6.3V6M
1
Share Same GND plane
CT57
with SVR_VSS of AR
2
47U_0603_6.3V6M
Intel review request
Change 10U*4 to
47U*3
20160324
@JUMP@
PJP6
PAD-OPEN1 x1m
No sol der
3
+3.3V_TBT_L C
UT1B
L8
VCC0P9_D P_0
L11
VCC0P9_D P_1
L12
VCC0P9_D P_2
M8
VCC0P9_D P_3
T11
VCC0P9_D P_4
T12
VCC0P9_D P_5
L6
VCC0P9_A NA_DPSRC_0
M6
VCC0P9_A NA_DPSRC_1
V11
VCC0P9_A NA_DPSNK_0
V12
VCC0P9_A NA_DPSNK_1
V13
VCC0P9_A NA_DPSNK_2
M13
VCC0P9_P CIE_0
M15
VCC0P9_P CIE_1
M16
VCC0P9_P CIE_2
L19
VCC0P9_A NA_PCIE_1_ 0
N19
VCC0P9_A NA_PCIE_1_ 1
L18
VCC0P9_A NA_PCIE_2_ 0
M18
VCC0P9_A NA_PCIE_2_ 1
N18
VCC0P9_A NA_PCIE_2_ 2
R15
VCC0P9_U SB_0
R16
VCC0P9_U SB_1
R8
VCC0P9_C IO_0
R9
VCC0P9_C IO_1
R11
VCC0P9_C IO_2
R12
VCC0P9_C IO_3
L16
VCC3P3_A NA_PCIE
J16
VCC3P3_A NA_USB2
A6
VSS_ANA _0
A8
VSS_ANA _1
A10
VSS_ANA _2
A12
VSS_ANA _3
A14
VSS_ANA _4
A16
VSS_ANA _5
A18
VSS_ANA _6
A20
VSS_ANA _7
A22
VSS_ANA _8
B6
VSS_ANA _9
B8
VSS_ANA _10
B10
VSS_ANA _11
B12
VSS_ANA _12
B14
VSS_ANA _13
B16
VSS_ANA _14
B18
VSS_ANA _15
B20
VSS_ANA _16
B22
VSS_ANA _17
D8
VSS_ANA _18
D9
VSS_ANA _19
D11
VSS_ANA _20
D12
VSS_ANA _21
D13
VSS_ANA _22
D15
VSS_ANA _23
D16
VSS_ANA _24
D18
VSS_ANA _25
E8
VSS_ANA _26
E9
VSS_ANA _27
E11
VSS_ANA _28
E15
VSS_ANA _29
E16
VSS_ANA _30
E22
VSS_ANA _31
E23
VSS_ANA _32
F9
VSS_ANA _33
F16
VSS_ANA _34
F20
VSS_ANA _35
G22
VSS_ANA _36
G23
VSS_ANA _37
H1
VSS_ANA _38
H2
VSS_ANA _39
H12
VSS_ANA _40
H13
VSS_ANA _41
H15
VSS_ANA _42
H16
VSS_ANA _43
H20
VSS_ANA _44
J5
VSS_ANA _45
J18
VSS_ANA _46
J19
VSS_ANA _47
J20
VSS_ANA _48
J22
VSS_ANA _49
J23
VSS_ANA _50
K1
VSS_ANA _51
K2
VSS_ANA _52
L5
VSS_ANA _53
L20
VSS_ANA _54
L22
VSS_ANA _55
L23
VSS_ANA _56
M1
VSS_ANA _57
M2
VSS_ANA _58
M5
VSS_ANA _59
M19
VSS_ANA _60
M20
VSS_ANA _61
N5
VSS_ANA _62
N20
VSS_ANA _63
N22
VSS_ANA _64
N23
VSS_ANA _65
Merion Limit height
RT48,RT49 change to 0201 from 0603
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DIS CLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size
Size
Size
Date:Sheeto f
Date:Sheeto f
Date:Sheeto f
Compal Electronics, Inc.
TBT-AR-SP(2/2) VCC/VSS
TBT-AR-SP(2/2) VCC/VSS
TBT-AR-SP(2/2) VCC/VSS
Document NumberRe v
Document NumberRe v
Document NumberRe v
LA-G871P
LA-G871P
LA-G871P
1
43109Tuesday, March 05, 2019
43109Tuesday, March 05, 2019
43109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 44
5
4
3
2
1
+3.3V_TBTA_FLA SH
1
CT70
0.1U_0201_1 0V6K
RT50
3.3K_0201_5%
DD
CC
BB
2
12
TBTA_ROM_HOLD#_ PD
TBTA_ROM_CLK_P D
TBTA_ROM_DI_PD
DIV = R2/(R1+R2)
DIV_ma xDIV_m in
0.080.00
0.180.10
0.280.20
0.380.30
0.480.40
0.580.50
0.680.60
1.007
0.70
8
7
6
5
UT6
VCC
HOLD#(IO3)
CLK
DI(IO0)
GD25Q80CSIGR_S O8
Config uration
1
CS#
2
DO(IO1)
3
WP#(IO2)
4
GND
Descrip tionFactory Device
UFP onl y
5V @0.9A Sink capabil ity w ith "Ask for Max/" for
anything from 0.9 -3.0A
0
TBT Alternate Modes not supported
DisplayPort Alternate Modes not s upported
TI VID supported
UFP onl y
5V @0.9A Sink capabil ity w ith "Ask for Max/" for
anything from 0.9 -3.0A
1
TBT Alternate Modes not supported
DisplayPort Alternate Modes -Sink, C and D pin configuration
TI VID supported
UFP onl y
5V @3.0A Source capability
2
TBT Alternate Modes not supported
DisplayPort Alternate Modes not s upported
TI VID supported
UFP onl y
5V @3.0A Source capability
3
TBT Alternate Modes not supported
DisplayPort Alternate Modes -Sink, C and D pin configuration
TI VID supported
DisplayPort Alternate Modes - Sourc e, C, D, and E
pin confi gurations.
TI VID supported
Accepts power role swaps but w ill not initiate.
Accepts data rol e swap to UFP and c an initia te.
DisplayPort Alternate Modes - Sourc e, C, D, and E
pin confi gurations.
TI VID supported
Accepts power role swaps but w ill not initiate.
Accepts data rol e swap to DFP and c an initia te.
Infinite boot retry from Flash to Host I/F cycles.
TBTA_ROM_CS#_P D
TBTA_ROM_DO_PD
TBTA_ROM_W P#_PD
+3.3V_TBTA_FLA SH
RT51
RT52
12
3.3K_0201_5%
3.3K_0201_5%
For AR port1
RT53
12
UPD1_SMBCLK<58>
12
UPD1_SMBDAT<58>
3.3K_0201_5%
UPD1_SMB INT#<58 >
X10 +3.3V_VDD_PIC_PDA change connect to +3.3V_ALW
+3.3V_TBTA_FLA SH
10K_0201_1 %
RT76
12
PD1_GPIO8
12
RT377
43K_0402_1 %
Follow ARD 0.98 Thunderbolt Route USB2.0 ports as per WHL architecture
UART_MOSI
RT81100K_0201_5 %
RT821M_0201_5%@
+3.3V_TBTA_FLA SH
12
UART_MISO
12
TI ref ckt: 100k
Intel ref ckt: 1M
12
RT95100K_0201_5%
12
RT96100K_0201_5%
12
RT580_0201_5%@
12
RT590_0201_5%@
12
RT600_0201_5%@
+3.3V_VDD _PIC+3. 3V_VDD_PIC_PD A
12
@
RT4820_0 201_5%
+3.3V_ALW
12
RT4830_0 201_5%@
TI is 3x1uf
USB20_P1<10>
USB20_N1<10>
TBTA_USB20_P<42>
TBTA_USB20_N<42>
TBTA_AUXN_C
TBTA_AUXP_C
UPD1_SMB CLK_R
UPD1_SMB DAT_R
UPD1_SMB INT#_R
1
1
CT71
CT72
2
2
2.2U_0402_16V6K
2.2U_0402_16V6K
EN_PD_HV_ 1<82,84>
TBTA_HPD<42>
12
12
RT4000_020 1_5%@
12
RT4010_020 1_5%@
12
RT4020_020 1_5%
@
RT4030_020 1_5%
@
TBTA_LSTX<42>
TBTA_LSRX<42>
+VCC1V8D_ TBTA_LDO
RT970_0201_5%
@
+TBTA_LDO_BMC
+VCC1V8D_ TBTA_LDO
+VCC1V8A _TBTA_LDO
1
CT73
2
2.2U_0402_16V6K
+3.3V_TBTA_FLA SH
+3.3V_ALW
GPIO8: USB_TYPEC_FAULT#
@
T219
PAD~D
@
T220
PAD~D
TBTA_LSTX
TBTA_LSRX
UPD1_SMB CLK_R
UPD1_SMB DAT_R
TBTA_AUXP<42>
TBTA_AUXN<42>
12
Follow TI SPEC
CT74 change to 10U
12
RT663.3K_0201_5%@
12
RT673.3K_0201_5%@
12
RT6810K_0201_5%@
12
RT711M_0201_5%
UART_MOSI
UART_MISO
1
1
Follow TI SPEC
RT86 change to 100K
12
RT86100K_0201_5%
12
12
RT890_0201_5%
@
RT900_0201_5%
@
1 2
CT800.1U_0201_10V 6K
1 2
CT810.1U_0201_10V 6K
+3.3V_TBTA_FLA SH
RT98
@
0_0201_5%
12
RT99
@
0_0201_5%
12
+5V_ALW
12
+3.3V_VDD _PIC_PDA
TBT_I2C_SDA<42>
TBT_I2C_SCL<42>
TBTA_I2C_INT<42>
12
RT830_0201_5%@
JUMP@
PJP8
PAD-OPEN1x2m
1
CT74
2
10U_0402_6.3V6M
UPD1_SMB DAT_R
UPD1_SMB CLK_R
UPD1_SMB INT#_R
PD1_GPIO2
PD1_GPIO8
TBTA_ROM_CLK_P D
TBTA_ROM_DI_PD
TBTA_ROM_DO_PD
TBTA_ROM_CS#_P D
TBTA_USB20_P _R
TBTA_USB20_N_ R
SWD_D ATA
SWD_C LK
TBTA_MRESET
TBTA_DEBUG3
TBTA_DEBUG4
TBTA_AUXP_C
TBTA_AUXN_C
TBTA_ROSC
12
RT100
15K_0201_1%
TI is 1x47uf+1x0.1uf
12
RT630_0201_5%@
D10
G11
C10
E10
G10
E11
F10
1
1
CT75
2
2
22U_0603_10V6M
UT5
F1
I2C_ADDR
D1
I2C_SDA1
D2
I2C_SCL1
C1
I2C_IRQ1_N
A5
I2C_SDA2
B5
I2C_SCL2
B6
I2C_IRQ2_N
B2
GPIO0
C2
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
D7
GPIO7
H6
GPIO8
A3
SPI_CLK
B4
SPI_MOSI
A4
SPI_MISO
B3
SPI_SS_N
L5
USB_RP_P
K5
USB_RP_N
E2
UART_TX
F2
UART_RX
F4
SWD_DATA
G4
SWD_CLK
MRESET
L4
TBT_LSTX/R2P
K4
TBT_LSRX/P2R
L3
DIG_AUD_P/DEBUG3
K3
DIG_AUD_N/DEBUG4
L2
DEBUG1
K2
DEBUG2
J1
AUX_P
J2
AUX_N
BUSPOWER_N
G2
R_OSC
TBTA_CC1 <4 5>
TBTA_CC2 <45>
+3.3V_TBTA_FLA SH
TBT_RESET_N_EC <42,58>
RF requea t
+5V_ALW _PDA
100P_0402_50V8J~D
12
CT22RF@
1
2
TBTA_SBU1 <45>
TBTA_SBU2 <45>
1
CT85
CT86
2
220P_0402_50V8J
220P_0402_50V8J
+20V_TBTA_VB US_1
1
1
CT77
CT78
CT76
2
2
22U_0603_10V6M
22U_0603_10V6M
22U_0603_10V6M
12
RT640_0201 _5%@
12
RT650_0201 _5%@
+5V_ALW _PDA
E1
A2
K1
B1
H1
VDDIO
VIN_3V3
LDO_1V8A
LDO_1V8D
GND_7
GND_6
HRESET
GND_5
GND_8
F5
E6
E5
A1
E7
D6
12
RT101
100K_0201_5%
LDO_BMC
GND_9
G5
H10
GND_11
GND_10
H5
H4
B11
A11
PP_5V0_2
PP_5V0_1
PP_CABLE
GND_12
GND_14
GND_13
GND_16
GND_15
F6
B8
E8
D8
0.22U_0402_ 16V7K
D11
C11
A7
A6
GND_2
GND_1
PP_5V0_4
PP_5V0_3
SS
GND_21
GND_20
GND_19
GND_18
GND_17
F8
F7
H7
G8
G7
G6
1
CT87
2
B7
A8
GND_4
GND_3
GND_24
GND_23
GND_22
L1
H8
L11
12
HV_GATE1_A
HV_GATE2_A
A9
B9
A10
B10
SENSEP
SENSEN
HV_GATE1
VBUS_1
VBUS_2
VBUS_3
VBUS_4
VOUT_3V3
LDO_3V3
C_USB_TP
C_USB_TN
C_USB_BP
C_USB_BN
C_CC1
C_CC2
RPD_G1
RPD_G2
DEBUG_CTL1
DEBUG_CTL2
C_SBU1
C_SBU2
RESET_N
SN1804044ZB HR_NFBGA96
RT103
0_0201_5%
@
+20V_TBTA_VB US_1
HV_GATE2
TI has 1x1uf
12
CT82
+3.3V_PDA _VOUT
1
CT83
2
1U_0603_50V6K
1U_0201_6.3V6M
H11
J10
J11
K11
H2
G1
K6
L6
K7
L7
TI has 2x220pf
L9
L10
WHEN CON NECT B USPOWERZ TO GND,
CONNECT ALSO RPD _Gn to C_CCn
K9
K10
RT1040_020 1_5%@
RT1050_020 1_5%@
TBTA_DBG_CTL1
E4
TBTA_DBG_CTL2
D5
K8
L8
TBTA_RESET_N_E C_R
F11
12
12
TBTA_TOP_P <45>
TBTA_TOP_N <45>
TBTA_BOT_P <45>
TBTA_BOT_N <45>
RT10610K_ 0201_5%
RT10710K_ 0201_5%
@
RT1100_020 1_5%
+3.3V_TBTA_FLA SH
1
CT84
2
12
12
12
10U_0402_6.3V6M
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
2
Title
Size
Size
Size
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
[Type C]PD Controller TI
[Type C]PD Controller TI
[Type C]PD Controller TI
Document Num berRe v
Document Num berRe v
Document Num berRe v
LA-G871P
LA-G871P
LA-G871P
1
44109Tuesday, Marc h 05, 2019
44109Tuesday, Marc h 05, 2019
44109Tuesday, Marc h 05, 2019
1.0
1.0
1.0
Page 45
5
TBT_A_TTX_C_ DRX_P1
TBT_A_TTX_C_ DRX_N1
DD
TBTA_CC2<44>
TBTA_BOT_P<44>
TBTA_BOT_N<44>
TBTA_SBU2<44>
TBT_A_TRX_C_D TX_N0
TBT_A_TRX_C_D TX_P0
12
CT990.47U_02 01_25V
12
RT1230_0201_5%@EMI@
12
RT1220_0201_5%@EMI@
12
CT1010.47U_0201_2 5V
TBTA_CC2
TBTA_BOT_P_R
TBTA_BOT_N_R
TBTA_SBU2
4
+20V_TBTA_VBUS
MerionuseSMTtype,notHybri
JUSBC1
CONN@
A1
GND_1
A2
SSTXP1
A3
SSTXN1
A4
VBUS_1
A5
CC1
A6
DP1
A7
DN1
A8
SUB1
A9
VBUS_2
A10
SSRXN2
SSRXP2
GND_2
GND_5
GND_6
GND_9
NPTH_1
TOP
Bottom
A11
A12
1
2
5
7
JAE_DX07SD24JJ2R1 300~D
GND_4
SSRXP1
SSRXN1
VBUS_4
SBU2
VBUS_3
SSTXN2
SSTXP2
GND_3
GND_8
GND_7
GND_10
NPTH_2
+20V_TBTA_VBUS
d
B12
B11
B10
B9
B8
B7
DN2
B6
DP2
B5
CC2
B4
B3
B2
B1
4
3
6
8
TBTA_SBU1
TBTA_TOP_N_R
TBTA_TOP_P_R
TBTA_CC1
3
TBT_A_TRX_C_D TX_P1
TBT_A_TRX_C_D TX_N1
12
CT1000.47U_0201_25V
12
RT1210_0201_5%@EMI@
12
RT1200_0201_5%@EMI@
12
CT1020.47U_0201_25V
TBT_A_TTX_C_D RX_N0
TBT_A_TTX_C_D RX_P0
TBTA_SBU1 <44>
TBTA_TOP_N <44>
TBTA_TOP_P <4 4>
TBTA_CC1 <44>
2
RF Request
+20V_TBTA_VBUS
12P_0402_50V8J
RF@
1
CT189
2
82P_0402_50V8J
RF@
1
CT190
2
+20V_TBTA_VBUS
12
ESD@
DT4
AZ4A24-01F.R7G_DFN060 3P2Y2
Merion Limit height
DT4 change to H=0.32mm(MAX)
1
Link DX07SD24JJ2R1300 done 0123
CC
Remove Low Speed VBUS-Short Protection
Place holder for future VBUS-short
TBT_A_TRX_DTX_P0<42>
TBT_A_TRX_DTX_N0<42>
TBT_A_TTX_DR X_P0< 42>
TBT_A_TTX_DR X_N0<42>
TBT_A_TRX_DTX_P1<42>
TBT_A_TRX_DTX_N1<42>
TBT_A_TTX_DR X_P1< 42>
TBT_A_TTX_DR X_N1<42>
BB
AA
TBT_A_TRX_DT X_P0
TBT_A_TRX_DT X_N0
TBT_A_TTX_DR X_P0
TBT_A_TTX_DR X_N0
TBT_A_TRX_DT X_P1
TBT_A_TRX_DT X_N1
TBT_A_TTX_DR X_P1
TBT_A_TTX_DR X_N1
TBT_A_TTX_C_ DRX_P1
TBT_A_TTX_C_ DRX_N1
TBT_A_TTX_C_ DRX_P0
TBT_A_TTX_C_ DRX_N0
fix (reduce current surge)
12
RT1902.2_0201_1%
12
RT1912.2_0201_1%
12
RT1922.2_0201_1%
12
RT1932.2_0201_1%
12
RT1942.2_0201_1%
12
RT1952.2_0201_1%
12
RT1962.2_0201_1%
12
RT1972.2_0201_1%
Discharge SSTX/SSRX resistors - must be
placed if 330nF cap is being used.
12
RT49122 1K_0201_1%
12
RT49022 1K_0201_1%
12
RT48822 1K_0201_1%
12
RT48922 1K_0201_1%
AC coupling is recommended for
VBUS-short protection on SSRX lines. If not
needed, place 0 Ohm resistor instead.
TBT_A_TRX_R_D TX_P0
TBT_A_TRX_R_D TX_N0
TBT_A_TTX_R_ DRX_P0
TBT_A_TTX_R_ DRX_N0
TBT_A_TRX_R_D TX_P1
TBT_A_TRX_R_D TX_N1
TBT_A_TTX_R_ DRX_P1
TBT_A_TTX_R_ DRX_N1
TBT_A_TRX_C_D TX_P1
TBT_A_TRX_C_D TX_N1
TBT_A_TRX_C_D TX_P0
TBT_A_TRX_C_D TX_N0
CT3260.33U_0201_25V6K
CT3270.33U_0201_25V6K
CT950.22U_ 0201_25V6K
CT960.22U_ 0201_25V6K
CT3280.33U_0201_25V6K
CT3290.33U_0201_25V6K
CT970.22U_ 0201_25V6K
CT980.22U_ 0201_25V6K
12
RT221221K _0201_1%
12
RT222221K _0201_1%
12
RT219221K _0201_1%
12
RT220221K _0201_1%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
TBT_A_TRX_C_D TX_P0
TBT_A_TRX_C_D TX_N0
TBT_A_TTX_C_ DRX_P0
TBT_A_TTX_C_ DRX_N0
TBT_A_TRX_C_D TX_P1
TBT_A_TRX_C_D TX_N1
TBT_A_TTX_C_ DRX_P1
TBT_A_TTX_C_ DRX_N1
DT5
TBT_A_TTX_R_ DRX_P0
TBT_A_TTX_R_ DRX_N0
TBT_A_TRX_R_D TX_P1
TBT_A_TRX_R_D TX_N1
TBTA_SBU1T BTA_SBU1
TBTA_TOP_N_RTBTA_TOP_N_R
TBTA_CC1TBTA_CC1
ESD@
12
DESD3V3Z1BCSF-7 X2-DSN 0603-2
DT6
ESD@
12
DESD3V3Z1BCSF-7 X2-DSN 0603-2
DT9
ESD@
12
DESD3V3Z1BCSF-7 X2-DSN 0603-2
DT10
ESD@
12
DESD3V3Z1BCSF-7 X2-DSN 0603-2
DT39
ESD@
1
1
2
2
4
4
5
5
3
3
8
AZ1045-04F_DFN25 10P10E-10-9
9
10
8
9
7
7
6
6
Merion14DT39,DT40changepindefinforlayoutroutin
TBTA_TOP_P_RTBTA_TOP_P_R
g
DT13
TBT_A_TRX_R_D TX_P0
TBT_A_TRX_R_D TX_N0
TBT_A_TTX_R_ DRX_P1
TBT_A_TTX_R_ DRX_N1
ESD@
12
DESD3V3Z1BCSF-7 X2-DSN 0603-2
DT14
ESD@
12
DESD3V3Z1BCSF-7 X2-DSN 0603-2
DT17
ESD@
12
DESD3V3Z1BCSF-7 X2-DSN 0603-2
DT18
ESD@
12
DESD3V3Z1BCSF-7 X2-DSN 0603-2
e
DT40
TBTA_SBU2TBTA_SBU2
TBTA_BOT_N_R
TBTA_BOT_P_R
TBTA_CC2TBTA_CC2
ESD@
1
1
2
2
4
4
5
5
3
3
8
AZ1045-04F_DFN25 10P10E-10-9
9
10
8
9
7
7
6
6
TBTA_BOT_N_R
TBTA_BOT_P_R
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document N umberRe v
Size Document N umberRe v
Size Document N umberRe v
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
USB 3.0 CONN TYPE C
USB 3.0 CONN TYPE C
USB 3.0 CONN TYPE C
LA-G871P
LA-G871P
LA-G871P
1
45109Tuesday, March 05, 2019
45109Tuesday, March 05, 2019
45109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 46
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
TYPE-C_Port2 (1/2)
TYPE-C_Port2 (1/2)
TYPE-C_Port2 (1/2)
LA-G871P
LA-G871P
LA-G871P
46109Tuesday, March 05, 2 019
46109Tuesday, March 05, 2 019
46109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 47
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
TYPE-C_Port2 (2/2)
TYPE-C_Port2 (2/2)
TYPE-C_Port2 (2/2)
LA-G871P
LA-G871P
LA-G871P
47109Tuesday, March 05, 2 019
47109Tuesday, March 05, 2 019
47109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 48
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
TYPE-C_Port3 (1/2)
TYPE-C_Port3 (1/2)
TYPE-C_Port3 (1/2)
LA-G871P
LA-G871P
LA-G871P
48109Tuesday, March 05, 2 019
48109Tuesday, March 05, 2 019
48109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 49
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
TYPE-C_Port3 (2/2)
TYPE-C_Port3 (2/2)
TYPE-C_Port3 (2/2)
LA-G871P
LA-G871P
LA-G871P
49109Tuesday, March 05, 2 019
49109Tuesday, March 05, 2 019
49109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 50
5
Reserve for external PD power
4
3
2
1
+5V_ALW
DT1,DT2,DT3 change footprint to
1N4148WS -7-F_SOD32 3-2
DD
+5V_TBT _VBUS
1N4148W S-L_SOD323 -2
1U_0201_10V6M
@
CC
1
CT193
2
follow DFX request
1N4148W S-L_SOD323 -2
1N4148W S-L_SOD323 -2
DT3@
12
DT1@
12
DT2@
12
+5V_TBT A_VBUS_D
+5V_PD_ VDD
100K_0402_5%
0.1U_0201_10V6K
@
12
RT393
1
2
@
UT8
1
VCC
3
VOUT
AP2204R -5.0TRG1_SOT89 -3
GND
2
@
CT88
1
2
1U_0201_10V6M
@
CT89
+20V_TB TA_VBUS_1
1U_0603_25V6K
12
@
CT94
@
RT111
12
100K_04 02_5%
1
CT90
@
1U_0201 _10V6M
2
@
UT7
1
VCC
2
GND
3
EN
AP2112K -3.3TRG1_SOT23 -5
VOUT
ADJ/NC
5
4
+3.3V_VD D_PIC_R
100P_0201_25V8J
@RF@
1
CT359
2
RF Request
place near UT7
+3.3V_TB TA_FLASH
0.1U_0201_10V6K
2.2U_0402_10V6M
@
1
1
CT91
2
2
place near UT17
12
RT3990_04 02_5%@
12
RT3980_04 02_5%@
@
CT92
+3.3V_VD D_PIC
1031 change
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
[Type C]PD Power
[Type C]PD Power
[Type C]PD Power
LA-G871P
LA-G871P
LA-G871P
50109Tuesday, March 05, 2 019
50109Tuesday, March 05, 2 019
50109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 51
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
LAN
LAN
LAN
LA-G871P
LA-G871P
LA-G871P
51109Tuesday, March 05, 2 019
51109Tuesday, March 05, 2 019
51109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 52
RF Request
+2.7V_ANT
100P_0402_50V8J
RF@
CZ198
place near JNGFF2
CNV_COEX1 <6>
CNV_COEX2 <6>
CNV_COEX3 <6>
NA
3
100P_0201_25V8J
27P_0201_25V8
RF@
RF@
1
1
CZ307
CZ233
2
2
WLAN
M3042_PCIE#_SATA
3
+1.8V_ANT
100P_0201_25V8J
RF@
27P_0201_25V8
RF@
1
1
CZ234
CZ308
2
2
CNV_PRX_D TX_N1<6>
CNV_PRX_D TX_P1<6>
CNV_PRX_D TX_N0<6>
CNV_PRX_D TX_P0<6>
CLK_CNV_P RX_DTX_N<6>
CLK_CNV_P RX_DTX_P<6>
PCIE_PTX_DRX _P10<10>
PCIE_PTX_DRX _N10<10>
CZ120.1U_0402_25V 6
CZ130.1U_0402_25V 6
CNV_PTX_DRX _N1<6>
CNV_PTX_DRX _P1<6>
CNV_PTX_DRX _N0<6>
CNV_PTX_DRX _P0<6>
CLK_CNV_P TX_DRX_N<6>
CLK_CNV_P TX_DRX_P<6>
WLAN_ WIGIG60GHZ_DIS#<58>
BT_RADIO_DIS#< 58>
WWAN_MIPI_ ANT_ DAT and WWAN_MIPI_ ANT_CLK
(1)Th e trace le ngth < 30cm
This max leng th guidan ce is practical level of definitio n.
(2)Spacing to all other sig nal need 4x line width
1 2
1 2
PCIE_PRX_DTX _P10<10>
PCIE_PRX_DTX _N10<10>
CLKREQ_PCIE #1<11>
CLK_PCIE_P1<11>
CLK_PCIE_N1<11>
PCIE_WA KE#<42,59 ,68>
USB20_P10 _R
USB20_N10 _R
CLK_CNV_P RX_DTX_N
CLK_CNV_P RX_DTX_P
CNV_PTX_DRX _N1
CNV_PTX_DRX _P1
CNV_PTX_DRX _N0
CNV_PTX_DRX _P0
CLK_CNV_P TX_DRX_N
CLK_CNV_P TX_DRX_P
For WWAN 4x4 Antenna
1130 change1130 change
@RF@
12
RZ14600_0201_5%
+1.8V_ANT
+2.7V_ANT
WW AN_MIPI_ANT_CLK
WW AN_MIPI_ANT_DAT
High
Low
Low
Low
Low
CONN@
JANT1
1
1
2
2
3
3
4
4
5
5
6
GND1
7
GND2
8
GND3
9
GND4
10
GND5
11
GND6
12
GND7
13
GND8
I-PEX_20854-0 05E-00
Relink 20854-005E-00 done 0827
RF Request
+2.7V_ANT
place CZ227,CZ228 as close as JANT1 place CZ229,CZ230 as close as JANT2
120P_0402_50V8
120P_0402_50V8
RF@
1
1
CZ227
2
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
CNV_PRX_D TX_N1
CNV_PRX_D TX_P1
CNV_PRX_D TX_N0
CNV_PRX_D TX_P0
PCIE_PTX_C_DRX_P10
PCIE_PTX_C_DRX_N10
PCIE_WA KE#
RB751S-40_ SOD523-2
RB751S-40_ SOD523-2
@RF@
RZ14610_0201_5%
+1.8V_ANT
+2.7V_ANT
RF@
CZ228
3.3V_1
3.3V_2
W_DISABLE#
LED1#
I2S_CLK
I2S_RX
I2S_TX
W_DISABLE2#
I2S_WA
UIM-RESET
UIM-CLK
UIM-DATA
UIM-PWR
DEVSLP
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
PERST#
CLKREQ#
PEWAKE#
NC_1
NC_2
COEX3
COEX2
COEX1
SIM_DETECT
SUSCLK
3.3V_3
3.3V_4
3.3V_5
GND_12
GND_13
4
+3.3V_WW AN
2
4
WW AN_FULL_PW R_EN
6
WWAN_RADIO_DIS#_R
8
SLOT2_SATA_LE D#
10
1211 change,add netname +2.7V_ANT_R and +1.8V_ANT_R
+2.7V_ANT_R
20
22
+1.8V_ANT_R
24
GPS_DISABLE #_R
26
28
UIM_RESET
30
UIM_CLK
32
UIM_DATA
34
36
38
40
42
44
46
48
PCH_PLTRST#_A ND
50
52
PCIE_WA KE#
54
WW AN_MIPI_ANT_DAT
56
WW AN_MIPI_ANT_CLK
58
WWAN_COEX3
60
WWAN_COEX2
62
WWAN_COEX1
64
SIM_DET
66
WW AN_ANT_CONFIG
68
70
72
74
76
0103 change
77
+3.3V_WW AN
WWAN_FULL_PW R_EN <9>
12
RZ14770_0201_5%@
12
RZ900_0603_5%
12
RZ910_0603_5%
1031 change,RZ90 RZ91 reserve for FUSE location
+SIM_PWR
ISH_I2C2_SCL_R
ISH_I2C2_SDA_ R
RZ760_0201_5%@
RZ770_0201_5%@
9/24: Reserve for embedded location ,refer Intel PDG 0.9
470_0402_1%
i7@
12
RZ1450
t
0
WWAN_RADIO_DIS#<58>
GPS_DISABLE#<58>
WW AN_FULL_PW R_EN
12
RZ4310K_0402_5%
Module provides for 4 x4 Antenna use
12
12
CLKREQ_PCIE #0 < 11>
12
RZ1280_020 1_5%@RF@
12
RZ1290_020 1_5%@RF@
12
RZ1300_020 1_5%@RF@
12
RZ3730_020 1_5%@RF@
12
RZ3720_020 1_5%@RF@
12
RZ3740_020 1_5%@RF@
ANT_CONFIG
Antenna Configuration
RZ1450
4x4 Antenna
Pop
Depop
2x2 Antenna
WWAN_RADIO_DIS#_R
21
DZ5
RB751S-40_ SOD523-2
RB751S-40_ SOD523-2
GPS_DISABLE#_R
21
DZ6
12
+2.7V_ANT
+1.8V_ANT
M3042_DEVSLP <10>
ISH_I2C2_SCL < 9>
ISH_I2C2_SDA < 9>
WLAN_ COEX3
WLAN_ COEX2
WLAN_ COEX1
CNV_COEX1
CNV_COEX2
CNV_COEX3
5
NGFF slot B Key B
CONN@
JNGFF2
11
21
23
12
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
78
79
1
CONFIG_3
3
GND_1
5
GND_2
7
USB_D+
9
USB_D-
GND_3
CONFIG_0
WOWWAN#
DPR
GND_4
PERN1/USB3.0-RX-/SSIC-RXN
PERP1/USB3.0-RX+/SSIC-RXP
GND_5
PETN1/USB3.0-TX-/SSIC-TXN
PETP1/USB3.0-TX+/SSIC-TXP
GND_6
PERN0/SATA-B+
PERP0/SATA-B-
GND_7
PETN0/SATA-A-
PETP0/SATA-A+
GND_8
REFCLKN
REFCLKP
GND_9
ANTCTL0
ANTCTL1
ANTCTL2
ANTCTL3
RESET#
CONFIG1/PEDET_OC-PCIE/GND-SATA
GND_10
GND_11
CONFIG2/USB3.0IND/GND-OTHER
NPTH_1
NPTH_2
DEREN_40-42 313-06711RHFA N
FULL_CARD_POWER_OFF#
NGFF_CONFIG_3<5 8>
DD
NGFF_CONFIG_0<5 8>
WW AN_WA KE#<58>
Swap PN for support SATA
PCIE_PRX_DTX _P12<10>
PCIE_PRX_DTX _N12<10>
1 2
PCIE_PTX_DRX _N12<10>
PCIE_PTX_DRX _P12<10>
CZ2100.1 U_0402_25V6
1 2
CZ2110.1 U_0402_25V6
CLK_PCIE_N0<11>
CLK_PCIE_P0<11>
NGFF_CONFIG_1<54,58>
NGFF_CONFIG_2<58>
USB20_P7_ L
USB20_N7_ L
RZ3260_ 0201_5%@RF@
PCIE_PRX_L_ DTX_N11
PCIE_PRX_L_ DTX_P11
PCIE_PTX_L_DR X_N11
PCIE_PTX_L_DRX_P11
PCIE_PTX_C_DRX_N12
PCIE_PTX_C_DRX_P12
Link DEREN_40-42313-06711RHFAN done 0410
RF Request
CC
+3.3V_WW AN
.047U_0402_16V7K
.047U_0402_16V7K
33P_0402_50V8J
22U_0603_6.3V6M
12
12
CZ17
CZ20
12
12
12
CZ18
CZ19
Merion14swapLI16,LI17netforlayoutroutin
PCIE_PRX_SW_DTX_N11<54>
PCIE_PRX_SW_DTX_P11<54>
+3.3V_WW AN
33P_0402_50V8J
CZ21
g
Follow KW13 MLK delete C I29,CI30
PCIE_PTX_SW_DRX_N11<54>
BB
PCIE_PTX_SW_DRX_P11<54>
47P_0402_50V8J
RF@
12
CZ23
Place close JNGFF2 connec tor
100P_0402_50V8J
2000P_0402_50V7K
RF@
RF@
12
12
CZ24
CZ25
LI16
RF@
12
HCM1012GH90 0BP_4P
LI17
RF@
12
HCM1012GH90 0BP_4P
100U_B3_6.3VM_R45M
RF@
27P_0402_50V8J
RF@
1
CZ26
1
+
CZ311
2
2
MeriondeleteRI27~RI30Forlayoutplayoutplacement
34
34
1213 change
Add CZ311 and CZ312 for RF request
1130change
27P_0402_50V8J
RF@
Merion14Limitheigh
1
CZ26changetoSGA00006800
CZ312
fromSGA00005T0
2
PCIE_PRX_L_DTX_N11
PCIE_PRX_L_DTX_P11
PCIE_PTX_L_DRX_N11
PCIE_PTX_L_DRX_P11
SIM Card Push-Push
JSIM1 CONN@
C8
+SIM_PWR
4.7U_0402_6.3V6M
CZ37
UIM_DATA
UIM_CLK
UIM_RESET
12
SIM_DET
RFU1
C7
IO
C6
VPP
C5
GND
C4
RFU2
C3
CLK
C2
RST
C1
VCC
1
DLSW
2
DTSW
TAISO_159-100030 0600
GND1
GND2
GND3
GND4
GND5
GND6
GND7
NPTH1
NPTH2
Link TAISO_159-1000300600 done 0903
UIM_DATA
5
+SIM_PWR
12
12
@RF@
15K_0402_5%
RZ335
33P_0402_50V8J
@RF@
CZ39
RF Request
UIM_CLK
47P_0402_50V8J
AA
@RF@
12
CZ38
@RF@
51_0402_5%
12
RZ334
3
4
5
6
7
8
9
10
11
UIM_RESET
DW5821e SPEC Request
@ESD@
DZ13
UIM_DATA
1
1
UIM_CLK
2
2
UIM_RESET
4
4
SIM_DET
5
5
3
3
8
AZ1045-04F_D FN2510P10E-10 -9
+SIM_PWR
33P_0402_50V8J
@RF@
0.1U_0402_25V6
RF@
1
12
CZ40
CZ41
2
RF Request
UIM_DATA
9
10
UIM_CLK
8
9
UIM_RESET
7
7
SIM_DET
6
6
USB20_P7<10>
USB20_N7<10>
CONFIG_0CONFIG_2 CONFIG_3
STATE #
GND
GND
14
HIGH
15
HIGHHIGH
4
MeriondeleteRI47,RI48Forlayoutplayoutplacement
LI8
12
MCM1012B9 00F06BP_4P
CONFIG_1
GND
GND
GND
HIGH
GND
GND
GND
HIGH
HIGH
RF@
USB20_P7_L
USB20_N7_L
34
Module Type
GND
SSD-SATA
GND
SSD-PCIE(2 lane)
GNDHIGH
HIGH
WW AN
HCA-PCIE(1 lane)
HIGH
2
NGFF slot E Key E
1
GND_1
3
USB_D+
5
USB_D-
7
GND_2
9
SIDO_CLK
11
SDIO_CMD
13
SDO_DAT0
15
SDO_DAT1
17
SDO_DAT2
19
SDO_DAT3
21
SDIO_WAKE#
23
SDIO_RESET#
33
GND_4
35
PETP0
37
PETN0
39
GND_5
41
PERP0
43
PERN0
45
GND_6
47
REFCLKP0
49
REFCLKN0
51
GND_7
53
CLKEQ0#
55
PEWAKE0#
57
GND_8
59
RSRVD/PETP1
61
RSRVD/PETN1
63
GND_9
65
RSRVD_2/PERP1
67
RSRVD_4/PERN1
69
GND_10
71
RSVD_7
73
RSVD_8
75
GND_11
77
GND_13
79
NPTH_2
LOTES_APCI0128 -P005A
Link APCI0128-P005A done 0122
1218
Change net name from CNV_RF_RESET to CNV_DET#_EC
WLAN_WIGIG60GHZ_DIS#_R
21
DZ1
BT_RADIO_DIS#_R
21
DZ2
CONN@
2
I-PEX_20854-0 05E-00
120P_0402_50V8
RF@
1
CZ230
2
JANT2
1
1
2
2
3
3
4
4
5
5
6
GND1
7
GND2
8
GND3
9
GND4
10
GND5
11
GND6
12
GND7
13
GND8
12
WW AN_MIPI_ANT_CLK
WW AN_MIPI_ANT_DAT
+2.7V_ANT
+1.8V_ANT+ 1.8V_ANT
120P_0402_50V8
RF@
1
CZ229
2
CONN@
3.3VAUX_1
3.3VAUX_2
LED1#
PCM_CLK
PCM_SYNC
PCM_IN
PCM_OUT
LED2#
GND_3
UART_WAKE#
UART_RX
UART_TX
UART_CTS
UART_RTS
CLink_RST
CLink_DATA
CLink_CLK
COEX3
COEX2
COEX1
SUSCLK(32KHz)
PERST0#
W_DISABLE2#
W_DISABLE1#
I2C_DATA
I2C_CLK
ALERT
RSVD_1
RSVD_3
RSVD_5
RSVD_6
3.3VAUX_3
3.3VAUX_4
GND_12
NPTH_1
JNGFF1
CNV_RF_RESET#<12,52>
+3.3V_WLAN
2
4
6
8
10
12
14
16
18
20
22
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
CNV_DET#_EC<5 8>
CNV_BRI_PTX_D RX_R
CNV_RF_RES ET#
CLKREQ_CNV #_R
CNV_BRI_PRX _DTX_R
CNV_RGI_PTX_DR X_R
CNV_RGI_PRX_ DTX_R
CNV_BRI_PTX_D RX_R
WLAN_ COEX3
WLAN_ COEX2
WLAN_ COEX1
WIGIG_32KHZ
PCH_PLTRST#_A ND
BT_RADIO_DIS#_R
WLAN_WIGIG60GHZ_DIS#_R
ISH_UART0_RXD_ R
ISH_UART0_TXD_R
ISH_UART0_CTS#_R
12
75K PD at PCH side
VGS(th)Max=1.5V
CNV_RF_RESET# <12,52>
RZ138122_0402_5%
10K_0402_5%
@
1206 change
RZ752
Follow NB14 UU AR, for CNVI CLK request
+3.3V_ALW
G
2
+3.3V_WLAN
RF Request
+3.3V_WLAN
15P_0402_50V8J
RF@
12
CZ33
USB20_N10<10>
USB20_P10<10>
RZ780_0201_5%@
RZ790_0201_5%@
RZ800_0201_5%@
12
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size
Size
Size
Document Num berRe v
Document Num berRe v
Document Num berRe v
Date :Sheetof
Date :Sheetof
Date :Sheetof
1
CLKREQ_CNV# <12>
CNV_BRI_PRX _DTX <9>
CNV_RGI_PTX_DR X_R <9>
CNV_RGI_PRX_ DTX <9>
CNV_BRI_PTX_D RX_R <9>
SUSCLK <11,68>
REFCLK_CNV _L <11>
RZ8270_020 1_5%@
CNVI_EN# <12>
+1.8V_PRIM
1206 change
Follow NB14 UU AR
Add RZ603 for CNVi intel request
Close to connector
12
RZ60310K_ 0402_5%@
CLKREQ_CNV #
12
RZ13850_02 01_5%@
12
12
RZ138322_0402_5%
PCH_CL_RS T1# <8>
PCH_CL_DA TA1 <8>
PCH_CL_CLK 1 <8>
12
PCH_PLTRST#_A ND <11,38,42,68, 70>
9/24: Reserve for embedded location ,refer Intel PDG 0.9
12
13
D
S
RZ560_0201_5%@
12
12
12
100K_0402_5%
RZ377
1218
Add RZ827 connect to CNVI_EN# for reserve
12
QZ17
PJE138K_ SOT523-3
1130 change
10U_0603_10V6M
1
12
CZ27
2
Place near JNGFF1.2/JNGFF1.4Place near JNGFF1.72/JNGFF1.74
100P_0402_50V8J~D
15P_0402_50V8J
RF@
RF@
12
12
CZ204
CZ36
RF Request
LI9
RF@
MCM1012B9 00F06BP_4P
NGFF Card
NGFF Card
NGFF Card
LA-G871P
LA-G871P
LA-G871P
1
0.01UF_0402_25V7K
12
34
4.7U_0402_10V6M
0.1U_0201_10V6K
1
1
CZ29
CZ31
2
2
100P_0402_50V8J~D
RF@
27P_0402_50V8J
RF@
1
1
CZ205
CZ206
2
2
USB20_N10 _R
USB20_P10 _R
52109Tuesday, Marc h 05, 2019
52109Tuesday, Marc h 05, 2019
52109Tuesday, Marc h 05, 2019
0.01UF_0402_25V7K
0.1U_0201_10V6K
1
CZ28
CZ30
2
Place near JNGFF1 c onnector
1213 change RF request
CZ206 and CZ207 from depop to pop and Change Value from 100 p to 27p
15P_0402_50V8J
15P_0402_50V8J
RF@
RF@
12
12
CZ34
CZ35
MeriondeleteRI49,RI50Forlayoutplayoutplacement
12
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CZ32
27P_0402_50V8J
RF@
CZ207
1.0
1.0
1.0
Page 53
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
WIGIG / WIDI
WIGIG / WIDI
WIGIG / WIDI
LA-G871P
LA-G871P
LA-G871P
53109Tuesday, March 05, 2 019
53109Tuesday, March 05, 2 019
53109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 54
5
DD
4
3
2
1
PCIE/USB MUX/DEMUX SW
Link TI HD3SS3212 done
+3.3V_WWAN
0.01U_0402_16V7K
CC
UZ29
19
B0p
18
B0n
17
B1p
16
B1n
15
C0p
14
C0n
13
C1p
12
C1n
9
SEL
2
OEn
HD3SS3212RK SR_VQFN20_2P5X4P5
GND
GND
GND
HIGH
HIGH
LH
HX
GND
GND
HIGH
HIGH
USB3_PRX_DTX_P4
USB3_PRX_DTX_N4
USB3_PTX_C_DR X_P4
USB3_PTX_C_DR X_N4
PCIE_PRX_DTX_P11
PCIE_PRX_DTX_N11
PCIE_PTX_C_DRX_P11
PCIE_PTX_C_DRX_N11
NGFF_CONFIG_1
CONFIG_1
GND
HIGH
GND
GND
HIGHHIGH
CONFIG_2 CONFIG_3
USB3_PRX_DTX_P4<10>
USB3_PRX_DTX_N4<10>
USB3_PTX_DRX_P4<10>
USB3_PTX_DRX_N4<10>
PCIE_PRX_DTX_P11<10>
PCIE_PRX_DTX_N11<10>
PCIE_PTX_DRX_P11<10>
PCIE_PTX_DRX_N11<10>
Functio n
B to A
1 2
CZ1500.1U_0402_10V7K
1 2
CZ1510.1U_0402_10V7K
1 2
CZ1520.22U_0402_10V6K
1 2
CZ1530.22U_0402_10V6K
NGFF_CONFIG_1<52,58>
SEL OEn
LL
C to A
All ports Hi-Z,
BB
IC power down
STATE #
CONFIG_0
0
1
8
14
15
GND
GND
GND
HIGH
HIGH
1
NC1
6
VCC
10
NC2
3
A0p
4
A0n
7
A1p
8
A1n
5
GND1
11
GND2
20
GND3
21
PGND
SSD-PCIE(2 lane)
HCA-PCIE(1 lane)
PCIE_PRX_SW_DT X_P11
PCIE_PRX_SW_DT X_N11
PCIE_PTX_SW_DR X_P11
PCIE_PTX_SW_DR X_N11
Module Type
SSD-SATA
WWAN
NA
1
2
M3042_PCIE#_SATA
HIGH
LOW
LOW
LOW
LOW
10U_0402_10V6M
.1U_0402_16V7K
Follow TI SPEC
Add reserved CZ156 10uF.
@
1
1
CZ154
2
PCIE_PRX_SW_DTX_P11 <52>
PCIE_PRX_SW_DTX_N11 <52>
PCIE_PTX_SW_DRX_P11 <52>
PCIE_PTX_SW_DRX_N11 <5 2>
CZ154 change to 0.0 1uF feom 0.1uF.
CZ156
CZ155
2
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document N umberRe v
Size Document N umberRe v
Size Document N umberRe v
Date :Sheetof
Date :Sheetof
Date :Sheet
Compal Electronics, Inc.
USB/PCIE MUX HD3SS3212
USB/PCIE MUX HD3SS3212
USB/PCIE MUX HD3SS3212
LA-G871P
LA-G871P
LA-G871P
1
54109Tuesday, March 05, 2019
54109Tuesday, March 05, 2019
54109Tuesday, March 05, 2019
1.0
1.0
1.0
of
Page 55
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
Reserve for PCIE device
Reserve for PCIE device
Reserve for PCIE device
LA-G871P
LA-G871P
LA-G871P
55109Tuesday, March 05, 2 019
55109Tuesday, March 05, 2 019
55109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 56
5
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units i n one speaker box.)
Internal Speakers Header
40 mils trace keep 20 mil spacing
12
LA6BLM15P D800SN1D_2PEMI@
12
INT_SPK_R+
INT_SPK_R-
DD
1000P_0402_50V7K
12
LA7BLM15P D800SN1D_2PEMI@
12
LA8BLM15P D800SN1D_2PEMI@
12
LA9BLM15P D800SN1D_2PEMI@
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
12
12
12
CA22@EMI@
CA24@EMI@
CA19@EMI@
CA23@EMI@
SMART_SPK_DET0#<12>
SMART_SPK_DET1#<9>
Close to UA1
Close to UA1 pin14
HDA_BIT_CLK_R
33_0402_5%
12
RA17RF@
10P_0402_50V8J
12
CA33RF@
CC
+3.3V_RUN_AUDIO
Place closely to Pin 48.
AUD_HP_NB _SENSE
DMIC_CLK0
12
place close to UA1 pin5
100K_0402_1%
12
RA59
AUD_SENS E_A
200K_0402_1%
12
RA60
100P_0402_50V8J
CA54RF@
0.1U_0402_25V6
@
12
CA41
Only Merion14 support 3 vendor
10
INT_SPKR_L+INT_SPK_L+
INT_SPKR_L-INT_SPK_L-
INT_SPKR_R+
INT_SPKR_R-
SMART_SPK_DET0#
SMART_SPK_DET1#
9
8
7
6
5
4
3
2
1
ACES_5027 8-00801-001
Link ACES_50278-00801-001 DONE 0809
2
2
1
1
3
2
2
1
1
Add for solve
pop noise and
detect issue
CLASS-D POWER DOWN CONTROL CIRCUIT
BB
12
RA480_0201_5%@
21
DA8
1
2
3
4
5
6
7
5
@
@
@
UZ5
VIN1_1
VIN1_2
ON1
VBIAS
ON2
VIN2_1
VIN2_2
EM5209VF_ SON14_2X3
RB751S-40_ SOD523-2
12
RA500_0201_5%
+5V_RUN_A UDIO_UZ5
14
VOUT1_2
13
VOUT1_1
12
CT1
11
GND
10
CT2
9
VOUT2_2
+3.3V_RUN_AUDIO_UZ5
8
VOUT2_1
15
GPAD
PD#
+5V_RUN_AUDIO
12
CZ125 0.1U_0201_ 10V6K@
CZ126
@
CZ127
@
CZ128 0.1U_0201_ 10V6K@
+5V_RUN
@JUMP@
PJP15
+3.3V_RUN+3.3V_RUN_AUDIO
PAD-OPEN1x1m
1 2
1 2
220P_0402_ 50V7K
1 2
1000P_0402 _50V7K
PJP16@JUMP @
12
PAD-OPEN1x1m
1 2
NB_MUTE#<58>
HDA_RST#_R<12>
HDA_Link is 3.3V,no need level shi ft circuit
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN
0809 change to 1U 0201*2 for MLCC shortage
only Samsung,Taiyo,Murata can use
Vendor3
VECO
Zylux
Low
High
Low
High
HDA_SDOUT_R
HDA_SDIN0_R
12
RA933_0402_5%
Place R A9 close to codec
12
12
RA14 EMI@22_0402_5%
12
RA1810K_0402_5 %
12
CA311U_ 0201_6.3V6M
AUD_SENSE_B
12
RA61100K_04 02_1%
12
CA352.2 U_0402_6.3V6 M
12
RA44100K_04 02_5%
12
CA5110U_0603_10 V6M
12
CA25
12
RA62.2 K_0402_5%
12
RA52.2 K_0402_5%
CPVEE
CBN
CBP
12
CA5210U_0603_10 V6M
12
CA5310U _0603_10V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1
1
CA29
CA76
2
2
place at AGND and DGND plane
12
RA35 0_04 02_5%@
12
RA36 0_04 02_5%@
12
RA37 0_04 02_5%@
RA52100 K_0402_5%
PD#
1031 change
1
2
1U_0201_6.3V6K
CA49
3
+3.3V_RUN_ AUDIO_IO
0.1U_0201_10V6K
10U_0603_10V6M
1
12
CA55
CA56
2
place close to pin18
LA5
12
0.1U_0201_10V6K
10U_0603_10V6M
BLM15PX6 00SN1D_2P
CA8
1
12
CA9
2
UA1
6
I2C DATA
7
I2C CLK
15
SYNC
14
BCLK
17
SDATA-OUT
13
DC DET/EPAD
16
SDATA-IN
11
I2S-MCLK
10
I2S-BCLK
9
I2S-OUT
12
I2S-LRCK
8
I2S-IN
1
I2S-EN/SPDIF-OUT/GPIO2/DMIC-DATA34/DM IC-CLK-IN
4
GPIO0/DMIC-DATA12
5
GPIO1/DMIC-CLK
2
PDB
48
JD1
47
JD2
38
VREF
39
LDO1-CAP
32
MIC2-CAP
29
MIC2-VREFO-R
28
MIC2-VREFO-L
25
CPVEE
24
CBN
23
CBP
21
LDO2-CAP
19
LDO3-CAP
CPVEECBP
1U_0201_6.3V6K
1
CA77
2
RING2
AUD_HP_OUT_L
AUD_HP_OUT_R
SLEEVE
JUMP@
PJP19
12
PAD-OPEN1x1m
3
EMI@
LA10B LM15PX330S N1D_2PESD@
LA15B LM15PX330S N1D_2PEMI@
LA16
LA11B LM15PX330S N1D_2PESD@
+5V_RUN_PVDD_L
MIC2-L/RING2
MIC2-R/SLEEVE
SPK-OUT-R+
5VSTB/AUX MODE
CPVDD/AVDD2
ALC3254-VA 3-CG_MQFN48_6X 6
12
12
12
12
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
Add t his Filter to avoid other
components/chips be influenced
ESD@
ESD@
3
3
2
DA1
DA2
AZ5123-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
1
680P_0402_50V7K
@ESD@
1
CA13
2
AUD_HP_NB _SENSE
3
2
1
SPKR_R
12
SPKR <12>
BEEP <58>
HP-Out-Right
HP-Out-L ef t
Universal Jack
7
4
1
5
6
2
3
ESD@
DA3
AZ5123-02S.R7G_SOT23-3
680P_0402_50V7K
@ESD@
Link 2SJ3095-085111F done 0123
1
CA12
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size
Size
Size
Document Num berRe v
Document Num berRe v
Document Num berRe v
Date :Sheetof
Date :Sheetof
Date :Sheetof
1
100P_0402_50V8J
CA72@
10K_0402_5%
12
RA51
+1.8V_RUN_ AUDIO
RF@
33P_0402_50V8J
CA69
1
2
Nokia-MIC
BEEP_R
iPhone-MIC
Global Headset
JHP1
CONN@
GND
#4 G/M
#1 L/R
#5
#6 AGND
#2 R/L
#3 M/G
SINGA_2SJ30 95-085111F
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Codec ALC3204
Codec ALC3204
Codec ALC3204
LA-G871P
LA-G871P
LA-G871P
1
+5V_RUN_A UDIO
Norma l
Open
100P_0402_50V8J
12
12
CA62@
RF Request
12P_0402_50V8J
RF@
1
1
CA63
2
2
RF Request
+1.8V_RUN
12P_0402_50V8J
RF@
1
CA65
2
RF Request
+3.3V_RUN_ AUDIO
12P_0402_50V8J
RF@
1
CA67
2
56109Tuesday, Marc h 05, 2019
56109Tuesday, Marc h 05, 2019
56109Tuesday, Marc h 05, 2019
10K_0402_5%
RA45
68P_0402_50V8J
RF@
CA64
68P_0402_50V8J
RF@
1
CA66
2
68P_0402_50V8J
RF@
1
CA68
2
1.0
1.0
1.0
Page 57
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
TYPEC_ID <59>
SYSTEM_ID <59>
BOARD_ID <59>
1
@
PAD~D
1
@
PAD~D
GPS_DISABLE# <52>
HOST_DEBUG_TX <79>
ME_FWP <79>
UPD1_SMB INT# <44>
PCIE_WAKE#_R <59>
PTP_DISABLE# <63>
FPR_PWR_EN# <66>
FPR_SSO_EN# <66>
NGFF_CONFIG_1 <52,54>
NGFF_CONFIG_0 <52>
BREATH_LED# <64>
BAT1_LED# <64>
BAT2_LED# <64>
LCD_VCC_TEST_EN <38 >
USH_EXPANDER_SMBDAT <66>
USH_EXPANDER_SMBCLK <66>
VCCDSW_EN < 11>
1
@
PAD~D
PBAT_CHARGER_SMBDAT <83,84>
PBAT_CHARGER_SMBCLK <83,84>
NGFF_CONFIG_2 <52>
LED_MASK# <64>
UPD1_SMBDAT <44>
UPD1_SMBCLK <44>
12
RE64300_0402 _5%
12
RE3123 00_0402_5%
12
RE3180_0201_ 5%@
RE6080_0201_ 5%@
USB_POWERSHARE_VBUS_EN <71>
12
RE6010 _0201_5%@
12
RE5391 00_0402_5%
3.3V_TS_EN <38>
SSD_SCP# <68>
12
12
RE3610 _0201_5%@
RE6030 _0201_5%@
1
T341
@
PAD~D
ACAV_IN <79,84,91>
ALWON <85>
POWER_SW_IN# <59,79>
3.3V_WWA N_EN <78>
1 2
CE5410P_0402_50V8 J@
12
RE6043_0402_5%
1 2
CE242200P_0402_50V 7K
1 2
CE262200P_0402_50V 7K
1 2
CE272200P_0402_50V 7K
VSET_5105 <59>
I_ADP <84>
THERMTRIP2# <59>
12
RE288100_040 2_5%
RE546
21
RB751S-40_ SOD523-2
RTCRST_ON_POW ER_R1RTCRST_ON_POW ER_R
2
G
22P_0402_50V8J
12
CE65
+3.3V_ALW_UE1
+1.8V_PRIM_VTR3
RUN_ON_EC<59>
BT_RADIO_DIS#<52>
PBAT_PRES#< 83,84>
PANEL_MONITOR<79>
AC_PRESENT<11>
SML1_SMBCLK<8>
WWAN_W AKE#<52>
SIO_PWRBTN#<11,79>
LID_CL_SIO#<59>
JTAG_TDI<79>
JTAG_TDO<79>
JTAG_CLK<79>
JTAG_TMS<79>
TACH_FAN1<77>
LCD_TST<38>
PWM_FAN1<77>
PCH_RSMRST#<63,79>
BIA_PWM_EC<38>
FPR_SCAN_ INT#<66>
HW_AC AVIN_NB<82,8 4>
PANEL_BKEN_EC<38>
FPR_DET#<66>
BCM5882_A LERT#< 66>
MSDATA<79>
NB_MUTE#<56>
EN_INVPWR<38>
IMVP_VR_ON_EC<59>
FPR_UEFI_MGMT#<66>
M_BIST<79>
RTD3_SELECT<42>
AC_DISC#<82>
USH_DET#<66>
BC_CLK_EC E1117<63>
NGFF_CONFIG_3<5 2>
12
ESPI_RESET#<8,79>
ESPI_ALERT#<8>
ESPI_CLK_5105<8,79>
ESPI_CS#<8,79>
ESPI_IO0<8,79>
ESPI_IO1<8,79>
ESPI_IO2<8,79>
ESPI_IO3<8,79>
PS_ID<82>
BEEP<56>
AC_DIS<84>
MSCLK<79>
4
+RTC_CELL_VBAT
0.1U_0201_10V6K
CE11
1
2
+3.3V_EC_ PLL
PCH_DPW ROK_EC
RUN_ON_EC
SIO_EXT_W AKE#_EC
BT_RADIO_DIS#
SIO_SLP_SUS #_R
PANEL_MON ITOR
WW AN_WA KE#
FPR_LOW _PWR_M ODE#
WLAN_ WIGIG60GHZ_DIS#
SLP_W LAN#_GATE_R
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
LCD_TST
CNV_DET#_EC
PCH_RSMRS T#
PS_ID
FPR_SCAN_ INT#
HW_AC AVIN_NB
BEEP
FPR_DET#
AC_DIS
MSCLK
MSDATA
EN_INVPW R
RESET_IN#
IMVP_VR_ON_ EC
RTD3_SELECT
BSMB_W P_INT#_R
RTCRST_ON
WW AN_RADIO_DIS#
SYSPW R_PRES
VBUS1_EC OK
ESPI_ALERT#
ENABLE_D S#
SSD_SCP_ PWR_EN
RESET_OUT
DCIN1_EN
MEC_XTAL1
MEC_XTAL2_R
4
1031 change
UE1
A2
VBAT
B7
VTR_ANALOG
K2
VREF_ADC
F1
VTR_PLL
H1
VTR_REG
G8
VTR1
M9
VTR2
N5
VTR3
F8
GPIO020
E8
GPIO045
M12
GPIO120
C2
GPIO166
F9
GPIO175
N4
GPIO230
M8
GPIO231
K8
GPIO233
E11
GPIO007/SMB03_DATA/PS2_CLK0B
D8
GPIO010/SMB03_CLK/PS2_DAT0B
M13
GPIO110/PS2_CLK2
K12
GPIO111/PS2_DAT2
L13
GPIO112/PS2_CLK1A
K11
GPIO113/PS2_DAT1A
K10
GPIO114/PS2_CLK0A/nEC_SCI
N11
GPIO115/PS2_DAT0A
E10
GPIO154/SMB02_DATA/PS2_CLK1B
C12
GPIO155/SMB02_CLK/PS2_DAT1B
E9
GPIO145/SMB09_DATA/JTAG_TDI
F6
GPIO146/SMB09_CLK/JTAG_TDO
C8
GPIO147/SMB08_DATA/JTAG_CLK
C5
GPIO150/SMB08_CLK/JTAG_TMS
G13
JTAG_RST#
E3
GPIO050/FAN_TACH0/GTACH0
D1
GPIO051/FAN_TACH1/GTACH1
M2
GPIO052/FAN_TACH2/LRESET#
L10
GPIO053/PWM0/GPWM0
L11
GPIO054/PWM1/GPWM1
M5
GPIO055/PWM2/SHD_CS#/(RSMRST#)
J8
GPIO056/PWM3/SHD_CLK
N1
GPIO001/PWM4
L8
GPIO002/PWM5
N6
GPIO014/PWM6/GPTP-IN6
J9
GPIO015/PWM7
H11
GPIO035/PWM8/CTOUT1
D9
GPIO133/PWM9
H12
GPIO134/PWM10/UART1_RTS#
G10
GPIO135/UART1_CTS#
H10
GPIO170/TFDP_CLK/UART1_TX
G9
GPIO171/TFDP_DATA/UART1_RX
A4
GPIO022/GPTP-IN0
B2
GPIO023/GPTP-IN1
C1
GPIO024/nRESETI
N7
GPIO031/GPTP-OUT1
K9
GPIO032/GPTP-OUT0
N8
GPIO040/GPTP-OUT2
F13
GPIO121/PVT_IO0
E13
GPIO124/GPTP-OUT6/PVT_CS#
C13
GPIO125/GPTP-OUT5/PVT_CLK
E12
GPIO126/PVT_IO3
F11
GPIO122/BCM0_DAT/PVT_IO1
F12
GPIO123/BCM0_CLK/PVT_IO2
D12
GPIO046/BCM1_DAT
D13
GPIO047/BCM1_CLK
F4
GPIO041/SYS_SHDN#
B1
SYSPWR_PRES
K7
GPIO011/nSMI
N3
GPIO021/LPCPD#
K6
GPIO061/LPCPD#/ESPI_RESET#
H7
GPIO063/SER_IRQ/ESPI_ALERT#
K1
GPIO064/LRESET#
G7
GPIO065/PCI_CLK/ESPI_CLK
H6
GPIO066/LFRAME#/ESPI_CS#
K5
GPIO070/LAD0/ESPI_IO0
L4
GPIO071/LAD1/ESPI_IO1
G6
GPIO072/LAD2/ESPI_IO2
L5
GPIO073/LAD3/ESPI_IO3
L2
GPIO067/CLKRUN#
M1
GPIO100/nEC_SCI
G4
GPIO106/PWROK
L12
GPIO107/nSMI
A1
XTAL1
A3
XTAL2
Merion Limit height
QE2 change to SB000014O00 H=0.6mm(MAX)
RUN_ON<17,59,78,87>
RUN_ON#
1219 Change
VSS2
VSS1
A6
A13
1
QE2
S1
2
G1
D1
S2
5
G2
D2
PJX138K_ SOT563-6
3
RE6710K_0402_5%
VSS3
E6
6
4
12
5
+RTC_CELL
+3.3V_ALW_UE1
+3.3V_ALW
10U_0402_6.3V6M
1
JUMP@
PJP22
12
PAD-OPEN1x1m
CE16
2
+3.3V_ALW_UE1
DD
CC
BB
AA
0.1U_0201_10V6K
0.1U_0201_10V6K
CE20
CE19
1
1
2
2
close to pin G8/M9
RF Request
+3.3V_ALW
12P_0402_50V8J
RF@
68P_0402_50V8J
RF@
1
1
CE59
CE60
2
2
+1.8V_PRIM
+3.3V_ALW
12
1
CE22
0.1U_0201_1 0V6K
2
@
RE505100K_0402 _5%
RE52610K_0402_5%@
RE5324.7K_0402_5%
12
RE810100K_040 2_5%
12
RE811100K_040 2_5%
12
RE812100K_040 2_5%
12
RE95100K_0402_5%
+1.8V_PRIM_ VTR3
12
@
100K_0402_ 5%
SSD_SCP_ PWR_EN
+3.3V_ALW
100K_0402_5%
12
1
1U_0201_6.3V6M
1
JTAG1 @
@SHORT PADS~D
2
2
100_0402_1%
12
1
CE30
2
32 KHz Clock
MEC_XTAL1MEC_XTAL2
12
YE1
12
10P_0402_50V8J
32.768KHZ_9 PF_X1A00014 1000200
CE28
+3.3V_ALW_UE1
+3.3V_ALW_UE1
JUMP@
PJP20
PAD-OPEN1x1m
12
12
12
CV2_ON_R
IMVP_VR_ON_ EC
RUN_ON_EC
TBT_RESET_N_EC
RE823
RE63
JTAG_RST#
RE65@
MEC_XTAL2_R
Close to pin H1
+1.8V_PRIM_VTR3
CE21
1
0.1U_0201_1 0V6K
2
Close to pin N5
LOM_CABLE_DETECT#
USH_DET#
BCM5882_A LERT#
+3.3V_ALW2
+1.8V_PRIM_VTR3
12
12
12
@
0_0201_5%
8/28 schematic review
10P_0402_50V8J
12
5
0.1U_0201_10V6K
1
2
RE571K_0402_5%@
RE549
100K_0402_ 5%
ENABLE_D S#
RE550
@
100K_0402_ 5%
RE290
CE29
PCH_DPWROK<11>
CE15
12
RE320_0402_5 %@
0.1U_0201_10V6K
1
CE13
2
12
RE314100_0402 _1%
SIO_EXT_WAKE#<9>
SIO_SLP_SUS#<11>
1218
Delete RE100 and Change net name
from CNVI_RF_RESET to CNVI_EN#
BSMB_W P_INT#< 92>
1
2
+VSS_PLL
SLP_WLAN#_GATE<78>
CNV_DET#_EC< 52>
+3.3V_ALW
12
12
100K_0402_5%
RE58
SSD_SCP_PWR_EN<78>
SYS_PWROK<11,79>
DCIN1_EN_R<82>
WHL Supprot NDS3 only
DS3@
22U_0402_6.3V6M
@
CE17
RE5520_020 1_5%@
RE362
RE8190_0201_ 5%@
Deep Sle ep support
non Deep Sleep
Deep Sleep
For EMI request
ESPI_CLK_5105
33_0402_5%
@EMI@
12
RE350
33P_0402_50V8J
@EMI@
12
CE57
1U_0201_6.3V6M
0.1U_0201_10V6K
1
1
CE14
CE23
2
2
0.1U_0201_10V6K
1
CE18
2
12
RE5360_020 1_5%DS3@
12
RE7030_020 1_5%@
12
RE34943K_ 0402_1%
12
12
100K_0402_ 5%
12
VBUS1_ECOK_R<82>
1
0
RE5480_0201 _5%@
RE6000_0201 _5%@
WLAN_WIGIG60GHZ_DIS#<52>
CLK_TP_SIO_I2C_DAT<63>
DAT_TP_SIO_I2C_CLK<63>
RE6020_0201_ 5%@
SML1_SMBDATA<8>
FPR_LOW_PWR_MODE#<66>
TBT_RESET_N_EC<42,44>
WWAN_RADIO_DIS#<52>
BC_DAT_ECE1117<63>
12
12
Page 59
5
4
3
2
1
For Merion UMA
+RTC_CELL
100K_0402_5%
12
RE31
DD
CC
BB
+1.0V_VCCST
+1.0VS_VCCIO
13
D
QE11
@
L2N7002W T1G_SC-70-3
12
RE900_0402_5 %@
2
POWER_SW_IN#<58,79>
LID_CL_SIO#< 58>
+3.3V_ALW
SIO_SLP_S3# <11,17,42,59,79>
G
12
RE702.2K_0402_5%
S
LID_CL_SIO#
8.2K_0402_ 5%
H_THERMTRIP#<14,23,24>
12
+3.3V_ALW
RE69
1
2
100K_0402_5%
RE25
12
.047U_0402_16V7K
12
12
RE331K _0402_5%
2.2U_0402_6.3V6M
CE12
1031 change
RE26
10_0402_5%
CE8
C
2
B
E
31
12
LMBT3904WT1G_SC70-3
QE4
0.1U_0201_1 0V6K
LID_CL# <64>
THERMTRIP2# <58>
1
CE36
0.1U_0201_1 0V6K
2
@
CE10
1 2
POWER_SW#_M B <66,77,79>
IMVP_VR_ON_EC<58>
SIO_SLP_S3#<11,17,42,59,79>
RF Request
+3.3V_ALW
1
CE61
2
68P_0402_50V8J
RF@
RE343 CE62
240K 4700p
130K 4700p
*
62K
33K
8.2K
4.3K
2K
1K
TYPEC_ID<58>
4700p
4700p
4700p
4700p
4700p
4700p
RUN_ON_EC<58>
REV
Single Port ACE w/o AR
Single Port ACE w/AR
Dual Port ACE w/o AR
Dual Port ACE w/AR
Dual Port ACE (w/AR +w/o AR)
TYPEC_ID rise time is measured from 0%~63.2%.
+3.3V_ALW
12
12
PCIE_WAKE#_R<58>
IMVP_VR_ON_ EC
SIO_SLP_S3#
MC74VHC1G0 8DFT2G_SC70-5
RUN_ON_EC
MC74VHC1G0 8DFT2G_SC70-5
RE343
130K_0402_ 5%
CE62
4700P_0402 _25V7K
12
RE2750_0201_5%@
Stuff RE275 and no stuf f RE274 keep E5 design
Stuff RE274 and no stuf f RE275 to save two GPIOs on EC(PCH_PCIE_W AKE# should be output with OD)
12
RE3040_0201_5%@
@
CE53
+3.3V_ALW
1 2
0.1U_0201_1 0V6K
5
1
P
B
4
O
2
A
G
UE3
3
12
RE2800_0201_5%@
12
RE2920_0201_5%@
@
+3.3V_ALW
0.1U_0201_1 0V6K
5
1
P
B
O
2
A
G
UE5
3
BOARD_ID<58>
CE52
1 2
4
12
RE2740_0201_5%@
IMVP_VR_ON
6/8 Change to SA00007WE00 DII
+3.3V_ALW
12
12
RE79 CE40
240K 4700p
130K 4700p
4700p
62K
4700p
33K
8.2K
4700p
4700p
4.3K
*
4700p
2K
4700p
1K
BOARD_ID rise time is measured from 0%~63.2%. SYSTEM_ID rise time is measured from 0%~63.2%.
12
VSET_5105
0.1U_0402_25V6
CE38
1.58K_0402_1%
12
RE77
Merion Limit height
UE4 change to SA00007YE00 H=0.4mm(MAX)
1
2
3
IMVP_VR_ON <88>
RUN_ON <17,58,78,87>
RE79
4.3K_0402_ 1%
0212 change
CE40
4700P_0402 _25V7K
REV
X00
X01
X02
X03
reserved
A00
VSET_5105 <58>
PCIE_WAKE# <42,52,68>
PCH_PCIE_WAKE# <11,42,58>
UE4
74AUP1G07FZ 4-7_X2-DFN1410-6
6
VCC
NC1
5
NC2
A
4
Y
GND
SYSTEM_ID<58>
240K 4700p
130K 4700p
62K
*
4.3K 4700p
2K
1K
+3.3V_ALW
VCCST_PWRGD <11,79>
+3.3V_ALW
12
12
CE47
4700P_0402 _25V7K
CE47RE3 00
4700p
4700p3 3K
4700p8.2K
4700p 1 5P
4700p
RE300
33K_0402_5 %
PANEL SIZE
11"
12"
13"
14"
15"
17"
Thermal diode mapping
5085 Channel
DP1/DN1
DP2/DN2
DN2a/DP2a
DP3/DN3
DP4/DN4
DP4/DN4 for Skin on
100P_0402_50V8J
@
C
CE39
1 2
31
QE6, place QE6 close to
Vcore VR choke.
E
LMBT3904W T1G_SC70-3
AA
5
2
B
QE6
Locat i on
CPU (QE3)
2280 SSD (QE5)
DDR (QE7)
NA
CPU VR (QE6)
REM_DIODE4_P <58>
REM_DIODE4_N <58>
Place under CPU
Place CE3 5 close to the QE3 as possible
100P_0402_50V8J
C
CE35@
1 2
E
31
LMBT3904W T1G_SC70-3
DP2/DN2 for WiGig on QE5, place QE5 close
to WiGig and CE37 close to QE5
DN2a/DP2a for DDR on QE7, place QE7 close
to DDR and CE46 close to QE7
100P_0402_50V8J
31
E
12
B
2
CE46@
C
QE7
LMBT3904WT1G_SC70-3
QE3
2
B
100P_0402_50V8J
CE37@
4
REM_DIODE1_P <58>
REM_DIODE1_N <58>
C
12
E
31
LMBT3904W T1G_SC70-3
2
B
QE5
REM_DIODE2_P <58>
REM_DIODE2_N <58>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
Secure & Reset IC
Secure & Reset IC
Secure & Reset IC
LA-G871P
LA-G871P
LA-G871P
60109Tuesday, March 05, 2 019
60109Tuesday, March 05, 2 019
60109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 61
DIMMA
A0h
DIMMB
A2h
XDP
1
5
Merion SMBus Block Diagram
CK14
SMB
CH15
DD
SML 0
CH14
CF15
MEM_SMBC LK
MEM_SMBDATA
SML0_SMBCLK
SML0_SMBD ATA
4
1K
+3.3 V_AL W_ PC H
1K
L2N7002DW1T1G
@499
@499
+3.3 V_AL W_ PC H
L2N7002DW1T1G
3
DDR_XDP_WAN_SMBCLK
DDR_XDP_WAN_SMBDAT
@1K
WHL-U
SML 0B
CN15
CM15
SML0B_SMBD ATA
SML0B_SMBCLK
@1K
+3.3 V_AL W_ PC H
2
2.2K
2.2K
+3.3 V_R UN
253
254
253
254
51
53
SML 1
CM24CN2 3
CC
0x46(8-b it)
SML1_SMBD ATA
SML1_SMBCLK
D8E 11
0303
KBC
MEC 5106
04
04
C3
B4
F10
1K
1K
UPD1_SMBCLK
UPD1_SMBDAT
UPD1_SMBINT #
+3.3 V_AL W_ PC H
2.2K
2.2K
+3.3 V_A LW
@3.3K
@3.3K
+3.3 V_TB TA_ FL AS H
B5
A5
B6
PD
TPS65982
I2C
2.2K
2.2K
2.2K
+3.3 V_ TP
@2.2K
@2.2K
+3.3 V_A LW
+3.3 V_A LW
+3.3 V_A LW
100 ohm
100 ohm
@100 ohm
@100 ohm
@100 ohm
C9
USH
C10
CV3 USH/B
2
TP
3
4
Reserved
5
Wireless Power
Connector
6
21
Charger
22
4
BATTERY
5
CONN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umberRe v
Size Document N umberRe v
Size Document N umberRe v
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
SMBus block diagram
SMBus block diagram
SMBus block diagram
LA-G871P
LA-G871P
LA-G871P
1
61109Tuesday, March 05, 2019
61109Tuesday, March 05, 2019
61109Tuesday, March 05, 2019
1.0
1.0
1.0
BB
B3
01
E5
01
USH_EXPANDER_SMBCLK
USH_EXPANDER_SMBDAT
2.2K
2.2K
2.2K
02
02
E10
CLK_TP_SIO_I2C_DAT
DAT_TP_SIO_I2C_CLK
C12
Only Merion14
B6
E12
N2
M3
WP_G PU_SMCLK
WP_GPU_SMDAT
BSMB_W P_INT#
PBAT_CHARGER_SMBCLK
PBAT_CHARGER_SMBDAT
4
0505F7
AA
10
10
5
Page 62
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
LEDs (Controller)
LEDs (Controller)
LEDs (Controller)
LA-G871P
LA-G871P
LA-G871P
62109Tuesday, March 05, 2 019
62109Tuesday, March 05, 2 019
62109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 63
5
4
3
Touch Pad
+3.3V_TP
4.7K_0402_5%
DD
4.7K_0402_5%
12
12
RZ19
RZ18
PS2
DAT_TP_SIO_I2C_CLK<58>
CLK_TP_SIO_I2C_DAT<58>
12
10P_0402_50V8J
10P_0402_50V8J
12
CZ81
CZ80
RZ220_0201_5%@
RZ230_0201_5%@
RZ3460_02 01_5%@
RZ3470_02 01_5%@
12
12
12
12
DAT_TP_ SIO_R
CLK_TP_ SIO_R
I2C1_SDA_ TP_R
I2C1_SCK_ TP_R
I2C From EC
10K_0402_5%
12
+3.3V_TP
@
RZ116
10K_0402_5%
12
@
RZ117
+3.3V_TP
CC
I2C1_SDA_TP<9>
I2C1_SCK_TP<9>
12
2.2K_0402_5%
2.2K_0402_5%
12
RZ21
RZ20
RZ260_0201_ 5%@
RZ290_0201_ 5%@
12
12
I2C1_SDA_ TP_R
I2C1_SCK_ TP_R
I2C From CPU
Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for W in7)
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in W indows
Route PS2 from EC to the touch pad also for co ntingency plan if I2C has issues
+3.3V_RUN+3.3V_TP
JUMP@
PJP35
12
PAD-OPEN 1x1m
Keyboard
KB_DET#<12>
+5V_RUN
BC_INT#_ECE1117<58>
BC_DAT_ECE1117<58>
BC_CLK_ECE1117<58>
PTP_DISABLE#<58>
+3.3V_TP
TOUCHPAD_INTR#<14,58>
+3.3V_ALW
RZ14750_ 0201_5%@
KB_DET#
BC_INT#_E CE1117
BC_DAT_ ECE1117
BC_CLK_ ECE1117
12
2
PTP_DISABLE#_R
DAT_TP_SIO_R
CLK_TP_SIO_R
I2C1_SDA_ TP_R
I2C1_SCK_ TP_R
+3.3V_TP
1
RF@
68P_040 2_50V8J
2
CONN@
JKBTP1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
GND1
22
GND2
HRS_TF3 1-20S-0P5SH-800
CZ83
KB_DET#
BC_INT#_E CE1117
BC_DAT_ ECE1117
BC_CLK_ ECE1117
DAT_TP_ SIO_R
CLK_TP_ SIO_R
+3.3V_TP
Link HRS_TF31-20S-0P5SH-800 done 0313
1
RF Request
12
CZ8468P_04 02_50V8JRF@
12
CZ8568P_04 02_50V8J@RF@
12
CZ8668P_04 02_50V8J@RF@
12
CZ8768P_04 02_50V8J@RF@
12
CZ8868P_04 02_50V8J@RF@
12
CZ8968P_04 02_50V8J@RF@
+5V_RUN+3.3V_ALW
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1
@
CZ90
2
1
1
@
CZ92
CZ91
2
2
Place close to JKBTP1
@
BB
RSMRST circuit
PROM_BIOS_R<8>
1K_0402_5%
12
RZ401
MP depop RZ401; MP RZ400 change to short pad
PCH_RSMRST#<58,79 >
ALW_PW RGD_3V_5V<11,85>
AA
5
12
RZ40010K_04 02_5%
PROM_BIOS
4
+3.3V_ALW
12
0.1U_020 1_10V6K
5
1
P
B
4
O
2
A
G
3
MC74VHC 1G08DFT2G_SC 70-5
CZ82
@
PCH_RSMRST#_AND<11 ,79>
UZ6
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
2
Date :Sheeto f
Compal Electronics, Inc.
Keyboard
Keyboard
Keyboard
LA-G871P
LA-G871P
LA-G871P
63109Tuesday, March 05, 2 019
63109Tuesday, March 05, 2 019
63109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 64
5
4
3
2
1
Battery LED
BAT2_LED#<58>
BAT1_LED#<58>
DD
12
RZ361150_ 0402_5%
12
RZ28150_ 0402_5%
1213 change for ME request
From 330ohm to 150ohm
BATT_WHITE#
BATT_YELLOW#
CC
LED P/N c hange to SC50000FL00 from SC50000BA00
Breath LED for Merion 14
CZ93
@
12
0.1U_020 1_10V6K
5
1
LED_MASK#<58>
LID_CL#<5 9,64>
P
B
4
O
2
A
G
MC74VHC 1G08DFT2G_SC 70-5
3
MASK_BA SE_LEDS#
UZ10
BREATH_LED#<58>
QZ7A
L2N7002 DW1T1G_S C88-6
1
2
MASK_BASE_LEDS#
6
BREATH_LED#_QB REATH_WHITE_LED_SNIFF#
12
RZ321K_040 2_5%
1031 change
LED3
LTW -C193DC-C_W HITE
Place LED3 close to SW3
+5V_ALW+3.3V_ALW
21
LID SWITCHLED board CONN
+3.3V_AL W
+5V_ALW
HRS_TF3 1-4S-0P5SH-800
6
GND2
5
GND1
4
4
3
3
2
2
1
1
JLED1
CONN@
BB
Place CZ 94 near UZ1.
0.1U_0201_10V6K
1
@
CZ94
2
1
UZ1
2
VDD
APX8131 AI-TRG_SOT23-3
3
VOUT
GND
Hall sensor: SA00009EM00
LID_CL# <5 9,64>
BATT_YELLOW#<79>
BATT_YELL OW#
BATT_W HITE#
Link TF31-4S-0P5SH-800 done 0504
(MAX hight is 1.45mm)
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheet
Compal Electronics, Inc.
LED & LID
LED & LID
LED & LID
LA-G871P
LA-G871P
LA-G871P
64109Tuesday, March 05, 2 019
64109Tuesday, March 05, 2 019
64109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
o f
Page 65
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
Reserve for KB/TP/LED/LID
Reserve for KB/TP/LED/LID
Reserve for KB/TP/LED/LID
LA-G871P
LA-G871P
LA-G871P
65109Tuesday, March 05, 2 019
65109Tuesday, March 05, 2 019
65109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 66
1
CONN@
JUSH1
28
GND2
27
GND1
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
HRS_TF31C-26S-0 P5SH-800
0.1U_0201_10V6K
1
@
CZ68
2
68P_0402_50V8J
RF@
1
CZ73
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
USH & TPM
USH & TPM
USH & TPM
LA-G871P
LA-G871P
LA-G871P
1
1.0
1.0
66109Tuesday, Marc h 05, 2019
66109Tuesday, Marc h 05, 2019
66109Tuesday, Marc h 05, 2019
1.0
FPR_SCAN_INT#<58,66>
USH_PWR_STATE#< 58>
CONTACTLESS_DET#<12>
RF Request
1 2
1 2
2
+3.3V_ALW
RZ82.2K_0402 _5%
RZ92.2K_0402 _5%
RZ10100K_0402_5%
12
12
12
1031 change
USH_EXPANDER_SMBCLK
USH_EXPANDER_SMBDAT
USH_PWR_STATE#
USH CONN
1031 change
12
POWER_SW#_M B<59,77,79>
CV2_ON<58>
USB20_N9_USH<66>
USB20_P9_USH<66>
RZ14140_0201_5%@
RZ14110_0201_5%@
FPR_RST#<66>
12
RZ1140_0201_5%@
21
DZ8RB751 S-40_SOD523-2
USH_DET#<58>
1
2
12
RZ14730_0201_5%@
0.1U_0201_10V6K
@
CZ64
USH_EXPANDER_SMBCLK<58>
USH_EXPANDER_SMBDAT<58>
12
RF Request
68P_0402_50V8J
RF@
1
CZ69
2
2
POWER _SW#_MB _USH
FPR_RST#_USH
CV2_ON
USB20_N9_ USH
USB20_P9_ USH
USB20_N8<10>
USB20_P8<10>
BCM5882_ALERT#< 58>
+3.3V_ALW
+5V_ALW
+3.3V_RUN
+5V_RUN
FPR_SCAN_ INT#_R
USH_PW R_STATE#
CONTACTLESS_DE T#_R
NFC_ACTIVITY_STATUS#_R
Link HRS_TF31C-26S-0P5SH-800 done 0313
Close to JUSH1
+5V_RUN+5V_ALW
0.1U_0201_10V6K
1
2
+5V_RUN+5V_ALW
68P_0402_50V8J
1
2
+3.3V_ALW+3.3V_RUN
0.1U_0201_10V6K
1
@
@
CZ66
CZ67
2
+3.3V_ALW+3.3V_RUN
RF@
68P_0402_50V8J
RF@
1
CZ71
CZ72
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size
Size
Size
Date :Sheetof
Date :Sheetof
Date :Sheetof
Document Num berRe v
Document Num berRe v
Document Num berRe v
5
4
3
For ST/Nuvoton TPM
+3.3V_ALW_PCH
TPM_PIRQ#
12
RZ69 10 K_0402_5%
DD
750@
0.1U_0201_10V6K
750@
10U_0402_6.3V6M
CZ75
1
1
2
2
place CZ50, CZ75 as close as UZ12.8place CZ53,CZ54,CZ55 as close as UZ12.22
CC
place CZ51, CZ52 as close as UZ12.1
PCH_SPI_CLK _2_R
33_0402_5%
@EMI@
RZ63
0.1U_0402_25V6
12
@EMI@
12
CZ56
750@
10U_0402_6.3V6M
0.1U_0201_10V6K
CZ50
750@
CZ52
1
1
CZ51
2
PCH_SPI_CS#2<8>
2
PCH_SPI_D0_R1<8>
PCH_SPI_D1_R1<8>
PCH_SPI_CLK_R1<8>
12
RZ610_0201_5%@
VPRO@
12
RZ5949.9_0402_1%
12
RZ5849.9_0402_1%
VPRO@
12
RZ6049.9_0402_1%VPRO @
Close to UZ12
RF Request
+3.3V_ALW
68P_0402_50V8J
RF@
12P_0402_50V8J
RF@
1
1
CZ58
CZ57
2
2
+UZ12_TPM
+3.3V_ALW _UZ12
PCH_SPI_CS# 2_R
TPM_PIRQ#<9>
PCH_SPI_D0_ 2_R
PCH_SPI_D1_ 2_R
TPM_GPIO0
PCH_SPI_CLK _2_R
PLTRST_TPM#<11>
+3.3V_ALW _PCH
+3.3V_RUN
+3.3V_ALW
+3.3V_RUN
SIO_SLP_S0#<9,11,17,79,8 7>
UZ12
8
NiC_5
1
NiC_1
20
SPI_CS#
18
SPI_PIRQ#
21
MOSI
24
MISO
6
GPIO
19
SPI_CLK
7
PP
17
SPI_RST#
ST33HTPH2032AH C1_VQFN32_5X 5
Link SA0000C5G10 symbol done 0725
FP in PWR BUTTON connector
NEED CONFIRM MODULE PINDEFINE
JFPBTN1
CONN@
BB
FOX_QT510166-L0 10-7H
Link FOX_QT510166-L010-7H done
Compa l
MB CONN Symbol
2
4
6
8
10
AA
14
9
3
FPR_DET#
1
1
2
2
3
3
USB20_P9_ FP
4
4
5
5
USB20_N9_ FP
6
6
7
7
8
8
9
9
10
RESERVE
10
FPR_LOW _PWR_M ODE#
11
11
FPR_RST#
12
FPR_UEFI_MGM T#
12
13
13
14
14
FPR_SCAN_ INT#
15
15
FPR_SSO_EN #
16
16
Sign al
GND
USB DP(D+)2
USB DM(D-)
GND
RESERVED
FP RESET#
+3.3V_FPBTN
FPR_SSO_EN#
FPR_SCAN_INT#
FPR_UEFI_MGMT#
NA
NA
NA
NA
FPR DET(GND)116
5
FPR Sy mbol
1
3
4
5
612
7
816
915
1013
1111 FPR_LOW_PWR_MODE#
12
137
145
15
FPR_DET# <58>
1
T418
@
PAD~D
FPR_LOW_PWR_MODE# <58>
FPR_RST# <66>
FPR_UEFI_MGMT# <58>
+3.3V_FPBTN
FPR_SCAN_INT# <58,66>
FPR_SSO_EN# <58>
+3.3V_FPBTN
12
RZ1392
100K_0201_ 5%
FPR_RST#
ESD Request 0824
FPR_DET#FPR_DE T#
RESERVE
FPR_LOW _PWR_M ODE#
FPR_RST#FPR_RS T#
AZ1045-04F_D FN2510P10E-10 -9
Merion Limit height
DZ11 change to H=0.9mm(MAX)
3
2
CEST523NC5VB_SOT-523-3
@ESD@
DZ11
1
1206 change
+3.3V_FPB TN
0.1U_0201_10V6K
1
2
@ESD@
DZ14
1
1
2
2
4
4
5
5
3
3
8
9
10
8
9
7
7
6
6
4
RZ14080_0402_5%@S T33@
RZ14090_0402_5%750@
RZ890_0402_5%750@
RZ14100_0402_5%750@
12
RZ36210K _0402_5%@
USB20_P9_ FP
USB20_N9_ FP
+3.3V_FPBTN
@
CZ309
RESERVE
FPR_LOW _PWR_M ODE#
12
12
12
12
22
VPS
31
NiC_21
16
NiC_13
27
NiC_17
26
NiC_16
25
NiC_15
30
NiC_20
29
NiC_19
28
NiC_18
14
NiC_11
15
NiC_12
13
NiC_10
12
NiC_9
11
NiC_8
10
NiC_7
5
NiC_4
4
NiC_3
3
NiC_2
32
NiC_22
23
NiC_14
9
NC_6
2
GND0
33
THPAD
For NPTC750
Depop RZ112, RZ1408
Pop RZ1407, RZ1409, RZ89, RZ1410, CZ50~CZ53, CZ75
12
RZ13890_0201_ 5%@
12
RZ13880_0201_ 5%@
12
RZ3510_02 01_5%@
12
RZ3500_02 01_5%@
12
RZ13910_0402_5%@
12
RZ13900_0402_5%@
NTK3139PT1G_SOT72 3-3
13
D
+3.3V_VPS_UZ12
+UZ12_TPM
+3.3V_ALW_UZ12
TPM_GPIO0
12
RZ1120_020 1_5%@ST33@
RZ14070_0201_5%750 @
QZ18
FPR_UEFI_MGM T#FPR_UEFI_MGM T#
+3.3V_FPBTN
FPR_SCAN_ INT#
FPR_SSO_EN #
TPM_GPIO0_NU
12
+3.3V_VPS _UZ12
TPM_GPIO0_NU
+3.3V_VPS _UZ12
USB20_P9_USH <66>
USB20_N9_USH <66>
+3.3V_RUN
S
QZ18 change to SB00000SS00
G
2
For Merion layout limit height
FPR_PW R_EN#_R
12
RZ3800_ 0201_5%@
0.1U_0402_25V6K
12
@
CZ200
@ESD@
DZ15
1
1
2
2
4
4
5
5
3
3
8
AZ1045-04F_D FN2510P10E-10 -9
1
2
USB20_P9 <10>
USB20_N9 <10>
0.1U_0201_10V6K
ST33@
CZ54
+3.3V_ALW
10U_0603_10V6M
ST33@
1
CZ55
2
FPR_PWR_EN# <58>
9
10
8
9
7
7
6
6
0.1U_0201_10V6K
750@
1
CZ53
2
+3.3V_FPBTN
FPR_SCAN_ INT#
FPR_SSO_EN #
USH_EXPA NDER_SMBCL K
USH_EXPA NDER_SMBDA T
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
3
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
CZ6268P_0402_50V 8J@RF@
CZ6368P_0402_50V 8J@RF@
Page 67
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
HDD/ODD/FFS Connector
HDD/ODD/FFS Connector
HDD/ODD/FFS Connector
LA-G871P
LA-G871P
LA-G871P
67109Tuesday, March 05, 2 019
67109Tuesday, March 05, 2 019
67109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 68
5
4
3
2
1
Add Power Decoupling for support Intel Teton Glacier
RF Request
+3.3V_HDD_M2
100P_0402_50V8J~D
27P_0402_50V8J
68P_0402_50V8J
@RF@
1
1
DD
CN60
2
2
RF@
RF@
12
CN78
CN77
Place close JNGFF3 pin 12,14,16,18Place close JNGFF3 pin 2,4Place close JNGFF3 pin 70,72,74
+3.3V_HDD_M2
0.01U_0402_16V7K
1
CN79
2
0.1U_0402_10V7K
1
12
CN61
2
+3.3V_HDD_M2+3.3V_HDD_M2
22U_0603_6.3V6M
CN63
0.01U_0402_16V7K
1
1
CN80
2
2
0.1U_0402_10V7K
0.01U_0402_16V7K
1
CN62
CN81
2
0.01U_0402_16V7K
22U_0603_6.3V6M
12
0.01U_0402_16V7K
1
1
CN64
CN84
2
2
0.1U_0402_10V7K
1
CN82
12
CN86
2
22U_0603_6.3V6M
CN87
Place near JNGFF3
2280 SSD
NGFF slot C Key M
+3.3V_HDD_M2
JNGFF3
CONN@
1
GND_1
3
GND_2
5
PCIE_PRX_ DTX_N13<10>
PCIE_PRX_ DTX_P13< 10>
PCIE_PTX_ DRX_N13<10>
PCIE_PTX_ DRX_P13< 10>
CC
+3.3V_HDD_M2
12
RN37@10K_0402_5%
BB
PCIE_PRX_ DTX_N14<10 >
PCIE_PRX_ DTX_P14< 10>
PCIE_PTX_ DRX_N14<1 0>
PCIE_PTX_ DRX_P14<10>
PCIE_PRX_ DTX_N15<10>
PCIE_PRX_ DTX_P15< 10>
PCIE_PTX_ DRX_N15<10>
PCIE_PTX_ DRX_P15< 10>
PCIE_PRX_ DTX_P16< 10>
PCIE_PRX_ DTX_N16<10 >
PCIE_PTX_ DRX_N16<1 0>
PCIE_PTX_ DRX_P16<10>
M2280_DEVSLP
if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD
12
CN650.22U _0402_10V6K
12
CN660.22U _0402_10V6K
12
CN670.22U _0402_10V6K
12
CN680.22U _0402_10V6K
12
CN690.22U _0402_10V6K
12
CN700.22U _0402_10V6K
12
CN710.22U _0402_10V6K
12
CN720.22U _0402_10V6K
PCIE_PTX_ C_DRX_N13
PCIE_PTX_ C_DRX_P13
PCIE_PTX_ C_DRX_N14
PCIE_PTX_ C_DRX_P14
PCIE_PTX_ C_DRX_N15
PCIE_PTX_ C_DRX_P15
PCIE_PTX_ C_DRX_N16
PCIE_PTX_ C_DRX_P16
CLK_PCIE_ N2<1 1>
CLK_PCIE_ P2<11>
M2280_PCIE_SATA#<10>
PERn3
7
PERp3
9
GND_3
11
PETp3
13
PETn3
15
GND_4
17
PERn2
19
PERp2
21
GND5
23
PETp2
25
PETn2
27
GND6
29
PERn1
31
PERp1
33
GND7
35
PETn1
37
PETp1
39
GND8
41
PERn0/SATA-B+
43
PERp0/SATA-B-
45
GND9
47
PETn0/SATA-A-
49
PETp0/SATA-A+
51
GND10
53
REFCLKN
55
REFCLKP
57
GND11
67
69
71
73
75
77
79
LOTES_A PCI0170-P001A
Key M
N/C_19
PEDET (OC-PCIe/GND-SATA)
GND_12
GND_13
GND_14
GND_16
NPTH_2
SUSCLK(32kHz) (O)(0/3.3V)
3.3VAUX_1
3.3VAUX_2
N/C_1
N/C_2
DAS/DSS#
3.3VAUX_3
3.3VAUX_4
3.3VAUX_5
3.3VAUX_6
N/C_3
N/C_4
N/C_5
N/C_6
N/C_7
N/C_8
N/C_9
N/C_10
N/C_11
DEVSLP
N/C_12
N/C_13
N/C_14
N/C_15
N/C_16
PERST#
CLKREQ#
PEWake#
N/C_17
N/C_18
3.3VAUX_7
3.3VAUX_8
3.3VAUX_9
GND_15
NPTH_1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
68
70
72
74
76
78
SSD_SCP #_R
NVME_LE D#
PCIE_W AKE#
SUSCLK_R
+3.3V_S SD from SSD storage protec tion power ga te control
0212 change
RN130 covering green printing for co-lay materials
2.8A
12
RN1290_0201_5%@
12
RN1000_0201_5%@
PCIE_WAKE#<42,52,59>
12
RN990_0 201_5%@
12
RN1310.01_0805_ 1%@
PJP31
JUMP@
PAD-OPEN 1x3m
RN1300.01_0805_ 1%@
M2280_DEVSLP <10>
PCH_PLT RST#_AND<11,38 ,42,52,70>
CLKREQ_PCIE#2<11>
12
12
SSD_SCP# <58>
SUSCLK <11,52>
+3.3V_SSD
+3.3V_RUN
Link APCI0170-P001A done 0123
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
M2 2280 Socket
M2 2280 Socket
M2 2280 Socket
LA-G871P
LA-G871P
LA-G871P
68109Tuesday, March 05, 2 019
68109Tuesday, March 05, 2 019
68109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 69
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
eMMC / UFS
eMMC / UFS
eMMC / UFS
LA-G871P
LA-G871P
LA-G871P
69109Tuesday, March 05, 2 019
69109Tuesday, March 05, 2 019
69109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 70
5
4
3
2
1
JUMP@
PJP14
RF Request
@RF@
82P_0402_50V8J
1
CR28
2
HOST_SD_W P#
High
Low
+3.3V_MM I_IN
@RF@
@RF@
82P_0402_50V8J
12P_0402_50V8J
1
1
2
CR26
CR25
2
SDW P
Low
HighWrite Protect(FW L OCK)
STATUS
Write Enable
+3.3V_MMI_IN
PCIE_PTX_DRX_P9<10>
PCIE_PTX_DRX_N9<10>
PCIE_PRX_DTX_P9<10>
PCIE_PRX_DTX_N9<10>
+3.3V_MMI_AUX
+3.3V_MM I_AUX
DD
CC
BB
@RF@
12P_0402_50V8J
1
CR27
2
12
PAD-OPEN 1x2m
RR2740_060 3_5%@
RR1910K _0402_5%
CR110.1U_ 0402_25V6
CR120.1U_ 0402_25V6
CR130.1U_ 0402_25V6
CR140.1U_ 0402_25V6
+1.2V_LDO
CR13 close to UR2.10
CR9 CR10 close to UR2.14
4.7U_0402_10V6M
1
CR5
2
+3.3V_MMI_AUX
12
MEDIACARD _IRQ#
12
CLKREQ_PCIE#4<11 >
12
12
12
12
0.1U_0201_10V6K
1
1
CR6
2
2
HOST_SD_W P#<12>
+3.3V_MMI_IN+3.3V_RUN
MEDIACARD_IRQ#<8>
PCH_PLTRST#_AND<11,38 ,42,52,68>
0.1U_0201_10V6K
CLK_PCIE_P4<11>
CLK_PCIE_N4<1 1>
CR7
SDWP
support D3 Hot(if D3 cold PIN11, PIN27 need Add MOS on/off 3V3AUX)
+3.3V_MMI_IN
10U_0402_6.3V6M
0.1U_0201_10V6K
CR4
1
1
CR3
2
2
27
11
12
CARD_3V3
3V3_IN
3V3aux
DV33_18
RTS5242
SD_LN1_P
SD_LN1_M
SD_LN0_P
SD_LN0_M
SDREG2
GPIO
E-PAD
RTS5242 -GR_QFN32_4X4
33
+3.3V_RUN_CARD+1 .8V_RUN_CARD
2
CR17
1
SP1
SP2
SP3
SP4
SP5
SP6
SP7
0.1U_0201_10V6K
18
15
16
17
19
20
21
29
22
23
26
25
24
28
1
2
+DV33_1 8
SD/MMCDAT1/RCLK-
SD/MMCDAT0/RCLK+
SD/MMCCLK
SD/MMCCMD
SD/MMCDAT3
SD/MMCDAT2
SDWP
SD_UHS2_D1P
SD_UHS2_D1N
SD_UHS2_D0P
SD_UHS2_D0N
+SDREG2
SD_GPIO
CR18
4.7U_0402_10V6M
7/18 Vender suggest.
PCIE_PTX_C_DRX_P9
PCIE_PTX_C_DRX_N9
PCIE_PRX_C_DTX_P9
PCIE_PRX_C_DTX_N9
+1.8V_RUN_CARD
QR1
L2N7002 WT1G_SC-70 -3
13
D
S
G
2
SD/MMCCD#
+RREF
12
RR4
4.7U_0402_6.3V6M
1
2
1
2
5
6
3
4
7
8
32
31
30
10
14
13
9
6.2K_0402_1%
+3.3V_MMI_AUX
0.1U_0201_10V6K
1
CR1
CR2
2
UR1
PERST#
CLK_REQ#
REFCLKP
REFCLKN
HSIP
HSIN
HSOP
HSON
WAKE#
MS_INS#
SD_CD#
AV12
DV12S
SD_VDD2
RREF
+3.3V_RUN_CARD
RR90_0201_5%@
RR100_0 201_5%@
RR50_0201_5%@EMI@
RR60_0201_5%@
RR70_0201_5%@
RR80_0201_5%@
7/18 Vender suggest
12
CR15
1U_0201 _6.3V6M
12
RR310 K_0402_5%
+3.3V_RUN_CARD
+1.8V_RUN_CARD
2
CR19
1
0.1U_0201_10V6K
12
CR221U_0201_6 .3V6M
12
12
12
12
12
12
+3.3V_MMI_AUX
1
CR20
2
4.7U_0402_10V6M
For PCIE Interface
SD/MMCDAT1/RCLK-_R
SD/MMCDAT0/RCLK+_R
SD/MMCCLK_R
SD/MMCCM D_R
SD/MMCDAT3_R
SD/MMCDAT2_R
SD/MMCCMD_R
SD/MMCCLK_R
SD/MMCCD#
SD/MMCDAT0/RCLK+_R
SD/MMCDAT1/RCLK-_R
SD/MMCDAT2_R
SD/MMCDAT3_R
SD_UHS2_D0P
SD_UHS2_D0N
SD_UHS2_D1P
SD_UHS2_D1N
@EMI@
5P_0402_50V8C
12
CR21
EMI depop locat i on
JSD1
CONN@
4
VDD1
15
VDD2
3
CMD
5
CLK
9
CD
16
SWIO
7
DAT0/RCLK+
8
DAT1/RCLK-
1
DAT2
2
CD/DAT3
18
D0+
19
D0-
22
D1+
21
D1-
6
VSS1
17
VSS2
20
VSS3
23
VSS4
24
NPTH1
T-SOL_15 8-1240902600
GND1
GND2
GND3
GND4
GND5
NPTH2
10
11
12
13
14
25
Link 158-1240902600 done 0123
AA
CR38,CR39 near JSD1.4CR40,CR41 near JSD1.14
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheet
Compal Electronics, Inc.
Card Reader RTS5242
Card Reader RTS5242
Card Reader RTS5242
LA-G871P
LA-G871P
LA-G871P
70109Tuesday, March 05, 2 019
70109Tuesday, March 05, 2 019
70109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
o f
Page 71
5
4
3
2
1
For Merion 14
+5V_USB_CHG_PW R
JUSB1
1
2
3
4
5
6
7
8
9
ESD@
DI5
USB20_N 2_R
USB20_P 2_R
USB3_PRX_DTX_N2
USB3_PRX_DTX_P2
USB3_PTX_C_DRX_N2
USB3_PTX_C_DRX_P2
Link ACON_TCRA2-9U1U93 done 0313
150U_B2_6.3VM_R35M
100U_A_6.3VM_R70M
DI4
DD
USB3_PRX_DTX_N2<10>
USB3_PRX_DTX_P2<10>
USB3_PTX_DRX_N2<10>
USB3_PTX_DRX_P2<10>
12
CI130.1U_0 402_25V6
12
CI160.1U_0 402_25V6
USB3_PRX_DTX_N2
USB3_PRX_DTX_P2
USB3_PTX_C_DRX_N2
USB3_PTX_C_DRX_P2
ESD@
1
1
2
2
4
4
5
5
3
3
8
AZ1045-0 4F_DFN2510P1 0E-10-9
9
10
8
9
7
7
6
6
USB3_PRX_DTX_N2
USB3_PRX_DTX_P2
USB3_PTX_C_DRX_N2
USB3_PTX_C_DRX_P2
@
1
1
+
+
CI32
2
2
0.1U_0201_10V6K
1
CI17
CI14
2
1206 change
3
2
CEST523NC5VB_SOT-523-3
1
CONN@
VBUS
D-
D+
GND5
SSRX-
GND1
SSRX+
GND2
GND6
GND3
SSTX-
GND4
SSTX+
ACON_TC RA2-9U1U93
10
11
12
13
Merion Limit height
DI5 change to H=0.9mm(MAX)
Merion14swapLI7netforlayoutroutin
EMI@
CC
+5V_ALW
UI3
1
VIN
USB20_N 2<10>
USB20_P 2<10>
USB_OC0#<10>
USB_POWERS HARE_VBUS_EN<58 >
USB_POWERS HARE_EN#<58>
BB
+5V_ALW
RI13
ILIM_SEL
12
10K_040 2_5%
+5V_ALW
1
2
47U_0603_6.3V6M
@
CI34
ILIM_SEL
47U_0603_6.3V6M
1
2
100P_0402_50V8J
RF@
@
1
CI31
CI33
2
2
DM_OUT
3
DP_OUT
13
FAULT#
4
ILIM_SEL
5
EN
6
CTL1
7
CTL2
8
CTL3
SLGC555 44CVTR_TQFN1 6_3X3
Thermal Pad
Link Seligro SA000097E10 Done
MAIN:SLG C55544C VTR
0.1U_0201_10V6K
CI19
1
2
VOUT
DP_IN
DM_IN
ILIM_L
ILIM_HI
GND
NC
+5V_USB_CHG_PW R
12
SW_USB20_ P2
10
SW_USB20_ N2
11
15
16
RI14
9
14
17
SW_ USB20_P2
SW_ USB20_N2
12
22.1K_04 02_1%
LI7
1
1
4
4
DLM0NSN 900HY2D_4P
2
2
3
3
g
USB20_P2_R
USB20_N2_R
RF Request
+5V_USB _CHG_PWR
68P_0402_50V8J
12P_0402_50V8J
RF@
1
1
CI43
2
2
RF@
CI44
Place near UI3.1
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
DFB request:
main SM070003Z00 (INPAQ_MCM1012B900 F06BP_4P)
Footprint use 2nd source SM0700044 00 (PANAS_EXC24C Q900U_4P)
Pitch change from 0.5mm to 0.55mm
+5V_ALW
12
Merion Limit height
DI2 change to H=0.9mm(MAX)
10U_0603_10V6M
0.1U_0201_10V6K
@
CI7
1
CI6
2
USB_PWR_E N1#<5 8>
UI1
5
IN
4
EN
SY6288D20 AAC_SOT23-5
OUT
GND
OCB
+USB_EX2_PW R
1
2
3
USB_OC1# <10 >
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheet
Compal Electronics, Inc.
JUSB2
JUSB2
JUSB2
LA-G871P
LA-G871P
LA-G871P
72109Tuesday, March 05, 2 019
72109Tuesday, March 05, 2 019
72109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
o f
Page 73
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
USB2/USB3 DB
USB2/USB3 DB
USB2/USB3 DB
LA-G871P
LA-G871P
LA-G871P
73109Tuesday, March 05, 2 019
73109Tuesday, March 05, 2 019
73109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 74
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
Dock
Dock
Dock
LA-G871P
LA-G871P
LA-G871P
74109Tuesday, March 05, 2 019
74109Tuesday, March 05, 2 019
74109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 75
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
Reserve for USB
Reserve for USB
Reserve for USB
LA-G871P
LA-G871P
LA-G871P
75109Tuesday, March 05, 2 019
75109Tuesday, March 05, 2 019
75109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 76
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
Reserve for USB
Reserve for USB
Reserve for USB
LA-G871P
LA-G871P
LA-G871P
76109Tuesday, March 05, 2 019
76109Tuesday, March 05, 2 019
76109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 77
+3.3V_RUN
5
4
3
2
1
12
RE4810K_ 0402_5%
12
RE5110K_ 0402_5%
DD
Link 50271-0040N-001 done 0123
JFAN1
1
1
2
2
3
3
4
4
5
GND1
6
GND2
ACES_50 271-0040N-001
CONN@
PWM_FAN1
TACH_FAN1
PWM_ FAN1
TACH_FA N1
10U_0402_6.3V6M
1
2
CE32
21
PWM_FAN1 <58 >
TACH_FAN1<58>
+5V_RUN
@
DE1
BZV55-B5 V6_SOD80C2
Fan follow X9 project PIN DEFINE
CC
POWER & INSTANT ON SWITCH
TOP
SW3
POWER_SW #_MB<59,66,79>
3
4
SKRBACE 010_4P
LED Circuit Control Table
1
2
1213 change
Update SW3 footprint
LED_MASK#LID_CL#
BB
Mask All LEDs (Unobtrusive mode)
Mask Base MB LEDs (Lid Closed)
0
10
Do not Mask LEDs (Lid Opened)
CPU
H2@
H_3P1
CONN@
H_3P7
H13@
1
5
H1@
H_3P7
1
H15@
H_2P6
H_2P6
1
H29@
H_0P6X2 P8
1
1
H16@
H_2P6
1
Fiducial Mark
FD1@
1
FIDUCIAL MARK ~D
FD2@
1
FIDUCIAL MARK ~D
FD3@
1
FIDUCIAL MARK ~D
FD4@
1
AA
FIDUCIAL MARK ~D
SHDCAN
1
P1
SION_C752 1R_1P-T
H3@
H_3P7
1
H17@
H_3P1
1
CLIP_0P8X 7P0
CLIP_0P8X 7P0
H4@
H5@
H_3P7
H_4P0
1
1
H18@
1
1213 change
From CLIP_0P6X7P0 to CLIP_0P8X7P0
JUSB1 CLIPS
CONN@
CLIP1
CONN@
1
P1
CONN@
CLIP4
1
P1
CLIP2
1
P1
CLIP_0P8X 7P0
CLIP5
1
P1
CLIP_0P8X 7P0
CONN@
H8@
H_4P0
1
X
11
H11@
H_2P6
1
CLIP3
1
P1
CLIP_0P8X 7P0
CLIP6
1
P1
CLIP_0P8X 7P0
4
H12@
H_2P6
1
CONN@
CONN@
H20@
H_3P2
1
H27@
H_3P6X2 P6
H21@
H_3P2
1
1
H30@
H_2P5X0 P7
1
H31@
H_2P5X0 P7
1
H14@
H_2P3
1
H28@
H_2P6
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
1213 change
From CLIP_0P6X7P0 to CLIP_0P8X7P0
CONN@
CLIP7
1
P1
CLIP_0P8X 7P0
CONN@
CLIP12
1
P1
CLIP_0P8X 7P0
JUSB2 CLIPS
CLIP8
1
P1
CLIP_0P8X 7P0
CLIP11
1
P1
CLIP_0P8X 7P0
3
CONN@
CONN@
CLIP9
1
P1
CLIP_0P8X 7P0
CLIP10
1
P1
CLIP_0P8X 7P0
CONN@
CONN@
1
CLIP_14P1 X2P6
CLIP17
P1
CONN@
2
CLIP13
CONN@
1
P1
EMIST_SUL -15A3M
CLIP14
CONN@
1
P1
EMIST_SUL -15A3M
UT1 AR CLIPS
CLIP15
CONN@
1
P1
EMIST_SUL -15A3M
CLIP16
CONN@
1
P1
EMIST_SUL -15A3M
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
PWRBTN, PAD, ME, FAN
PWRBTN, PAD, ME, FAN
PWRBTN, PAD, ME, FAN
LA-G871P
LA-G871P
LA-G871P
77109Tuesday, March 05, 2 019
77109Tuesday, March 05, 2 019
77109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 78
5
4
3
2
1
+3.3V_WWAN/+3.3V_LAN source
EM5209VF_SON14_2 X3
+3.3V_ALW
7
VIN2_2
6
DD
3.3V_WWAN_E N<58>
3.3V_WWAN_E N
12
RZ40100K_0402_5%
3.3V_WWAN_E N
+5V_ALW
VIN2_1
5
ON2
4
VBIAS
3
ON1
2
VIN1_2
1
VIN1_1
UZ43
GPAD
VOUT2_2
VOUT2_1
VOUT1_2
VOUT1_1
GND
15
+3.3V_WW AN_UZ43
8
9
10
CT2
11
12
CT1
13
Merion no RJ45 LAN port
14
+3.3V_ALW_PCH/+3.3V_RUN source
+3.3V_ALW
UZ3
1
VOUT1_1
VIN1_1
2
VOUT1_2
12
PCH_PRIM_EN<11,87>
CC
RZ640_0201 _5%@
+5V_ALW
RUN_ON
RUN_ON<17,58,59 ,78,87>
VIN1_2
3
ON1
4
VBIAS
5
ON2
6
VOUT2_1
VIN2_1
7
VOUT2_2
VIN2_2
EM5209VF_SON14_2 X3
GND
GPAD
CT1
CT2
+3.3V_ALW_PCH _UZ3
14
13
12
11
10
9
+3.3V_RUN_UZ3
8
15
JUMP@
PJP41
12
PAD-OPEN1x3m
1 2
CZ119 0.1U_0201_10V6K
1 2
CZ109 470P_04 02_50V7K
JUMP@
PJP38
12
PAD-OPEN1x1m
1 2
CZ112 0.1U_02 01_10V6K
1 2
CZ113 100P_04 02_50V8J
1 2
CZ114 1000P_0 402_50V7K
1 2
CZ115 0.1U_02 01_10V6K
JUMP@
PJP39
12
PAD-OPEN1x3m
+3.3V_WWAN
2.5A
0.63A
+3.3V_ALW_PCH
3.435A
+3.3V_RUN
+5V_RUN/+3.3V_WLAN source
+3.3V_WWAN_UZ43
1
CZ124
RF@
2200P_0402_ 50V7K
2
RF Request
EC request to reserve OR gate for WLAN power enable
Merion Limit height
QZ15 change to SB00001KM00 H=0.9mm(MAX)
Reserve R/C for Audio power sequence, + 5V->+3.3V-> +1.8V
AUX_EN_WOWL< 58>
0_0201_5%
12
CZ197
+3.3V_ALW
12
2
G
13
D
QZ15
PJE138K_SOT52 3-3
+5V_ALW
100K_0402_5%
RZ518
S
+1.8V_PRIM
RUN_ON_1.8V
SLP_WLAN#_M
UZ8
1
2
3
4
AOZ1336_DFN8_2X2
+3.3V_ALW_PCH
20K_0402_5%
12
@
RZ379
7
VIN1
VOUT1
+1.8V_RUN_UZ8
8
VIN2
VOUT2
6
ON
CT
VBIAS
5
GND1
9
GND2
+3.3V_ALW
20K_0402_5%
12
RZ1483
Merion Limit height
DZ9 change to SCS00008B80 H=0.6mm(MAX)
12
RZ710_0201_5%@
DZ9
3
1
2
BAT54CTB_SOT-5 23-3
12
RZ700_0201_5%@
JUMP@
0.013A
PJP42
12
PAD-OPEN1x1m
1 2
CZ120 0.1U_02 01_10V6K
1 2
CZ121 470P_04 02_50V7K
WLAN_PW R_EN
+1.8V_RUN
JUMP@
3.076A
PJP40
+5V_ALW
BB
RZ38100K_0402_5%
AA
12
RUN_ON<17,58,59,78,87>
WLAN_PW R_EN
+3.3V_ALW
WLAN_PW R_EN
UZ47
1
VOUT1_1
VIN1_1
2
VOUT1_2
VIN1_2
3
ON1
4
VBIAS
5
ON2
6
VOUT2_1
VIN2_1
7
VOUT2_2
VIN2_2
EM5209VF_DFN14_ 3X2
GPAD
CT1
GND
CT2
+5V_RUN_UZ47
14
13
12
11
10
+3.3V_WLAN_UZ47
9
8
15
12
PAD-OPEN1x2m
1 2
CZ116 0.1U_02 01_10V6K
1 2
CZ117470P_0402 _50V7K
1 2
CZ118 470P_04 02_50V7K
1 2
CZ122 0.1U_02 01_10V6K
12
PAD-OPEN1x2m
JUMP@
PJP36
+5V_RUN
+3.3V_WLAN
2A
RUN_ON<17,58,59 ,78,87>
SSD_SCP_PW R_EN_D
RZ1472
@
100K_0402_5 %
12
SSD_SCP_PW R_EN_D
+3.3V_ALW
5
UZ54
@
1
MC74VHC1G32DFT 2G_SC70-5~D
P
INB
4
O
2
INA
G
3
12
RZ14710_0 201_5%@
+3.3V_ALW
@
100K_0402_5 %
12
RZ1474
+1.8V_PRIM
13
D
@
PJE138K_SOT52 3-3
+3.3V_ALW
UZ53@
1
2
SSD_EN
3
+5V_ALW
Merion Limit height
QZ22 change to SB00001KM00 H=0.9mm(MAX)
2
G
S
QZ22
4
AOZ1336_DFN8_2X2
SSD_SCP_PW R_EN
VIN1
VIN2
ON
VBIAS
7
VOUT1
8
VOUT2
6
CT
5
GND1
9
GND2
SSD_SCP_PWR_EN <58>
+3.3V_SSD
1 2
CZ305 0.1U_02 01_10V6K@
1 2
CZ306 470P_04 02_50V7K@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document N umberRe v
Size Document N umberRe v
Size Document N umberRe v
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
Power control
Power control
Power control
LA-G871P
LA-G871P
LA-G871P
1
78109Tuesday, March 05, 2019
78109Tuesday, March 05, 2019
78109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 79
5
4
3
2
1
CONN@
JAPS1
+3.3V_ALW_PCH
SIO_SLP_S3#<11,17,42,59>
+3.3V_ALW
SIO_SLP_S5#<11>
SIO_SLP_S4#<11,17,86,87>
SIO_SLP_A#< 11>
+3.3V_ALW
PCH_RTCRST#<11,5 8>
POWER_SW#_M B<59,66,77>
SYS_RESET#<11>
DD
CC
BB
AA
SIO_SLP_S0#<9,11,17,66,8 7>
11
12
JXT_FP241AH -010GAAM
JXT_FP241AH-010GAAMLINKDONE
GND1
GND2
+1.0V_PRIM
VCCST_PWRGD<11,59>
PCH_RSMRST#_AND<11,63>
JDEG1
1
2
3
4
5
6
7
8
9
10
CONN@
RC2160_0402_5%@
Place near
JXDP1
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
PCH_RTCRST#
SYS_RESET#
SIO_SLP_S0#
1
2
3
4
5
6
7
8
9
10
12
+1.0V_PRIM_XDP
0.1U_0201_10V6K
@
CC288
1
2
XDP_OBS0_R<14>
XDP_OBS1_R<14>
+1.0VS_VCCIO
+1.0V_VCCST
+3.3V_RUN
+1.0V_PRIM_XDP
+EC_DEBU G_VCC
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
GND1
20
GND2
CVILU_CF4218F H0R0-05-NH
12
RE71
10_0402_1%
RE813
10K_0402_5%
DEBUG_TX
+1.0V_PRIM_ XDP
0.1U_0201_10V6K
@
CC299
1
2
RC5 need to close to JCPU1
RC1231K_0201_5 %@
12
RC1241K_0201_5 %CXDP@
12
FIVR_EN
CFG0
PCH_SPI_DO_XDP<8>
SYS_PWROK<11,58>
12
RC132150 _0402_5%
12
RC235150 _0402_5%@
12
RC23610K _0201_5%@
12
RC1373K_040 2_5%
12
RC13851_0201 _5%@
12
RE814
10K_0402_5%
12
RE300_ 0201_5%@
RC217
RC1261K_0201_5 %@
RC1280_0201_5%@
RC129
DDR_XDP_WAN_SMBDAT<8,23,24>
DDR_XDP_WAN_SMBCLK<8,23,24>
FIVR_EN_R
FIVR_EN
FIVR_EN
XDP_DBRESET#
CPU_XDP_PREQ#
12
RE815
RC2390_0201_5%@
RC2400_0201_5%@
12
RE816
10K_0402_5%
SBIOS_TX<6>
CPU_XDP_PREQ#<14>
CPU_XDP_PRDY#<14>
12
12
12
12
12
12
PCH_JTAG_TCK<14>
CPU_XDP_TCLK<14>
JXT_FP241AH-010GAAMLINKDONE
12
10K_0402_5%
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
MSCLK
MSDATA
HOST_DEBUG_TX
HOST_DEBUG_TX <58>
MSDATA <58>
MSCLK <58>
CPU XDP
H_VCCST_PWRGD_XDP
SIO_PWRBTN#<11,58>
0_0201_5%@
0_0201_5%@
CPU_XDP_TCLKXDP_TMS
11
GND1
12
GND2
JXT_FP241AH -010GAAM
+3.3V_ALW
JTAG_TDI <58>
JTAG_TMS <58>
JTAG_CLK <58>
JTAG_TDO <58>
12
RE3060_02 01_5%@
+1.0V_PRIM_XDP
CFG0
CFG1
CFG2
CFG3
XDP_OBS0
XDP_OBS1
CFG4
CFG5
CFG6
CFG7
FIVR_EN_R
RESET_OUT#_R
+3.3V_ALW_PCH
JESPI
10
CONN@
10K_0402_5%
12
RE72
XDP_PRSN T_PIN1
12
1
2
Place near JXDP1.47
5
+3.3V_RUN
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
100K_0402_5%
10K_0402_5%
10K_0402_5%
12
12
12
RE75@
RE74
RE73
RE86
10K_0402_5 %
12
CFG[0..19]<13>
12
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
GND
12
CONN@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
GND
CFG3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
63
RC1210_0201_5%@
RC1220_0201_5%@
JXDP1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
62
JXT_FP270H-06 1G1AM
Link FP270H-061G1AM done 013 1
RC133
1.5K_0201_5%
CXDP@
PCH_SPI_DO_XDP
RESET_OUT#_R
0.1U_0201_25V6K
@
CC334
Place near JXDP1.48
XDP_DBRESET#
4
+1.0V_PRIM_XDP
ITP_PMODE
XDP_DBRESET#
TDO_XDP
TRST#_XDP
TDI_XDP
0.1U_0201_25V6K
1
2
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
CXDP@
CC326
ESPI_IO0 <8,58>
ESPI_IO1 <8,58>
ESPI_IO2 <8,58>
ESPI_IO3 <8,58>
ESPI_CS# <8,58>
ESPI_RESET# <8,58>
ESPI_CLK_5105 <8,58>
12
RC3280_0 201_5%@
TDO_XDP
TDI_XDP
XDP_TMS
TRST#_XDP
XDP_TMS
TDI_XDP
TDO_XDP
CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>
ITP_PMODE <13>
XDP_DBRESET# <11>
PCH_SPI_DO2_XDP <8>
TDO_XDPH_VCCST_PWRGD_X DP
@ESD@
0.1U_0201_25V6K
1
CC306
2
ESD request,Place near JXDP1 side.
12
RC8500_0 201_5%@
12
RC8510_0 201_5%@
12
RC8520_0 201_5%@
12
RC8530_0 201_5%@
12
RC7350_0 201_5%@
12
RC7360_0 201_5%@
12
RC7370_0 201_5%@
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
CPU_XDP_TMS
CPU_XDP_TDI
CPU_XDP_TDO
CPU_XDP_TRST#
CPU_XDP_TCLK
1
2
For BL_PWR_SRC & LCDVDD monitor
XDP_JTAGXCPU_XDP_TCL K
CPU_XDP_TDO
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_TRS T#
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
12
RC56951_0201 _5%
12
RC568
100_0201_5 %
12
RC13051_0201 _5%
12
RC13151_ 0201_5%@
12
RC13451_ 0201_5%@
12
RC135100 _0201_5%
12
RC13651_ 0201_5%@
12
RC13951_ 0201_5%
@ESD@
0.1U_0201_25V6K
CC307
Place near JXDP1.41
3
+BL_PWR_SRC
0.1U_0201_25V6K
1
RB751S-40_ SOD523-2
CV634
2
+LCDVDD
0.1U_0201_25V6K
1
RB751S-40_ SOD523-2
CV652
2
XDP_JTAGX <14>
CPU_XDP_TDO <14>
CPU_XDP_TDI <14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>
PCH_JTAG_TMS <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
+1.0V_VCC STG
+1.0V_VCCSTG
SIO_PWRBTN#
21
DV11
21
DV12
+13.5VB
2
10K_0402_5%
12
RV627
QV18
13
MMBT3906H_S OT23-3
47K_0402_5%
12
RV625
2200P_0402_50V7K
200K_0402_5%
12
CV633
RV626
12
BL_PW R_MONITOR
LMBT3904W T1G_SC70-3
+3.3V_RUN
2
10K_0402_5%
12
RV631
QV20
13
MMBT3906H_S OT23-3
47K_0402_5%
12
RV630
2200P_0402_50V7K
200K_0402_5%
12
CV651
RV629
12
LCDVDD_MON ITOR
LMBT3904W T1G_SC70-3
+LCDVDD
100K_0402_5%
12
RV623
PANEL_PW RGD
12
C
2
B
E
QV19
31
C
2
B
E
QV21
31
M-BIST
DZ12
@
ACAV_IN<58,84,91>
M_BIST<58>
+3.3V_ALW
PCH_RSMRST#<58,63>
+3.3V_ALW_DSW
1.5K_0201_5%
@
RC241
12
0.1U_0201_25V6K
@
1
CC269
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.
ME_FWP PCH has internal 20K PD.
(suspend power rail)
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT) -->Pin2 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin1 & Pin2 short
M_BIST_R
12
12
12
12
LMBT3904W T1G_SC70-3
POWER_SW_IN#<58,59>
ME_FW P
PT,ST pop RC222 and SW1; MP pop RC221
RC222
@
1K_0402_5%
12
ME_FWP_PCH<12>
ME_FWP<58>
2
RC2210_0201_5%@
12
ME_FWP_PCH
ME_FW P
QZ21
BAT1_LED#_R
C
2
B
E
31
ME_FWP_PCH
@
1
2
3
4
5
Link SSAJ120100 done 0514
12
RV6280_0201_5%@
0.1U_0402_25V6
1M_0402_5%
CV632
12
RV624
RF Request
+13.5VB
100P_0402_50V8J~D
RF@
47P_0402_50V8J
RF@
1
12
CV756
CV755
2
place as close as QV18
R2
R1=10K;R2= 10K
2
R1
13
QZ3
LMUN5111T1G_S C70-3
12
RZ25150_0402_5%
0212 Change
SW1
1
C
2
G1
G2
SSAJ1201 00_3P
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
XDP/CMC/APS...debug
XDP/CMC/APS...debug
XDP/CMC/APS...debug
Document Num berRe v
Document Num berRe v
Document Num berRe v
PANEL_MON ITOR <58>
BATT_YELLOW# <64>
LA-G871P
LA-G871P
LA-G871P
1
1.0
1.0
79109Tuesday, Marc h 05, 2019
79109Tuesday, Marc h 05, 2019
79109Tuesday, Marc h 05, 2019
1.0
Page 80
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
Google Debug & INAs
Google Debug & INAs
Google Debug & INAs
LA-G871P
LA-G871P
LA-G871P
80109Tuesday, March 05, 2 019
80109Tuesday, March 05, 2 019
80109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 81
5
DD
CC
4
3
2
1
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size
Size
Size
Date:Sheetof
Date:Sheetof
Date:Sheetof
Compal Electronics, Inc.
PWR-Block Diagram
PWR-Block Diagram
PWR-Block Diagram
Document NumberRe v
Document NumberRe v
Document NumberRe v
LA-G871P
LA-G871P
LA-G871P
1
81109Tuesday, March 05, 2019
81109Tuesday, March 05, 2019
81109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 82
1
12
PR852
@
100K_0402_5%
2
EN_PD_HV_1 <44,82,84>
CMOUT <84>
34
D
PQ811B
L2N7002DW1T1G 2N SC88-6
PROCHOT#_CHG <84>
D
PQ812
S
L2N7002WT1G_SC-70-3
Compal Electro nics, Inc.
Compal Electro nics, Inc.
Compal Electro nics, Inc.
Title
Title
Title
DC Connector/1Ty pe-C PD Selector
DC Connector/1Ty pe-C PD Selector
DC Connector/1Ty pe-C PD Selector
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
LA-G871P
LA-G871P
LA-G871P
Date:Sheetof
Date:Sheetof
Date:Sheetof
1
1.0
1.0
1.0
82109Tuesday, March 05, 2019
82109Tuesday, March 05, 2019
82109Tuesday, March 05, 2019
+20V_LDO_input
1000P_0402_50V7K
PC11
12
HW_ACAVIN_NB <58,82,84>
PD801
S SCH DIO 5A 100V 15UA 0.88V TO227-3
2
3
PQ801
EMZB08P03V_EDFN3X3-8-5
5
4
12
34
PR816
5
0_0402_5%
PR826
0_0402_5%
1
1
PR827
0_0402_5%
+3.3V_ALW
12
PR830
100K_0402_5%
61
D
PQ808A
S
L2N7002DW1T1G 2N SC88-6
PR841
2
PR844
2
1
0_0402_5%
2
PD803
1
BAT54CW_SOT323-3
1
1
2
3
1
PR804
2
PR812
49.9K_0402_1%
PQ804B
L2N7002DW1T1G_SC88-6
12
2
2
+3.3V_ALW
5
G
2
22_0805_5%
PR892
1
2
12
3
PR893
22_0805_5%
1
2
PC802
1500P_0402_50V7K
499K_0402_1%
PR824
@
100K_0402_5%
61
D
2
G
S
12
PR839
100K_0402_5%
2
G
34
D
PQ809B
L2N7002DW1T1G 2N SC88-6
S
1
PR845
@0@
0_0402_5%
2
S
D
1 3
AO3409 P-CHANNEL SOT-23
+3.3V_ALW+3.3V_ALW
PQ810A
+3.3V_ALW
L2N7002DW1T1G 2N SC88-6
2
+20V_TBTA_VBUS_1
+19.5V_DC_IN
12
PR802
300K_0402_5%
PQ805
G
2
12
PR808
100K_0402_5%
3
PQ806B
4
L2N7002DW1T1G_SC88-6
12
PR825
@
100K_0402_5%
5
G
S
12
PR838
100K_0402_5%
61
D
PQ809A
L2N7002DW1T1G 2N SC88-6
S
5
1
AC_DISC# <58>
34
D
PQ810B
12
L2N7002DW1T1G 2N SC88-6
PR814
0_0402_5%
+3.3V_ALW
@
D
S
PC810
2
12
PR828
100K_0402_5%
61
1500P_0402_50V7K
0_0402_5%
1
PQ811A
L2N7002DW1T1G 2N SC88-6
+19.5V_SDC_IN
+3.3V_VDD_PIC
12
PR813
100K_0402_5%
61
PR820
1
2
PQ806A
0_0402_5%
L2N7002DW1T1G_SC88-6
PR829
2
2
5
G
G
S
13
2
G
DELL CONFIDENTIAL/PROPRIETARY
PD5
2
3
S2
PQ4
EMZB08P03V_EDFN3X3-8-5
4
12
PR16
49.9K_0402_1%
13
D
2
PQ7
G
S
L2N7002WT1G_SC-70-3
12
PQ803
G
2
12
1
6
0_0402_5%
2
PQ802A
1
L2N7002DW1T1G_SC88-6
L2N7002DW1T1G_SC88-6
PQ807
L2N7002WT1G_SC-70-3
S
G
2
1
2
PR821
100K_0402_5%
1
1
2
35
1
PR11
2
PR20
0_0402_5%
1
S
D
1 3
PR858
D
13
1
2
+3.3V_VDD_PIC
3
PS_ID <58>
12
499K_0402_1%
2
PC803
AO3409 P-CHANNEL SOT-23
2
13
D
L2N7002WT1G_SC-70-3
S
VBUS1_ECOK_R<58,82>
PR822
100K_0402_5%
3
+3.3V_VDD_DCIN
1
12
PC12
PC10
4.7U_0402_6.3V6M
2
82P_0402_50V8J
@RF@
12
PR10
300K_0402_5%
PC4
PQ5
S
G
2
12
D
1 3
0.022U_0402_25V7K
PR15
100K_0402_5%
AO3409 P-CHANNEL SOT-23
6
PQ1A
1
L2N7002DW1T1G_SC88-6
VBUS1_ECOK_R <58,82>
12
PR24
100K_0402_5%
S4S5
PQ800
EMZB08P03VL_P_DFN33-8-5
1
2
3
1
12
PR803
2
0.47U_0402_25V6K
499K_0402_1%
PR811
PQ814
2
G
12
2
PR861
0_0402_5%
PR818
2
1
0_0402_5%
EN_PD_HV_1< 44,82,84>
+3.3V_VDD_DCIN
PR19
0_0402_5%
2
2
1
PQ1B
L2N7002DW1T1G_SC88-6
+20V_VBUS_DC_SS
5
4
1
2
6
49.9K_0402_1%
PQ804A
1
L2N7002DW1T1G_SC88-6
PR834
0_0402_5%
2
1
PU2
VCC
3
VOUT
GND
RT9058-33GX_SOT89-3
12
PR17
100K_0402_5%
3
5
4
VBUS2_ECOK_R<58,82>
+3.3V_ALW
5
G
1
2
+19.5V_SDC_IN
PR25
0_0402_5%
2
1
12
PR862
100K_0402_5%
@
12
12
PR819
100K_0402_5%
VBUS1_ECOK_R<58,82>
VBUS2_ECOK_R<58,82>
12
PR833
100K_0402_5%
2
G
34
D
PQ808B
S
@0@
0_0402_5%
1
L2N7002DW1T1G 2N SC88-6
HW_ACAVIN_NB<58,82,84>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
S
D
1 3
AO3409 P-CHANNEL SOT-23
D
13
PC865
0.1U_0402_25V6
+3.3V_VDD_DCIN+3.3V_ALW
PR836
0_0402_5%
1
34
PQ813B
L2N7002DW1T1G_SC88-6
12
PR6
100K_0402_1%
12
PR8
15K_0402_1%
+19.5V_DC_IN
1
1
PC6
2
2
0.022U_0402_25V7K
12
PR46
0_0402_5%
PQ12
L2N7002WT1G_SC-70-3
13
D
2
G
S
PR22
0_0402_5%
1
12
PR27
100K_0402_5%
EN_PD_HV_1< 44,82,84>
S1_OVP
2
4
PR3
@0@
1
0_0402_5%
PSID circuit, it need with >6KV ESD
1 3
D
S
PQ2
FDV301N-G_SOT23-3
G
2
C
2
PQ3
B
LMBT3904WT1G_SC70-3
E
3 1
S1
PQ9
EMZB08P03VL_P_DFN33-8-5
1
2
3
4
PR12
1M_0402_5%
12
PR18
1M_0402_5%
12
PR49
0_0402_5%
VBUS2_ECOK_R <58,82>
13
D
2
2
PQ6
G
S
L2N7002WT1G_SC-70-3
+3.3V_VDD_PIC
S1_OVP <82>
4
2
5
+3.3V_ALW2
PR5
33_0402_5%
12
+19.5V_DC_IN_SS
PR857
0_0402_5%
1
PR859
0_0402_5%
12
PR860
@0@
0_0402_5%
1
1 2
PC814
@
PR853
0.1U_0402_10V7K
0_0402_5%
2
1
2
1
PR854
0_0402_5%
PU801
@
MC74VHC1G08DFT2G_SC70-5
+3.3V_ALW
PR4
2.2K_0402_5%
12
+5V_ALW
12
PR7
10K_0402_1%
S SCH DIO 5A 100V 15UA 0.88V TO227-3
1
12
PC8
2
PR14
100K_0402_5%
10U_0603_25V6M
PR801
300K_0402_5%
+3.3V_ALW
+3.3V_VDD_PIC+3.3V_ALW
PR807
100K_0402_5%
1
12
PR851
PR810
@
100K_0402_5%
2
100K_0402_5%
EN_PD_HV_1#
2
2
5
1
P
B
O
2
A
G
3
3
5
PQ802B
4
12
@0@
PR856
0_0402_5%
4
12
PR855
@
10K_0402_5%
DCIN2_EN_R<58>
+3.3V_ALW
5
PL3
EMI@
3
3
6
1
12
PR806
1K_0402_1%
HW_ACAVIN_NB
1
2
1
2
1
1
+3.3V_VDD_DCIN
PQ10A
L2N7002DW1T1G_SC88-6
DCIN1_EN_R<58>
PR823
100K_0402_5%
HW_ACAVIN_NB<58,82,84>
PC813
2.2U_0402_25V6M
2
1
2
PC809
EMI@
12
1
2
2
PR33
100K_0402_5%
5
PR28
100K_0402_5%
+20V_TBTA_VBUS_1
12
100P_0402_50V8J
PR835
47K_0402_1%
0_0402_5%
12
BLM15AG102SN1D_2P
2
1
PD4
@ESD@
L03ESDL5V0CG3-2_SOT-523-3
1
PR31
PQ11
1M_0402_5%
2
G
2
12
PR32
1M_0402_5%
S1_OVP <82>
3
PQ10B
4
L2N7002DW1T1G_SC88-6
PQ8
L2N7002WT1G_SC-70-3
S
G
2
1
1
12
2
PR865
2
100K_0402_5%
HW_ACAVIN_NB <58,82,84>
+20V_TBTA_VBUS_1
PR840
5
NB_PSIDPS_ID
DD
PL4
EMI@
FBMJ4516HS720NT_2P
Capacitors on +19.5V_DC_IN net need < 1000pF
2
1
PR41
2
PR47
2
2
5
1
B
2
A
3
PU3
@
PC801
@
1 2
PR866
PD800
@
3
2
BAT54CW_SOT323-3
3
2
PC807
EMI@
1000P_0402_50V7K
PC812
100P_0402_50V8J
61
2
12
1
1
PC7
2
PR13
2
4.7K_0805_5%
@
0.1U_0402_25V6
@EMI@
12
@0@
PR43
0_0402_5%
P
4
O
G
12
PR45
@
10K_0402_5%
1
LM393_P
PR805
1.8M_0402_1%
2
1
LM393_P
PU800A
8
AS393MMTR-G1_MSOP8
P
+
1
O
-
G
4
EMI Part
PL801
EMI@
5A_Z80_20M_0805_2P
2
1
12
PL800
5A_Z80_20M_0805_2P
EMI@
1
PC808
2
0.1U_0402_25V6
@EMI@
S1 OVP
PD802
30MA_30V_0.5UA_0.4V_SOD323-2
2
1
LM393_P
LM393_P
PU800B
8
AS393MMTR-G1_MSOP8
5
P
+
7
O
6
-
G
4
12
PR846
10K_0402_5%
2
+3.3V_VDD_DCIN
PC805
1200P_0402_50V7K
1
2
EN_PD_HV_1 <44,82,84>
PJPDC1
CONN@
7
GND2
6
GND1
5
5
4
+19.5V_DCIN_JACK
4
3
3
9
2
NPTH2
2
8
1
NPTH1
1
CVILU_CI0805M1HRC-NH
+3.3V_VDD_DCIN
HW_ACAVIN_NB<58,82,84>
CC
+3.3V_VDD_DCIN
+19.5V_DC_IN
1
1
PR800
PR809
2
2
422K_0402_1%
102K_0402_1%
(>17.1V)
1
1
PR817
PR815
2
24.9K_0402_1%
BB
2
37.4K_0402_1%
PC5
EMI@
0.1U_0402_10V7K
PR42
0_0402_5%
1
1
PR44
0_0402_5%
DCIN_AC _De tec tor
+3.3V_VDD_DCIN
+3.3V_VDD_PIC
1
1
PC800
2
2
100P_0402_50V8J
1
2
1000P_0402_50V7K
0_0402_5%
1
0_0402_5%
1
PC13
@
1
2
2
MC74VHC1G08DFT2G_SC70-5
0.01UF_0402_25V7K
0_0402_5%
12
PC804
220P_0402_50V7K
+20V_TBTA_VBUS
12
PC806
100P_0402_50V8J
@EMI@
+20V_VBUS_DC_SS
AA
12
PR870
@
499K_0402_1%
OVP setting:5.4V
+20V_TBTA_VBUS_1
1
PR831
2
499K_0402_1%
12
1
PC811
PR842
2
97.6K_0402_1%
10U_0402_6.3V6M
L2N7002DW1T1G_SC88-6
+3.3V_VDD_DCIN
12
PR832
102K_0402_1%
1
PR843
2
37.4K_0402_1%
PQ813A
5
Page 83
5
4
3
2
1
+3.3V_RTC_LDO
PD3
BAS40CW_SOT323-3
+COINCELL
12
PR2
1K_0402_5%
+Z4012
3
2
1
+RTC_CELL
12
PC3
1U_0402_25V6K
PD1
DD
CEST523NC5VB__SOT-523-3
1
1
2
2
ESD@
3
3
Primary Battery Connector
PBATT1
CONN@
1
1
2
2
3
3
4
4
5
5
12
12
PC2
PC1
EMI@
27P_0402_50V8J
2200P_0402_50V7K
@RF@
CC
6
6
7
7
8
8
9
9
10
10
11
GND1
12
GND2
DEREN_40-42251-01001RHF
PBAT_SMBCLK_C
PBAT_SMBDAT_C
PBAT_PRES#_C
GND
12
PR38
100_0402_5%
12
PR39
100_0402_5%
12
PR40
100_0402_5%
1
1
2
2
PD2
ESD@
CEST523NC5VB__SOT-523-3
3
3
+13.2VB_PBATT_C
PBAT_CHARGER_SMBCLK <58,84>
PBAT_CHARGER_SMBDAT <58,84 >
PL1
EMI@
FBMJ4516HS720NT_2P
12
PL2
EMI@
FBMJ4516HS720NT_2P
12
+13.2VB_BATT
+3.3V_ALW
12
PR1
100K_0402_5%
PBAT_PRES# <58,84>
COIN RTC Battery
2
G
12
PR9
10M_0402_5%
+COINCELL
RTC_DET# <8>
13
D
PQ13
L2N7002WT1G_SC-70-3
S
CONN@
1
2
ACES_50271-0020N-001
JRTC1
3
G1
1
4
G2
2
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
Title
Size
Size
Size
Date:Sheetof
Date:Sheetof
Date:Sheetof
Battery Connector/ RTC
Battery Connector/ RTC
Battery Connector/ RTC
Document NumberRe v
Document NumberRe v
Document NumberRe v
LA-G871P
LA-G871P
LA-G871P
1
83109Tuesday, March 05, 2019
83109Tuesday, March 05, 2019
83109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 84
C
8
PL701
7
2.2UH_PCM B103T-2R2MS_1 3A_20%
12
6
5
12
PR717
4.7_1206_5%
EMI@
SNUB1_CHG
12
PC746
680P_0402_50V7K
EMI@
CSOP_CHG _R
CSON_CHG_ R
PR736
0_0402_ 5%
12
12
PR737
0_0402_ 5%
BAT54CW _SOT323-3
+13.5VB
PC720
@EMI@
8
G2
7
D2/S1_3
6
D2/S1_2
5
D2/S1_1
9
D1_3
S1/D2
D1_1
D1_2
S2
10
PQ701
AOE6936 _DFN5X6E8-1 0
12
PR739
100K_0402_1%
G1
ACAV_IN1
1
2
3
4
@0@
LG2_CHGUG2_CHG
LX2_CHGLX1_CHG
12
PR718
4.7_1206_5%
EMI@
SNUB2_CHG
12
PC747
680P_0402_50V7K
EMI@
3
1
2
PD705
12
PC721
0.1U_0402_25V6
@EMI@
PR735
0_0402_ 5%
12
0.1U_040 2_10V7K
PR741
12
0_0402_ 5%
2200P_0402_50V7K
1 2
12
PC754
1
2
PC707
+13.5VB
12
PC728
PC729
0.1U_0201_25V6K
RF@
RF@
PC756
22P_0201_25V8
RF@
PR711
0.005_1 206_1%
4
1
2
3
LM393_P
5
P
IN1
4
12
O
IN2
G
PU701
3
MC74VHC1G 08DFT2G_SC70 -5
12
10U_0603_25V6M
12
0.1U_0201_25V6K
1
PC757
2
47P_0201_25V8J
RF@
+13.5VB_VCHGR
PR740
0_0402_ 5%
CSIN_CHG
14
CSIN
PROG
27
PROG_CHG
12
PR725
PR743
+19.5V_AC
4
3
CSIN_CHG_R
12
13
ASGATE
CMOP
28
COMP_CHG
105K_0402_1%
12
0_0402_5%
I_ADP
<58>
I_ADP
B
PR702
1_0603_ 1%
12
PC727
0.47U_04 02_25V6K
BST1_CHG_R
12
PR704
3.3_060 3_1%
UG1_CHG
BOOT1_CHG
12
11
BOOT1
UGATE1
PSYS
AMON/BMON
30
29
PSYS_CHG
VBAT1_CHG
AMON/BMON_CHG
12
PC750
0.1U_0402_25V6
<58>
12
10
31
PL700
EMI@
1UH_PCMB0 51H-1R0MS_8 A_20%
12
PJP700
@JUMP@
12
PAD-OPEN 4x4m
PD701
SMF4L22A_SOD123FL2
footprint change to
SMF4L2 2A_S OD123 FL2
12
PC726
1U_0402_25V6K
LG1_CHG
LX1_CHG
PU700
33
9
ISL9538 BHRTZ-T_TQFN32_4X4
PAD
VDDP_CHG
8
LGATE1
PHASE1
VDDP
LG2_CHG
7
LGATE2
LX2_CHG
6
PHASE2
5
UGATE2
BOOT2_CHG
4
BOOT2
VSYS_CHG
3
VSYS
CSOP_CHG
2
CSOP
CSON_CHG
1
CSON
BGATE
VBAT
32
BGATE_CHG
12
PR731
0_0402_5%
PSYS R on CPU Controller site
I_SYS
<58,88>
12
@
PR707
4.7_060 3_5%
12
1 2
12
PR738
100_040 2_5%
PC755
0.1U_040 2_25V6
12
PC701
PC700
0.1U_0402_25V6
@EMI@
@EMI@
VDD_CHG
1 2
PC738
4.7U_040 2_6.3V6M
BST2_CHG_R
PC740
0.47U_04 02_25V6K
PR721
0_0402_ 5%
12
12
12
PC702
10U_0805_25VAK
2200P_0402_50V7K
12
PR714
4.7_060 3_5%
1 2
PC745
@
0.1U_040 2_25V6
12
PC752
1U_0402 _25V6K
+13.2VB_BATT
+19.5V_CHARGER
12
12
PC704
PC703
@
10U_0805_25VAK
10U_0805_25VAK
1
12
+
PC706
PC705
2
@
10U_0603_25V6M
15U_B2_25VM_R100M
UG1_CHGLG1_CHG
LX1_CHGLX2_CHG
9
1
G1
D1_3
2
S1/D2
D2/S1_3
3
D1_1
D2/S1_2
4
D2/S1_1
D1_2
S2
10
PQ700
AOE6936 _DFN5X6E8-1 0
G2
+13.5VB
PC748
@
1U_0402 _25V6K
1 2
PR733
1_0603_ 1%
12
12
PR734
1_0603_ 1%
1 2
PC753
0.22U_04 02_25V6K
EN_PD_HV _1<44,8 2>
HW_ACA VIN_NB<58 ,82>
A
+19.5V_SDC_IN
11
PR700
0.01_12 06_1%
1
2
CSIP_CHG_R
12
PR701
1_0603_ 1%
PC719
4.7U_040 2_6.3V6M
1 2
12
PC725
DCIN_CHG
VDD_CHG
SDA_CHG
SCL_CHG
10P_040 2_50V8J
@0@
1U_0402_25V6K
ADP_CHG
17
DCIN
18
VDD
19
ACIN
20
OTGEN/CMIN
21
SDA
22
SCL
23
PROCHOT#
24
ACOK
PC744
1 2
BATGONE_CH G
PR726
100K_04 02_1%
12
PR727 0_0 402_5%
12
PR745
0_0402_ 5%
12
CSIP_CHG
16
15
ADP
CSIP
OTGPG/CMOUT
BATGONE
26
25
OTGPG/CMOUT_CHG
12
PR705
442K_04 02_1%
ACIN_CHG
12
PR706
100K_04 02_5%
PR709
0_0402_ 5%
12
Not to change short pad
PR703
0_0603_ 5%
12
PR746
@0@
0_0402_ 5%
12
PR712
@0@
0_0402_ 5%
12
12
PR713 0 _0402_5%
12
PR715 0 _0402_5%
12
PR719
0_0402_ 5%
12
PR722 0_0 402_5%
PR723
@
100K_04 02_1%
12
ACIN_CHG<91>
OTGEN/CMIN_C HGUG2_CHG
PROCHOT#_CH G
ACOK_CHG
PD700
+19.5V_SDC_IN
+19.5V_DC_IN_SS
30MA_30 V_0.5UA_0. 4V_SOD323-2
22
+13.5VB
30MA_30 V_0.5UA_0. 4V_SOD323-2
+20V_VBUS_DC_SS
1 2
ACAV_IN1<91 >
AC_DIS<58>
12
33
12
PD702
12
PD704
21
RB520SM-3 0T2R_EMD2-2
PC737
2.2U_040 2_25V6M
4.7U_040 2_6.3V6M
PQ703
13
D
2
154K_04 02_1%
G
S
L2N7002 WT1G_SC-70 -3
PR720
1M_0402 _1%
1 2
PC739
PR716
PR708
1_0805_ 5%~D
12
12
0.1U_040 2_25V6
12
PBAT_PRES #<58,83>
PC736
PR710
100K_04 02_1%
PBAT_CHARG ER_SMBDAT<58,83>
PBAT_CHARG ER_SMBCLK<58,8 3>
PROCHOT#_CH G<82>
12
HW_ACA VIN_NB
PROCHOT#<14,58,8 8>
PR724
100K_0402_1%
12
+3.3V_ALW
CMOUT<82>
PROCHOT#
12
PR728
12
499_0402_1%
12
PC751
0.01UF_0402_25V7K
44
12
PC749
@
PR729
560P_0402_50V7K
0_0402_5%
I_BATT
I_BATT
Close to EC ADP_I pin
D
12
PC710
10U_0603_25V6M
12
PC732
82P_0201_50V8J
RF@
1
PC760
2
22P_0201_25V8
47P_0201_25V8J
RF@
1
2
35
1
+
PC715
2
15U_B2_25VM_R100M
12
12
PC734
PC733
RF@
12
PQ702
EMZB08P0 3V_EDFN3X3 -8-5
PC735
82P_0201_50V8J
RF@
RF@
2200P_0201_16V7K
2200P_0201_16V7K
12
RF demand
PC761
100P_0201_25V8J
RF@
12
12
12
PC723
PC722
1U_0402_25V6K
0.1U_0201_25V6K
@RF@
@RF@
+13.2VB_BATT
12
12
PC709
PC708
10U_0603_25V6M
10U_0603_25V6M
12
12
PC731
PC730
82P_0201_50V8J
0.1U_0201_25V6K
RF@
RF@
12
12
PC758
PC759
100P_0201_25V8J
RF@
RF@
4
12
12
PC742
PC741
10U_0603_25V6M
10U_0603_25V6M
100K_0402_1%
12
PR744
12
PC743
@
ACAV_IN <58,7 9,91>
BGATE_CHG
4700P_0402_25V7K
For IT8010 voltage leakage issue
Compal Electronics, Inc.
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DELL CONFIDENTIAL/PROPRIETARY
C
Title
Title
Title
Size Document Num berRe v
Size Document Num berRe v
Size Document Num berRe v
Date :Sh eetof
Date :Sh eetof
Date :Sh eetof
Compal Electronics, Inc.
Charger
Charger
Charger
LA-G871P
LA-G871P
LA-G871P
Tuesday, March 05, 2019
Tuesday, March 05, 2019
Tuesday, March 05, 2019
D
1.0
1.0
84
84
84
1.0
109
109
109
Page 85
E
PR119
0_0402_5%
12
1
PR120
0_0402_5%
D
2
ALW_PWRGD_3V _5V <11,63>
A
11
B
C
PGOOD_3V
PGOOD_5V
PR102
+13.5VB
BST_3V_R
+3.3V_ALW2
PC102
12
0.1U_0402_25V6
PR106
1
@EMI@
4.7_1206_5%
2
SNUB_3V
1
PC112
2
@EMI@
680P_0402_50V7K
1.5UH_9A_20%_7X7X3_M
1
PJP100
JUMP@
1
2
PAD-OPEN 1x2m~D
1
1
PC100
PC101
27P_0201_25V8
RF@
PC103
2
2
0.1U_0402_25V6
RF@
RF@
RF demand
22
+3.3V_ALW
1
PC131
2
RF@
2200P_0402_50V7K
PR107
100K_0402_5%
1
PGOOD_3V
12
82P_0402_50V8J
+13.5VB_3V
1
PC133
2
RF@
100P_0402_50V8J
2
BST_3V
5
4
3
1
ENLDO_3V5V
11
IN4
EN2
IN3
EN1
13
12
FB_3V
2
BS
IN2
IN1
LX3
LX2
GND4
LDO
NC3
GND3
NC2
OUT
FF
15
14
PC113
1000P_0402_50V7K
1
20
19
18
17
16
21
2
LDO_3V
1K_0402_5%
1
2
LX_3V
3V5V_EN
PU100
6
LX1
7
GND1
8
SY8288BRAC_QFN20_3X3
GND2
9
PG
10
NC1
12
1
PC105
PC134
PC104
2
10U_0603_25V6M
RF@
10U_0603_25V6M
100P_0402_50V8J
PR100
1
0_0603_5%
LX_3V
PR104
0_0402_5%
2
1
PR105
2
1
0_0402_5%
3.3V LDO 150mA~300mA
PC111
4.7U_0402_6.3V6M
12
PR108
2
1
2
+3.3V_RTC_LDO
ENLDO_3V5V
PR103
PL100
2
499K_0402_1%
1
1
2
499K_0402_1%
1
1
PC107
PC106
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
Vout is 3.234V~3.366V
+13.5VB
PJP101
JUMP@
21
PAD-OPEN 1x2m~D
1
PC115
PC141
2
27P_0201_25V8
RF@
33
RF@
RF demand
Not to change short p ad
2
ALWON<58>
44
1
PR114
0_0402_5%
+13.5VB_5V
1
1
PC116
2
2
0.1U_0402_25V6
RF@
2200P_0402_50V7K
1
12
PC139
PC132
2
82P_0402_50V8J
RF@
RF@
100P_0402_50V8J
@
+3.3V_ALW
3V5V_EN
12
12
PC128
PR116
4.7U_0402_6.3V6M
1M_0402_1%
EN1 and EN2 dont't floating
12
PC117
PC140
10U_0603_25V6M
RF@
100P_0402_50V8J
PR113
100K_0402_5%
12
PGOOD_5V
BST_5V
5
4
3
1
12
12
PC118
10U_0603_25V6M
LX_5V
PU102
6
7
8
9
10
LX1
GND1
SYV828CRAC_QFN20_3X3
GND2
PG
NC1
2
IN4
EN2
11
12
BS
IN3
IN2
IN1
20
LX3
19
LX2
18
GND4
17
VCC
16
NC2
21
GND3
LDO
OUT
FF
EN1
15
14
13
+5V_ALW2
12
3V5V_EN
ENLDO_3V5V
PC126
4.7U_0402_6.3V6M
PC127
1000P_0402_50V7K
FB_5V
12
PR111
2
1
0_0603_5%
LX_5V
2
1
PC119
2.2U_0402_6.3V6M
5V LDO 150mA~300mA
PR117
1K_0402_5%
1
BST_5V_R
2
PC114
2
1
0.1U_0402_25V6
12
PR112
@EMI@
SNUB_5V
1
PC125
2
@EMI@
PL101
1.5UH_9A_20%_7X7X3_M
1
4.7_1206_5%
680P_0402_50V7K
2
12
1
PC120
2
22U_0603_6.3V6M
+13.5VB
2
12
1
1
PC108
2
2
22U_0603_6.3V6M
1
PC110
PC109
22U_0603_6.3V6M
PC129
2
22U_0603_6.3V6M
+3.3V_ALWP+3.3V_ALW
12
PC121
22U_0603_6.3V6M
12
1
PC122
22U_0603_6.3V6M
PC124
PC123
2
5VALWP
TDC 7.54 A
Peak Current 7.9A
OCP Current 11.5 A
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
@
22U_0603_6.3V6M
JUMP@
1
JUMP_43X118
JUMP@
1
JUMP_43X118
PC130
22U_0603_6.3V6M
3VALWP
TDC 6.51A
Peak Current 9.3 A
OCP Current 11.5 A
12
PC161
PC162
PC135
@
22U_0603_6.3V6M
22U_0603_6.3V6M
RF@
PJP102
2
2
1
PJP103
2
2
1
12
12
PC163
@
22U_0603_6.3V6M
+3.3V_ALWP
1
1
PC136
2
2
27P_0402_50V8J
RF@
100P_0402_50V8J
+5V_ALW+5V_ALWP
1
PC164
PC137
@
2
22U_0603_6.3V6M
RF@
PC138
100P_0402_50V8J
+5V_ALWP
12
12
PC142
RF@
RF@
100P_0402_50V8J
27P_0201_25V8
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Title
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
Date:Sheeto f
Date:Sheeto f
Date:Sheeto f
Compal Electronics, Inc.
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
LA-G871P
LA-G871P
LA-G871P
85109Tuesday, March 05, 2019
85109Tuesday, March 05, 2019
85109Tuesday, March 05, 2019
E
1.0
1.0
1.0
Page 86
5
DD
4
3
2
1
+13.5VB
PJP202
JUMP@
21
PAD-OPEN 1x2m~D
CC
12
12
PC201
PC200
10U_0603_25V6M
PC230
RF@
10U_0603_25V6M
12
12
PC231
27P_0201_25V8
PC202
RF@
RF@
100P_0201_25V8J
12
12
PC203
RF@
82P_0402_50V8J
12
0.1U_0402_25V6
RF demand
+3.3V_ALW
12
PR205
@0@
12
@0@
0.6V_DDR _VTT_ON<23>
0_0402_ 5%
ILMT_DDR
PR207
0_0402_ 5%
SIO_SLP_S4#<11,17,79,87>
12
PR208
0_0402_ 5%
PR210
0_0402_ 5%
12
The current limit is
set to 8A, 12A or 16A
when this pin is pull
low, floating or pull
high
+1.2V_DDR OCP set 12A
BB
+3.3V_AL W
1U_0201_6.3V6M
PC226
1U_0201_6.3V6M
12
PR209
@
+13.5VB_ DDR
PC206
12
1M_0402_5%
PR212
1M_0402_5%
PU200
10
IN
13
VCC_DDR
2.2U_0402_6.3V6M
12
PC207
ILMT_DDR
SIO_SLP_S4#_R
BYP
14
VCC
4
VTTGND
9
PGND
15
SGND
17
ILMT
1
S5
2
S3
SY8210AQV C_QFN19_4X3
Layout for Pin4,9,15
VDDQSNS
VLDOIN
VTT
VTTSNS
VTTREF
19
OT
18
PG
12
BS
11
LX
16
FB
8
7
6
5
3
BS_DDR
VTTREF_ DDR
PR203
0_0603_ 5%
12
LX_DDR
FB_DDR
+1.2V_DD RP
0.1U_040 2_25V6
BS_DDR_ R
1U_0201_6.3V6M
PC227
12
PC205
12
12
RF@
PR202
4.7_1206 _5%
12
PL201
12
1UH_PCM B063T-1R0MS_1 2A_20%
PC209
22U_060 3_6.3V6M
12
+0.6VSP
1U_0201_6.3V6M
22U_0603_6.3V6M
PC218
12
PC219
VTTGND , PGND seperate GND via
PGNE Cin_cap shape GND via
0.6V_DDR_VTT_ON_R
SGND alone GND
12
PC221
@
0.1U_0402_10V7K
12
12
PC222
@
0.1U_0402_10V7K
Mode S3 S5 VOUT VTT
Normal H H on on
Stadby L H on off
Shutdown L L off off
RF@
PC204
680P_04 02_50V7K
SNUB_DD R
12
330P_0402_50V7K
12
JUMP@
JUMP_43X118
1
102K_0402_1%
12
PR204
PC208
R1
100K_0402_1%
12
PR206
R2
+1.2V_MEM+1.2V_DDRP
PJP200
2
2
1
22U_0603_6.3V6M
22U_0603_6.3V6M
PC210
12
12
+1.2V_D DR
TDC 5.433A
Peak Current 7.761A
OCP Current 12A Fix by IC
+1.2V_DDRP
22U_0603_6.3V6M
PC211
PC212
12
10U_0603_10V6M
22U_0603_6.3V6M
PC214
PC213
12
12
JUMP@
JUMP_43 X39
1
1
0.6Volt +/- 5%
TDC 1.05A
Peak Current 1.5A
OCP Current 2A (fix)
12
PJP201
2
10U_0603_10V6M
PC223
12
PC224
PC228
27P_0201_25V8
RF@
RF@
100P_0402_50V8J
2200P_0402_50V7K
@EMI@
@EMI@
12
12
PC217
PC216
12
12
PC225
RF@
100P_0402_50V8J
100P_0402_50V8J
+0.6V_DDR_VTT+0.6VSP
2
Note: S3 - sleep ; S5 - power off
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
+1.2V_MEN/+0.6V_DDR_VTT
+1.2V_MEN/+0.6V_DDR_VTT
+1.2V_MEN/+0.6V_DDR_VTT
LA-G871P
LA-G871P
LA-G871P
86109Tuesday, March 05, 2 019
86109Tuesday, March 05, 2 019
86109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 87
2
12
@0@
PR404
0_0402_5%
+1VS_VCCIOP+1.0VS_VCCIO
LPM_1VS_VCCIO
17
14
15
16
TP
LPM
PGND1
PGND2
1
VOS
SW1
SW2
SS
AGND
FBS
7
6
5
SS_1VS_VCCIO
FBS_1VS_VCCIO
12
PR427
0_0402_5%
+1VS_VCCIOP
1UH_1277AS-H-1R0N-P2_3.3A_30%
LX_1VS_VCCIO
2
3
12
4
PG
@EMI@
4.7_0603_5%
SNUB_1VS_VCCIO
12
@EMI@
470P_0402_50V7K
PR405
PC401
PL402
12
12
PR412
0_0402_5%
+1VS_VCCIOP
12
@0@
0_0402_5%
JUMP@
JUMP_43X79
1
1
Not to change short pad
PR421
12
PR422
0_0402_5%
PJP401
2
2
12
12
PC407
PC406
22U_0603_6.3V6M
VCCIO_SENSE <17>
VSSIO_SENSE <17>
+1VS_VCCIOP
12
12
PC425
PC426
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
Sense net-name fol low HW site (Need to check)
12
@
10K_0402_1%
12
10K_0402_1%
PR413
PR415
3
+3.3V_ALW
12
10K_0402_1%
12
@
10K_0402_1%
Vin=3 ~17V
+5V_ALW
PR414
VID0_1VS_VCCIO
VID1_1VS_VCCIO
PR416
PC408
0.1U_0402_25V6
@EMI@
PL405
@
3A_Z120_40M_0603_2P
12
JUMP@
12
PAD-OPEN1x1m
12
PC409
100P_0402_50V8J
RF@
Follow WHL RVP
CPU_C10_GATE#<6,17>
RUN_ON<17,58,59,78>
PJP403
12
PC403
10U_0603_10V6M
12
12
PC405
RF demand
47P_0402_50V8J
RF@
SIO_SLP_S0#<9,11,17,66,79>
PR402
12
0_0402_5%
PC404
10U_0603_10V6M
PR429
0_0402_5%
+3.3V_ALW
12
12
PR425
@0@
0_0402_5%
12
12
PR403
1M_0402_1%
PC402
@
EN_1VS_VCCIO
0.1U_0402_25V6
13
PU401
12
11
10
9
PVIN2
PVIN1
SY8057BQDC_QFN16_3X3
AVIN
VID0
8
EN
VID1
VIN_1VS_VCCIO
12
VID0_1VS_VCCIO
VID1_1VS_VCCIO
1.0V_PRIM_PWRGD <58>
+3.3V_ALW
BST_1.05VALWP_RBS T_1.05VALWP
4
PC304
0.1U_0402_25V6
1 2
FB_1.05VALWP
PR303
RF@
4.7_1206_5%
12
PL301
0.68UH_7.9A_20%_5X5X3_M
12
SNUB_1.05VALWP
12
PR306
22.1K_0402_1%
12
PR311
29.4K_0402_1%
PC302
RF@
680P_0402_50V7K
1 2
12
12
+1.05VALWP
12
PC307
330P_0402_50V7K
PR308
1K_0402_5%
PJP302
JUMP@
2
1
+1.0V_PRIM
2
1
JUMP_43X118
+1.05VALWP
12
PC308
PC309
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
12
PC310
12
PC315
PC316
PC311
RF@
RF@
100P_0402_50V8J
100P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
5
PR313
12
100K_0402_5%
PC350
@
1 2
+13.5VB
DD
PJP301
JUMP@
21
PAD-OPEN 1x2m~D
PCH_PRIM_EN<11,78,87>
The current limit is set to 6A, 9A or 12A when this pin
is pull low, floating or pull high
12
PC317
27P_0201_25V8
RF@
PR312
22K_0402_1%
12
1M_0402_1%
+3.3V_ALW
12
@0@
PR307
0_0402_5%
12
@0@
PR310
0_0402_5%
12
PC318
82P_0201_50V8J
RF@
PR302
ILMT_1.05VALWP
PC301
RF@
12
12
82P_0201_50V8J
EN_1.05VALWP
12
PC360
0.1U_0402_25V6
12
PC303
100P_0402_50V8J
RF@
+3.3V_ALW
12
PC305
10U_0603_25V6M
PU301
+13.5VB_1.05VALWP
2
IN1
3
12
IN2
4
IN3
PC306
5
10U_0603_25V6M
IN4
7
GND1
8
GND2
18
GND3
11
EN
13
ILMT
15
BYP
SY8286RAC_QFN20_3X3
PC314
PC312
1 2
1 2
1U_0201_6.3V6M
1U_0201_6.3V6M
+1.0V_PRIM
TDC 3.642A
Peak Current 5.203A
OCP Current 9 A Fix by IC
TYP MAX
Choke DCR 11.0mohm , 12.0mohm
0.022U_0402_25V7K
9
PG
BS
LX1
LX2
LX3
FB
VCC
NC1
NC2
NC3
PAD
PR304
0_0603_5%
12
1
LX_1.05VALWP
6
19
20
14
VCC_1.05VALWP
17
10
12
PC313
12
2.2U_0402_6.3V6M
16
21
1
VID1 LOGIC
LPM LOGICOUTPUT VOLTAGE
0
SY8057BQ DC10
X
0
1
1
1
1
1
+1.0VS_VCCIO
TDC 2.1 A
Peak Current 4 A
OCP Current 6 A Fix by IC
TYP MAX
Choke DCR 48.0mohm
VID0 LOGIC
X
0
1
0
11.05
0(LPM)
0.80
0.95
1.00
+1.8V_PRIM
TDC 1.56 A
Peak Current 2.229 A
OCP Current 3.2 A f i x by I C
CC
+3.3V_ALW
PCH_PRIM_EN<11,78,87>
BB
AA
PL502
@
3A_Z120_40M_0603_2P
12
PJP501
JUMP@
12
PAD-OPEN1x1m
PR504
12
0_0402_5%
1M_0402_1%
Note :
When design Vin=5V, please stuff snubber
to prevent Vin d amage
JUMP@
12
+3.3V_ALW
PAD-OPEN1x1m
Downsize from 0603 to 0402
SIO_SLP_S4#<11,17,79,86>
intel needs PD 100K for PCH GLITCH ISSUE MITIGATION
(pull-down on HW site )
1.0V_PRIM_PWRGD
PR505
@
PJP505
PR513
12
0_0402_5%
@
1M_0402_1%
VIN_1.8VALW
12
PR514
VIN_2.5V_MEM
12
12
12
PR314
0_0402_5%
12
12
PC505
@
.1U_0402_16V7K
PC514
4.7U_0402_6.3V6M
22U_0603_6.3V6M
EN_1.8VALW
12
12
PC530
PC517
@
4.7U_0402_6.3V6M
EN_2.5V_MEM
PC513
@
.1U_0402_16V7K
PU501
4
LX
IN
5
GND
PG
6
EN
FB
RT8097ALGE_SOT23-6
PU503
EM1109V-AD_DFN3308-8_3X3
9
GND2
OUT
8
IN
NC1
7
NC3
ADJ/NC
6
NC2
GND1
5
EN
LX_1.8VALW
3
2
1
1
2
3
4
+1.8VALWP
PAD-OPEN1x1m
Imax= 2A, Ipeak= 3A
FB=0. 6V
PL501
1UH_1277AS-H-1R0N-P2_3.3A_30%
12
12
PR502
RF@
4.7_0603_5%
20K_0402_1%
SNUB_1.8VALW
12
PC506
RF@
680P_0402_50V7K
FB_1.8VALW
PR506
10K_0402_1%
Vout=0.6V* (1+ Rup/Rdown)
+2.5V_MEM
TDC 0.645A by power budget
AP7361 U-DFN3030-8 Pd limit=1.7W
Peak loading=0.921A.
Pd=(3.3-2.5)*0.921=0.7368W < 1.7W
OCP Current 1.5 A f i x by I C
+1.0V_PRIM_CORE
TDC 2.237 A
Peak Current 3.195A
OCP Current 6.8 A Fix by IC
TYP MAX
Choke DCR 48.0mohm
X
0
1
0
11.05
0.75(LPM)
0.9
0.95
1.00
X
0
1
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
+1VALWP/VCCIO/PRIM_CORE/1.8V/2.5V
+1VALWP/VCCIO/PRIM_CORE/1.8V/2.5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
+1VALWP/VCCIO/PRIM_CORE/1.8V/2.5V
Size Document NumberRe v
Size Document NumberRe v
Size Document NumberRe v
LA-G871P
LA-G871P
LA-G871P
87109Tu esday, March 05, 2019
87109Tu esday, March 05, 2019
Date:Sheetof
Date:Sheetof
Date:Sheetof
1
87109Tu esday, March 05, 2019
1.0
1.0
1.0
Page 88
5
4
3
2
1
+1.0V_VCCST
12
PR601
PR604
@
75_0402_ 1%
45.3_040 2_1%
+3.3V_RUN
PCH_PWROK<11>
IMVP_VR_ON<59>
PR620 0_0402_5%
I_SYS<58,84>
PSYS R on CPU site
PH603
470K_0402_5%_B25/50 4700K
2200P_0402_50V7K
PH603 near PU612 MOS Side
VCC_SENSE_GT<16>
VSS_SENSE_GT<16>
4
12
PR605
100_0402 _1%
PR616 0_0402_5%
12
PR693
11.8K_0402_1%
12
IMON_B_IA
NTC_B_IA
COMP_B_IA
FB_B_IA
ISUMN_B_IA
FCCM_B_IA<89>
PWM1_B_IA<89>
PWM2_B_IA<89>
12
PR647
27.4K_0402_1%
12
PC629
12
PC639
1500P_0402_50V7K
12
12
PR648
1.91K_0402_1%
PC651
@
12
330P_0402_50V7K
PC654
12
0.01UF_0402_25V7K
PC602
49.9_0402_1%
0.1U_0402 _25V6
12
12
PR6250_0402_5%
12
PR62610_0402_1%
PR612 1.91K_0402_1%
12
12
PR614 0_0402_5%
12
PU602
1
PSYS_CPU_CO RE
PSYS
2
IMON_B
3
NTC_B
4
COMP_B
5
FB_B
6
RTN_B
7
ISUMP_B
8
ISUMN_B
9
ISEN1_B
10
ISEN2_B
41
AGND
PC625
330P_0402_50V7K
12
PR629
86.6K_0402_1%
12
12
PR635
10K_0402_1%
PR639
3.09K_0402_1%
12
PC636
33P_0402_50V8J
12
PR645
316_0402_1%
12
PR618
VR_HOT#_CPU_CORE
VR_READY_CPU_CORE
VR_ENABLE_CPU_CORE
40
39
38
VR_HOT#
VR_READY
VR_ENABLE
PWM2_B
PWM1_B
FCCM_B
13
12
11
12
PR650
12
PC647
680P_0402_50V7K
12
PC653
@
12
100K_0402_5%
12
VIN_CPU_CO RE
VCC_CPU_CO RE
PROG2_CPU_CORE
PROG1_CPU_CORE
SVID_ALERT#_PWR_CPU
SVID_DAT_PWR_CPU
SVID_CLK_PWR_CPU
35
37
36
34
33
32
31
VIN
SDA
VCC
SCLK
PROG1
PROG2
ALERT#
PWM_C
FCCM_C
ISUMN_C
ISUMP_C
RTN_C
COMP_C
IMON_C
PWM_A
FCCM_A
ISUMN_A
ISUMP_A
RTN_A
COMP_A
NTC_A
IMON_A
FB_A
20
19
18
16
15
14
17
ISL95857CHRTZ-T_TQFN40_5X5
FB_A_GT
NTC_A_GT
COMP_A_GT
IMON_A_GT
ISUMN_A_GT
2K_0402_ 1%
4.42K_0402_1%
12
@
20M_0402_5%
0.082U_04 02_16V7K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
VIDSCLK<15>
@
1200P_0402_50V7K
12
PC621
820P_0402_25V7
0.082U_04 02_16V7K
VIDALERT_N<15>
VIDSOUT<15>
PC617
12
12
PR613
@
97.6K_0402_1%
12
PC613
330P_0402_50V7K
@
316_0402_1%
12
PR622
@
2.49K_0402_1%
12
12
12
PR621
PR623
2K_0402_1%
DD
CC
PROCHOT#<14,58,84>
PH601 near PU610 MOS Side
470K_0402_5%_B25/50 4700K
VCC_SENSE_IA<15>
VSS_SENSE_IA<15>
12
PC605 47P_0402_50V8J
PH601
12
12
PR631
27.4K_0402_1%
PC614
2200P_0402_50V7K
12
PC618
@
12
330P_0402_50V7K
PC619
12
0.01UF_0402_25V7K
12
PR617
4.3K_0402_1%
12
PC616
@
68P_0402_50V8J
12
PR678
100_0402_1%
12
PR610
10K_0402_1%
PC620
@
Local sense put on HW site
ISUMP_IA<89>
@
20M_0402_5%
ISUMN_IA<89>
BB
PR658
12
PR628
12
12
4.99K_040 2_1%
12
12
PR633
12
PH602
10K_0402 _5%_B25/50 425 0K
PC641
PH602 near PL610 Choke Side
.1U_0402_ 16V7K
11K_0402 _1%
PC635
U42@
0.022U_0402_16V7K
12
PC638
U42@
0.022U_0402_16V7K
12
12
PC624
@
0.022U_04 02_16V7K
ISEN1_IA<89>
ISEN2_IA<89>
PR632
PC626
1K_0402_1%
@
0.1U_0402 _25V6
12
@
523_0402_1%
12
ISEN1_IA
ISEN2_IA
PC627
2200P_0402_50V7K
PR638
PR634
U22@
0_0402_5%
12
12
PR615
U22@
0_0402_5%
12
Not to change short pad
+5V_ALW
Not to change short pad
Local sense put on HW site
AA
5
12
PR602
12
0_0402_5%
PR603
12
12
PR608
PR611
9.31K_0402_1%
FB_C
PR657
PR653
0_0402_5%
12
PC603
PC604
4.7U_0402 _6.3V6M
1U_0402_ 25V6K
PWM_C_SA
30
FCCM_C_SA
29
ISUMN_C_SA
28
27
26
FB_C_SA
25
COMP_C_SA
24
IMON_C_SAPWM_SA
23
22
PWM_A_GT <89>
21
FCCM_A_GT <89>
12
12
PC630
PR644
PC642
0.068U_0402_16V7K
12
PC646
2200P_0402_25V7K
12
PR656
11K_0402_1%
12
12
12
ISUMP_GT <89>
3
PR640
2200P_04 02_50V7K
12
1K_0402_ 1%
PC645
PH605
PH605 near PL612 Choke Side
10K_0402_5%_B25/50 4250K
+5V_ALW
+13.5VB_CPU
PC611
0.22U_0402_25V6K
365_0402 _1%
12
.1U_0402_ 16V7K
ISUMN_GT <89>
12
12
PWM_C_SA
PC628
BST_SA
PR606
0_0402_5%
12
33P_0402 _50V8J
12
PC643
330P_040 2_50V7K
BST_SA_R
PU614
ISL95808HRZ-TS2778_DFN8_2X2~D
1
UGATE
2
BOOT
3
PWM
4
GND
TP
9
12
PR630
2.49K_040 2_1%
12
4700P_04 02_25V7K
PC631
12
12
PR651
39.2K_040 2_1%
PR652
@
12
@
+13.5VB_VCCSA
UG_SA
PR619 2. 2_0603_5%
12
8
PHASE
7
FCCM
6
VCC
5
LGATE
+5V_ALW
12
PR636 634_0402_1%
12
PC632
1000P_0402_50V7K
PR646
12
316_0402_1%
PR649
12
1.62K_0402_1%
2K_0402_ 1%
PC601
680P_040 2_50V7K
2
FCCM_SA
LG_SA
12
PR679
0_0402_5%
12
PC685
FCCM_C_SA
4.7U_0402 _6.3V6M
12
1K_0402_1%
PC640
12
2200P_0402_50V7K
10
PR641
Low noise MLCC
4
D1_3
D1
S2_1
5
3
D1_2
S2_2
6
VCC_SA U42
TDC 4.0A
Peak Current 6A
OCP current 10A
Choke DCR 6.2 m ohm
PJP603
JUMP@
12
PAD-OPEN1x1m
+13.5VB
+13.5VB_VCCSA
12
12
PC608
PC612
10U_0603 _25V6M
10U_0603 _25V6M
2
1
PQ614
AONH36334 _DFN3X3A8-10
G1
D1_1
LX_SA
9
D2/S1
G2
S2_3
8
7
12
.1U_0402_16V7K
12
@
0.082U_0402_16V7K
PC637
PC644
PC650
RF@
12
PR627
4.7_1206 _5%
SNUB_SA
12
PC622
680P_040 2_50V7K
RF@
0.033U_04 02_25V7K
12
12
PC610
PC609
82P_0201 _50V8J
27P_0201 _25V8
RF@
RF@
PL614
0.47UH_NA_12.2A_20%
12
12
ISUMP_SA
PC633
4700P_04 02_25V7K
4
3
PR624
3.65K_0603_1%
1
+VCC_SA
2
ISUMN_SA
ISUMP_SA
12
PR642
12
2.61K_040 2_1%
PR643
12
10KB_0402 _5%
11K_0402 _1%
PH604
ISUMN_SA
PH604 near PL614 Choke Side
VSS_SENSE_SA <17>
PC649
0.01UF_0402_25V7K
12
12
@
PC652
330P_0402_50V7K
12
VCC_SENSE_SA <17>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document NumberRe v
Size Document NumberRe v
Size Document NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheet
Compal Electronics, Inc.
CPU_CORE
CPU_CORE
CPU_CORE
LA-G871P
LA-G871P
LA-G871P
88109Tuesday, March 05, 2019
88109Tuesday, March 05, 2019
88109Tuesday, March 05, 2019
1
o f
1.0
1.0
1.0
Page 89
1
21
+13.5VB_CPU+13.5VB_VCCGT
PC670
EMI@
680P_04 02_50V7K
SNUB_GT
1 2
PL612
0.15UH_MM D-06CZER15MEX 5L__35A_2 0%
4
3
12
PR661
3.65K_0 603_1%
<88>
ISUMP_GT
1
+VCC_GT
2
<88>
ISUMN_GT
PC666
RF@
PC663
1 2
0.22U_04 02_25V6K
12
BST_GT_R
PR665
3.9_060 3_1%
2
VCC_GT (U42)
+13.5VB_VCCGT
12
12
PC667
0.1U_0402_25V6
RF@
2200P_0402_50V7K
12
12
PC692
PC691
27P_0201_25V8
82P_0201_50V8J
RF@
RF@
TDC 18A
Peak Current 31A
OCP current 37.2A
Choke DCR 0.9 +-5%m ohm
PJP602
JUMP@
PAD-OPEN 1x2m~D
RF demand
PR669
EMI@
4.7_120 6_5%
12
BST_GT
VCC_GT
FCCM_GT
PWM_GT
PU612
10
PGND1
9
VIN2
8
VIN1
7
PHASE
6
NC1
5
BOOT
4
AGND1
3
VCC
2
FCCM
1
PWM
FDMF3035_ PQFN31_5X5
PGND2
PVCC
AGND2
LX_GT
11
SW1
12
SW2
13
GL1
14
15
16
NC2
17
NC3
19
GL2
18
+5V_ALW
12
PC668
4.7U_0402_6.3V6M
+VCC_CORE
<88,89>
ISEN2N_IA
12
U42@
10_0402 _1%
ISUMN_IA
3
+VCC_CORE
PR673
<88,89>
+5V_ALW
PC675
10U_0603_25V6M
Low noise MLCC
12
PC674
12
PR680
1_0603_ 5%
12
12
12
10U_0603_25V6M
PC687
0.1U_0402_25V6
FCCM_A_GT<88>
PWM_A_ GT< 88>
12
PC664
PC665
10U_0603_25V6M
10U_0603_25V6M
12
PC669
4.7U_0402_6.3V6M
PR662
0_0402_ 5%
12
PR664
0_0402_ 5%
12
5
+13.5VB_CPU
RF@
12
PC689
PU610
10
PGND1
9
VIN2
8
VIN1
7
PHASE
6
NC1
5
BOOT
4
AGND1
3
VCC
2
FCCM
1
PWM
FDMF3035_ PQFN31_5X5
10
BST2_IA
VCC2_IA
PWM2_I A
RF@
12
12
PC690
27P_0201_25V8
82P_0201_50V8J
SW1
SW2
GL1
PGND2
PVCC
NC2
NC3
GL2
AGND2
PU613
U42@
PGND1
9
VIN2
8
VIN1
7
PGND2
PHASE
6
NC1
5
BOOT
4
AGND1
3
VCC
2
FCCM
1
AGND2
PWM
FDMF3035_ PQFN31_5X5
PVCC
1
+
PC606
2
100U_D_20VM_R55M
11
12
13
14
15
16
17
19
18
11
SW1
12
SW2
13
GL1
14
15
16
NC2
17
NC3
19
GL2
18
RF@
Low noise MLCC
0.22U_04 02_25V6K
BST1_IA_R
12
PC673
U42@
10U_0603_25V6M
12
PC677
U42@
0_0402_ 5%
12
0_0402_ 5%
12
RF@
PC659
PC655
1 2
12
PR660
3.9_060 3_1%
Low noise MLCC
PC671
U42@
1 2
0.22U_04 02_25V6K
12
BST2_IA_R
U42@
PR672
3.9_060 3_1%
4.7U_0402_6.3V6M
PR671
PR692
12
PC660
0.1U_0402_25V6
2200P_0402_50V7K
BST1_IA
VCC1_IA
FCCM1_IA
PWM1_I A
FCCM2_IA
12
12
DD
CC
BB
+5V_ALW
PC682
10U_0603_25V6M
PC656
PR688
1_0603_ 5%
12
FCCM_B_IA<88 ,89>
PWM1_B _IA<88>
12
PC683
U42@
10U_0603_25V6M
12
10U_0603_25V6M
PC684
U42@
+5V_ALW
PC657
12
12
10U_0603_25V6M
U42@
1_0603_ 5%
12
FCCM_B_IA<88 ,89>
PWM2_B _IA<88>
10U_0603_25V6M
PC686
12
12
0.1U_0402_25V6
PC676
PC672
U42@
10U_0603_25V6M
PC688
U42@
PR691
12
PC658
10U_0603_25V6M
4.7U_0402_6.3V6M
PR659
0_0402_ 5%
12
PR687
0_0402_ 5%
12
12
0.1U_0402_25V6
4
+13.5VB
PJP601
JUMP@
12
PAD-OPEN 4x4m
PL602
@EMI@
12
9A Z80 1 0M 1812_2P
1
+
PC607
2
100U_D_20VM_R55M
LX1_IA
+5V_ALW
LX2_IA
PR663
RF@
PC661
4.7U_0402_6.3V6M
12
+5V_ALW
12
PC697
U42@
4.7U_0402_6.3V6M
VCC_core (U42)
TDC 48A
Peak Current 70A
OCP current 84A
Choke DCR 0.9 +-5%m ohm
Follow as below
WHL U42 15W, Core (IA) VR TDC value has been increased from 42A to 48A.
This new value will be reflected in WHL PDG/Power Map document next release
in W W13 (IBP# 575412 ).
PL610
0.15UH_MM D-06CZER15MEX 5L__35A_2 0%
4
1
2
PR667
ISEN1_IA<8 8>
ISEN2N_IA
U42@
3.65K_0 603_1%
12
ISUMP_IA
ISEN1P_IA
U42@
<88,89>
PR674
ISEN2_IA<88 >
ISEN1N_IA
3
12
100K_04 02_1%
12
PR670
@
100K_04 02_1%
U42@
ISEN2P_IA
<88,89>
12
3.65K_0 603_1%
12
4.7_1206_5%
SNUB1_IA
12
ISUMP_IA
PC662
RF@
680P_0402_50V7K
12
PR676
4.7_1206_5%
RF@U42@
SNUB2_IA
12
PC678
680P_0402_50V7K
RF@U42@
ISEN1N_IA
12
PR668
100K_04 02_1%
PR666
10_0402 _1%
ISUMN_IA
PL613
0.15UH_MM D-06CZER15MEX 5L__35A_2 0%
4
1
2
3
PR675
U42@
12
100K_04 02_1%
PR677
@
12
AA
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+VCC_GT Place on CPU:
22U_0603 *23 pcs
1U_0201 *11 pcs
330u_D3 *2 pcs
1
2
22U_0603_6.3V6M
1U_0201_6.3V6M
1
12
PC1112
22U_0603_6.3V6M
1
2
2
PC1114
PC1113
22U_0603_6.3V6M
PC1115
22U_0603_6.3V6M
22U_0603_6.3V6M
RF demand
12
1
12
12
2
PC1071
PC1072
33
47U_0603_6.3V6M
12
PC1089
1U_0201_6.3V6M
PC1073
47U_0603_6.3V6M
47U_0603_6.3V6M
1
2
1
+
PC1090
2
1U_0201_6.3V6M
1
1
2
2
PC1075
PC1074
47U_0603_6.3V6M
47U_0603_6.3V6M
1
1
+
+
PC1091
PC1092
2
2
470U_D2_2VM_R4.5M
330U_D2_2.5VM_R9M
1
12
PC1076
47U_0603_6.3V6M
1
+
PC1093
2
220U_D7_2VM_R4.5M
12
12
12
2
PC1078
PC1077
47U_0603_6.3V6M
PC1094
@
220U_D7_2VM_R4.5M
PC1079
47U_0603_6.3V6M
1
+
PC1095
2
330U_D2_2.5VM_R9M
PC1080
47U_0603_6.3V6M
47U_0603_6.3V6M
12
1
PC1096
2
RF@
100P_0201_25V8J
12
1
1
2
PC1082
PC1081
22U_0603_6.3V6M
22U_0603_6.3V6M
@
@
1
PC1097
PC1098
2
27P_0201_25V8
RF@
RF@
100P_0201_25V8J
12
1
2
PC1083
22U_0603_6.3V6M
@
12
PC1099
82P_0201_50V8J
RF@
2
PC1084
PC1085
22U_0603_6.3V6M
22U_0603_6.3V6M
@
@
1
12
PC1181
PC1180
2
27P_0201_25V8
27P_0201_25V8
RF@
RF@
1
1
2
2
PC1086
22U_0603_6.3V6M
@
PC1088
PC1087
22U_0603_6.3V6M
22U_0603_6.3V6M
@
@
+VCC_SA
12
1
2
1
12
2
PC1151
PC1152
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
2
PC1153
22U_0603_6.3V6M
1
2
2
PC1155
PC1154
22U_0603_6.3V6M
22U_0603_6.3V6M
1
12
2
PC1156
22U_0603_6.3V6M
PC1158
PC1157
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
2
2
PC1159
22U_0603_6.3V6M
PC1161
PC1160
22U_0603_6.3V6M
22U_0603_6.3V6M
RF demand
1
1
PC1166
PC1167
2
2
RF@
RF@
100P_0201_25V8J
100P_0201_25V8J
44
RF demand
12
12
PC1169
PC1168
27P_0201_25V8
82P_0201_50V8J
RF@
RF@
+VCC_SA Place on CPU
22U_0603 *11 pcs
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
Title
Size
Size
Size
Date:Sheetof
Date:Sheetof
Date:Sheetof
Compal Electronics, Inc.
Charger UVP/VCORE OVP
Charger UVP/VCORE OVP
Charger UVP/VCORE OVP
Document NumberR ev
Document NumberR ev
Document NumberR ev
LA-G871P
LA-G871P
LA-G871P
1
91109Tuesday, March 05, 2019
91109Tuesday, March 05, 2019
91109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 92
1
@ESDWL@
3
3
BSMB_WP_INT# <58>
2
+19.5VB_WC_SDC
WP_GPU_SMDAT <58>
WP_GPU_SMCLK <58>
+19.5VB_WC_C
@WL@
100_0402_5%
12
12
@WL@
100_0402_5%
12
@WL@
100_0402_5%
12
@WL@
0_0402_5%
3
PR954
PR955
PR956
PD901
@ESDWL@
L03ESDL5V0CG3-2_SOT-523-3
PR953
@EMIWL@
FBMJ4516HS720NT_2P
@EMIWL@
FBMJ4516HS720NT_2P
1
1
2
2
12
12
3
+3.3V_ALW
PL901
PL902
3
PD902
L03ESDL5V0CG3-2_SOT-523-3
1
1
2
2
+19.5VB_WC_SDC
5
DD
CC
4
Wireless Power Connector
WC1
@CONN@
12
PC906
2200P_0402_50V7K
@EMIWL@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
GND1
12
GND2
DEREN_40-42251-01001RHF
WP_SMBCLK_C
WP_SMBDAT_C
WP_INT_C
BB
AA
GND
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
Title
Size
Size
Size
Date:Sheetof
Date:Sheetof
Date:Sheetof
Compal Electronics, Inc.
Reserve for PWR
Reserve for PWR
Reserve for PWR
Document NumberR ev
Document NumberR ev
Document NumberR ev
LA-G871P
LA-G871P
LA-G871P
1
92109Tuesday, March 05, 2019
92109Tuesday, March 05, 2019
92109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 93
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DD
CC
4
3
2
1
Reserve
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AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
Date :Sheetof
Date :Sheetof
Date :Sheetof
Compal Electronics, Inc.
Reserve for PWR
Reserve for PWR
Reserve for PWR
LA-G871P
LA-G871P
LA-G871P
1
93109Tuesday, March 05, 2019
93109Tuesday, March 05, 2019
93109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 94
5
DD
CC
4
3
2
1
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AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
5
4
3
2
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
Reserve for PWR
Reserve for PWR
Reserve for PWR
LA-G871P
LA-G871P
LA-G871P
94109Tuesday, March 05, 2 019
94109Tuesday, March 05, 2 019
94109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 95
5
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CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
5
4
3
2
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date :Sheeto f
Date :Sheeto f
Date :Sheeto f
Compal Electronics, Inc.
Reserve for PWR
Reserve for PWR
Reserve for PWR
LA-G871P
LA-G871P
LA-G871P
95109Tuesday, March 05, 2 019
95109Tuesday, March 05, 2 019
95109Tuesday, March 05, 2 019
1
1.0
1.0
1.0
Page 96
5
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CC
4
3
2
1
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AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
Title
Size
Size
Size
Date:Sheetof
Date:Sheetof
Date:Sheetof
Compal Electronics, Inc.
Reserve for PWR
Reserve for PWR
Reserve for PWR
Document NumberRe v
Document NumberRe v
Document NumberRe v
LA-G871P
LA-G871P
LA-G871P
1
96109Tuesday, March 05, 2019
96109Tuesday, March 05, 2019
96109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 97
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
Title
Size
Size
Size
Date:Sheetof
Date:Sheetof
Date:Sheetof
Compal Electronics, Inc.
Reserve for PWR
Reserve for PWR
Reserve for PWR
Document NumberR ev
Document NumberR ev
Document NumberR ev
LA-G871P
LA-G871P
LA-G871P
1
97109Tuesday, March 05, 2019
97109Tuesday, March 05, 2019
97109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 98
5
DD
CC
4
3
2
1
Reserve
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
Title
Size
Size
Size
Date:Sheetof
Date:Sheetof
Date:Sheetof
Compal Electronics, Inc.
Reserve for PWR
Reserve for PWR
Reserve for PWR
Document NumberR ev
Document NumberR ev
Document NumberR ev
LA-G871P
LA-G871P
LA-G871P
1
98109Tuesday, March 05, 2019
98109Tuesday, March 05, 2019
98109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 99
5
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1
U42
PC626 U42@
PR613 U42@
PR621 U42@
PC624 U42@
DD
0.1U_0402_25V6
PR638 U42@
523_0402_1%
97.6K_0402_1%
PR622 U42@
2.49K_0402_1%
316_0402_1%
PC616 U42@
68P_0402_50V8J
0.022U_0402_16V7K
PC617 U42@
1200P_0402_50V7K
U22
PC626 U22@
0.047U_0402_25V7K
PR638 U22@
422_0402_1%
CC
PR613 U22@
84.5K_0402_1%
PR622 U22@
1.65K_0402_1%
PR621 U22@
316_0402_1%
PC616 U22@
33P_0402_50V8K
PC624 U22@
0.033U_0402_25V7K
PC617 U22@
1200P_0402_50V7K
BB
AA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
Title
Size
Size
Size
Date:Sheetof
Date:Sheetof
Date:Sheetof
Compal Electronics, Inc.
BOM Option
BOM Option
BOM Option
Document NumberR ev
Document NumberR ev
Document NumberR ev
LA-G871P
LA-G871P
LA-G871P
1
99109Tuesday, March 05, 2019
99109Tuesday, March 05, 2019
99109Tuesday, March 05, 2019
1.0
1.0
1.0
Page 100
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1
Version Change List ( P. I. R. List )
Item
Page#
Date
Issue
Description
P08 9
1
P08 2
P08 6
2
DD
P08 8
P08 9
06/ 04
06/ 08
07/ 02
3
P08 8
4
P09 9
07/ 13
Fairchild & AOS Dr .MOS vendor rem ove PVCC reserv ed resistors
Change to common P/N
Merion Top side Z-height limitati on 07/ 12P0 90
CPU intel validation fo rm test tune value
Delete reserve d PR686/PR689/P R681 on PVCC side
1. PC624 change to SE07 6223K80 ( S CER CAP 0.022U 16V K X7R 0402)
2. PC804 change to SE074221K8 0 (S CE R CAP 220P 50V K X7R 0402)
3. PC633 change to SE075472K8 0 (S CER CAP 4700P 25V K X7R 0402)
4. PL2 01 ch ange t o SH0 0000YE00 (common P/N)
5. PL614 change to SH00001 ED00 (common P/ N)
1. Un-stu ff PC109 4 (@)
2. Add stu ff PC1095 - 3 30uF ( Bottom sid e)
1. Change the PR636 from 665 Ohm to 634 Ohm. - (VCCSA R i)
-> SD00 000Z280, S R ES 1/16W 634 +-1% 0402
2. Change the PR640 from 374 Ohm t o 365 O hm. - ( VCCGT Ri)
-> SD03 4365080, S R ES 1/16W 365 +-1% 0402
3. Change the PC646 from 0 .047uF t o 0.00 22uF. - (VC CGT R C)
-> SE07 5222K80, S C ER CAP 2200P 25V K X7R 0402
4. Change the PC642 from 0 .033uF t o 0.068u F. - (VCCGT RC)
-> SE00 0003J80, S C ER CAP 0.068 U 16V K X7R 0402
5. Change the PC62 1 from 680pF to 820pF. - (VCCIA F B RC).
-> SE0000089 80, S CER C AP 820P 25V K X7R 0402
6. Change the PR611 from 1 .87kOhm to 9.31k Ohm. - (PROG2)
-> SD 034931180, S RES 1/16W 9.31K +-1% 0 402
Solution
Description
Rev.
X01
X01
X01
X01
5
P08 3
07/ 20
6
CC
7
P08 208 /1 0
8
9
P08 2
10
11
12
P08 3
P08 2
P08 3
08/ 15
08/ 15
08/ 15P0 87
13
All
14
BB
08/ 20
08/ 30
15
16
17
P08 2
18
AA
08/ 22
09/ 11
08/ 22P0 82
Modify 1 barrel / 1 Ty pe-C External LDO circuit for Cha rger UVP & VCORE O VP circu it desig n
ESD requestP08 2
LPS fu nction test fail on G3 mode . Need to return LDO(P U2) de sign circuit.P08 207 /3 0
PQ8 gate for Back drive issueAdd R/C delay PR865/PC865 : 100K(SD028100380) and 0.1uF _0402_25V(SE000 00G880)P08 207 /3 0
LM393 resistor val ue fine tune
Check and m odify connector P/N for ME request
R/C delay fine tune for WH L bring up sequence
RF requ est
RTC issue for HW requestP08 308 /2 1
Charger UVP & VCO RE OV P circ uit
LPS functi on modi fy
PD1, P D2, P D4 cha nge t o SCA0 0002A00 for ESD demand
Need stuf f ite m :
PU2/ PC10/ PC11/ P R47/ PR33/ PR27/ P R17/ PD800 / PR80 6 / PR809/ PR832/ PR859 / P R810 / PR813
Need delete l ocation : PR48 / PR34 / PR35 / PR36 / PR37/ P R847 / PR848 / PR849/ PR 850
Need un-stu ff item : PR851 / PR860 / PR852
PR800 change to 422K_0402_1% ( SD034422380)
PR815 change to 37.4K_0402_1% (SD034374280)
PR832 change to 102K_0402_1% ( SD028102380)
PR843 change to 37.4K_0402_1% (SD034374280)
PR831 c hange t o 1M_ 0402_1% (SD034100480)
PR842 change to 191K_0402_1% ( SD034191380)
PR651 value change to 39.2K for ISL 95857CISL95857 CPU Co ntroller change to Rev.C08/ 10P0 88
Re-define the RTC/DCIN/Battery con nector from @ to CONN@.Follow Sch ematic na ming ru le
1. Add un-stuff PR870 and p ull up source i s +20V_VBUS_DC_ SS ; 499K_0402_ 1% (SD03449938 0)
2. Modify PR831 value to 499K_0402_1 % (SD034499380) and pull up so urce change to +20V_TBTA_VBUS_1
3. Modify PR842 v alue to 97.6K_0402_1% (SD034976280)
4. PC811 change to SE00000UD00 (10U 6.3V M X5 R 0402 )
1. PD800 change to un-stuf f
2. Add PR866 0_0402_ 5%
3. Ad d PD 803 ( BAT54CW_SOT323 -3)
4. Add un-s tuff PR868 0_0603_5%
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
SizeDocument NumberRe v
SizeDocument NumberRe v
SizeDocument NumberRe v
Date:Sheetof
Date:Sheetof
Date:Sheetof
Compal Electronics, Inc.
PWR P.I.R
PWR P.I.R
PWR P.I.R
100109Tuesday, March 05, 2019
100109Tuesday, March 05, 2019
100109Tuesday, March 05, 2019
1
1.0
1.0
1.0
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