DELL Cedar, Janus Block Diagram

5

Project code:4PD00I010001

Cedar/Janus Block Diagram

PCB P/N: 13302-1 Revision: A00

D D

GPU

VRAM(DDR3L) *4

2GB

78,79

DDR3L

DIS only

VGA Conn. (Janus only)

C C

14.0"/15"/17" LCD (16:9)

Touch Panel

B B

29

Combo Jack

MIC_IN/GND

HP_R/L

2CH SPEAKER (2CH 2W/4ohm)

29

VGA

HDMI V1.4a (Cedar only)

52

LPC debug port

NVIDIA N15V-GM-S-A2 GB2-64 (23x23) 25W

DP/VGA Converter (Janus only)

RTD2168

54

Camera

Digital MIC

52

HDA CODEC

Realtek

ALC3234

27

65

4

73,74,75,76,77

HDMI

eDP

USB2.0 x 1

HDA

LPC BUS

PCIE x 4

55

3

Intel CPU

DDR3L 1333/1600MHz Channel A

Broadwell ULT

28W (UMA) 15W (DIS)

LAN

WPT-LP

8 USB 2.0/1.1 ports

4 USB 3.0 port s

High Definition A udio

DP

4 SATA ports

8 PCIE ports

LPC I/F

ACPI 4.0a

PCIE x 1

USB2.0 x 1

10/100 & 10/100/1000 co-lay

RealTek Cedar:(10/100)RTL8106 E Janus:(10/100/1000)RTL8111G

WLAN

802.11a/b/g/n BT V4.0 combo

Left side

USB1(USB3.0)

USB3.0 x 1

Left side

USB2.0 x 1

USB2(USB2.0)

Right side

USB3(USB2.0)

CardReader

Realtek RTS5170

34,35

2

58

DDR3L 1333/1600

SODIMM A

30

IO Board

SD Card Slot

12

RJ45 Conn.

1

CHARGER

HPA02224RGRR-1-GP

INPUTS

AD+

BT+

SYSTEM DC/DC

TPS51225RUKR-GP

INPUTS

DCBATOUT

CPU Core Power

ISL95813HRZ-GP

INPUTS

DCBATOUT

DDR3L SUS

TPS51716RUKR-GP

INPUTS

DCBATOUT 1D35V_S3

CPU 1.05V

RT8237CZQW-2-GP

31

DCBATOUT

CPU 1D5V_S0

TLV70215DBVR-GP

3D3V_S5

OUTPUTS

DCBATOUT

OUTPUTS

3D3V_AUX_S5 5V_AUX_S5 5V_S5 3D3V_S5

OUTPUTS

VCC_CORE

OUTPUTS

0D65V_S0

OUTPUTSINPUTS

1D05V_S0

OUTPUTSINPUTS

1D5V_S0

Switches

INPUTS

1D35V_S3

5V_S5 5V_S0

1D05V_S0

3D3V_S0

1D35V_S3

46,47

33

36 83

OUTPUTS

1D35V_S0

3D3V_S03D3V_S5

1D05V_VGA_S0

3D3V_VGA_S0

1D35V_VGA_S0

44

45

49

48

51

PCB LAYER

L1:Top L2:VCC L3:Signal L4:Signal L5:GND L6:Signal

Thermal

NUVOTON NCT7718W

Fan Control

ANPEC

A A

APL5606AKI

FAN

SMBUS

26

Int. KB

KBC

NUVOTON

NPCE285P

62

Image sensor

PS2

Touch PAD

SATA(Gen3) x 1

SPI

24

Flash ROM

8MB Quad Read

25

SATA(Gen1) x 1

I2C

62

www.schematic-x.blogspot.com

5

4

3

HDD

ODD

56

2

Wistron Corporation

21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

C

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Janus HSW 40/50/70

2104Friday, February 07, 2014

1

of

X02

5

D D

4

3

2

1

(Blanking)

C C

B B

Wistron Corporation

A A

Title

(Reserved)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

(Reserved)

Janus HSW 40/50/70

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

3104Friday, February 07, 2014

1

5

4

3

2

1

SSID = CPU

1D05S_VCCST

RN401

XDP_TMS

D D

XDP_TDI

XDP_TDO

XDP_TRST# XDP_TCLK

R402 51R2J-2-GP

R402 51R2J-2-GP R406 51R2J-2-GPR406 51R2J-2-GP

RN401

1 2 3

DY

4 5

SRN51J-1-GP

DY

1 2 1 2

8 7 6

1D05S_VCCST

Remove TP401 for TP604 spacing.

12

R401

62R2J-GP

Layout Note:

C C

Impedance control:50 ohm

H_PROCHOT#[24,42,44,46]

DY

H_THERMTRIP_EN[36]

1 2

R411

0R2J-2-GP

TP403TP403

TP402TP402

H_PECI[24]

1 2

R403

1

56R2J-4-GP

Layout Note: Close to CPU

DDR_PG_CTRL[12]

B B

R407 200R2F-L-GPR407 200R2F-L-GP

1 2

R408 121R2F-GPR408 121R2F-GP

1 2

R409 100R2F-L1-GP-UR409 100R2F-L1-GP-U

1 2

SM_RCOMP_0

SM_RCOMP_1

SM_RCOMP_2

H_CATERR#

1

H_PROCHOT#_R XDP_TRST#

H_CPUPWRGD

R405

12

10KR2J-3-GP

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 SM_DRAMRST# DDR_PG_CTRL

CPU1B

D61

PROC_DETECT#

K61

CATERR#

N62

PECI

K63

PROCHOT#

C61

PROCPWRGD

AU60

SM_RCOMP0

AV60

SM_RCOMP1

AU61

SM_RCOMP2

AV15

SM_DRAMRST#

AV61

SM_PG_CNTL1

HASWELL-6-GP-U

71.HASWE.G0U

SM_DRAMRST#

Layout Note:

Design Guideline:

MISC

THERMAL

PWR

DDR3L

HSW_ULT_DDR3L

1D35V_S3

12

R410

R410 470R2J-2-GP

470R2J-2-GP

JTAG

R404

1 2

0R0402-PAD

2 OF 19

XDP_PRDY#

J62

PRDY#

PREQ#

PROC_TCK

PROC_TMS

PROC_TRST#

PROC_TDI

PROC_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

K62 E60 E61 E59 F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

XDP_PREQ# XDP_TCLK XDP_TMS

XDP_TDI XDP_TDO

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

Layout Note:

Place close to DIMM

DDR3_DRAMRST# [12]

XDP_PRDY# [96] XDP_PREQ# [96] XDP_TCLK [ 96] XDP_TMS [96] XDP_TRST# [96] XDP_TDI [96] XDP_TDO [96]

XDP_BPM[7:0]

XDP_BPM[7:0] [96]

SM_RCOMP keep routing length less than 500 mils.

Wistron Corporation

A A

Title

CPU (THERMAL/MISC/PM)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

CPU (THERMAL/MISC/PM)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

4104Friday, February 07, 2014

1

A00

5

4

3

2

1

SSID = CPU

DDR3L ball type: Non-Interleaved Type

HSW_ULT _DD R3L

CPU1D

AW31

AW29

AW27

AW25

AM29

AM26

AW23

AW21

AW19

AW17

AM22

AM20

AY31

AY29

AV31 AU31 AV29 AU29 AY27

AY25

AV27 AU27 AV25 AU25

AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26

AK25 AL25 AY23

AY21

AV23 AU23 AV21 AU21 AY19

AY17

AV19 AU19 AV17 AU17 AR21 AR22 AL21

AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20

AR18 AP18

CPU1D

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

HSW_ULT _DD R3L

CPU1C

M_A_DQ[63:0][12]

D D

C C

M_A_DQ[63:0]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AH63 AH62 AK63 AK62 AH61 AH60 AK61

AK60 AM63 AM62

AP63

AP62 AM61 AM60

AP61

AP60

AP58

AR58 AM57

AK57

AL58

AK58

AR57

AN57

AP55

AR55 AM54

AK54

AL55

AK55

AR54

AN54

AY58 AW58

AY56 AW56

AV58

AU58

AV56

AU56

AY54 AW54

AY52 AW52

AV54

AU54

AV52

AU52

AK40

AK42

AM43

AM45

AK45

AK43

AM40

AM42

AM46

AK46

AM49

AK49

AM48

AK48

AM51

AK51

CPU1C

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

HSW_ULT _DD R3L

DDR CHANNEL A

3 OF 19

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_RAS#

SA_WE#

SA_CAS#

SA_BA0 SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32

AY34 AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49 AR51 AP51

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

+V_SM_VREF_CNT

M_A_DIMA_CLK_DDR#0 [12] M_A_DIMA_CLK_DDR0 [12] M_A_DIMA_CLK_DDR#1 [12] M_A_DIMA_CLK_DDR1 [12]

M_A_DIMA_CKE0 [12] M_A_DIMA_CKE1 [12]

M_A_DIMA_CS#0 [12] M_A_DIMA_CS#1 [12]

TP_M_A_DIMA_ODT0

M_A_RAS# [12]

M_A_WE# [12]

M_A_CAS# [12]

M_A_BS0 [12] M_A_BS1 [12] M_A_BS2 [12]

M_A_A[15:0] [12]

M_A_DQS#[7:0] [12]

M_A_DQS[7:0] [12]

+V_SM_VREF_CNT [37] DDR_WR_VREF01 [37]

TP501TP501

1

HSW_ULT _DD R3L

DDR CHANNEL B

4 OF 19

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS#

SB_WE#

SB_CAS#

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32

AM35 AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

HASWELL-6-GP-U

B B

A A

5

4

3

HASWELL-6-GP-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDR)

Janus HSW 40/50/70

1

5104Friday, February 07, 2014

A00

5

SSID = CPU

4

3

2

1

D D

CFG[19:0][96]

C C

PCH strap pin:

#514405

CFG[19:0]

1 2

R601

R601 49D9R2F-GP

49D9R2F-GP

1 2

R603

R603 8K2R2F-1-GP

8K2R2F-1-GP

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP

TD_IREF

CFG3

AC60 AC62 AC63 AA63 AA60

Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60

AA62

U63

AA61

U62

V63

H18 B12

J20

CPU1S

A5

E1 D1

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP

RSVD#A5

RSVD#E1 RSVD#D1 RSVD#J20 RSVD#H18 TD_IREF

12

DY

R604

R604 1KR2J-1-GP

1KR2J-1-GP

HSW_ULT_DDR3L

RESERVED

PROC_OPI_RCOMP

19 OF 19

RSVD_TP#AV63 RSVD_TP#AU63

RSVD_TP#C63 RSVD_TP#C62

RSVD#B43

RSVD_TP#A51 RSVD_TP#B51

RSVD_TP#L60

RSVD#N60

RSVD#W23

RSVD#Y22

RSVD#AV62

RSVD#D58

VSS VSS

RSVD#P20 RSVD#R20

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

0 : ENABLED

CFG[3]

SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

AV63 AU63

C63 C62 B43

A51 B51

L60

N60

W23

PROC_OPI_COMP3

Y22

PROC_OPI_COMP

AY15

AV62 D58

P22 N21

HVM_CLK#

P20

HVM_CLK

R20

RSVDAV63 RSVDAU63

RSVDC63 RSVDC62 EDP_SPARE

RSVDA51 RSVDB51

RSVDL60

TP601TP601

1

TP602TP602

1

TP603TP603

1

TP604TP604

1

TP605TP605

1

TP606TP606

1

TP607TP607

1

TP608TP608

1

Intel Recommend

R606 49D9R2F-GP

1 2

DY

R602 49D9R2F-GPR602 49D9R2F-GP

1 2

1

TP619TP619

1

TP620TP620

#514405

Layout Note:

1.Referenced "continuous" VSS plane only.

2.Avoid routing next to clock pins or noisy signals.

3.Trace width: 12~15mil

4.Isolation Spacing: 12mil

5.Max length: 500mil

1 : DISABLED

B B

CFG4

12

R605

R605 1KR2J-1-GP

1KR2J-1-GP

DISPLAY PORT PRESENCE STRAP

0 : ENABLED

CFG[4]

AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT

1 : DISABLED

NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (CFG)

Janus HSW 40/50/70

6104Friday, February 07, 2014

1

A00

5

SSID = CPU

4

3

2

1

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

VCC_CORE

HSW_ULT_DDR3L

CPU1L

D D

1D35V_S3

1D05S_VCCST

NC#1

VCC

A

DY

GND3Y

VR_SVID_ALERT#

H_CPU_SVIDDAT

3D3V_S5

SCD1U16V2KX-3GP

C702

1D05S_VCCST

12

DY

12

R706

R706 10KR2J-3-GP

10KR2J-3-GP

DY

R709

R709 47KR2F-GP

47KR2F-GP

DY

5

4

12

Need to fine tune to 1.05V.

EC701

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Length match<25mil

VCC_SENSE[46]

VR_SVID_ALERT#[46]

H_CPU_SVIDCLK[46] H_CPU_SVIDDAT[46]

H_VR_ENABLE[46]

PWR_DEBUG[96]

1D05S_VCCST

H_VCCST_PWRGD [96]

12

DY

SCD1U16V2KX-3GP

1D05V_S0

0R0603-PAD-1-GP-U

R711

1 2

1D05S_VCCST

DY

VCC_CORE

12

R702

100R2F-L1-GP-U

TP701TP701

R701

43R2J-GP

1 2

H_CPU_SVIDCLK H_CPU_SVIDDAT

R710 10KR2J-3-GP

1 2

DY

1 2

TP702TP702 TP703TP703 TP704TP704 TP705TP705

DY

1 1 1 1

IMVP _PWR GD_R

R705 150R2J-L1-GP-UR705 150R2J-L1-GP-U

0.1A

12

C701

C703

DY

C703

DY

SC1U10V2KX-1GP

SC22U6D3V5MX-2GP

VCC_CORE

TP_VCCIO_OUT

1

+VCCIOA_OUT

H_CPU_SVIDALRT#

H_VCCST_PWRGD

PWR_DEBUG

RSVDP60 RSVDP61 RSVDN59 RSVDN61

1D05S_VCCST

VCC_CORE

R703 75R2F-2-GPR703 75R2F-2-GP

1 2

R704 130R2F-1-GPR704 130R2F-1-GP

1 2

#487822

C C

U701

1

1D05V_VTT_PWRGD[36,48]

B B

2

74LVC1G07GW-GP

73.01G07.0HG

1 2

R707

R707 100KR2F-L1-GP

100KR2F-L1-GP

CPU1L

L59

J58

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

F59 N58

AC58

E63

AB23

A59

E20 AD23 AA23 AE59

L62

N63

L63

B59

F60

C59

D63

H59

P62

P60

P61

N59

N61

T59 AD60 AD59 AA59 AE60 AC59 AG58

U59

V59

AC22 AE22 AE23

AB57 AD57 AG57

C24

C28

C32

HASWELL-6-GP-U

RSVD#L59 RSVD#J58

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCC RSVD#N58 RSVD#AC58

VCC_SENSE RSVD#AB23 VCCIO_OUT VCCIOA_OUT RSVD#AD23 RSVD#AA23 RSVD#AE59

VIDALERT# VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

VSS PWR_DEBUG# VSS RSVD_TP#P60 RSVD_TP#P61 RSVD_TP#N59 RSVD_TP#N61 RSVD#T59 RSVD#AD60 RSVD#AD59 RSVD#AA59 RSVD#AE60 RSVD#AC59 RSVD#AG58 RSVD#U59 RSVD#V59

VCCST VCCST VCCST

VCC VCC VCC VCC VCC VCC

HSW_ULT_DDR3L

HSW ULT POW ER

12 OF 19

IMVP _PWR GD[24,46]

A A

5

4

1 2

R713

R713 100KR2F-L1-GP

100KR2F-L1-GP

IMVP _PWR GD_R

12

R712

R712 47KR2F-GP

47KR2F-GP

3

EC702

12

DY

SCD1U16V2KX-3GP

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet of

CPU (VCC CORE)

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

7104

1

A00

5

www.vinaﬁx.vn

4

3

2

1

SSID = CPU

D D

HSW_ULT_DDR3L

CPU1A

HSW_ULT_DDR3L

1 OF 19

PCH_DPB_N0[55]

PCH_DPB_P0[55 ]

PCH_DPB_N1[55]

PCH_DPB_P1[55 ]

C C

DP to VGA Converter

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

C58

DDI1_TXP1

B55

DDI1_TXN2

A55

DDI1_TXP2

A57

DDI1_TXN3

B57

DDI1_TXP3

C51

DDI2_TXN0

C50

DDI2_TXP0

C53

DDI2_TXN1

B54

DDI2_TXP1

C49

DDI2_TXN2

B50

DDI2_TXP2

A53

DDI2_TXN3

B53

DDI2_TXP3

HASWELL-6-GP-U

EDPDDI

EDP_RCOMP

EDP_DISP_UTIL

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

EDP_COMP EDP_BRIGHTNESS

EDP_TX0_DN [52] EDP_TX0_DP [52] EDP_TX1_DN [52] EDP_TX1_DP [52]

EDP_AUX_DN [52] EDP_AUX_DP [52]

1

TP801TP801

R801

24D9R2F-L-GP

+VCCIOA_OUT

Design Guideline: EDP_COMP keep routing length max 100 mils.

12

Trace Width:20 mils.

B B

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDI/EDP)

Janus HSW 40/50/70

8104Friday, February 07, 2014

X02

5

4

3

2

1

SSID = CPU

HSW_ULT_DDR3L

CPU1P

D33

VSS

D34

D D

C C

B B

VSS

D35

VSS

D37

VSS

D38

VSS

D39

VSS

D41

VSS

D42

VSS

D43

VSS

D45

VSS

D46

VSS

D47

VSS

D49

VSS

D5

VSS

D50

VSS

D51

VSS

D53

VSS

D54

VSS

D55

VSS

D57

VSS

D59

VSS

D62

VSS

D8

VSS

E11

VSS

E17

VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS

G18

VSS

G22

VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS

H13

VSS

HASWELL-6-GP-U

HSW_ULT_DDR3L

16 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS_SENSE

VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

VSS_SENSE

12

VSS_SENSE [46]

Layout Note:

R901

100R2F-L1-GP-U

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Length match<25mil

Wistron Corporation

A A

Title

CPU (VSS)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

CPU (VSS)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

9104Friday, February 07, 2014

1

A00

5

4

3

2

1

SSID = CPU

1D35V_S3

D D

12

C1002

C1001

SC10U10V5KX-2GP

12

C C

C1018

C1017

SC2D2U6D3V2MX-GP

12

DY

C1003

C1004

SC10U10V5KX-2GP

12

DY

C1020

C1019

DY

SC2D2U6D3V2MX-GP

12

DY

C1006

C1005

SC10U10V5KX-2GP

Layout Note:

Direct tie to CPU VccIn/Vss balls

Layout Note:

As close to CPU as possible

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (Power CAP1)

Size Document Number Rev

A3

Date: Sheet of

CPU (Power CAP1)

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

10 104Friday, February 07, 2014

1

A00

5

4

3

2

1

MAX: 1.92A

1.838A 41mA 42mA

D D

R1101

1 2

0R0805-PAD-1-GP-U

CAP need close to pin K9 L10

+V1.05DX_MODPHY_PCH1D05V_HSIO

C1101

C1102

12

SC1U10V2KX-1GP

1D05V_HSIO

L1101 0R3J-0-U-GPL1101 0R3J-0-U-GP

1 2

12

CAP need close to pin B18

+V1.05S_AUSB3PLL

C1103

12

DY

C1104

SC1U10V2KX-1GP

+V1.05S_AUSB3PLL

12

DY

C1123

SC10U10V5KX-2GP

1D05V_HSIO

L1102 0R3J-0-U-GPL1102 0R3J-0-U-GP

1 2

C1105

12

SC10U10V5KX-2GP

CAP need close to pin B11

+V1.05S_ASATA3PLL

12

DY

C1106

SC1U10V2KX-1GP

SC10U10V5KX-2GP

C1107

SC10U10V5KX-2GP

57mA 62mA 185mA

DY

SC1U10V2KX-1GP

12

+V1.05S_APLLOPI

12

DY

C1110

SC10U10V5KX-2GP

+V3.3A_PSUS3D3V_S5_PCH

R1103

1 2

0R0603-PAD-1-GP-U

C1124

SC10U10V5KX-2GP

CAP need close to pin AC9

DY

12

C1108

SC10U10V5KX-2GP

L1103 IND-2D2UH-196-GP

1 2

68.2R21D.10R

C1111

12

SC1U10V2KX-1GP

CAP need close to pin J18

12

DY

+V1.05S_AXCK_DCB1D05V_S0

+V1.05S_AXCK_DCB

12

DY

C1112

C1125

SC10U10V5KX-2GP

1D05V_S0

C C

R1102

1 2

0R0603-PAD-1-GP-U

+V1.05S_APLLOPI

C1109

12

CAP need close to pin AA21

31mA 658mA 1.632A 1mA

1D05V_S0

IND-2 D2UH -196-G P

IND-2 D2UH -196-G P L1104

L1104

1 2

68.2R21D.10R

B B

+V1.05S_AXCK_LCPLL

C1113

12

DY

C1114

1D05V_S0

R1104

1 2

0R0603-PAD-1-GP-U

DY

C1116

12

C1115

1D05V_S0

12

R1105

1 2

0R0805-PAD-1-GP-U

C1117

12

C1118

+V1.05S_CORE_PCH+1.05M_ASW

C1120

SCD1U16V2KX-3GP

12

DY

C1119

SCD1U16V2KX-3GP

12

DY

C1121

SCD1U16V2KX-3GP

RTC_AUX_S5

12

C1122

12

SC1U10V2KX-1GP

SC10U10V5KX-2GP

SC1U10V2KX-1GP

SC10U10V5KX-2GP

CAP need close to pin A20

A A

5

SC10U10V5KX-2GP

CAP need close to pin AE9

4

SC10U10V5KX-2GP

CAP need close to pin AE8 J11

3

SC1U10V2KX-1GP

SC10U10V5KX-2GP

CAP need close to pin AG10

2

SC1U10V2KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (Power CAP2)

Size Document Number Rev

A3

Date: Sheet of

CPU (Power CAP2)

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

11 104Friday, February 07, 2014

1

A00

5

4

3

2

1

SSID = MEMORY

SA0_DIMA SA1_DIMA

12

R1202

DM1

D D

M_VREF_CA_DIMMA

12

DY

12

C1215

DY

12

C1218

C1202

SCD1U16V2KX-3GP

M_VREF_DQ_DIMMA

12

C1206

C1205

SC2D2U10V3KX-1GP

12

C1216

SC1U10V2KX-1GP

12

C1201

C C

B B

A A

SCD1U16V2KX-3GP

12

C1204

0D675V_S0

SCD1U16V2KX-3GP

12

C1214

SC1U10V2KX-1GP

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

Layout Note:

Place these caps close to VREF_CA

SCD1U16V2KX-3GP

Layout Note:

Place these caps close to VREF_DQ

SCD1U16V2KX-3GP

DDR3_DRAMRST#[4]

M_A_A[15:0][5]

M_A_BS2[5]

M_A_BS0[5] M_A_BS1[5]

M_A_DQ[63:0][5]

Layout Note:

Place these caps close to VTT1 and VTT2.

M_A_DQS#[7:0][5]

M_A_DQS[7:0][5]

M_VREF_CA_DIMMA M_VREF_DQ_DIMMA

M_A_DIMA_ODT0 M_A_DIMA_ODT1

0D675V_S0

12

C1217

SCD1U16V2KX-3GP

DY

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ13 M_A_DQ8 M_A_DQ14 M_A_DQ10 M_A_DQ9 M_A_DQ12 M_A_DQ15 M_A_DQ11 M_A_DQ29 M_A_DQ28 M_A_DQ30 M_A_DQ31 M_A_DQ25 M_A_DQ24 M_A_DQ27 M_A_DQ26 M_A_DQ44 M_A_DQ41 M_A_DQ43 M_A_DQ47 M_A_DQ45 M_A_DQ40 M_A_DQ42 M_A_DQ46 M_A_DQ51 M_A_DQ50 M_A_DQ49 M_A_DQ48 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ6 M_A_DQ5 M_A_DQ4 M_A_DQ3 M_A_DQ7 M_A_DQ21 M_A_DQ20 M_A_DQ17 M_A_DQ16 M_A_DQ18 M_A_DQ19 M_A_DQ22 M_A_DQ23 M_A_DQ36 M_A_DQ33 M_A_DQ34 M_A_DQ38 M_A_DQ37 M_A_DQ32 M_A_DQ35 M_A_DQ39 M_A_DQ62 M_A_DQ58 M_A_DQ60 M_A_DQ61 M_A_DQ63 M_A_DQ59 M_A_DQ56 M_A_DQ57

M_A_DQS#1 M_A_DQS#3 M_A_DQS#5 M_A_DQS#6 M_A_DQS#0 M_A_DQS#2 M_A_DQS#4 M_A_DQS#7

M_A_DQS1 M_A_DQS3 M_A_DQS5 M_A_DQS6 M_A_DQS0 M_A_DQS2 M_A_DQS4 M_A_DQS7

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-48-GP-U

62.10017.P41

RAS#

CAS#

CKE0 CKE1

EVENT#

VDDSPD

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

CS0# CS1#

CK0#

CK1#

NC#1 NC#2

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIMA

197

SA0

SA1_DIMA

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D35V_S3

M_A_RAS# [5] M_A_WE# [5] M_A_CAS# [5]

M_A_DIMA_CS#0 [5] M_A_DIMA_CS#1 [5]

M_A_DIMA_CKE0 [5] M_A_DIMA_CKE1 [5]

M_A_DIMA_CLK_DDR0 [5] M_A_DIMA_CLK_DDR#0 [5]

M_A_DIMA_CLK_DDR1 [5] M_A_DIMA_CLK_DDR#1 [5]

PCH_SMBDATA [18,62,96] PCH_SMBCLK [18,62,96]

3D3V_S0

12

C1203

DY

SCD1U16V2KX-3GP

1D35V_S3

Layout Note:

Place these Caps near SO-DIMMA.

R1202

0R0402-PAD

TC1201

C1210

12

DY

C1207

SC10U10V5KX-2GP

ST330U2VDM-4-GP

12

C1211

SCD1U16V2KX-3GP

12

DY

12

DY

DDR_PG_CTRL[4]

Q1201 must use Vth=1V.

close to dimm

5

4

3

Note: SA0 DIM0 = 0 , SA1_DIM0 = 0

12

SO-DIMM A SPD Address is 0xA0

R1201

0R0402-PAD

SO-DIMM A TS Address is 0x30

12

C1208

C1209

SC10U10V5KX-2GP

12

C1213

C1212

SC1U10V2KX-1GP

R1205

DDR_PG_CTRL_R

1 2

0R0402-PAD

C1220SCD1U16V2KX-3GP C1220SCD1U16V2KX-3GP12C1221SCD1U16V2KX-3GP C1221SCD1U16V2KX-3GP

84.05067.031

12

C1222SCD1U16V2KX-3GP C1222SCD1U16V2KX-3GP

1D35V_S3

Q1201

DMN5L06K-7-GP

G

Vth = 1V max.

DS

2

5V_S5

12

DY

R1208

R1208 220KR2J-L2-GP

220KR2J-L2-GP

DDR_VTT_PG_CTRL

R1204

R1204 2MR2-GP

2MR2-GP

1D35V_S3

D

G

Q1202

Q1202 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

S

M_A_B_DIMM_ODT

DDR_VTT_PG_CTRL [49]

R1206 66D5R2F-GPR1206 66D5R2F-GP

1 2

R1207 66D5R2F-GPR1207 66D5R2F-GP

1 2

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Date: Sheet of

Friday, February 07, 2014

DDR3-SODIMM1

Janus HSW 40/50/70

M_A_DIMA_ODT0

M_A_DIMA_ODT1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

12 104

1

12 104

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)DDR3-SODIMM2

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

13 104

1

A00

5

D D

4

3

2

1

C C

(Blanking)

B B

Wistron Corporation

A A

Title

(Reserved)_SODIMM _SODIMM4

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

14 104Friday, February 07, 2014

1

A00

5

4

3

2

1

SSID = CPU

PCH strap pin:

Port B Detected

DDPB_CTRLDATA

D D

DDPC_CTRLDATA

Low = Disable Port B (default) High = Enable Port B

*

Low = Disable Port C (default)

*

High = Enable Port C

The internal pull-do wn is disabled af ter PLTRST# deasserts

3D3V_S0

1

RN1501

SRN2K2J-1-GP

HSW_ULT_DDR3L

eDP SIDEBAND

PCIE

HSW_ULT_DDR3L

DISPLAY

CPU1I

L_BKLT_CTRL[52] L_BKLT_EN[2 4] EDP_VDD_EN[52]

RN1503

1 2 3

OPS

C C

3D3V_S0

SRN10KJ-5-GP

R1509

1 2

OPS

UMA

RN1505

1 2 3 4 5

SRN10KJ-6-GP

DGPU_HOLD_RST#

4

DGPU_PWR_EN PIRQB#

DGPU_PWROK

100KR2J-1-GP

8 7 6

PIRQC# PIRQD#

PIRQB#

INT_ TP#[20,24,62]

CLK_PCIE_WLAN_REQ3# [18,58]

PIRQA#[20]

TP1501TP1501

R1512

R1512 0R2J-2-GP

0R2J-2-GP

DGPU_PWR_EN[82,83]

DGPU_HOLD_RST#[73]

1 2

DGPU_PWROK[24,82,83 ]

12

DY

EC1501

SC1KP50V2KX-1GP

PIRQC# PIRQD# PCI_PME#

1

INT_ TP#_G PIO55

12

DY

EC1502

SC1KP50V2KX-1GP

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA#/GPIO77

P4

PIRQB#/GPIO78

N4

PIRQC#/GPIO79

N2

PIRQD#/GPIO80

AD4

PME#

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

HASWELL-6-GP-U

9 OF 19

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

DDPB_HPD DDPC_HPD

EDP_HPD

B9 C9 D9 D11

C5 B6 B5 A6

C8 A8 D6

SRN2K2J-1-GP

DDPB_CTRLCLK DDPB_CTRLDATA

DDPC_CTRLDATA

EE Note: If layout is on constraint, please reserve TP for DDPC_CTRLCLK.

CRT_PCH_HPD [55]

EDP_HPD [52]

23

4

1

TP1502TP1502

PCH_DPB_AUXN [55]

PCH_DPB_AUXP [55]

B B

A A

5

3D3V_S0

12

R1510

R1510 10KR2J-3-GP

10KR2J-3-GP

Cedar

CEDAR/JANUS_ID

R1511

R1511 10KR2J-3-GP

10KR2J-3-GP

Janus

CEDAR/JANUS_ID [19]

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

PCH ( EDP/GPIO/DDI )

Janus HSW 40/50/70

15 104Friday, February 07, 2014

1

X02

5

4

3

2

1

SSID = PCH

HSW_ULT_DDR3L

CPU1K

CPU_RXN_C_dGPU_TXN0[73] CPU_RXP_C_dGPU_TXP0[73]

dGPU_RXN_C_CPU_TXN0[73] dGPU_RXP_C_CPU_TXP0[7 3]

D D

CPU_RXN_C_dGPU_TXN1[73] CPU_RXP_C_dGPU_TXP1[73 ]

dGPU_RXN_C_CPU_TXN1[73] dGPU_RXP_C_CPU_TXP1[7 3]

CPU_RXN_C_dGPU_TXN2[73] CPU_RXP_C_dGPU_TXP2[73 ]

dGPU_RXN_C_CPU_TXN2[73] dGPU_RXP_C_CPU_TXP2[7 3]

CPU_RXN_C_dGPU_TXN3[73] CPU_RXP_C_dGPU_TXP3[73 ]

dGPU_RXN_C_CPU_TXN3[73] dGPU_RXP_C_CPU_TXP3[7 3]

PCIE_PRX_WLANTX_N3[58] PCIE_PRX_WLANTX_P3[58]

PCIE_PTX_WLANRX_N3_C[58] PCIE_PTX_WLANRX_P3_C[58]

PCIE_PRX_LANTX_N4[30] PCIE_PRX_LANTX_P4[3 0]

PCIE_PTX_LANRX_N4_C[30]

C C

PCIE_PTX_LANRX_P4_C[30]

+V1.05S_AUSB3PLL

B B

C1606

C1606 C1605

C1605

C1608

C1608 C1607

C1607

C1610

C1610 C1609

C1609

C1612

C1612 C1611

C1611

C1601

C1601 C1602

C1602

C1603

C1603 C1604

C1604

Layout Note:

1. PCIE_RCOMP/ PCIE_IREF trace width=12~15mil

2. Isolation Spacing: 12mil

3. Total trace length<500mil

1 2 1 2

R1601

3KR2F-GP

1 2

SCD1U16V2KX-3GP

dGPU_RXN_CPU_TXN0

OPS

dGPU_RXP_CPU_TXP0

OPS

SCD1U16V2KX-3GP

dGPU_RXN_CPU_TXN1

OPS

dGPU_RXP_CPU_TXP1

OPS

SCD1U16V2KX-3GP

dGPU_RXN_CPU_TXN2

OPS

dGPU_RXP_CPU_TXP2

OPS

SCD1U16V2KX-3GP

dGPU_RXN_CPU_TXN3

OPS

dGPU_RXP_CPU_TXP3

OPS

SCD1U16V2KX-3GP

PCIE_PTX_WLANRX_N3 PCIE_PTX_WLANRX_P3

SCD1U16V2KX-3GP

PCIE_PTX_LANRX_N4 PCIE_PTX_LANRX_P4

SCD1U16V2KX-3GP

PCIE_RCOMP

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

RSVD#E15

E13

RSVD#E13

A27

PCIE_RCOMP

B27

PCIE_IREF

GPU

WLAN

LAN

HASWELL-6-GP-U

HSW_ULT_DDR3L

PCIE USB

11 OF 19

USB2N0

USB2P0

USB2N1

USB2P1

USB2N2

USB2P2

USB2N3

USB2P3

USB2N4

USB2P4

USB2N5

USB2P5

USB2N6

USB2P6

USB2N7

USB2P7

USB3RN1 USB3RP1

USB3TN1

USB3TP1

USB3RN2 USB3RP2

USB3TN2

USB3TP2

USBRBIAS#

USBRBIAS RSVD#AN10 RSVD#AM10

OC0/GPIO40# OC1/GPIO41# OC2/GPIO42# OC3/GPIO43#

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11 AN10 AM10

AL3 AT1 AH2 AV3

USB_PN3 USB_PP3

USB_COMP

USB_OC#0_1 USB_OC#2_3 USB_OC#4_5 USB_OC#6_7

PM_SUSWARN#_R[17]

USB 2.0 Table

Pair

USB_PN0 [34] USB_PP0 [34]

USB_PN1 [34] USB_PP1 [34]

USB_PN2 [63]

1 2

USB_OC#0_1 [18,35] USB_OC#2_3 [35]

USB_OC#4_5 [20]

USB_OC#2_3 USB_OC#6_7

USB_PP2 [63]

USB_PN4 [52] USB_PP4 [52]

USB_PN5 [58] USB_PP5 [58]

USB_PN6 [52] USB_PP6 [52]

USB_PN7 [63] USB_PP7 [63]

USB3_PRX_CTX_N0 [34] USB3_PRX_CTX_P0 [34]

USB3_PTX_CRX_N0 [34] USB3_PTX_CRX_P0 [34]

1. USB_COMP using 50 ohm single-ended impedance

2. Isolation Spacing :15mil

3. Total trace length<500mil

RN1601

8 7 6

SRN10KJ-6-GP

Layout Note:

3D3V_S5_PCH

1 2 3 45

TP1601TP1601

1

TP1602TP1602

1

R1602

R1602 22D6R2F-L1-GP

22D6R2F-L1-GP

MCP_GPIO73[18]

Device

USB3.0 port1

0

USB2.0 Port2 (Debug Port)

1

USB2.0 Port3 (IOBD)

2

X

3

CAMERA

4

WLAN

5

Touch Panel

6

Card Reader

7

#515621

PCIE Table

Port

1

2

3

4

5(L0~L3)

A A

6(L3)

6(L2)

6(L0~L1)

5

Device

N/A

Share BUS

USB3.0_3

USB3.0_4

WLAN

LAN

GPU

HDD

SATA0

ODD SATA1

N/A

GPU GPU GPU GPU

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GPU GPU GPU GPU

Title

Size Document Number Rev

A3

Date: Sheet of

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

PCH (PCIE/USB)

Janus HSW 40/50/70

16 104Friday, February 07, 2014

1

A00

5

4

3

2

1

SSID = PCH

RN1703

1

D D

R1717 10KR2J-3-GP

XDP_DBRESET#[96]

SYS_PWROK[24,96] PCH_PWROK[24,26,36]

C C

PM_SUSWARN#_R[16]

PM_PWRBTN#[24,96] AC_PRESENT[2 4,76]

BATLOW#[20]

AC_PRESENT

EC1707

12

DY

SCD1U16V2KX-3GP

3D3V_S5

B B

A A

SCD1U16V2KX-3GP

RN1701

1 2 3

SRN10KJ-5-GP

R1703

1 2

1KR2J-1-GP

3D3V_S5_PCH

1 2

DY

R1724 10KR2J-3-GP

12

DY

EC1706

SC1KP50V2KX-1GP

EC1702

4

(CRB#514469)

12

DY

SC1KP50V2KX-1GP

EC1703

5

MCP_GPIO12 AC_PRESENT

PM_SUS_STAT#

SC1KP50V2KX-1GP

2 3

SRN10KJ-5-GP

12

DY

PCH_WAKE#

12

DY

EC1704

SC1KP50V2KX-1GP

12

DY

4

EC1705

3D3V_S0

12

R1706

1 2

0R0402-PAD

PLT_RST#[24,30,36 ,52,58,65,73,96]

100KR2J-1-GP

MCP_GPIO12 [20]

XDP_DBRESET#

12

DY

SC1KP50V2KX-1GP

PM_RSMRST# PM_PCH_PWROK

SYS_PWROK

R1701

R1701 10KR2J-3-GP

10KR2J-3-GP

R1715

SYS_PWROK PLT_RST# PCH_PWROK KBC_DPWROK

R1707

1 2

0R0402-PAD

TP1706TP1706 TP1705TP1705

12

DY

1 1

R1713

1 2

0R0402-PAD

12

C1701

C1701 SC220P50V2KX-3GP

SC220P50V2KX-3GP

DY

PCH strap pin:

On Die DSW VR Enable

DSWVRMEN

This signal has no integrated pull-up /pull-down.

HSW_ULT_DDR3L

CPU1H

PM_SUSACK#_R XDP_DBRESET# PCH_DPWROK PM_RSMRST# SYS_PWROK

PM_PCH_PWROK

MPWROK PCI_PLTRST#

PM_RSMRST# PM_SUSWARN#_R PM_PWRBTN# AC_PRESENT BATLOW# PCH_SLP_S0# PCH_SLP_WLAN#

PCI_PLTRST#

4

AK2

SUSACK#

AC3

SYS_RESET#

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST#

AW6

RSMRST#

AV4

SUSWARN#/SUSPWRDNACK#/ GPIO30

AL7

PWRBTN#

AJ8

ACPRESENT/GPIO31

AN4

BATLOW#/GPI O72

AF3

SLP_S0#

AM5

SLP_WLAN#/GPI O29

HASWELL-6-GP-U

PM_SUSACK#[2 4]

PM_SUSWARN#[24]

HSW_ULT_DDR3L

SYSTEM POWER MANAGEMENT

NON DS3

R1708

1 2

0R2J-2-GP

RN1702

2 3

DS3

1

4

SRN0J-6-GP

3D3V_AUX_S5

R1726

R1726 10KR2J-3-GP

10KR2J-3-GP

1 2

3V_5V_POK#

SUS_STAT#/GPIO61

PM_SUSACK#_RPM_SUSWARN#_R

PM_SUSACK#_R PM_SUSWARN#_R

R1727

100KR2J-1-GP

1 2

NON DS3

5

6

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

3

Q1701

2N7002KDW-GP

8 OF 19

DSWVRMEN

DPWROK

WAKE#

CLKRUN#/GPIO32

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4# SLP_S3#

SLP_A#

SLP_SUS#

SLP_LAN#

34

2

1

AW7 AV5 AJ5

V5 AG4 AE6 AP5

AJ6 AT4 AL5 AP4 AJ7

PCH_DPWROK

PM_RSMRST#

3V_5V_POK_C

Low = Disable High = Enable (default)

*

DSWODVREN

PCH_WAKE#

PM_CLKRUN# PM_SUS_STAT# SUS_CLK_PCH PM_SLP_S5#

PM_SLP_S4# PM_SLP_S3# PM_SLP_A# PM_SLP_SUS# PM_SLP_LAN#

R1718 0R2J-2-GP

1KR2J-1-GP

1KR2J-1-GP R1702

R1702

1 2

R1728

1 2

NON DS3

0R2J-2-GP

R1729

1 2

0R2J-2-GP

DS3

NON DS3

1

1 2

DS3

R1704

0R2J-2-GP

1 2 1 2

DY

R1705

R1705 0R2J-2-GP

0R2J-2-GP

R1709

1 2

TP1702TP1702

R1710

1 2

TP1703TP1703

TP1704TP1704

TP1707TP1707

DS3

1 2

RSMRST#_KBC [24]

3V_5V_POK [45]

PM_SLP_SUS#

R1705: DY for OBFF disable

0R0402-PAD

0R2J-2-GP

R1725

R1725 100KR2F-L1-GP

100KR2F-L1-GP

2

DSWODVREN

PCIE_WAKE# [24,30]

PM_CLKRUN#_EC [24]

SUS_CLK [24]

PM_SLP_S4# [24,49]

PM_SLP_S3# [24,36,48,49,51]

PM_SLP_SUS# [24,38]

KBC_DPWROK [24]

PM_CLKRUN#

SUS_CLK_PCH

Title

Size Document Number Rev

A3

Date: Sheet of

R1720

330KR2J-L1-GP

1 2

DY

R1721

330KR2J-L1-GP

R1714

8K2R2F-1-GP

1 2

RTC_AUX_S5

3D3V_S0

EC1701

DY

SC4D7P50V2CN-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (PM)

Janus HSW 40/50/70

DY

1 2

17 104Friday, February 07, 2014

1

A00

5

4

3

2

1

SSID = PCH

C1801

R1810

XTAL24_IN XTAL24_IN_R

D D

3D3V_S0

RN1801

LPC_AD2 LPC_AD1 LPC_AD3 LPC_AD0

MCP_GPIO76

8

PEG_CLKREQ#

7

CLK_PCIE_REQ#

6

8 7 6

SRN0J-7-GP-U

LPC_FRAME#[24,65]

SPI_CLK_R[24,25] SPI_CS0#_R[24,25]

SPI_SI_R[24,25 ] SPI_SO_R[24,25]

SPI_WP#[25] SPI_HOLD#[25]

Based on the swap report.

RN1806

LPC_LAD2_PCH

1

LPC_LAD1_PCH

2

LPC_LAD3_PCH

3

LPC_LAD0_PCH

45

1

23

RN1802

RN1802 SRN1KJ-7-GP

SRN1KJ-7-GP

4

PCH_SPI_DQ3

PCH_SPI_DQ2

MCP_GPIO76 [20]

CLK_PCIE_REQ#

CLK_PCIE_WLAN_REQ3#

CLK_PCIE_LAN_REQ4#

PEG_CLKREQ#

CLK_PCIE_REQ#

LPC_LAD0_PCH LPC_LAD1_PCH LPC_LAD2_PCH LPC_LAD3_PCH

1 2

1 2 1 2

1 2 1 2 1 2 1 2

LPC_LFRAME#_PCH

PCH_SPI_CLK

R180633R2J-2-GP R180633R2J-2-GP

PCH_SPI_CS0#

R18070R0402-PAD R18070R0402-PAD

PCH_SPI_SI

R18080R0402-PAD R18080R0402-PAD

PCH_SPI_SO

R18090R0402-PAD R18090R0402-PAD

PCH_SPI_DQ2

R18110R0402-PAD R18110R0402-PAD

PCH_SPI_DQ3

R18120R0402-PAD R18120R0402-PAD

R1801 0R0402-PADR1801 0R0 402-PAD

CPU1F

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0#/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1#/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2#/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3#/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4#/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5#/GPIO23

HASWELL-6-GP-U

CPU1G

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME#

AA3

SPI_CLK

Y7

SPI_CS0#

Y4

SPI_CS1#

AC2

SPI_CS2#

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

HASWELL-6-GP-U

HSW_ULT_DDR3L

WLAN

LAN

GPU

HSW_ULT_DDR3L

LPC

CLOCK

SIGNALS

SMBUS

C-LINKSPI

DIFFCLK_BIASREF

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SML1ALERT#/PCHHOT#/GPI O73

SML1DATA/GPIO74

6 OF 19

XTAL24_IN

XTAL24_OUT

RSVD#K21 RSVD#M21

TESTLOW_C 35 TESTLOW_C 34 TESTLOW_AK 8 TESTLOW_AL 8

CLKOUT_LPC_0 CLKOUT_LPC_1

7 OF 19

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK/GPIO75

CL_CLK

CL_DATA

CL_RST#

A25 B25

K21 M21 C26

C35 C34 AK8 AL8

AN15 AP15

B35 A35

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

AF2 AD2 AF4

XTAL24_IN XTAL24_OUT

XCLK_BIASREF

MCP_TESTLOW1 MCP_TESTLOW2 MCP_TESTLOW3 MCP_TESTLOW4

CLK_PCI_LPC_R CLK_PCI_KBC_R

MCP_GPIO11 SMB_CLK SMB_DATA CARD_PWR_EN SML0_CLK SML0_DATA MCP_GPIO73 SML1_CLK SML1_DATA

TP_CL_CLK TP_CL_DATA TP_CL_RST#

R1803 3KR2F-GPR1803 3KR2F-GP

1 2

RN1803

4

SRN10KJ-5-GP

DEBUG

R1804 0R2J-2-GP

1 2

R1805 33R2J-2-GPR1805 33R2J-2-GP

1 2

MCP_GPIO73 [16] SML1_CLK [24,26 ,76] SML1_DATA [24,26, 76]

TP1801TP180 1

1

TP1802TP180 2

1

TP1803TP180 3

1

SMB_DATA

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

SMB_CLK

+V1.05S_AXCK_LCPLL

1

RN1804

23

4

DY

12

23 1

SRN10KJ-5-GP

EC1801

SC10P50V2JN-4GPDYEC1801

SC10P50V2JN-4GP

12

DY

3D3V_S03D3V_S5

2N7002KDW-GP

6

5

Q1801

XTAL24_OUT

CLK_PCI_LPC [65] CLK_PCI_KBC [24]

PCIE_CLK_XDP_N [9 6] PCIE_CLK_XDP_P [96]

EC1802

SC10P50V2JN-4GPDYEC1802

SC10P50V2JN-4GP

1

2

34

USB_OC#0_1[16,35]

1 2 3 4 5

SRN10KJ-6-GP

CLK_PCIE_WLAN_N3[58 ] CLK_PCIE_WLAN_P3[58]

CLK_PCIE_WLAN_REQ3#[15,58]

CLK_PCIE_LAN_N4[30] CLK_PCIE_LAN_P4[30]

CLK_PCIE_LAN_REQ4#[20,30]

CLK_PCIE_VGA#[73] CLK_PCIE_VGA[73]

C C

LPC_AD[3..0][24,65]

B B

PEG_CLKREQ#[73]

LPC_AD[3..0]

R1810

1 2

0R0402-PAD

R1802

R1802 1MR2J-1-GP

1MR2J-1-GP

CLK_PCI_LPC_R

RN1810

4

SRN10KJ-5-GP

23

4 1

R1813 0R2J-2-GP

SML1_CLK SML1_DATA SML0_DATA SML0_CLK

CARD_PWR_EN

MCP_GPIO11

SMB_CLK SMB_DATA

23 1

PCH_SMBDATA [12,55,62 ,96]

PCH_SMBCLK [12,55,6 2,96]

12

EC_SCI#[20,24]

C1801

SC15P50V2JN-2-G P

X1801

X1801 XTAL-24MHZ-81- GP

XTAL-24MHZ-81- GP

82.30004.841

C1802

SC15P50V2JN-2-G P

1 2

CRT_DEBUG

RN1807

8 7 6

SRN2K2J-4-GP

RN1809

SRN10KJ-6-GP

8 7 6

SRN2K2J-1-GP

4

RN1811

3D3V_S0

12

CLK_DP2VGA [55 ]

3D3V_S5_PCH

1 2 3 45

23 1

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (CLOCK/SMBUS/CL/LPC/SPI)

Size Document Number Rev

Custom

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

18 104Friday, February 07, 2014

1

X02

5

4

3

2

1

SSID = CPU

RTC_X1

1 2

R1915 10MR2J-L-GPR1915 10MR2J-L-GP

X1901

1

4

2 3

XTAL-32D768KHZ-65-GP

82.30001.841

HSW_ULT_DDR3L

RTC

AUDIO SATA

Unused SATA[3:0]GP pins must be terminated to either

3.3V rail or GND using 8.2K to 10K on the motherboard. Either pull-up or pull-down is acceptable.

HDA_SDIN0[27]

R1903

TP1902TP1902

TP1901TP1901

RTC_AUX_S5

12

HDA_BITCLK HDA_SYNC HDA_RST# HDA_SDIN0

HDA_SDOUT TP_HDA_DOCK_EN#

1

PCH_JTAG_TRST#

1

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

XDP_TCK_JTAGX

R1901

R1901 1MR2J-1-GP

1MR2J-1-GP

RTC_X1 RTC_X2

SM_INTRUDER#

PCH_INTVRMEN SRTC_RST# RTC_RST#

C1903

SC15P50V2JN-2-GP

CPU1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER#

AV7

INTVRMEN

AV6

SRTCRST#

AU7

RTCRST#

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST#/I2S_MCLK#

AY10

HDA_SDI0/I2S0_RX D

AU12

HDA_SDI1/I2S1_RX D

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN#/I2S1_ TXD#

AV10

HDA_DOCK_RST#/I2S1 _SFRM#

AY8

I2S1_SCLK

AU62

PCH_TRST#

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD#AL11

AC4

RSVD#AC4

AE63

JTAGX

AV2

RSVD#AV2

HASWELL-6-GP-U

1 2

JTAG

D D

PCH strap pin:

R1913

Integrat ed SUS 1 V VRM Enable

INTVRMEN

C C

Low = External VRs High = Internal VRs

RTCRST_ON[24]

*

R1902

10KR2J-3-GP

R1913

1 2

DY

330KR2J-L1-GP

12

PCH_INTVRMEN

Q1901

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

D

(#514849)

C1901

SC1U10V2KX-1GP

RTC_AUX_S5

21

12

G1901

GAP-OPEN

1

23

RN1901

RN1901 SRN20KJ-1-GP

SRN20KJ-1-GP

4

12

C1902

C1902 SC1U10V2KX-1GP

SC1U10V2KX-1GP

330KR2J-L1-GP

Layout: Place at the open door area.

R1907 33R2J-2-GPR1907 33R2J-2-GP

HDA_CODEC_BITCLK[27]

HDA_CODEC_SYNC[27]

PCH strap pin:

Flash Descriptor Security Overide/ Intel ME De bug Mode

HDA_SDO UT

The internal pull-do wn is disabled af ter PLTRST# deasserts

B B

Low = Default High = Enable

EC1901

SC10P50V2JN-4GP

HDA_CODEC_BITCLK SATA_LED#

1 2

DY

*

HDA_CODEC_RST#[27,29]

HDA_CODEC_SDOUT[27]

ME_UNLOCK[24]

1D05S_VCCST

1 2

R1908 0R0402-PADR1908 0R0402-PAD

1 2

R1911 0R0402-PADR1911 0R0402-PAD

1 2

R1912 33R2J-2-GPR1912 33R2J-2-GP

1 2

R1909 1KR2J-1-GPR1909 1KR2J-1-GP

1 2

DY

DY DY

DY

1 2

DY

12

R1916 51R2J-2-GP

R1917 51R2J-2-GP

R1918 51R2J-2-GP

R1919 1KR2J-1-GP

R1920 51R2J-2-GP

HDA_BITCLK

HDA_SYNC

HDA_RST#

HDA_SDOUT

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

XDP_TCK_JTAGX

PCH_JTAG_TCK

RTC_X2

C1904

C1904 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

1 2

5 OF 19

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0

SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

RSVD#L11 RSVD#K10

SATA_RCOMP

SATALED#

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1 U1 V6 AC1

A12 L11 K10 C12 U3

EC_SMI#

MCP_GPIO36

SATA_IREF

SATA_RCOMP SATA_LED#

SATA_ODD_PRSNT#

EC_SMI# MCP_GPIO36

SATA3_PRX_HDDTX_N0 [56] SATA3_PRX_HDDTX_P0 [56] SATA3_PTX_HDDRX_N0 [56] SATA3_PTX_HDDRX_P0 [56]

SATA_PRX_ODDTX_N2 [56] SATA_PRX_ODDTX_P2 [56] SATA_PTX_ODDRX_N2 [56] SATA_PTX_ODDRX_P2 [56]

EC_SMI# [24]

SATA_ODD_PRSNT# [56]

CEDAR/JANUS_ID [15]

Layout Note:

4mil trace at break-out and 3 12-15mil trace with <0.2 ohms and length total <= 500mils.

RN1902

1

8

2

7

3

6

4 5

SRN10KJ-6-GP

R1905

DY

10KR2J-3-GP

3D3V_S0

12

HDD1

ODD

+V1.05S_ASATA3PLL

R1904

1 2

0R0402-PAD

1 2

R1906

R1906 3KR2F-GP

3KR2F-GP

3D3V_S0

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (RTC/SATA/HDA/JTAG)

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

19 104Friday, February 07, 2014

1

A00

SSID = CPU

5

3D3V_S5

RN2006

BATLOW#

1

4

MCP_GPIO27

2 3

SRN10KJ-5-GP

3D3V_S5_PCH

R2015

10KR2J-3-GP

1 2

R2010

10KR2J-3-GP

1 2

3D3V_S5_PCH

R2013

R2013 10KR2J-3-GP

10KR2J-3-GP

1 2

MCP_R

3D3V_S5_PCH

3D3V_S0

R2010

HSW

D D

C C

INT_T P#_G PIO8

INT_T P#_G PIO46 MCP_GPIO56

1 2 1 2 1 2 1 2

1 2 1 2

1 2

RN2012

RN2012 SRN10KJ-6-GP

SRN10KJ-6-GP

1

8

2

7

3

6

4 5

RN2011

RN2011 SRN10KJ-6-GP

SRN10KJ-6-GP

1

8

2

7

3

6

4 5

BIOS strap pin:

BIOS VRAM Size Strap pi n

1G

2G

B B

BIOS strap pin:

BIOS UMA/ DIS Stra p pin

UMA

DIS

BIOS strap pin:

BIOS UMA/ DIS Stra p pin

N15V-G M-S(DVC 40/50)

A A

N15S-G T (DVC7 0)

GPU_EVENT#[76]

GC6_FB_EN[24,75,76,83]

R20010R 0402-PAD-1-GP R20010R0402-PAD-1-GP R20020R 0402-PAD-1-GP R20020R0402-PAD-1-GP R20040R 0402-PAD-1-GP R20040R0402-PAD-1-GP R20090R 0402-PAD-1-GP R20090R0402-PAD-1-GP

R20160R 0402-PAD-1-GP R20160R0402-PAD-1-GP R20170R 0402-PAD-1-GP R20170R0402-PAD-1-GP

R20200R 0402-PAD-1-GP R20200R0402-PAD-1-GP

R20220R 0402-PAD-1-GP R20220R0402-PAD-1-GP

EC_SWI#

RTC_DET#

WLAN_PLT_RST#

PIRQA# DBC_EN

BLUETOOTH_EN

BOARD_ID2

BOARD_ID3

BATLOW# [17]

MCP_GPIO58 MCP_GPIO44

MCP_GPIO56 MCP_GPIO26

MCP_GPIO14

MCP_GPIO28

MCP_GPIO13

MCP_GPIO57

BOARD_ID1

0

1

0

1

0

1

5

MCP_GPIO76[18]

MCP_GPIO12[17]

SATA_ODD_DA#[56] RTC_DET#[25]

R2029

1 2

0R0402-PAD

HSIOPC[21]

R2028 0R0402-PADR2028 0R0402-PAD

1 2

INT_T P#[15,24,62]

EC_SWI#[24] EC_SCI#[18,24]

HDA_SPKR[27]

USB_OC#4_5 [16]

CLK_PCIE_LAN_REQ4# [18,30] PIRQA# [15]

VRAM_2G

BOARD_ID1

VRAM_1G

BOARD_ID2

BOARD_ID3

N15V-GM

INT_T P#[15,24,62]

OPS

UMA

N15S-GT

3D3V_S0

1 2

0R2J-2-GP

TP2002TP2002

1 2

0R2J-2-GP

TP2001TP2001

12

R2023

R2023 10KR2J-3-GP

10KR2J-3-GP

12

R2024

R2024 10KR2J-3-GP

10KR2J-3-GP

12

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

12

R2008

R2008 10KR2J-3-GP

10KR2J-3-GP

12

R2025

R2025 10KR2J-3-GP

10KR2J-3-GP

12

R2026

R2026 10KR2J-3-GP

10KR2J-3-GP

R2031

DY

R2030

BDW

MCP_GPIO76 INT_T P#_G PIO8 MCP_GPIO12 MCP_GPIO15

RTC_DET# MCP_GPIO27 MCP_GPIO28 MCP_GPIO26

MCP_GPIO57 MCP_GPIO58 WLAN_PLT_RST# MCP_GPIO44 GPU_EVENT_MCP# BOARD_ID1 BOARD_ID2 BOARD_ID3 HSIOPC MCP_GPIO13 MCP_GPIO14

CAMERA_PWR_EN

1

GC6_FB_EN_MCP INT_T P#_G PIO46

EC_SWI# EC_SCI# HDD_DEVSLP

1

HDA_SPKR

4

HSW_ULT _DD R3L

CPU1J

P1

BMBUSY#/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

HASWELL-6-GP-U

HSW_ULT _DD R3L

GPIO

CPU/

CPU/ MISC

MISC

SERIAL IO

10 OF 19

THRMTRIP#

RCIN#/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD#AF20 RSVD#AB21

GSPI0_CS#/GPIO83

GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86

GSPI1_CS#/GPIO87

GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92

UART0_RTS#/GPIO93 UART0_CTS#/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1 UART1_RST#/GPIO2 UART1_CTS#/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

PCH_THERMTRIP

D60

H_RCIN#

V4

INT_S ERIRQ

T4

PCH_OPIRCOMP

AW15 AF20 AB21

R6 L6 N6

LPSS_GSPI0_MOSI_BBS0_R

L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4

I2C0_S DA

F2

I2C0_S CL

F3

I2C1_S DA

G4

I2C1_S CL

F1 E3

COLOR_ENGINE

F4

LPSS_SDIO_D0_CMNHD R

D3 E4 C3 E2

PCH strap pin:

NO REBOOT

HDA_SPKR

The internal pu ll-down is disabled after PLTRST# deasserts

High = Disable

Low = Enable (Default)

*

PCH strap pin:

Top-Block Swap Override mode

High = Enable "Top-Block swap" mode

SDIO_D0

Low = Disable "Top-Block swap" mode (Default)

/ GPIO66

*

The internal pu ll-down is disabled after PLTRST# deasserts

Need SW double confirm if that's needed Top-Block swap

PCH strap pin:

TLS Confidentiality

Low = Disable Intel ME Crypto TLS (Default)

*

GPIO15

The internal pu ll-down is disabled after RSMRST# deasserts.

High = Enable Intel ME Crypto TLS

PCH strap pin:

Boot BIOS Strap Bi t BBS

Boot BIOS Destination

The internal pu ll-down is disabled after PLTRST# deasserts

Need double confirm, GPIO table set to GPI if that's needed PH or PL

Low = SPI (Default)

*

High = LPC

4

3D3V_S0

1KR2J-1-GP

1KR2J-1-GP R2006

R2006

1 2

3D3V_S0

12

DY

3D3V_S5_PCH

12

DY

3D3V_S0

12

R2012

DY

1KR2J-1-GP

LPSS_GSPI0_MOSI_BBS0_R

HDA_SPKR

DY

R2011

R2011 1KR2J-1-GP

1KR2J-1-GP

LPSS_SDIO_D0_CMNHD R

R2014

R2014 1KR2J-1-GP

1KR2J-1-GP

KB_DET# [62] KB_LED_BL_DET [62] DBC_EN [52] PANEL_SIZE_ID [52]

BLUETOOTH_EN [58]

MCP_GPIO15

3

1D05S_VCCST

12

R2018

R2018 1KR2J-1-GP

1KR2J-1-GP

1 2

R2003

R2003 49D9R2F-GP

49D9R2F-GP

I2C1_S DA [62 ]

I2C1_S CL [62 ]

3

R2027

1 2

DY

SATA_ODD_PWRGT [56]

SATA_ODD_DA#[56]

TP2003TP2003

1

0R2J-2-GP

H_THERMTRIP# [36] H_RCIN# [24]

INT_S ERIRQ [24]

Layout Note:

1.Referenced "continuous" VSS plane only.

2.Avoid routing next to clock pins or noisy signals.

3. Trace width: 12~15mil

4. Isolation Spacing: 12mil

5. Max length: 500mil

3D3V_S0

RN2002

SRN10KJ-6-GP

H_RCIN#

INT_S ERIRQ KB_DET#

I2C0_S DA I2C0_S CL

HSIOPC

I2C1_S DA I2C1_S CL

R2007

8 7 6

SRN10KJ-5-GP

SRN10KJ-5-GP RN2007

RN2007

1 2 3

1 2

RN2008

1

DY

2 3

SRN10KJ-5-GP

1 2 3 45

3D3V_S0

4

100KR2J-1-GP

4

3D3V_S0

2

Title

Size Document Number Rev

A2

Date: Sheet of

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (GPIO/MISC)

Janus HSW 40/50/70

1

A00

20 104Friday, February 07, 2014

A00

SSID = CPU

5

4

3

2

1

DSW

3D3V_S5_PCH

+3.3A_DSW_PRTCSUS

C2105

SC1U10V2KX-1GPDYC2105

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

12

+V1.05DX_MODPHY_PCH

+V1.05S_AIDLE

+V1.05S_AUSB3PLL

+V1.05S_ASATA3PLL

TP2102TP2102

TP2107TP2107

TP2108TP2108

TP2103TP2103 TP2104TP2104 TP2101TP2101

TP_VCCAPLLOPI_VAL

1

+V1.05S_APLLOPI

+V1.05A_VCCUSB3SUS

1

+V3.3A_1.5A_HDA

+V1.05A_USB2SUS

1

+V3.3A_PSUS

+V3.3A_DSW_P

12

C2123

SC10U6D3V3MX-GP

+V1.05S_AXCK_DCB

+V1.05S_AXCK_LCPLL

+V1.05S_SSCF100

+V1.05S_SSCFF

TP_V1.05S_SSCF100

1

TP_V1.05S_AXCK_DCB

1

TP_V1.05S_SSCFF

1

+V3.3A_PSUS

+V3.3S_PCORE

B18 B11

Y20

AA21

W21

AH14

AH13

AC9 AA9

AH10

J18 K19 A20

J17 R21

T21 K18 M20 V21

AE20 AE21

K9

L10

M9 N8 P9

J13

V8

W9

CPU1M

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD#Y20 VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD#K18 RSVD#M20 RSVD#V21 VCCSUS3_3 VCCSUS3_3

HSIO

OPI

USB3

HDA

VRM

GPIO/LPC

LPT LP POWER

HSW_ULT_DDR3L

RTC

SPI

CORE

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

USB2

13 OF 19

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP#AG19 DCPSUSBYP#AG20

VCCASW

DCPSUS1#AD10

DCPSUS1#AD8

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO VCCSDIO

DCPSUS4

RSVD#AC20

VCC1_05

AH11 AG10 AE7

Y8

AG14 AG13

J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8

J15 K14 K16

U8 T9

AB8

AC20 AG16 AG17

D D

1D05V_S0

R2105

1 2

0R0402-PAD

DY

+V3.3A_1.5A_HDA3D3V_S5_PCH

R2108

1 2

0R0603-PAD-1-GP-U

3D3V_S5 3D3V_S0

C C

1D05V_S0

R2101

1 2

0R0402-PAD

R2117

1 2

0R0402-PAD

DY

12

+V3.3A_DSW_P

C2136

C2136 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

+V1.05S_SSCF100

C2137

SC1U10V2KX-1GP

C2116

R2112

1 2

0R0402-PAD

C2109

+VCCRTCEXT

1D05V_S0

+V1.05S_CORE_PCH

+1.05M_ASW

+V1.05A_SUS_PCH

1D5V_S0

+V3.3S_1.8S_LPSS_SDIO

+V1.05A_AOSCSUS

TP_V1.05S_APLLOPI

SCD1U16V2KX-3GP

R2102

1 2

12

0R0603-PAD-1-GP-U

SC1U10V2KX-1GP

RTC_AUX_S5

1 2

C2110

Broadwell(#514849): No series resistors (0 ohm). Haswell(#486713):Series resistor:5 ohm.

R2110

R2110 5D1R2F-GP

5D1R2F-GP

1 2

BDW/HSW

1

3D3V_S0

PCH_VCCDSW_R+PCH_VCCDSW

TP2106TP2106

WistronSKB: match Intel design_20130417 (#489999_2013WW15)

12

TP2109TP2109

1

TP2105TP2105

1

C2135

SC1U10V2KX-1GP

C2135

SC1U10V2KX-1GP

12

Intel Recommend

3D3V_S5

12

C2147

SCD1U16V2KX-3GP

C2114

SC1U10V2KX-1GP

1 2

C2101

C2128

SC1U10V2KX-1GP

C2128

SC1U10V2KX-1GP

C2101

1 2

SCD47U6D3V2KX-GP

1D05V_S0

+V3.3A_DSW_P +PCH_VCCDSW

HASWELL-6-GP-U

1D05V_S0

B B

A A

R2118

1 2

0R0402-PAD

12

5

+V1.05S_SSCFF

C2138

SC1U10V2KX-1GP

+V1.05S_SSCFF

R2123

HSIOPC[20]

4

1 2

DY

0R2J-2-GP

5V_S5

1D05V_S0

DY

HSIOPC_R

12

C2141

C2141 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

HASWELL-6-GP-U

1 2

Non-HSIO

9

U2101

ON

1

VDD

2

D#2

3

D#3 D#44S#5

DY

SLG59M1470VTR-GP

74.59147.093

3

R2122

0R5J-5-GP

GND

S#7 S#6

1D05V_HSIO1D05V_S0

+V3.3S_1.8S_LPSS_SDIO

1 2

0R0402-PAD

1D05V_HSIO

R2114

8 7 6 5

HSIO_OUT

R2114 0R5J-5-GP

0R5J-5-GP

1 2

DY

12

C2142

C2142 SC10U10V5KX-2GP

SC10U10V5KX-2GP

2

Title

Size Document Number Rev

A3

Date: Sheet of

12

CPU (POWER2)

Janus HSW 40/50/70

0R0402-PAD

C2104

C2104 SC1U10V2KX-1GP

SC1U10V2KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

R2103

1

3D3V_S0

A00

21 104Friday, February 07, 2014

A00

5

4

3

2

1

SSID = PCH

D D

HSW_ULT_DDR3L

CPU1Q

HSW_ULT_DDR3L

17 OF 19

DC_TEST_AY2_AW2

TP2201TP2201

TP2204TP2204

C C

B B

TP_DC_TEST_AY60

1

DC_TEST_AY61_AW61 DC_TEST_AY62_AW62

1

DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_B62_B63

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

HASWELL-6-GP-U

CPU1R

AT2

RSVD#AT2

AU44

RSVD#AU44

AV44

RSVD#AV44

D15

RSVD#D15

F22

RSVD#F22

H22

RSVD#H22

J21

RSVD#J21

HASWELL-6-GP-U

HSW_ULT_DDR3L

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

18 OF 19

RSVD#N23 RSVD#R23

RSVD#T23

RSVD#U10

RSVD#AL1

RSVD#AM11

RSVD#AP7 RSVD#AU10 RSVD#AU15

RSVD#AW14

RSVD#AY14

DC_TEST_A3_B3

A3

TP_DC_TEST_A4DC_TEST_AY3_AW3

A4

TP_DC_TEST_A60

A60

DC_TEST_A61_B61

A61

TP_DC_TEST_A62TP_DC_TEST_B2

A62

TP_DC_TEST_AV1

AV1

TP_DC_TEST_AW1

AW1

DC_TEST_AY2_AW2

AW2

DC_TEST_AY3_AW3

AW3

DC_TEST_AY61_AW61DC_TEST_C1_C2

AW61

DC_TEST_AY62_AW62

AW62

TP_DC_TEST_AW63

AW63

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

TP2202TP2202

1

TP2203TP2203

1

TP2205TP2205

1

TP2206TP2206

1

TP2207TP2207

1

TP2208TP2208

1

Wistron Corporation

A A

Title

CPU (RSVD)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

CPU (RSVD)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

22 104Friday, February 07, 2014

1

A00

5

4

3

2

1

SSID = PCH

D D

HSW_ULT_DDR3L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HSW_ULT_DDR3L

CPU1N

A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56

AA1 AA58 AB10 AB20 AB22

AB7 AC61 AD21

AD3 AD63

C C

B B

AE10

AE5 AE58 AF11 AF12 AF14 AF15 AF17 AF18

AG1

AG11 AG21 AG23 AG60 AG61 AG62 AG63

AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

HASWELL-6-GP-U

14 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

AP22 AP23 AP26 AP29

AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

HSW_ULT_DDR3L

CPU1O

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HASWELL-6-GP-U

15 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU(VSS)

Janus HSW 40/50/70

23 104Friday, February 07, 2014

1

A00

5

4

3

2

1

SSID = KBC

D D

C C

B B

1D05V_S0

R2401

1 2

0R0402-PAD

Layout Note:

Need very close to EC

3D3V_S0

C2412SCD1U16V2KX-3 GP C2412SCD1U16V2KX-3GP

12

C2413

DY

SC2D2U10V3KX-1GP

ALL_SYS_PWRGD assert, delay 10ms; PCH_PWROK assert.

GC6_FB_EN[20,75,76,83]

R2417

1 2

LCD_TST[52]

0R0402-PAD

LCD_TST_EN[52]

TP_LID_CLOSE#[62]

DGPU_PWROK[15,82,83]

ALL_SYS_PWRGD de-assert, delay 100ms; SYS_PWROK assert.

LVDS backlight Control from PS8625

TOUCH_PANEL_INTR#[52]

INT_TP#[15,20,62]

3D3V_AUX_KBC

R2453

12

DY

10KR2J-3-GP

L_BKLT_EN[15]

eDP backlight Control from PCH

1 2

0R2J-2-GP

EC_AGND

1 2

0R2J-2-GP

1 2

0R2J-2-GP

R2437

OPS

R2411

1 2

DY

R2448 0R2J-2-GPR2448 0R2J-2-GP

1 2

R2444

1 2

0R0402-PAD

R2451

DY

R2450

DY

EC_VTT

12

C2401

C2414

1 2

OVER_CURRENT_P8#[76]

0R2J-2-GP

SCD1U16V2KX-3GP

AD_IA[44]

SCD1U16V2KX-3GP

PCH_PWROK[17,26,36] PM_SLP_SUS#[17,38] BOOST_MON[44]

FAN1_DAC_1[26]

AD_IA_HW[44]

IMVP_PWRGD[7,46]

BAT_SCL[43,44] BAT_SDA[43,44]

SML1_CLK[18,26,76]

SML1_DATA[18,26,76]

PM_LAN_ENABLE[30]

RTCRST_ON[19]

ALL_SYS_PWRGD[36]

PWR_CHG_AD_OFF[42]

AD_IA_HW2[44]

BLON_OUT[52]

FAN_TACH1[26]

PM_PWRBTN#[17,96]

PM_SLP_S3#[17,36,48,49,51]

EC_BRIGHTNESS[52]

KBC_BEEP[27]

BATT_WHITE_LED#[61]

AC_IN_KBC#[42]

KB_BL_CTRL[62]

CHG_AMBER_LED#[61]

KBC_DPWROK[17]

VD_IN1[26]

VD_OUT1#[26]

AC_PRESENT[17,76]

SYS_PWROK[17,96]

USB_PWR_EN#[35]

WIFI_RF_EN[58] PM_SUSWARN#[17]

TOUCH_PANEL_INTR_KBC#

E51_TxD[58]

PM_CLKRUN#_EC[17]

AMP_MUTE#[27]

12

R2447

R2447 100KR2J-1-GP

100KR2J-1-GP

VBAT

C2404

SCD1U16V2KX-3GP

PSID_EC[42]

TPCLK[62]

TPDATA[62]

1 2

1KR2J-1-GP

L_BKLT_EN_EC

3D3V_AUX_KBC_VCC

12

C2405

DY

SC2D2U10V3KX-1GP

EC_AGND

19 46 76 88

115

102

4

EC_VTT

12

97

PCB_VER_AD

98

99 100 108

96

95

MODEL_ID_DET

94

101 105

GC6_FB_EN_KBC

106 107

BAT_SCL

70

BAT_SDA

69

67

68 119 120

PROCHOT_EC

24

LCD_TST_EN

28

TP_LID_CLOSE#_KBC

26

ECSWI#_KBC

123

72

71

10

11

25

27

31 117

DGPU_PWROK_KBC

R2449

INT_T P#_K BC

L_BKLT_EN_EC

VD1_EN#

63

64

32 118

62

65

22

16

81

66

104

110 112

84

83

82

79

124 121 111

9

8

30

EC_GPIO47 High Active

PROCHOT_EC

12

R2442

100KR2J-1-GP

DY

12

DY

C2407SCD1U16V2KX-3 GPDYC2407SCD1U16V2KX-3 GP

C2406SCD1U16V2KX-3 GP C2406SCD1U16V2KX-3GP

KBC24

VCC VCC VCC VCC VCC

AVCC

VDD

VTT

KBSOUT0/GPOB0/SOUT_CR/JENK#

GPIO90/AD0 GPIO91/AD1 GPIO92/AD2 GPIO93/AD3 GPIO05/AD4 GPIO04/AD5 GPIO03/EXT_PURST#/AD6 GPIO07/AD7/VD_IN2

GPIO94/DA0 GPIO95/DA1 GPIO96/DA2 GPIO97/DA3

GPIO17/SCL1/N2TCK GPIO22/SDA1/N2TMS GPIO73/SCL2/N2TCK GPIO74/SDA2/N2TMS GPIO23/SCL3/N2TCK GPIO31/SDA3/N2TMS GPIO47/SCL4A/N2TCK GPIO53/SDA4A/N2TMS GPIO51/TA3/N2TCK GPIO67/SOUT1/N2TMS

GPIO37/PSCLK1 GPIO35/PSDAT1 GPIO26/PSCLK2 GPIO27/PSDAT2 GPIO50/PSCLK3 GPIO52/PSDAT3

GPIO56/TA1 GPIO20/TA2/IOX_DIN_DIO GPIO14/TB1 GPIO01/TB2

GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM GPIO32/D_PWM GPIO45/E_PWM/DTR1#_BOUT1 GPIO40/F_PWM/1_WIRE/RI1# GPIO66/G_PWM/PSL_GPIO66 GPO33/H_PWM/VD1_EN#

GPIO80/VD_IN1

GPIO82/IOX_LDSH/VD_OUT1 GPIO84/IOX_SCLK/VD_OUT2

GPIO77/SPI_MISO GPIO76/SPI_MOSI GPIO75/SPI_SCK GPIO02/SPI_CS#

GPIO10/LPCPD# GPIO85/GA20 GPIO83/SOUT_CR GPIO65/SMI#

GPIO11/CLKRUN# GPIO55/CLKOUT/IOX_DIN_DIO

NPCE285PA0DX-GP

071.00285.000G

R2438

R2438 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q2401

G

D

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

KBSOUT10/P80_CLK/GPIOC2 KBSOUT11/P80_DAT/GPIOC3

KBSOUT14/GP(I)O62/XORTR#

KBSOUT15/GPIO61/XOR_OUT

PSL_IN2#/GPI06/EXT_PURST#

3D3V_AUX_KBC

R2402

1 2

0R0603-PAD-1-GP-U

R2403

2D2R3-1-U-GP

1 2

PCB_VER_AD

12

DY

C2408SCD1U16V2KX-3 GP C2408SCD1U16V2KX-3GP

C2410SCD1U16V2KX-3 GP C2410SCD1U16V2KX-3GP

C2409SCD1U16V2KX-3 GPDYC2409SCD1U16V2KX-3 GP

C2411SC2D2U10V3KX-1GP C2411SC2D2U10V3KX-1GP

KROW0

54

KBSIN0/GPIOA0/N2TCK KBSIN1/GPIOA1/N2TMS

KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7

KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS

KBSOUT3/GPIOB3/TDI

KBSOUT4/GPOB4

KBSOUT5/GPIOB5/TDO

KBSOUT6/GPIOB6/RDY#

KBSOUT7/GPIOB7 KBSOUT8/GPIOC0

KBSOUT9/GPOC1/SDP_VIS#

KBSOUT12/GPO64/TEST#

KBSOUT13/GP(I)O63/TRIST#

GPIO60/KBSOUT16/DSR1# GPIO57/KBSOUT17/DCD1#

LFRAME#/GPIOF6 LRESET#/GPIOF7

GPIOC6/F_CS0#

GPIOC7/F_SCK

GPIO30/F_WP#/RTS1#

GPIO41/F_WP#/PSL_GPIO41

GPIOC5/F_SDIO/F_SDIO0

GPIOC4/F_SDI/F_SDIO1 GPIO81/F_WP#/F_SDIO2

GPIO00/32KCLKIN/F_SDIO3

PSL_IN1#/GPI70

PSL_OUT#/GPIO71

ECSCI#/GPIO54

KBRST#/GPIO86

SERIRQ/GPIOF0

GPIO36/TB3/CTS1#

GPIO44/SCL4B PSL_IN4#/GPI43 PSL_IN3#/GPI42

GPIO46/SDA4B/CIRRXM

GPIO87/CIRRXM/SIN_CR

GPIO34/SIN1/CIRRXL

Layout Note:

Connect GND and AGND planes via either 0R resistor or connect directly.

H_PROCHOT#_EC

LAD0/GPIOF1 LAD1/GPIOF2 LAD2/GPIOF3 LAD3/GPIOF4 LCLK/GPIOF5

EXT_RST#

VBKUP

VCORF

GPIO24

1 2

VSBY

PECI

GND GND GND GND GND GND

AGND

R2440

0R0402-PAD

55 56 57 58 59 60 61

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

126 127 128 1 2 3 7

90 92 109 80 87 86 91 77

73 93 74

29 85 122

75 114 44 13 125 6 15

21 20 17 23

113 14

5 18 45 78 89 116

103

DY

EC_AGND

12

C2421

C2421 SC47P50V2JN-3GP

SC47P50V2JN-3GP

KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

PLT_RST#_EC

EC_SPI_CS#_C EC_SPI_CLK_C

BAT_IN# EC_SPI_DI_C EC_SPI_DO_C

SUSCLK_KBC

PSL_IN1# PSL_IN2# PSL_OUT#

ECSCI#_KBC ECRST#

EC_VBKUP KBC_VCORF PECI

ECSMI#_KBC

EC_AGND

C2402

12

A00

DY

1 2

SCD1U16V2KX-3GP

0R0402-PAD

0R0402-PAD R2435

R2435

VBAT

12

R2404

64K9R2F-1-GP

12

R2406

R2406 100KR2F-L1-GP

100KR2F-L1-GP

EC_AGND

KROW[0..7] [62]

KCOL[0..16] [62]

3D3V_AUX_KBC

1 2

LPC_AD[3..0] [18,65]

CLK_PCI_KBC [18] LPC_FRAME# [18,65]

33R2J-2-GPR2419 33R2J-2-GPR2419

12

33R2J-2-GPR2420 33R2J-2-GPR2420

12

R2422 33R2J-2-GPR2422 33R2J-2-GP

12

R2423 33R2J-2-GPR2423 33R2J-2-GP

12

R2441

1 2

0R0402-PAD

Layout Note:

Need very close to EC

H_RCIN# [20]

R2428

1 2

0R0402-PAD

INT_SERIRQ [20]

RSMRST#_KBC [17]

PM_SLP_S4# [17,49] BOOST_MODE# [44] LID_CLOSE# [64] ME_UNLOCK [19]

PCIE_WAKE# [17,30] S5_ENABLE [36]

VBAT

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

X01

X02

X03 2.304V

A00

Reserved

Reserved 100.0K 215.0K 1.048V

R2452

R2452 1KR2J-1-GP

1KR2J-1-GP

TP_ON# [62]

SPI_CS0#_R [18,25] SPI_CLK_R [18,25] CAP_LED# [62] BAT_IN# [42,43,44] SPI_SI_R [18,25] SPI_SO_R [18,25] PM_SUSACK# [17] SUS_CLK [17]

3D3V_AUX_S5 RTC_AUX_S5

1 2

R2429

C2422

SC100P50V2JN-3GPDYC2422

SC100P50V2JN-3GP

43R2J-GP

12

DY

D2401

LID_CLOSE#

K A

RB751V-40-H-GP 83.R2004.H8F

D2402

K A

DY

RB751V-40-H-GP 83.R2004.H8F

100.0KX00

100.0K

100.0K 1.358V

C2415

DY

SC220P50V2KX-3GP

1 2

C2416

SC1U10V2KX-1GP

1 2

H_PECI [4]

Layout Note:

Need very close to EC

TOUCH_PANEL_INTR# [52]

TP_LID_CLOSE# [62]

PURE_HW_SHUTDOWN#[26,36,76]H_PROCHOT# [4,42,44,46]

R2416

1 2

0R0402-PAD

10KR2J-3-GP

3D3V_AUX_S5

R2439

12

LMBT3906LT1G-1-GP

3.0V

10.0K

2.75V

20.0K

2.48V

33.0K

47.0K

2.24V

64.9K

2.0V

76.8

1.87V

1.65VReserved

100.0K

143.0K

174.0KReserved 100.0K

1.204V

PLT_RST# [17,30,36,52,58,65,73,96]

Power Switch Logic(PSL)

KBC_PWRBTN#[61]

AC_IN#[44]

PSL_OUT#

R2424

0R2J-2-GP

1 2

ECRST#

DY

C2418

SC1U10V2KX-1GP

12

E

DY

B

Q2404

C

64K9R2F-1-GP

R2427

1 2

0R0402-PAD

R2430

1 2

0R0402-PAD

R2446

Cedar_UMA

MODEL_ID_DET

3D3V_AUX_S5

R2432

1 2

1KR2J-1-GP

1 2

R2445

12

57K6R2F-GP

Cedar_OPS

C2403

R2425

R2425 330KR2J-L1-GP

330KR2J-L1-GP

PSL_IN2#

PSL_IN1#

SCD1U16V2KX-3GP

KBC_ON#_GATE_L

MODEL_ID_DET(GPIO07)

Janus-OPS

12

1 2

DY

EC_AGND

12

Janus_OPS

12

Janus-UMA

R2405

TBD

10KR2F-2-GP

TBD 2.702V TBD TBD TBD TBD TBD

Cedar-OPS CedarUMA

TBD

R2407

TBD

100KR2F-L1-GP

TBD TBD TBD TBD TBD TBD TBD

3D3V_AUX_S5 3D3V_AUX_S5

R2431

R2431 330KR2J-L1-GP

330KR2J-L1-GP

1 2

R2433

R2433 20KR2F-L-GP

20KR2F-L-GP

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

100.0K 3.0V

100.0K

ECSCI#_KBC

ECSMI#_KBC

ECSWI#_KBC

BAT_SCL BAT_SDA

ECRST#

AC_IN# BAT_IN#

AC_IN_KBC#

FAN_TACH1

TOUCH_PANEL_INTR#

Touch Panel PH internally.

LID_CLOSE#

USB_PWR_EN#

C2417 SCD1U16V2KX-3GPC2417 SCD1U16V2KX-3GP

1 2

G

Q2402

Q2402 DMP2130L-7-GP

DMP2130L-7-GP

84.02130.031

2ND = 84.03413.A31

G

S

G

D

Q2403

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

KBC_ON#_GATE

10.0K(64.10025.6DL)

13.7K(64.13725.6DL)

17.8K(64.17825.6DL)

22.1K(64.22125.6DL)

27.0K(64.27025.6DL)

32.4K(64.32425.6DL)

37.4K(64.37425.6DL)

43.2K(64.43225.6DL)

57.6K(64.57625.6DL)

64.9K(64.64925.6DL)

73.2K(64.73225.6DL) 1.905V

82.5K(64.82525.6DL) 1.808V

93.1K(64.93125.6DL) 107K(64.10735.6DL) 120K(64.12035.6DL) 137K(64.13735.6DL) 154K(64.15435.6DL) 200K(64.20035.6DL) 1.099V 232K(64.23236.6DL)

R24080R0402-PAD-1-GP R24080R0402-PAD-1-GP

1 2

R24090R0402-PAD-1-GP R24090R0402-PAD-1-GP

1 2

R24100R0402-PAD-1-GP R24100R0402-PAD-1-GP

1 2

RN2401

1234

SRN4K7J-8-GP

R2418 10KR2J-3-GPR2418 10KR2J-3-GP

1 2

3D3V_AUX_KBC

R2413 100KR2J-1-GP

1 2

DY

R2414 10KR2J-3-GPR2414 10KR2J-3-GP

1 2

R2426 100KR2J-1-GPR2426 100KR2J-1-GP

1 2

R2415 10KR2J-3-GPR2415 10KR2J-3-GP

1 2

R2443 10KR2J-3-GP

1 2

DY

R2421 100KR2J-1-GP

1 2

DY

R2412 100KR2J-1-GP

1 2

DY

R2434

DY

0R2J-2-GP

1 2

3D3V_AUX_KBC

D

EC_SCI# [18,20]

EC_SMI# [19]

EC_SWI# [20]

3D3V_AUX_KBC

3D3V_S0

3D3V_S5

3D3V_AUX_KBC

12

R2436

R2436 10KR2J-3-GP

10KR2J-3-GP

S5_ENABLE

2.902V

2.801V

2.598V

2.492V

2.402V

2.201V49.9K(64.49925.6DL)

2.093V

2.001V

1.709V

1.594V

1.499V

1.392V

1.299V

0.994V

A A

Title

Size Document Number Rev

Size Document Number Rev A1

A1

Friday, February 07, 2014

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

KBC Nuvoton NPCE885

Janus HSW 40/50/70

24 104

A00

5

SSID = Flash.ROM

4

3

2

1

R2501

4K7R2J-2-GP

12

DY

8 7

5

3D3V_S5

1 2

4

DY

1

3D3V_S5

SPI_HOLD# SPI_CLK_R SPI_SI_R

RN2501

RN2501 SRN4K7J-8-GP

SRN4K7J-8-GP

2 3

SPI25

1

CS#

2

DO/IO1

3

WP#/IO2

4

GND

W25Q64FVSSIQ-GP

72.25Q64.K01

VCC

HOLD#/IO3

CLK

DI/IO0

3D3V_S5

8 7 6 5

EC2501

SC4D7P50V2CN-1GP

72.25Q64.K01

72.25647.00A

C2501

DY

C2501

12

DY

SC10U10V5KX-2GP

QUAD/DUAL fast read DUAL fast readSource

SPI Flash ROM(8M) for PCH

D D

SPI_CS0#_R[18,24]

SPI_SO_R[18,24]

SPI_WP#[18 ]

EC2502

SC4D7P50V2CN-1GP

C C

SPI_CS0#_R SPI_SO_R SPI_WP#

EC2502

SKT25

1 2

DY

3 6 4

SKT-G6179HT0321-001-GP

62.10089.011

072.25B64.0001

3D3V_S5

12

DY

EC2503

EC2503 SC10P50V2JN-4GP

SC10P50V2JN-4GP

O

12

C2502

C2502 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SPI_HOLD# [18] SPI_CLK_R [18,24] SPI_SI_R [18,24]

O

OO

Single SPI shared flash connection (SPI Quad I/O mode)

Refer to "NCPE985x/ NPCE995x board design reference guide"

SSID = RBATT

B B

A A

5

AFTP2502AFTP2502

RTC1

PWR GND

NP1 NP2

BAT-060003HA002M213ZL-GP-U1

62.70014.001

2nd = 62.70001.061

3rd = 20.F2316.002

1 2 NP1 NP2

+RTC_VCC

1

D2501

R2502

1KR2J-1-GP

AFTP2501AFTP2501

1

12

4

12

R2504

R2504 10MR2J-L-GP

10MR2J-L-GP

RTC_PWR

1

2

BAS40C-2-GP

75.00040.07D

2nd = 75.00040.C7D

3rd = 75.00040.A7D

Q2505

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

D

RTC_AUX_S5+RTC_VCC 3D3V_AUX_S5

3

12

C2503

SCD47U6D3V2KX-GP

DY

3

RTC_DET# [20]

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet of

2

Date: Sheet of

Flash/RTC

Janus HSW 40/50/70

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

25 104

1

A00

5

SSID = Thermal

4

3

2

1

Fan controller1

12

FAN1

5 3 2

1

4

AFTP2803AFTP2803

FAN_TACH1_C FAN_VCC1

26 104

5V_S0

C2605

12

C2611

SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP

1

A00

FAN261

R2605

0R2J-2-GP

1 2

5V_S0

FAN_TACH1[24]

SC4D7U6D3V3KX-GP

EC2602

12

SC10P50V2JN-4GP

2

0R2J-2-GP

DY

FAN_VCC1

C2604

FAN_TACH1

FAN_VCC1

12

DY

SCD1U16V2KX-3GP

12

DY

EC2601

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

6

5

8 7

ALERT#

6 5

3D3V_S0 3D3V_S0

2N7002KDW-GP

1

2

DY

34

Q2601

Q2602

G

D

S

T8

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

THERM_SYS_SHDN#

Close to Thermal sensor

1

T8

4

DY

23

12

DY

RN2602

RN2602 SRN2K2J-1-GP

SRN2K2J-1-GP

12

DY

C2608

SCD1U16V2KX-3GP

12

DY

C2610

12

R2609

24K9R2F-L-GP

R2610

NTC-100K-8-GP

THM_SML1_DATA

THM_SML1_CLK

THM_SML1_CLK THM_SML1_DATA

C2609

SCD1U16V2KX-3GP

PURE_KBCT8

1 2

R2612 0R2J-2-GP

SCD1U16V2KX-3GP

3D3V_AUX_KBC

R2602

1 2

T8

0R2J-2-GP

3D3V_AUX_KBC3D3V_AUX_S5

12

3

Layout Note:

Signal Routing Guideline: Trace width = 15mil

PURE_HW_SHUTDOW N# [24,36,76]

VD_OUT1#

R2607 2KR2F-3-GP

1 2

T8

Close to KBC VD_IN1 for system thermal sensor

R2608

24K9R2F-L-GP

C2612

12

SCD1U16V2KX-3GP

VD_IN1_C

12

C2613

SC100P50V2JN-3GP

VD_OUT1# [24]

VD_IN1 [24]

R2611

1 2

0R0402-PAD

FAN1_DAC_1[24]

Layout Note:

Need 10 mil trace width.

DY

D D

3D3V_S0

SML1_DATA[18,24,76]

84.2N702.A3F

2nd = 84.2N702.E3F

12

C2601

C2602

DY

84.T3904.H11

C C

B B

A A

Q2603

C

T8

E

LMBT3904LT1G-GP

2.System Sensor, Put on palm rest

3D3V_S0

R2603 18K7R2F-GP

R2604 2KR2F-3-GP

12

C2606

DY

1 2

T8

1 2

T8

5

C2606 SC470P50V3JN-2GP

SC470P50V3JN-2GP

B

Layout Note:

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

C2602

T8

SCD1U16V2KX-3GP

SC10U6D3V3MX-GP

NCT7718_DXP

12

T8

NCT7718_DXN

Layout Note:

C2812 close U2801

ALERT#

T_CRIT#

C2607

C2607 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

DY

12

T_CRIT#

R2601

R2601 0R2J-2-GP

0R2J-2-GP

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

SML1_CLK[18,24,7 6]

THM26

1

VDD

2

D+

3

T8

DT_CRIT#4GND

NCT7718W-GP

74.07718.0B9

PCH_PWROK[17,24,36 ]

THERM_SYS_SHDN#

ALERT#

4

SCL SDA

FAN261

FON#

1

FON#

2

VIN

3

VOUT VSET4GND

AP2113MTR-G1-GP

74.02113.0E1

R2606

1 2

0R0402-PAD

D2601

KA

DY

RB551V30-GP

83.R5003.H8H

THERMAL NCT7718W/Fan

Janus HSW 40/50/70

Friday, February 07, 2014

GND GND GND

FAN_TACH1_C

FAN_VCC1

12

C2603

2nd = 20.F1295.003

DY

SC2200P50V2KX-2GP

AFTP2802AFTP2802 AFTP2801AFTP2801

8 7 6 5

ETY-CON3-8-GP

20.F1841.003

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1 1

1

5

www.vinaﬁx.vn

SSID = AUDIO

4

3

2

1

D D

3D3V_S0 +3V_AVDD

25mA

R2701

1 2

0R0402-PAD

1.5A

5V_S0 +5V_PVDD

R2702

1 2

0R0805-PAD-1-GP-U

R2704

1 2

0R0805-PAD-1-GP-U

C C

moat

3D3V_S0

1D5V_S0

R2705 0R0402-PADR2705 0R0402-PAD

1 2

R2710 0R2J-2-GP

1 2

DY

Azalia I/F EMI

EC2708

12

DY

SCD1U16V2KX-3GP

B B

SCD1U16V2KX-3GP

Layout Note:

Close pin41

HDA_CODEC_SDOUT HDA_CODEC_BITCLK

EC2709

12

DY

SCD1U16V2KX-3GP

12

C2701

SC4D7U6D3V3KX-GP

Close pin36

C2708

C2706

12

SC4D7U6D3V3KX-GP

+3V_1D5V_AVDD

AUD_AGND

C2709

C2707

12

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

Layout Note:

Close pin46

Speaker trace width >40mil @ 2W4ohm speaker power

12

C2715

SC4D7U6D3V3KX-GP

Close pin40

Layout Note:

AMP_MUTE#[24]

DMIC_CLK[52]

SC22P50V2JN-4GP

Close pin3

AUD_AGND

DMIC_DATA_R

DY

C2723

DY

1 2

C2712 SC10U6D3V3MX-GPC2712 SC10U6D3V3MX-GP

1 2

AUD_SPK_L+[29]

AUD_SPK_L-[29]

AUD_SPK_R-[29]

AUD_SPK_R+[29]

R2708

0R0402-PAD

TP2702TP2702

EC2701

SC10P50V2JN-4GPDYEC2701

SC10P50V2JN-4GP

12

DMIC_DATA[52]

HDA_CODEC_SDOUT[19]

HDA_CODEC_BITCLK[19]

HDA_SDIN0[19]

HDA_CODEC_SYNC[19]

HDA_CODEC_RST#[19,29]

+3V_1D5V_AVDD

+5V_PVDD

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R-

AUD_SPK_R+

+5V_PVDD

1

LINE1_VREFO_R[29]

LINE1_VREFO_L[29]

AUD_HP1_JACK_L[29]

AUD_HP1_JACK_R[29]

12

C2703

C2703 SC1U10V2KX-1GP

SC1U10V2KX-1GP

CBP

LDO2_CAP

EAPD#

COMBO-GPI

C2716

SC4D7U6D3V3KX-GP

R2714

1 2

0R0402-PAD

R27160R2J-2-GP R27160R2J-2-GP

1 2

SC1U10V2KX-1GP

+3V_AVDD

HDA27

37

CBP

38

AVSS2

39

LDO2-CAP

40

AVDD2

41

PVDD1

42

SPK-OUT-L+

43

SPK-OUT-L-

44

SPK-OUT-R-

45

SPK-OUT-R+

46

PVDD2

47

PDB

48

SPDIF-OUT/GPIO2

49

GND

ALC3234-CG-GP

+3V_AVDD

12

DMIC_DATA_R

DMIC_CLK_R

R27190R0402-PAD R27190R0402-PAD

1 2

R27200R2J-2-GP R27200R2J-2-GP

1 2

R27180R0402-PAD R27180R0402-PAD

1 2

HDA_CODEC_SYNC

HDA_CODEC_RST#

C2704

1 2

CPVEE

CBN

29

30

31

32

33

34

35

36

CBN

CPVEE

CPVDD

71.03234.003

DVDD1GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3DVSS4SDATA-OUT5BCLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10RESET#11PCBEEP

C2717

12

SCD1U16V2KX-3GP

CODEC_SDOUT_R

CODEC_BITCLK_R

HDA_CODEC_SDIN0

LINE1-VREFO-L

HPOUT-L/PORT-I-L

HPOUT-R/PORT-I-R

MIC2-VREFO

LINE1-VREFO-R

MIC2_R/PORT-F-R/SLEEVE

SPDIFO/FRONT_JD/ JD3/GPIO3

LDO3_CAP

C2718SC4D7U6D3V3KX-GP C2718SC4D7U6D3V3KX-GP

12

C2705

12

SC2D2U6D3V2MX-GP

AUD_VREF

28

VREF

MIC2_L/PORT-F-L/RING

C2719SCD1U16V2KX-3GP C2719SCD1U16V2KX-3GP

12

Reserved for ALC3234

12

R2711

R2711 100KR2J-1-GP

100KR2J-1-GP

12

C2702

SC4D7U6D3V3KX-GP

LDO1_CAP

25

26

27

AVSS1

AVDD1

LDO1-CAP LINE2_L/PORT-E-L

LINE2_R/PORT-E-R

LINE1_L/PORT-C-L

LINE1_R/PORT-C-R

NC#20

MIC-CAP

MONO-OUT

MIC2/LINE2_JD/JD2

HP/LINE1_JD/JD1

12

AUD_PC_BEEP

+3V_AVDD

MIC2_VREFO [29]

AUD_AGND

+5V_AVDD

AUD_AGND

24

23

22

21

V3D3_STB

20

MIC_CAP

19

18

17

16

JDREF

15

14

AUD_SENSE_A

13

moat

12

C2711

Layout Note:

Place close to Pin 26

AUD_AGND

SC4D7U6D3V3KX-GP

LINE1_L [29]

LINE1_R [29]

R2712 0R2J-2-GPR2712 0R2J-2-GP

1 2

SLEEVE [29]

RING2 [29]

AUD_SENSE

Layout Note:

Place close to Pin 13

1 2

C2710

SCD1U16V2KX-3GP

C2713 SC10U6D3V3MX-GPC2713 SC10U6D3V3MX-GP

1 2

R2707 20KR2F-L-GP

1 2

DY

1 2

R2709

200KR2F-L-GP

HDA_SPKR[20]

KBC_BEEP[24]

R2703

0R0603-PAD-1-GP-U

RN2701

2 3 1

SRN0J-6-GP

moat

EC2707 SC1KP50V2KX-1GP

1 2

DY

EC2706 SC1KP50V2KX-1GP

1 2

DY

EC2705 SCD1U25V2KX-GPEC2705 SCD1U25V2KX-GP

1 2

EC2704 SC1KP50V2KX-1GP

1 2

DY

EC2703 SCD1U25V2KX-GPEC2703 SCD1U25V2KX-GP

5V_S0+5V_AVDD

AUD_AGND

Layout Note:

AUD_AGND

AUD_SENSE [29]

4

AUD_AGND

3D3V_S5

Width>40mil, to improve Headpohone Crosstalk noise Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

HDA_SPKR_R

KBC_BEEP_R

2nd = 83.R2003.W81

3rd = 75.00054.A7D

3rd = 75.00054.A7D 4th = 83.R2003.V81

4th = 83.R2003.V81

1 2

Layout Note:

Tied at point only under Codec or near the Codec

AUD_SENSE_A

moat

D2701

2

1

BAT54C-7-F-3-GP

75.00054.E7D

0R0805-PAD-1-GP-U

R2722

100KR2J-1-GP

AUD_PC_BEEP_C

3

R2706

12

+3V_AVDD

C2720

1 2

R2717

R2717 1KR2J-1-GP

1KR2J-1-GP

AUD_PC_BEEP

SCD1U16V2KX-3GP

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Audio Codec ALC3234

Janus HSW 40/50/70

1

27 104Monday, February 10, 2014

A00

5

Title

Size Document Number Rev

A2

Date: Sheet of

4

3

2

Date: Sheet of

5

D D

4

3

2

1

C C

B B

A A

5

4

(Blanking)

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document Number Rev

A4

Date: Sheet of

2

Janus HSW 40/50/70

Reserved

28 104Friday, February 07, 2014

1

A00

5

SSID = AUDIO

4

3

2

1

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

AUD_SPK_R+_C

R29040R0603-PAD-1-GP-U R29040R0603-PAD-1-GP-U

12

SC100P50V2JN-3GPDYEC2906

SC100P50V2JN-3GP

DY

12

AUD_SPK_R-_C

R29030R0603-PAD-1-GP-U R29030R0603-PAD-1-GP-U

12

AUD_SPK_L+_C

R29020R0603-PAD-1-GP-U R29020R0603-PAD-1-GP-U

12

AUD_SPK_L-_C

R29010R0603-PAD-1-GP-U R29010R0603-PAD-1-GP-U

12

AUD_AGND

EC2906

EC2905

SC100P50V2JN-3GPDYEC2905

SC100P50V2JN-3GP

12

DY

LINE1-L_C

LINE1-L_R

AUD_SPK_R+[27]

AUD_SPK_R-[27 ] AUD_SPK_L+[27] AUD_SPK_L-[27]

RN2901

1

4

2 3

SRN2K2J-1-GP

R2908 10R2F-L-GPR2908 10R2F-L-GP

1 2

R2922 1KR2J-1-GPR2922 1KR2J-1-GP

1 2

R2912 4K7R2J-2-GPR2912 4K7R2J-2-GP

1 2

R2910 10R2F-L-GPR2910 10R2F-L-GP

1 2

R2921 1KR2J-1-GPR2921 1KR2J-1-GP

1 2

R2913 4K7R2J-2-GPR2913 4K7R2J-2-GP

1 2

12

DY

EC2901

SC2K2P50V3KX-GP

12

DY

EC2902

EC2903

SC2K2P50V3KX-GP

12

DY

EC2904

SC2K2P50V3KX-GP

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1

EC2908

SC100P50V2JN-3GPDYEC2908

SC100P50V2JN-3GP

R2920

10KR2J-3-GPDYR2920

10KR2J-3-GP

12

DY

EC2907

SC100P50V2JN-3GPDYEC2907

SC100P50V2JN-3GP

R2919

10KR2J-3-GPDYR2919

10KR2J-3-GP

12

DY

D D

C C

MIC2_VREFO[27]

RING2[27 ]

AUD_HP1_JACK_L[27 ]

LINE1_L[27 ]

LINE1_VREFO_L[2 7]

AUD_HP1_JACK_R[27]

LINE1_R[27]

LINE1_VREFO_R[27]

SLEEVE[27]

C2907

C2908

1 2

SC4D7U6D3V3KX-GP

1 2

SC4D7U6D3V3KX-GP

Speaker

SPK1

1

2 3 4

ACES-CON4-29-GP

20.F1639.004

2nd = 20.F1804.004

AUD_SPK_L-_C AUD_SPK_L+_C AUD_SPK_R-_C

AUD_SPK_R+_C

AUD_PORTA_L_R_B AUD_PORTA_R_R_B

AUD_SENSE

R29060R0603-PAD-1-GP-U R29060R0603-PAD-1-GP-U

12

R29070R0603-PAD-1-GP-U R29070R0603-PAD-1-GP-U

12

R29090R0603-PAD-1-GP-U R29090R0603-PAD-1-GP-U

12

R29110R0603-PAD-1-GP-U R29110R0603-PAD-1-GP-U

12

5

6

CONN Pin

Pin1

Pin2

Pin3

Pin4

AFTP2901AFTP2901

1

AFTP2902AFTP2902

1

AFTP2903AFTP2903

1

AFTP2904AFTP2904

1

AFTP2906AFTP2906

1

AFTP2907AFTP2907

1 1 1

RING2_R AUD_PORTA_L_R_B

JACK_PLUG

AUD_PORTA_R_R_B

SLEEVE_R

AFTP2908AFTP2908 AFTP2909AFTP2909

AUD_AGND

Combo Jack

Net name

SPK_R+

SPK_R-

SPK_L+

SPK_L-

HPMIC1

3 1

5 6 2 4

MS

AUDIO-JK430-GP

022.10002.0001

JACK_PLUG_DETJACK_PLUG_DET

10 mils

3D3V_S0

12

AUD_AGND

R2914

R2914 10KR2J-3-GP

10KR2J-3-GP

AUD_DELAY

0R0402-PAD

0R0402-PAD R2916

R2916

NON_DELAY

B B

AUD_AGND AUD_AGND

AUD_PORTA_R_R_B

AUD_PORTA_L_R_B

RING2_R

AUD_SENSE

SLEEVE_R

AZ2025-01H-R7G-GP

DY

AZ2025-01H-R7G-GP

DY

AZ2025-01H-R7G-GP

ED2905

1 2

4

ED2904

1 2

AZ2025-01H-R7G-GP

DY

AZ2025-01H-R7G-GP

ED2903

ED2902

DY

1 2

AZ2025-01H-R7G-GP

ED2901

DY

ED2901

1 2

A A

moat

5

12

R2915

DY

470KR2J-2-GP

AUD_AGND

4th = 84.DMN66.03F

3rd = 75.00601.07C

2nd = 84.2N702.E3F

84.2N702.A3F

S

5

D

6

U2901

DY

2N7002KDW-GP

3

R2918

100KR2J-1-GP

D

34

GG

MUTE_CTRLSLEEVE_CTRL

2

S

1

+3V_AVDD5V_PWR_2

12

DY

12

DY

Delay circuit

R2917

DY

0R3J-0-U-GP

C2901

C2901 SC1U10V2KX-1GP

SC1U10V2KX-1GP

JACK_PLUG

AUD_DELAY

12

AUD_AGND

10 mils

AUD_DELAY

R2905

R2905 100KR2J-1-GP

100KR2J-1-GP

AUD_DELAY

AUD_AGND

R2923

1 2

0R0603-PAD-1-GP-U

HDA_CODEC_RST# [19,27]

SLEEVE [27]

2

12

C2902

C2902 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

NON_DELAY

AUD_AGND

G

Q2901

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet of

S

AUD_DELAY

D

10 mils

Speaker/HPMIC

Janus HSW 40/50/70

AUD_SENSE [27]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

29 104

A00

5

4

3

2

1

Layout: For RTL8111G(S) * Place C302 1 to C3024 cl ose to each VDD10 pi n--3, 8, 22, 30 For RTL8106E * Place C302 1,C3022 close to each VDD10 pin- - 8, 30

D D

C C

B B

C3002,R3001: Only for RTL8111 LDO mode.

C3002

8111G

Layout: For RTL8111G(S) * Place C300 7 and C3008 clos e to each VDD33 pi n-- 11, 32 For RTL8106E * Place C300 3 and C3008 clos e to each VDD33 pi n-- 23, 32

3D3V_LAN_S5 VDDREG

12

C3007

8111G/LAN_SW

C3007

12

SCD1U16V2KX-3GP

40 mils

SCD1U16V2KX-3GP

1 2

68.4R71E.10G

12

C3008

SCD1U16V2KX-3GP

R3001

1 2

8111G

0R3J-0-U-GP

L3001

IND- 4D7U H-242 -GP

LAN_SW

12

8106E

LAN_SW

12

C3012SC4D7U6D3V3KX-GP

0R0603-PAD-1-GP-U

C3003

SCD1U16V2KX-3GP

C3008: close to Pin32 C3007: close to Pin11 C3003: close to Pin23

PM_LAN_ENABLE[24]

12

R3006

1 2

R3023

100KR2J-1-GP

C3019 SCD1U16V2KX-3GP

PLT_RST#[17,24,36,52,58,65,73,96]

12

C3021: colse to Pin8 C3022 close to Pin30 C3023: close to Pin3 C3024: close to Pin22

VDD10REGOUT

C3021 SCD1U16V2KX-3GPC3021 SCD1U16V2KX-3GP

C3009

84.T3904.H11

3D3V_S5

Q3001

G

S

2N7002K-2-GP

8111G/LAN_SW

C3022 SCD1U16V2KX-3GPC3022 SCD1U16V2KX-3GP

12

LAN_SW

12

SCD1U16V2KX-3GP

3D3V_LAN_S5

1

23

DY

4

Q402_1

Q3003 LMBT3904LT1G-GP

CBE

DY

R3016

1 2

0R0603-PAD

12

C3013

SCD1U16V2KX-3GP

LAN_ENABLE_R_C

D

8111G/LAN_SW

C3023 SCD1U16V2KX-3GP

12

C3010

SC4D7U6D3V3KX-GP

X5R

RN3001

RN3001 SRN10KJ-5-GP

SRN10KJ-5-GP

PLT_RST#_LAN

R3021

R3021 10KR2J-3-GP

10KR2J-3-GP

R3022

1 2

20KR2J-L2-GP

C3024 SCD1U16V2KX-3GP

12

85mA

12

PM_LAN_ENABLE_R

DMP2130L-7-GP

S

G

C3015

C3015 SC1U10V2KX-1GP

SC1U10V2KX-1GP

84.02130.031

2nd = 84.00102.031

3rd = 84.03413.B31

LAN CHIP (10/100/1000M & 10/100M co-lay)

RTL8111G-CGTRTL8111GUS-CG RTL8106EUS-CG RTL8106E-CG

71.08111.W03 71.08111.U03

SWR mode SWR mode

LDO mode

10/100/1000M 10/100/1000M

LAN_MDI0P[31] LAN_MDI0N[31]

LAN_MDI1P[31] LAN_MDI1N[31] LAN_MDI2P[31] LAN_MDI2N[31]

3D3V_LAN_S5

C3004

C3005

12

DY

SC4D7U6D3V3KX-GP

Layout: C3004: close to Pin32 C3005: close to Pin11

3D3V_LAN_S5 rise time must be controlled between 0.5 mS and 100 mS.

3D3V_LAN_S5

Q3004

D

G

12

C3017

SCD1U16V2KX-3GP

DY

71.08106.003

10/100M

071.08106.0003

LDO mode

10/100M

LANXOUT

LANXIN

VDD10

RTL8111G-CGT-1-GP-U1

LAN_MDI3P[31] LAN_MDI3N[31]

41

C3001

SC15P50V2JN-2-GP

R3032

R3032 2K49R2F-GP

2K49R2F-GP

1 2

LOM30

33

GND

1

MDIP0

2

MDIN0

3

AVDD10

4

MDIP1

5

MDIN1

6

(NC)

MDIP2

7

(NC)

MDIN2

8

AVDD10

3D3V_LAN_S5 CLK_LAN_REQ4#_R PCIE_PTX_LANRX_P4_C PCIE_PTX_LANRX_N4_C CLK_PCIE_LAN_P4 CLK_PCIE_LAN_N4

C3011

1 2

SC15P50V2JN-2-GP

X3001

X3001 XTAL-25MHZ-181-GP

XTAL-25MHZ-181-GP

82.30020.G71

2 3

1 2

3D3V_LAN_S5

32

AVDD33

(NC)

71.08111.U03

(071.08106.0003)

(NC)

MDIP39MDIN3

C3014

REGOUT VDDREG VDD10 PCIE_WAKE# ISOLAT E#

PLT_RST#_LAN

LAN_TXN_C_PCH _RXN4 LAN_TXP_C_PCH_R XP4

R3033

1 2

10KR2J-3-GP

C3014

SCD1U16V2KX-3GP

1 2

SCD1U16V2KX-3GP

1 2

C3016

C3018

1 2

SC1U10V2KX-1GP

C3025 SCD1U16V2KX-3GPC3025 SCD1U16V2KX-3GP

1 2

PCIE_WAKE# [17,24]

3D3V_S5

3D3V_LAN_S5

12

R3003

DY

10KR2J-3-GP

CLK_LAN_REQ#_EN

84.T3904.H11

Q3002 LMBT3904LT1G-GP

CBE

DY

R3005

1 2

0R0402-PAD

LAN_TXP_C_PCH_R XP4 LAN_TXN_C_PCH _RXN4

PCIE_PTX_LANRX_P4_C PCIE_PTX_LANRX_N4_C

LED0

TP3003 TPAD14-OP-GPTP3003 TPAD14-OP-GP

1

LED1

TP3002 TPAD14-OP-GPTP3002 TPAD14-OP-GP

RSET

31

(NC)

10

1

LANXIN

LANXOUT

VDD10

LED2

TP3001 TPAD14-OP-GPTP3001 TPAD14-OP-GP

1

25

30

28

27

26

LED2

LED0

RSET

AVDD10

CKXTAL229CKXTAL1

LED1/GPO

(LED1)

24

(NC)

REGOUT

(GPO)

(DVDD33)

(NC)

HSIP13HSIN14REFCLK_P15REFCLK_N

CLKREQ#

AVDD33

12

11

23

VDDREG

22

(NC)

DVDD10

21

LANWAKE#

20

ISOLATE#

19

PERST#

18

HSON

17

HSOP

071.08106.0003(DVC)/71.08111.U03(DVJ)

16

RTL8111G-CGT (71.08111.U03/LDO Mode): 10/100/1000M < 252 mW. RTL8106E-CG (071.08106.0003): 10/100M <70mW.

PCIE_WAKE#

CLK_PCIE_LAN_REQ4#[18,20]

PCIE_PRX_LANTX_P4 [16] PCIE_PRX_LANTX_N4 [16]

PCIE_PTX_LANRX_P4_C [16] PCIE_PTX_LANRX_N4_C [16]

CLK_PCIE_LAN_P4 [18] CLK_PCIE_LAN_N4 [18]

R3014

12

1KR2J-1-GP

R3015

R3015 15KR2J-1-GP

15KR2J-1-GP

3D3V_LAN_S5

12

R3004

R3004 10KR2J-3-GP

10KR2J-3-GP

DY

CLK_LAN_REQ4#_R

3D3V_S0

12

1.0V Source

RTL8111G-CGT (71.08111.U03)

A A

5

4

RTL8111GUS-CG (71.08111.W03)/ RTL8106EUS-CG (71.08106.003)

RTL8106E-CG (071.08106.0003)

LDO

SWR

LDO

R3001 C3002 C3023 C3024 C3007

OOOOO

XXO OO

X

XXX

3

L3001 C3012 C3019 C3010C3009 C3003

XXX XX

OOOOO

XX

XXXX

2

X

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

O

Title

LAN RTL8111/RTL8106

Size Document Number Rev

A2

Date: Sheet of

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

1

A00

30 104Friday, February 07, 2014

A00

5

4

3

2

1

SSID = LOM

LAN TransFormer (10/100/1000M & 10/100M co-lay)

Layout note: 30 mil spacing between MDI differential pairs.

D D

MCT0 MCT1 MCT2

XF3102 XFORM-12P-48-GP

1CT:1CT

LAN_MDI3N[30]

LAN_MDI3P[30]

LAN_MDI2N[30]

LAN_MDI2P[30]

C C

LOM_TCT

12

C3106

C3106 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

LAN_MDI1N[30]

LAN_MDI1P[30]

LAN_MDI0N[30]

LAN_MDI0P[30]

1 2

DY

EC3108 SC10P50V2JN-4GP

1 2

DY

EC3107 SC10P50V2JN-4GP

1 2

DY

EC3106 SC10P50V2JN-4GP

1 2

DY

EC3105 SC10P50V2JN-4GP

1 2

DY

EC3104 SC10P50V2JN-4GP

1 2

DY

EC3103 SC10P50V2JN-4GP

1 2

DY

EC3102 SC10P50V2JN-4GP

1 2

DY

EC3101 SC10P50V2JN-4GP

12

11

10

10/100/1000

1CT:1CT

8

7

9

XF3101

9

7

8

10

11

12

XFORM-12P-48-GP

68.68167.30D

1CT:1CT

1

MCT0

3

2

5

MCT1

4

6

MCT2

4

5

2

MCT3

3

1

MDO3-

MDO3+

MDO2-

MDO2+

MDO1-

MDO1+

MDO0-

MDO0+

MCT3

123

45

RN3101

RN3101 SRN75J-1-GP

SRN75J-1-GP

678

MCT

12

C3101

C3101 SC100P3KV8JN-2-GP

SC100P3KV8JN-2-GP

78.1013N.1AL

LAN_MDI0P LAN_MDI0N

LAN_MDI1P LAN_MDI1N

LAN_MDI2P LAN_MDI2N

LAN_MDI3P LAN_MDI3N

MDO0+

MDO0MDO1+ MDO2+ MDO2MDO1MDO3+ MDO3-

Follow Reference Schematic 0.01uF~0. 4uF

B B

2nd = 022.10001.0561

U3101

1

IN1

NC#10

2

IN2

NC#9

GND3GND

4

IN3

NC#7

5

DY

IN4

NC#6

TVWDF1004AD0-1-GP

75.01004.073

U3102

1

IN1

NC#10

2

IN2

NC#9

GND3GND

4

IN3

NC#7

5

DY

IN4

NC#6

TVWDF1004AD0-1-GP

75.01004.073

RJ45-8P-165-GP

9

CHASSIS#9

1

MDO0+

2

MDO0-

3

MDO1+

4

MDO2+

5

MDO2-

6

MDO1-

7

MDO3+

8

MDO3-

10

CHASSIS#10

RJ45

022.10001.0551

LAN_MDI0P

10

LAN_MDI0N

9 8

LAN_MDI1P

7

LAN_MDI1N

6

LAN_MDI2P

10

LAN_MDI2N

9 8

LAN_MDI3P

7

LAN_MDI3N

6

Layout: Place near RJ45

AFTP3107AFTP3107 AFTP3102AFTP3102 AFTP3101AFTP3101 AFTP3103AFTP3103 AFTP3104AFTP3104 AFTP3106AFTP3106 AFTP3105AFTP3105 AFTP3108AFTP3108

A A

5

4

3

1 1 1 1 1 1 1 1

2

MDO0+ MDO0MDO1+ MDO2+ MDO2MDO1MDO3+ MDO3-

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

XFOM&RJ45

31 104Monday, February 10, 2014

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

Wistron Corporation

A A

Title

(Reserved)Card Reader

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

(Reserved)Card Reader

Janus HSW 40/50/70

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

32 104Friday, February 07, 2014

1

5

D D

4

3

2

1

(Blanking)

C C

B B

Wistron Corporation

A A

Title

(Reserved)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

(Reserved)

2

Janus HSW 40/50/70

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

33 104Friday, February 07, 2014

1

5

SSID = USB

TR3401

D D

C C

USB_PN1[16]

USB_PP1[16]

1 2

FILTER-4P-6-GP

69.10103.041

34

4

USB_PN1_R

USB_PP1_R

U3401

1

2

75.09904.07C

AZC099-04S-1-GP

USB20_VCCA

USB_PN1_R USB_PP1_R

Note:ZZ.09904.07C01

I/O1

I/O4

GND

VDD

I/O23I/O3

DY

1

1 1

6

5

4

3

USB20_VCCA

DY

AFTP6205AFTP6205

AFTP6204AFTP6204 AFTP6209AFTP6209

12

C3406

SCD1U16V2KX-3GP

USB20_VCCA

USB_PN1_R USB_PP1_RUSB_PP1_R

USB2.0 Port2

USB2

6 8 1

2 3 4

75

SKT-USB8-14-GP

22.10321.E91

2

1

U3402

USB3_PRX_CTX_N0_C USB3_PRX_CTX_N0_C

TR3404

USB_PN0_C

R3408

0R0402-PAD

R3409

0R0402-PAD

34

12

USB_PP0_C

USB3_PTX_CRX_P0_C

USB3_PTX_CRX_N0_C

4

USB_PN0[16 ]

USB_PP0[16]

B B

C3404

USB3_PTX_CRX_P0_R

USB3_PTX_CRX_P0[16]

A A

USB3_PTX_CRX_N0[16]

1 2

SCD1U16V2KX-3GP

C3403

1 2

SCD1U16V2KX-3GP

5

USB3_PTX_CRX_N0_R

1 2

FILTER-4P-6-GP

69.10103.041

USB3_PRX_CTX_P0_C USB3_PRX_CTX_P0_C

USB3_PTX_CRX_N0_C USB3_PTX_CRX_N0_C USB3_PTX_CRX_P0_C USB3_PTX_CRX_P0_C

USB3_PRX_CTX_P0[16]

USB3_PRX_CTX_N0[16]

1

IN1

NC#10

2

IN2

NC#9

GND3GND

4

IN3

NC#7

5

IN4

NC#6

DY

TVWDF1004AD0-1-GP

75.01004.073

10 9 8 7 6

R3410

12

0R0402-PAD

R3411

12

0R0402-PAD

3

USB_PN0_C

USB_PP0_C

USB3_PRX_CTX_P0_C

USB3_PRX_CTX_N0_C

U3403

Note:ZZ.09904.07C01

1

I/O1

I/O4

2

GND

VDD

I/O23I/O3

DY

AZC099-04S-1-GP

75.09904.07C

USB3_PTX_CRX_P0_C USB3_PTX_CRX_N0_C

6

5

4

USB3_PTX_CRX_P0_C

USB3_PTX_CRX_N0_C USB_PN0_C

USB_PP0_C USB3_PRX_CTX_P0_C

USB3_PRX_CTX_N0_C

C3402SC4D7P50V2CN-1GPDYC3402SC4D7P50V2CN-1GP

12

DY

2

USB30_VCCC

C3401SC4D7P50V2CN-1GPDYC3401SC4D7P50V2CN-1GP

12

DY

12

C3405

DY

SCD1U16V2KX-3GP

USB3.0 Port1

USB1

10

9 1

8 2 7 3 6 4 5

11

SKT-USB13-151-GP

22.10341.Q21

Title

Size Document Number Rev

Custom

Date: Sheet of

Janus HSW 40/50/70

USB30_VCCC USB_PN0_C USB_PP0_C

12

13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

USB 3.0

AFTP6217AFTP6217

1

34 104Monday, February 10, 2014

1

AFTP6210AFTP6210

1

AFTP6211AFTP6211

1

AFTP6212AFTP6212

1

A00

5

4

3

2

1

5V_S5

12

C3502

SC1U10V2KX-1GP

D D

SC1U10V2KX-1GP

C C

C3505

C3510

DY

5V_S5

USB_PWR_EN#[24] USB_OC#0_1 [16,18]

12

U3502

1

GND

2

IN

3

EN1#

DY

EN2#4FLG2

AP2182SG-13-GP

74.02182.071

8

FLG1

7

OUT1

6

OUT2

5

U3503

5

4

074.06288.009B

5

4

074.06288.009B

IN

EN#

Active Low

SY6288DAAC-GP

IN

EN#

Active Low

SY6288DAAC-GP

OUT GND

OC#

U3504

OUT GND

OC#

1 2 3

USB20_VCCA

USB30_VCCC

USB30_VCCC USB20_VCCA

USB_OC#0_1 [16,18]USB_PWR_EN#[24]

USB30_VCCC

DY

USB20_VCCA

C3503

SCD1U16V2KX-3GP

R3501

12

100KR2J-1-GP

12

C3506

USB3.0 Port1

C3508

12

C3508

12

C3507SCD1U16V2KX-3GP C3507SCD1U16V2KX-3GP

SC1U10V2KX-1GP

USB2.0 Port2

12

C3514

SC1U10V2KX-1GP

SC22U6D3V5MX-2GP

C3509

C3512

2A

12

C3513

SC22U6D3V5MX-2GP

12

DY

12

TC3502

TC3502 SC100U6D3V6MX-GP

SC100U6D3V6MX-GP

78.10710.52L

TC3501

DY

SC100U6D3V6MX-GP

78.10710.52L

Layout Note: Close CON1

5V_S5

12

B B

C3501

USB_PWR_EN#[24]

USB_OC#2_3[16]

SCD1U16V2KX-3GP

Support 2A

U3501

2

IN#2

3

4

5

OUT#6

IN#3

OUT#7 OUT#8

DY

EN/EN#

GND

FLT#

GND

TPS2000CDGNR-GP

74.02000.B71

2nd = 74.02301.079

USB20_VCCB

C3515

2A

12

C3516

SC22U6D3V5MX-2GP

USB2.0 Port3 (IO Board)

12

6 7 8

1 9

DY

R3502

12

C3517 SCD1U16V2KX-3GPC3517 SCD1U16V2KX-3GP

C3518

12

100KR2J-1-GP

C3518

12

SC1U10V2KX-1GP

5V_S5

USB_PWR_EN#[24] USB_OC#2_3 [16]

12

C3504

SCD1U16V2KX-3GP

A A

SCD1U16V2KX-3GP

5

Support 2A

U3505

5

4

074.06288.009B

IN

EN#

Active Low

SY6288DAAC-GP

OUT GND OC#

USB20_VCCB

1 2 3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

4

3

2

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

USB Power SW

1

A00

35 104Friday, February 07, 2014

A00

5

4

3

2

1

SSID = Reset.Suspend

Power Good

3D3V_S0

ROSA Run Power

D D

R3610

13 14 12

8 9 10

11 15

1 2

0R0402-PAD

1 2

0R0402-PAD

3V5V_CT1

3V5V_CT2

R3611

3D3V_S0

C3602

SC470P50V2KX-3GP

C3602

SC470P50V2KX-3GP

C3601

SC470P50V2KX-3GP

C3601

SC470P50V2KX-3GP

12

1D35V_VTT_PWRGD[49]

3D3V_AUX_S5

1 2

DY

R3607

100KR2J-1-GP

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

PM_SLP_S3#[1 7,24,48,49,51]

C C

PCH_PWROK[17,24,26 ]

PS_S3CNTRL

Q3601

2N7002KDW-GP

84.2N702.A3F

6

123 4

S

GDGD

S

5

DY

R3609

1 2

0R0402-PAD

3D3V_S5

5V_S5

3V5V_S0_ON

5V_S5

1D05V_VTT_PWRGD[7,48 ]

U3601

4

VBIAS

1

IN1#1

2

IN1#2

3

EN1

6

IN2#6

7

IN2#7

5

EN2

G5016KD1U-GP

074.05016.0093

OUT1#13 OUT1#14

CT1

OUT2#8 OUT2#9

CT2

GND GND

12

R3601

R3601 1KR2J-1-GP

1KR2J-1-GP

ALL_SYS_PWRGD [24]

5V_S0

12

C3605

SC10U10V5KX-2GP

C3605

SC10U10V5KX-2GP

5V_S0

C3603

SC10U10V5KX-2GP

C3603

SC10U10V5KX-2GP

5V_S0 Comsumption Peak current 5A

3D3V_S0

3D3V_S0 Comsumption Peak current 2.5A

R3608

1 2

DY

1D05V_S0

B B

H_THERMTRIP_EN[4 ]

R3606

PLT_RST#[17,24,30 ,52,58,65,73,96]

A A

5

1 2

4K7R2J-2-GP

12

R3605

R3605 2K2R2J-2-GP

2K2R2J-2-GP

4

3V_5V_EN[45]

H_THERMTRIP_EN

2ND = 83.00016.F11

3rd = 83.00016.P11

4th = 83.00016.G11

12

DY

R3602

200KR2F-L-GP

C3604

12

SCD1U16V2KX-3GP

DY

1KR2J-1-GP

E

B

84.02222.V11

C

D3602

D3602 BAS16-6-GP

BAS16-6-GP

2

3

1

83.00016.K11

R3603

1KR2J-1-GP

83.00016.K11

1 2

Check R3603 is 1k or 2k.

3

Q3602

MMBT2222A-3-GP

H_THERMTRIP# [20]

PURE_HW_SHUTDOW N# [24,26,76]

S5_ENABLE [24]

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Monday, February 10, 2014

Date: Sheet of

Power Plane Enable

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

36 104

1

A00

5

4

3

2

1

SSID = Reset.Suspend

Layout Note:

D D

SA_DIMM_VREFDQ

SODIMM1

C C

M_VREF_CA_DIMMA

DDR_VREF_S3

12

R3704

R3704 0R2J-2-GP

0R2J-2-GP

DY

Place Close SO-DIMM1

1D35V_S3

12

R3706

R3706 1K8R2F-GP

1K8R2F-GP

1 2

12

R3703

R3703 1K8R2F-GP

1K8R2F-GP

Layout Note:

Place Close SO-DIMM1

2R2F-GP

2R2F-GP R3708

R3708

1D35V_S3DDR_VREF_S3

12

C3701

C3701 SCD022U16V2KX-3GP

SCD022U16V2KX-3GP

+V_VREF_PATH3

12

R3707

R3707 24D9R2F-L-GP

24D9R2F-L-GP

+V_SM_VREF_CNT [5]

12

DY

12

R3701

R3701 1K8R2F-GP

1K8R2F-GP

R3709

R3709 1K8R2F-GP

1K8R2F-GP

M_VREF_DQ_DIMMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet of

3

2

Date: Sheet of

S3 Reduction Circuit

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

37 104

1

A00

R3710

0R2J-2-GP

2R2F-GP

2R2F-GP R3702

R3702

DDR_WR_VREF01[5]

B B

A A

5

1 2

12

C3702

C3702 SCD022U16V2KX-3GP

SCD022U16V2KX-3GP

+V_VREF_PATH1

12

R3711

R3711 24D9R2F-L-GP

24D9R2F-L-GP

4

5

4

3

2

1

3D3V_S5 3D3V_S5_PCH

D D

3D3V_S5

Obs reason:

R3801

1 2

NON DS3

0R5J-5-GP

For new project, pls help to use cost down version SY6288C10CAC for instead.

C3801

12

SC1U10V2KX-1GP

U3801

DS3

C C

PM_SLP_SUS#[17,24]

DS3

1 2

R3802

R3802 0R2J-2-GP

0R2J-2-GP

DS3_PWRCTL

U3801

DS3

1 2 3

DS3

GND

OUT#8

IN#2

OUT#7

IN#3

OUT#6

EN/EN#4OCB

SY6288CCAC-GP

74.06288.079

8 7 6 5

(OBS)

3D3V_S5_PCH

C3802

12

SC1U10V2KX-1GP

DS3

RdsON: 100m ohm

DS3

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Janus HSW 40/50/70

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DSW

38 104Friday, February 07, 2014

1

A00

5

D D

4

3

2

1

(Blanking)

C C

B B

Wistron Corporation

A A

Title

Size Document Number Rev

Date: Sheet of

5

4

3

Date: Sheet of

(Reserved) 1D05_M

A4

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

39 104Friday, February 07, 2014

1

A00

(Blanking)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document Number Rev

A4

Date: Sheet of

Reserved

Janus HSW 40/50/70

40 104Friday, February 07, 2014

A00

5

D D

4

3

2

1

C C

B B

A A

5

4

(Blanking)

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document Number Rev

A4

Date: Sheet of

2

Janus HSW 40/50/70

Reserved

41 104Friday, February 07, 2014

1

A00

5

4

3

2

1

SSID = PWR.Support

PR4202

PQ4202

PR4209

PQ4202

1 2

PQ3802_1

B

1 2

D S

DMN5L06K-7-GP

PQ4204

R1

B

R2

PDTC124EU-1-GP

84.00124.H1K

2nd = 84.05124.011

E

C

G

PQ4201

PR4206

1 2

DY

33R2J-2-GP

PD4201

PD4201 P6SBMJ24APT-GP

P6SBMJ24APT-GP

A K

PWR_CHG_AD_OFF_R

15KR2F-GP

3

12

PR4214

3K3R6J-GP

PQ3809_D

1

PD4204

PD4204 PESD24VS2UT-GP

PESD24VS2UT-GP

15KR2F-GP

100KR2J-1-GP

1 2

PR4210

1KR2J-1-GP

D D

Layout Note:

PSID Layout width > 25mil

PS_ID_R

JGND

EL4203

1 2

0R0J-GP

+DC_IN_C

PWR_CHG_AD_OFF[24]

1 1

DY

12

JGND JGND

AC_IN_KBC#[24]

0R0J-GP

AFTP3806AFTP3806 AFTP3803AFTP3803

EC4201

SC10U25V5KX-GP

ZZ.00PAD.V91

12

ACES-CON7-6-GP-U

NP2

7 6 5 4 3 2

1

NP1

DCIN1

20.F1783.007

2nd = 20.F1718.007

2nd = 20.F1718.007 3rd = 20.F1763.007

C C

3rd = 20.F1763.007

EC4202

PAD-2P-4516-GP-U

SCD1U25V2KX-GP

1

EL4201

1

EL4202

PAD-2P-4516-GP-U

PR4213

PR4213 100KR2J-1-GP

100KR2J-1-GP

60ohm@100MHz DCR=0.02 ohm Max current = 6000mA

2

ZZ.00PAD.V91

12

PR4212

PR4212 100KR2J-1-GP

100KR2J-1-GP

AC_IN#_G

12

PR4217

1 2

0R3J-0-U-GP

3 4

2

1

2N7002KDW-G P

PQ4206

PS_ID_R2

2

DY

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

5

6

84.T3904.H11

LMBT3904LT1G-GP

PSID_DISABLE#_R_C

84.05067.031

AD_OFF_L

C

E

DT MODE

5V_S5

12

PS_ID

12

PR4203

PR4203 10KR2J-3-GP

10KR2J-3-GP

PC4202

PC4202 SCD1U50V3KX-GP

SCD1U50V3KX-GP

PQ4205

R2

B

R1

PDTA124EU-1-GP

84.00124.K1K

2nd = 84.05124.A11

E

C

PR4205

1 2

33R2J-2-GP

AD_OFF_R

PC4201

3D3V_S5

DY

3D3V_S5

2

+DC_IN AD+

12

SC1U50V5ZY-1-GP-U

1 2

PR4208

47KR3J-L-GP

PR4211

PR4211 10KR2J-3-GP

10KR2J-3-GP

PR4207

240KR3-GP

12

1

PD4203

PD4203 LBAV99LT1G-1-GP

LBAV99LT1G-1-GP

75.00099.O7D

3

2nd = 75.00099.K7D

2nd = 75.00099.K7D 3rd = 75.00099.Q7D

3rd = 75.00099.Q7D 4th = 75.00099.D7D

4th = 75.00099.D7D

PU4201

S

1

S

2

S

3

GD

4 5

SI7121DN-T1-GE3-GP

Id=-9.6A Qg=-25nC Rdson=18~30mohm

12

PC4208

PQ3808D

SC1U25V3KX-1-GP

D

8

D

7

D

6

PQ4208

D

2N7002K-2-GP

84.2N702.J31

3D3V_S5

12

PR4204

PR4204 2K2R2J-2-GP

2K2R2J-2-GP

PSID_EC [24]

12

PC4205

DY

SCD01U50V2KX-1GP

PQ3808G

G

S

PC4203

SCD01U50V2KX-1GP

1KR2J-1-GP

12

PC4209

PC4204

DY

SCD01U50V2KX-1GP

PR4215

1 2

SCD01U50V2KX-1GP

12

PC4206

SC10U25V5KX-GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

B B

A A

AFTP3801AFTP3801 AFTP3802AFTP3802 AFTP3805AFTP3805

+DC_IN_C

1

PS_ID_R

1

+DC_IN_C

1

H_PROCHOT#[4,24,44,46]

5

4

4th = 84.DMN66.03F

PR4216

12

DY

100KR2J-1-GP

PQ4203

1

2

3 4

2N7002KDW-G P

3

6

PC4210

PQ4203_5

5

1 2

12

PR4218

PR4218 100KR2J-1-GP

100KR2J-1-GP

SCD47U6D3V2KX-GP

BAT_IN#

BAT_IN# [24,43,44]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

DCIN

Janus HSW 40/50/70

1

42 104Friday, February 07, 2014

A00

5

4

3

2

1

SSID = PWR.Support

PBAT_PRES1#

PBAT_SMBDAT1

BT+

D D

12

EC4304

SCD1U50V3KX-GP

DY

C C

12

PD4302

DY

12

PD4302 SMF18AT1G-GP

SMF18AT1G-GP

A K

RN4301

4 5 3 2 1

EC4305

DY

1 2

6 7 8

SRN100J-4-GP

SC10P50V2JN-4GP

AFTP3901AFTP3901

Batt Connecter

PBAT_SMBCLK1 PBAT_SMBDAT1 PBAT_PRES1#

BAT_ALERT

1

BAT1

10

1

2 3 4 5 6 7 8 9

11

ALP-CON9-6-GP-U

AFTP3906AFTP3906

1

AFTP3909AFTP3909

1

AFTP3910AFTP3910

1

EC4303

EC4303 SCD1U25V2KX-GP

SCD1U25V2KX-GP

BAT_SCL[24,44] BAT_SDA[24,44] BAT_IN#[24,42,44]

EC4302

EC4301

EC4302

SC10P50V2JN-4GP

DY

SC10P50V2JN-4GP

12

SC10P50V2JN-4GP

PBAT_SMBCLK1

BT+ BT+ BT+

1 1 1 1 1 1

AFTP3902AFTP3902 AFTP3903AFTP3903 AFTP3904AFTP3904 AFTP3905AFTP3905 AFTP3907AFTP3907 AFTP3908AFTP3908

20.81925.009

2nd = 20.81928.009

Placement: Close to Batt Connector

BAT_IN#

B B

3

D4302

D4302 LBAV99LT1G-1-GP

LBAV99LT1G-1-GP

75.00099.O7D

1

2

2nd = 75.00099.K7D

3rd = 75.00099.Q7D

A A

4th = 75.00099.D7D

5

BAT_SDA

3

D4303

D4303 LBAV99LT1G-1-GP

LBAV99LT1G-1-GP

75.00099.O7D

1

2

2nd = 75.00099.K7D

3rd = 75.00099.Q7D

4th = 75.00099.D7D

4

BAT_SCL

3

D4301

D4301 LBAV99LT1G-1-GP

LBAV99LT1G-1-GP

75.00099.O7D

1

2

2nd = 75.00099.K7D

3rd = 75.00099.Q7D

4th = 75.00099.D7D

3

3D3V_AUX_KBC

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

BATT CONN

Size Document Number Rev

A4

Date: Sheet of

2

Janus HSW 40/50/70

BATT CONN

43 104Friday, February 07, 2014

1

A00

5

4

3

2

1

SSID = Charger

PWR_CHG_ CMPIN

12

PR4429

PR4429 150KR2F-L-GP

150KR2F-L-GP

PU4402

S

D

S

D

1

PR4404

PWR_CHG_ ACOK

3D3V_AUX_KBC

12

PR4415

3K3R2F-2-GP

BAT_IN# [24,42,43]

12

PR4474

PR4474 100KR2J-1-GP

100KR2J-1-GP

H_PROCHOT# [4,24,42,46]

5

DY

6

PQ4410

84.2N702.A3F

10KR2F-2-GP

8

S

D

S

D

2

7

SGDD

3

6

45

SI7121DN-T1-G E3-GP

84.07121.037

12

2nd = 84.03605.037

Id= -10A Qg= -22nC Rdson=15~18mohm

DC_IN_D

2N7002KDW-GP

3 4

2

5

1

6

PQ4402

4th = 84.DMN66.03F

3rd = 75.00601.07C

2nd = 84.2N702.E3F

84.2N702.A3F

3D3V_AUX_S5

PR4438

100KR2J-1-GP

DY

12

1 2

PR4412

3K3R2F-2-GP

PWR_CHG_ CMPIN

DY

3D3V_AUX_KBC

EE need check pull high

AC_IN#[24]

PQ4405_5

PC4434

SC1U25V3KX-1-GPDYPC4434

SC1U25V3KX-1-GP

12

DY

PQ4405_6

PR4470

PR4470 100KR2F-L1-GP

100KR2F-L1-GP

DY

12

PR4473

1 2

DY

3D3V_S5

AD+_G_2

PR4408

1 2

10R5J-GP

PWR_CHG_ REGN

PWR_CHG_ CMPOUT

120KR2F-L-GP

PG4407 GAP-CLOSE-PWR-3-GPPG4407 GAP-CLOSE-PWR-3-GP

PG4408 GAP-CLOSE-PWR-3-GPPG4408 GAP-CLOSE-PWR-3-GP

PR4439

3D3V_AUX_S5

1 2

10KR2F-2-GP

PWR_CHG_ REGN

12

PR4425

PR4425 100KR2J-1-GP

100KR2J-1-GP

DY

12

DY

PC4401

SCD1U50V3KX-GP

12

PR4403

PR4401

1 2

AD+_G_1

10KR2F-2-GP

PWR_CHG_ VCC

PR4430

100KR2J-1-GP

PR4432

1 2

3D3V_AUX_S5

4

100KR2J-1-GP

12

PR4418

1 2

0R0402-PAD

PR4435

10KR2F-2-GP

12

PR4434

PR4434 100KR2J-1-GP

100KR2J-1-GP

12

120KR2F-L-GP

DY

12

PWR_CHG_ ILIM

PR4433

2N7002KDW-GP

D D

47KR2F-GP

C C

2N7002KDW-GP

PWR_CHG_CMPIN_R

3 4

2

AD_IA_HW2[24] AD_IA_HW [24 ]

CHG_AGND

AD+

12

PR4407

PR4407 309KR2F-GP

309KR2F-GP

12

PR4431

CHG_AGND

1

PQ4407

4th = 84.DMN66.03F

3rd = 75.00601.07C

2nd = 84.2N702.E3F

84.2N702.A3F

PWR_CHG_ CMPIN

PWR_CHG_ IOUT

PC4412

SCD01U50V2KX-1GP

3D3V_AUX_S5

12

PR4417

PR4417 100KR2J-1-GP

100KR2J-1-GP

12

PR4423

PR4423 59KR2F-GP

59KR2F-GP

DY

CHG_AGND

5

6

PWR_CHG_CMPIN_RR

12

CHECK EE

H_PROCHOT#[4,24,42,4 6]

B B

15V_S5

PR4471

0R2J-2-GP

PR4468

0R2J-2-GP

DY

DCBATOUT

CHECK EE

A A

follow customer circuits.

1MR2J-1-GP

DY

1 2

PD4404

1N4148WS-7-F-GP

K A

DY

PD4403_K

LMBT3906LT1G-1-GP

1 2

DY

1 2

PR4465

PR4465 0R2J-2-GP

0R2J-2-GP

PR4467

PD4403_A

PQ4409

PQ4406_D

AD+

12

DY

PR4469

100KR2J-1-GP

12

DY

PQ4408_E

E

B

DY

C

PQ4408_C

PR4475

PR4475 0R2J-2-GP

0R2J-2-GP

1 2

DY

12

PR4464

PR4464 680KR2J-GP

680KR2J-GP

DY

5

CHG_AGND

12

PR4427

PR4427 66K5R2F-GP

66K5R2F-GP

PR4411

PR4411 102KR2F-GP

102KR2F-GP

PR4413

PR4413 84K5R2F-GP

84K5R2F-GP

CHG_AGND

BAT_SCL[24,43]

BAT_SDA[24,43]

PQ4414

PQ4414 2N7002K-1-GP

2N7002K-1-GP

84.2N702.031

D S

PWR_CHG_ ACOK

DY

1 2

3D3V_S5

DY

PR4476

PR4476 0R2J-2-GP

0R2J-2-GP

12

G

1 2

PQ4405_3

PQ4405_2

AD+

3KR5J-GP

BOOST_MODE#[24 ]

100KR2F-L1-GP

PR4472

PC4433

PC4433 SCD47U6D3V2 KX-1-GP

SCD47U6D3V2 KX-1-GP

PQ4406_G

DY

PR4466

PR4466 0R2J-2-GP

0R2J-2-GP

2N7002KDW-GP

3 4

2

1

4th = 84.DMN66.03F

3rd = 75.00601.07C

2nd = 84.2N702.E3F

12

PC4010

CHG_AGND

SCD47U25V3KX-1GP

PWR_CHG_ ACDET

12

PR4414

3D3MR2J-GP

PWR_CHG_ BAT_SCL

PWR_CHG_ BAT_SDA

PWR_CHG_ IFAULT

AD+_TO_SYS

PR4402

1 2

D01R3721F-GP-U

12

PR4406

PG4402

0R2J-2-GP

12

DY

GAP-CLOSE-PWR-3-GP

1 2

PC4402

SCD1U25V2KX-GP

12

PC4404

SC1U25V3KX-1-GP

CHG_AGND

PWR_CHG_ACP

2

PU4404

20

ACP

VCC

6

ACDET

HPA02224RGRR-1-GP

3

CMPOUT

4

CMPIN

9

SCL

8

SDA

10

ILIM

11

BM#

74.02224.073

5

ACOK#

GND

21

CHG_AGND

Customer Request

BOOST_MON[24]

DCBATOUT

12

PG4403

GAP-CLOSE-PWR-3-GP

12

PC4403

SC1U25V3KX-1-GP

PWR_CHG_ACN

CHG_AGND

1

ACN

PWR_CHG_ BTST

17

BTST

16

REG

PWR_CHG_ HIDRV

18

HIDRV

PWR_CHG_ PHASE

19

PHASE

PWR_CHG_ LODRV

15

LODRV

13

SRP

12

SRN

PWR_CHG_ IOUT

7

IOUT

GND

14

GAP-CLOSE-PWR-3-GP

12

PG4411

CHG_AGND

BATTERY MON

AD+

12

PR4405

PR4405 470KR2J-2-GP

470KR2J-2-GP

83.1R504.A8F

2nd = 83.1R004.H8F

3rd = 83.1R504.B8F

4th = 83.2R004.08F

SD103AWS-1- GP

PR4409

0R3J-0-U-GP

1 2

PWR_CHG_BTST_R

12

PWR_CHG_ SRP

PWR_CHG_ SRN

1 2

PR4422

PR4422 0R2J-2-GP

0R2J-2-GP

PR4424

12

PC4422

12

8K45R2F-2-GP

SC220P50V2JN-3GP

DY

CHG_AGND

BOOST_MON_1 PU4401_6

1 2

DY

PR4452

0R2J-2-GP

PD4401

K A

PC4411

SCD047U25V2KX-GP

SC3300P50V3KX-1 GP

PC4427

12

DY

PU4403

S

1

S

2

S

3

GD

4 5

SI7121DN-T1-G E3-GP

84.07121.037

84.07121.037 2nd = 84.03605.037

2nd = 84.03605.037

PWR_CHG_ REGN

1 2

SC1U25V3KX-1-G P

PC4413

PR4421

1 2

10R2F-L-GP

PR4420

1 2

7D5R2F-GP

AD_IA [24]

PR4446

1 2

DY

SC1U25V3KX-1-GPDYPC4427

SC1U25V3KX-1-GP

20KR2F-L-GP

3

BT+

D

8

D

7

D

6

Id= -10A Qg= -22nC Rdson=15~18mohm

SIS412DN-T1-GE3 -GP

PC4407

1 2

DY

PC4420

PC4420 SCD1U25V2KX-GP

SCD1U25V2KX-GP

12

DY

12

PC4423

CHG_AGND

Close PR4416

BT+_R

DY

1 2

DCBATOUT_R

12

DY

PU4401_5

5

6

-

DY

123 4

DY

PU4405

65BOM charger

CHG_AGND

12

PC4421

SCD1U25V2KX-GP

GAP-CLOSE-PWR-3-GP

PG4404

PR4448

PR4448 0R2J-2-GP

0R2J-2-GP

1 2

DY

PR4410

6D8R2F-GP

1 2

DY

PC4424

SCD1U25V2KX-GP

PU4401_4

PU4407

+

INA199A1-G P

DCBATOUT

PC4431

SC1U25V3KX-1-GPDYPC4431

SC1U25V3KX-1-GP

12

678

DDD

SSS

GD

SSS

GD

123

4 5

IND-5D6U H-45-GP

PU4406

678

DDD

65BOM charger

SSS

GD

SSS

GD

123

4 5

84.00412.037

GAP-CLOSE-PWR-3-GP

PG4405

DY

1 2

+VCHGR_R BT+

12

PR4454

PR4454 10R2F-L-GP

10R2F-L-GP

DY

84.00412.037

PL4401

1 2

68.5R610.10U

SIS412DN-T1-GE3-GP

PWR_CHG_ CSOP_1

PWR_CHG_ CSON_1

CHARGER_SRC

12

PC4406

PC4408

SC4D7U25V5KX-GP

12

PC4426

PC4409

EC4401

DY

SC10U25V5KX-GP

EC4401

SC10U25V5KX-GP

DY

SCD1U50V3KX-GP

Charger Current=1.4~3.6A

PR4416

D01R3721F-GP-U

BT+_R

1 2

64.R0105.7FL

1 2

PG4410

1 2

PG4409

GAP-CLOSE-PWR-3-GP

EE need pull high and net name

PWR_CHG_ ACOK

12

DY

SC2200P50V2KX-2GP

12

PC4415

SC10U25V5KX-GP

3D3V_AUX_S5

BT+

12

DY

2

EC4402

SCD1U25V2KX-GP

PC4416

SC10U25V5KX-GP

12

PR4419

PR4419 100KR2J-1-GP

100KR2J-1-GP

12

PC4418

12

PC4417

DY

SC10U25V5KX-GP

PWR_CHG_ REGN

12

PR4428

DY

100KR2J-1-GP

PWR_CHG_ CMPOUT PQ 4008_2

12

PR4436

DY

120KR2F-L-GP

CHARGER_SRC

GAP-CLOSE-PWR

PC4419

SCD1U50V3KX-GP

160KR2F-GP

PG4412

PG4413

PG4414

PG4415

1 2

12

PR4437

PC4425

DCBATOUT

12

SCD01U50V2KX-1GP

2N7002KDW-GP

3 4

2

1

PQ4408

4th = 84.DMN66.03F

3rd = 75.00601.07C

2nd = 84.2N702.E3F

84.2N702.A3F

AC_IN#

5

6

PQ4008_6

PR4426

1 2

0R0402-PAD

H_PROCHOT# [4,24,42,46]

EC code only BQ24707

H_PROCHOT#

Title

Size Document Number Rev

Custom

Date: Sheet of

AD_IA_HW

45W

00

65W 1 0

90W

0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CHARGER HPA02224

Janus HSW 40/50/70

1

AD_IA_HW2

1

44 104Friday, February 07, 2014

A00

A

B

C

D

E

SSID = PWR.Plane.Regulator_5v3p3v

PWR_5V_VCLK

4 4

DCBATOUT

3 3

Design Current=3.3A

5.17A<OCP>6.11A

3D3V_S5

3D3V_PWR

PG4526

12

GAP-CLOSE-PWR

PG4517

12

GAP-CLOSE-PWR

PG4528

12

GAP-CLOSE-PWR

PG4522

12

GAP-CLOSE-PWR

PG4529

12

GAP-CLOSE-PWR

PT4501 and PT4502 manually change to 77.52271.06L

2 2

PG4525

GAP-CLOSE-PWR

PG4521

GAP-CLOSE-PWR

PG4524

GAP-CLOSE-PWR

PG4531

GAP-CLOSE-PWR

3D3V_PWR

PC4517

12

DY

PWR_DCBATOUT _3D3V

12

PT4502

12

SE220U6D3VM-38-GP

SCD1U16V2KX-3GP

79.22710.3KL

PR4512

6K8R2F-2-GP

PR4523

10KR2F-2-GP

PC4525

SCD1U50V3KX-GP

1 2

IND- 3D3U H-57G P

PG4535

12

GAP-CLOSE-PW R-3-GP

3V_FEEDBACK

12

DY

12

PC4528

12

DY

68.3R310.20A

PL4502

PR4533

2D2R5F-2-GP

PC4520

SC330P50V3KX-GP

12

PR4535

PR4535 0R2J-2-GP

0R2J-2-GP

PWR_3D3V_FB2_R

12

PC4523

PC4523 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

PC4509

SC10U25V5KX-GP

12

DY

PWR_DCBATOUT _3D3V

SC4D7U25V5KX-GP

SIS412DN-T1-GE3-GP

678

DDD

65BOM charger

SSS

123

12

678

DDD

65BOM charger

SSS

123

PWR_3D3V_SNUB

12

DY

PU4504

84.00412.037

PC4535

GD

4 5

GD

4 5

SCD1U50V3KX-GP

PU4505

PU4505 SIS412DN-T1-GE3-GP

SIS412DN-T1-GE3-GP

84.00412.037

3V_5V_POK[17]

12

3V_5V_EN[36]

PWR_3D3V_VBST2_1

3D3V_S5

12

PR4534

PR4534 100KR2J-1-GP

100KR2J-1-GP

DY

PR4528

1 2

1D5R3-GP

12

PR4517

PR4517 73K2R2F-GP

73K2R2F-GP

PWR_3D3V_DRVH2

PWR_3D3V_DRVL2

3D3V_PWR_2

Close to VFB Pin (pin5)

PR4501

0R2J-2-GP

PR4530

DY

0R2J-2-GP

PWR_3D3V_VBST2

PWR_3D3V_LL2

PWR_3D3V_FB2

PWR_3D3V_EN2

PWR_3D3V_CS2

SC4D7U6D3V3KX-GP

PR4532

1 2

0R0402-PAD

3D3V_AUX_S5

12

9

10

8

11

4

6

5

7

3D3V_PWR_2

PC4526

3D3V_AUX_S5

12

DY

PWR_5V_EN1_R

PR4507

PR4507 0R0402-PAD

0R0402-PAD

1 2

PU4503

VBST2

DRVH2

SW2

DRVL2

VFB2

EN2

CS2

TPS51225RUKR-GP

74.51225.073

PGOOD

DCBATOUT

PC4519

12

VIN

VREG3

3

12

PR4504

1 2

0R0402-PAD

PR4506

1 2

0R0402-PAD

SC10U25V5KX-GP

12

DY

17

VBST1

16

DRVH1

18

SW1

15

DRVL1

14

VO1

2

VFB1

20

EN1

1

CS1

19

VCLK

21

GND

VREG5

13

5V_PWR_2

12

PC4524

PC4524 SC1U6D3V3KX-2GP

SC1U6D3V3KX-2GP

PWR_5V_EN1

PWR_3D3V_EN2

PC4531

SCD01U50V2KX-1GP

12

PWR_5V_VBST1

PWR_5V_DRVH1

PWR_5V_LL1

PWR_5V_DRVL1

PWR_5V_VO1

PWR_5V_FB1

PWR_5V_EN1

PWR_5V_CS1

PWR_5V_VCLK

PR4524

1 2

1D5R3-GP

DCBATOUT

PWR_5V_VBST1_1

12

PR4531

PR4531 137KR2F-1-GP

137KR2F-1-GP

PWR_DCBATOUT _5V

PG4520

GAP-CLOSE-PWR

PG4536

GAP-CLOSE-PWR

PG4518

GAP-CLOSE-PWR

PG4534

GAP-CLOSE-PWR

PG4542

GAP-CLOSE-PWR

PG4543

GAP-CLOSE-PWR

PC4516

SCD1U50V3KX-GP

12

1 2

SC1KP50V2KX-1GP

PU4501

65BOM charger

PU4502

65BOM charger

4

12

PC4521

DY

2nd = 83.00054.Y81

3rd = 83.BAT54.P81

75.00054.C7D

5V_PWR

12

PC4515

SCD1U50V3KX-GP

DY

PWR_DCBATOUT _5V

PC4530

SIS412DN-T1-GE3-GP

12

678

DDD

SSS

GD

SSS

GD

123

4 5

567

8

DDD

D

DDD

D

SIS780DN-T1-GE3-GP

DY

G

SSS

123

DY

PWR_5V_FB1_R

SC18P50V2JN-1-GP

PC4514

SCD1U50V3KX-GP

12

1 2

IND- 2D2U H-46- GP-U

12

PR4529

PR4529 2D2R5F-2-GP

2D2R5F-2-GP

PWR_5V_SNUB

12

PC4536

PC4536 SC560P50V-GP

SC560P50V-GP

PR4525

0R2J-2-GP

PC4522

12

SCD1U50V3KX-GP

DY

BST15V_1

3

DY

1

PC4534

SCD1U50V3KX-GP

DY

PC4529

SC4D7U25V5KX-GP

68.2R210.20B

PL4501

12

DY

12

DY

PD4503

PD4503 BAT54SPT-1-GP

BAT54SPT-1-GP

2

BOOST_10V

12

SC1U25V3KX-1-GP

PC4527

SC10U25V5KX-GP

12

PC4532

SCD1U50V3KX-GP

PC4533

PG4532

GAP-CLOSE-PW R-3-GP

12

PR4527

PR4527 15K4R2F-GP

15K4R2F-GP

12

PR4526

PR4526 9K76R2F-1-GP

9K76R2F-1-GP

DY

1

12

BST15V_2

75.00054.C7D

PD4502

PD4502 BAT54SPT-1-GP

BAT54SPT-1-GP

GAP-CLOSE-PWR-3-GP

DY

5V_PWR

PC4518

12

DY

75.00054.C7D

2nd = 83.00054.Y81

3rd = 83.BAT54.P81

PG4530

12

PD4501

BZT52C15S-GP

A K

12

PT4501

SE220U6D3VM-38-GP

79.22710.3KL

SCD1U16V2KX-3GP

3

DY

2

15V_PWR

12

DY

Design Current=8.65A

12.98A<OCP>15.34A

Close to VFB Pin (pin2)

15V_S5

5V_PWR

PG4527

GAP-CLOSE-PWR

PG4519

GAP-CLOSE-PWR

PG4538

GAP-CLOSE-PWR

PG4537

GAP-CLOSE-PWR

PG4533

GAP-CLOSE-PWR

PG4523

GAP-CLOSE-PWR

PG4541

GAP-CLOSE-PWR

PG4540

GAP-CLOSE-PWR

PG4545

GAP-CLOSE-PWR

PG4544

GAP-CLOSE-PWR

5V_S5

12

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A O/P cap:CHIP CAP POL 220U 6.3V M 6.3*4.5 /Matsuki/ 17mOhm / 77.52271.09L H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037

1 1

L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037

A

B

TPS51225 & TPS51285 Co-lay

TPS51285TPS51225

PR4510

45.3KK 9.09K

PR4511

110K

22.1K

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18mohm/20mohm Isat =14Arms 68.2R210.20B O/P cap:CHIP CAP POL 220U 6.3V M 6.3*4.5 /Matsuki/ 17mOhm / 77.52271.09L H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

C

D

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

3V/5V TPS51225

Janus HSW 40/50/70

E

A00

45 104Friday, February 07, 2014

A00

5

4

3

2

1

SSID = CPU.Regulator

PR4614

PWR_VCC_PRGM1

1 2

D D

1D05S_VCCST

C C

H_VR_ENABLE[7]

H_PROCHOT#[4,24,42 ,44]

B B

IMVP _PWR GD[7,24 ]

130R2F-1-GP

54D9R2F-L1-GP

1 2

75R2F-2-GP

12

PC4606

PC4606 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1D05V_S0

3D3V_S0

PR4630

PR4620

PR4601

DY

12

1 2

2KR2F-3-GP

1 2

PWR_VCC_SDA

PWR_VCC_SCLK

PWR_VCC_ALERT#

PR4602

499R2F-2-GP

DY

R4622

H_CPU_SVIDDAT[7]

VR_SVID_ALERT#[7]

H_CPU_SVIDCLK[7]

PC4604

PC4604 SC1U10V3KX-3GP

SC1U10V3KX-3GP

PR4621 0R0402-PADPR4621 0R0402-PAD

12

PR4610 100KR2F-L1-GPPR4610 100KR2F-L1-GP

1 2

PC4609 SC1KP50V2KX-1GPPC4609 SC1KP50V2KX-1GP

PR4624

0R0402-PAD

PC4611

SC6800P50V3KX-GP

12

PWR_VCC_COMP_RC

12

DY

SCD1U16V2KX-3GP

PR4628

12

PR4617

12

16KR2F-GP

PR4622

12

NTC-470K-5-GP-U

B=4500K

PC4610

12

0R0402-PAD

5V_S0

12

PR4613

5K1R2F-2-GP

PWR_VCC_NTC_R

PR4619 0R0402-PADPR4619 0R0402-PAD

12

PR4618 0R0402-PADPR4618 0R0402-PAD

12

PR4616 0R0402-PADPR4616 0R0402-PAD

12

PWR_VCC_EN

PWR_VCC_IMON

PWR_VCC_VRHOT#

PWR_VCC_COMP

12

PR4615

1 2

3K83R2F-GP

PWR_VCC_SDA

PWR_VCC_ALERT#

PWR_VCC_SCLK

PU4601

12

VCC

1

VR_ON

3

IMON

4

VRHOT#

6

COMP

21

GND

PWR_VCC_POK

PWR_VCC_NTC

1 2

20

SCLK

PGOOD

2

close to H/S MOSFET

PR4622 manually change to 69.60037.001

15W/28W

90K9R2F-GP

PR4607

PWR_VCC_PRGM2

124KR2F-GP

19

ALERT#

ISL9 5813H RZ-GP

74.95813.B73

NTC

5

PR4604

12

10R2F-L-GP

PC4612

12

SC1KP50V2KX-1GP

11

18

SDA

RTN

8

17

PRGM2

PRGM1

PWR_VCC_BOOT

13

BOOT

PWR_VCC_UG

14

UG

PWR_VCC_PHASE

15

PHASE

PWR_VCC_LG

16

LG

PWR_VCC_FB

7

FB

PR4606

1 2

DY

0R2J-2-GP

ISUMP

ISUMN

9

10

0R2J-2-GP

PWR_VCC_ISUMP

PWR_VCC_ISUMN

PWR_VCC_BOOT [47]

PWR_VCC_UG [47]

PWR_VCC_PHASE [47]

PWR_VCC_LG [47]

PR4603

1 2

15W/28W

1K27R2F-L-GP

PWR_VCC_FB_RC

PWR_VCC_ISUMP [47]

PWR_VCC_ISUMN [47]

VSS_SENSE [9]

LL=2mohm

PC4601

1 2

DY

SCD1U16V2KX-3GP

PC4613

12

SC1KP50V2KX-1GP

VCC_SENSE [7]

PR4603

A A

15W

28W

5

4

3

1.27K

64.12715.6DL

1.58K

64.15815.6DL

PR4614

90.9K

64.90925.6DL

113K

64.11335.6DL

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ISL95813_CPUCORE(1/2)

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

46 104Friday, February 07, 2014

1

A00

5

4

3

2

1

PWR_DCBATOUT_VCCCORE

PC4704

12

PC4701

PU4701 manually change to 084.06970.0037.

PU4701

D D

C C

B B

PWR_VCC_UG[46]

PWR_VCC_BOOT[46]

PWR_VCC_LG[46]

PR4701

0R3J-0-U-GP

1 2

PWR_VCC_PHASE[46]

PWR_VCC_BOOT_RC

PC4706

1 2

SCD22U25V3KX-GP

PWR_VCC_PHASE

1

9

8

FDMS3600-02-RJK0215-COLAY-GP

1st = 084.06970.0037

2nd = 84.08S36.037

2 3 4 10

7 6 5

ZZ.00215.037

PR4707

10MR2F-GP

PR4702

3K65R2F-1-GP

12

PC4701

SC10U25V5KX-GP

PL4701 IND-D22UH-9-GP-U

1 2

68.R2210.10C

PG4701

PG4701 GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

1 2

PHASE1G

12

PR4703

1 2

4K42R2F-GP

PHASE_R_R

1 2

11KR2F-L-GP

PC4708

PC4703

PC4702

SC10U25V5KX-GP

close to CHOKE

PR4704

1 2

NTC-10K-26-GP-U

B=3370K

PR4708

PC4707

1 2

SCD047U25V2KX-GP

SCD1U16V2KX-3GP

1 2

SCD1U50V3KX-GP

VCC_CORE

PG4702

PG4702 GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

1 2

ISUM_R_C

PC4709

1 2

DY

SCD1U16V2KX-3GP

12

15W/28W

DCBATOUT

12

PT4702

SE33U25VM-10-GP

DY

For acoustic noice

Shark Bay ULT 15W CPU IccMAX=32A TDC=10A

35.2A<OCP<41.6A Frequency=750KHZ LL=-2.0 mV/A

PC4710

PC4710 SCD1U25V2KX-GP

SCD1U25V2KX-GP

PR4705

1 2

357R2F-GP

PR4706

ISUM _R_R

PR4706

1 2

DY

0R2J-2-GP

DCBATOUT PWR_DCBATOUT_VCCCORE

PG4703

1 2

GAP-CLOSE-PWR

PG4708

1 2

GAP-CLOSE-PWR

PG4704

1 2

GAP-CLOSE-PWR

PG4707

1 2

GAP-CLOSE-PWR

PG4705

1 2

GAP-CLOSE-PWR

PG4706

1 2

GAP-CLOSE-PWR

PWR_VCC_ISUMN [46]

PR4705 (Cyntec)

15W

357 ohm (64.35705.6DL)

412 ohm (64.41205.6DL)

28W

PR4705 (Maglayers)

383 ohm (64.38305.6DL)

15W

464 ohm (64.46405.6DL)

28W

OCP

38A

48A

38A

48A

Change PC4723 to 10U from 22U based on PI Simulation.

PWR_VCC_ISUMP [46]

12

PC4732

SC22U6D3V5MX-2GP

VCC_CORE

12

PC4733

4

VCC_CORE

12

SC22U6D3V5MX-2GP

PC4734

SC22U6D3V5MX-2GP

PC4736

SC22U6D3V5MX-2GP

12

PC4741

SC22U6D3V5MX-2GP

12

PC4721

SC22U6D3V5MX-2GP

DY

12

PC4722

SC22U6D3V5MX-2GP

12

PC4724

SC22U6D3V5MX-2GP

DY

12

PC4727

SC22U6D3V5MX-2GP

DY

12

PC4728

SC22U6D3V5MX-2GP

DY

12

PC4735

SC22U6D3V5MX-2GP

DY

Stuff PC4727, PC4737 for 28W.

3

12

PC4737

SC22U6D3V5MX-2GP

DY

12

PC4738

SC22U6D3V5MX-2GP

12

PC4739

SC22U6D3V5MX-2GP

12

PC4740

SC22U6D3V5MX-2GP

2

12

PC4742

PC4743

SC22U6D3V5MX-2GP

DY

Title

ISL95813_CPUCORE(2/2)

Size Document Number Rev

A3

Date: Sheet of

12

EC4701

EC4701 SCD1U25V2KX-GP

SCD1U25V2KX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

1

A00

47 104Friday, February 07, 2014

A00

22uF/6.3V/0805*13 330uF/2.5V/6.3*4.5/12mohm*1

12

PC4725

SC22U6D3V5MX-2GP

PC4717

SC22U6D3V5MX-2GP

12

PC4726

SC22U6D3V5MX-2GP

PC4718

SC22U6D3V5MX-2GP

12

PC4723

SC10U10V5KX-2GP

A A

SE330U2D5VM-8-GP

PT4701

12

DY

12

PC4729

SC22U6D3V5MX-2GP

PC4719

SC22U6D3V5MX-2GP

12

PC4730

SC22U6D3V5MX-2GP

PC4720

SC22U6D3V5MX-2GP

12

PC4731

SC22U6D3V5MX-2GP

PC4744

SC22U6D3V5MX-2GP

Change to 79.3371V.6CL

5

SSID = PWR.Plane.Regulator_1p05v

4

3

2

1

D D

PWR_DCBATOUT_1D05V

SC4D7U25V5KX-GP

PC4814

PC4826

12

1 2

PR4837

PR4837 2D2R5F-2-GP

2D2R5F-2-GP

PC4838

PC4838 SC560P50V-GP

SC560P50V-GP

PC4814

68.2R210.20B

PL4801

IND-2 D2UH -46-GP -U

SC10U25V5KX-GP

12

SIS412DN-T1-GE3-GP

DY

678

DDD

PU4808

0R0402-PAD

1D05V_VTT_PWRGD[7,36 ]

C C

B B

PM_SLP_S3#[1 7,24,36,49,51]

0R0402-PAD

(current limit ~ 7.3A)

0R0402-PAD

PR4821

PR4817

1 2

105KR2F-1-GP

PR4819

1 2

12

PU4806

PWR_1D05V_PW RGD PWR_1D05V_TRIP

PWR_1D05V_FB PWR_1D05V_CCM

12

DY

PC4821

SC1KP50V2KX-1GP

PR4824

PR4824 470KR2F-GP

470KR2F-GP

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18~20mohm Isat =14Arms 68.2R210.20B O/P cap: CHIP CAP POL 330U 2.5V M 6.3*4.5 2.3Arms Matsuti/77.53371.18L H/S:SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 L/S:SIS780DN-T1-GE3 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037

PU4806

1

PGOOD

2

CS

3

EN

4

FB

5

RF

RT8237CZQW-2-GP

74.08237.B73

GND

BOOT

UGATE

PHASE

VCC

LGATE

11 10

PWR_1D05V_UGATEPWR_1D05V_EN

9

PWR_1D05V_PHASE

8 7

PWR_1D05V_LGATE

6

PWR_1D05V_BOOT

PR4820

2D2R3-1-U-GP

1 2

PWR_1D05V_BOOT_R

5V_S5

12

PC4815

SC1U10V2KX-1GP

84.00412.037

84.00412.037 65BOM charger

65BOM charger

SCD1U50V3KX-GP

PC4822

12

PU4805

84.00412.037

65BOM charger

4 5

GD

678

DDD

SSS

123

12

DY

SIS412DN-T1-GE3-GP

SSS

123

PWR_1D05V_SNUB

12

DY

DCBATOUT PWR_DCBATOUT_1D05V

PG4838

12

GAP-CLOSE-PWR

PG4837

PC4825

SCD1U50V3KX-GP

12

PWR_1D05V_PW R

PR4822

10KR2F-2-GP

PWR_1D05V_FB

PR4823

PR4823 21KR2F-GP

21KR2F-GP

12

GAP-CLOSE-PWR

PG4834

12

GAP-CLOSE-PWR

PG4827

12

GAP-CLOSE-PWR

GAP-CLOSE-PWR-3-GP

PG4832

1 2

12

Vout=0.704V*(R1+R2)/R2

12

Design Current =4.43A

6.645A<OCP<7.97A

1D05V_PWR

PC4824

12

PC4823

DY

SC18P50V2JN-1-GP

PC4824

12

PT4803

SE330U2D5VM-14-GP

12

79.3371V.6CL

SCD1U16V2KX-3GP

1D05V_PWR 1D05V_S0

PG4828

12

GAP-CLOSE-PWR

PG4830

12

GAP-CLOSE-PWR

PG4831

12

GAP-CLOSE-PWR

PG4826

12

GAP-CLOSE-PWR

PG4824

12

GAP-CLOSE-PWR

PG4825

12

GAP-CLOSE-PWR

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8237_1D05V

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

48 104Friday, February 07, 2014

1

A00

5

SSID = PWR.Plane.Regulator_1p35v0p675v

4

3

2

1

GAP-CLOSE-PWR

PM_SLP_S3#[17,24,36,48,51]

+PWR_SRC_1D35V

PG4903

12

PG4904

12

PG4905

12

PG4906

12

R4909 0R0402-PADR4909 0R0402-PAD

R4910 0R2J-2-GP

12

PC4903SCD1U16V2KX-3GP PC4903SCD 1U16V2KX-3GP

PC4902SCD01U50V2KX-1GP PC4902SCD01U50V2KX-1GP

DY

12

PR4903

PR4903 10KR2F-2-GP

10KR2F-2-GP

12

PR4906

1D35V_PWR 1D35V_S3

PG4908

12

GAP-CLOSE-PWR

PG4909

12

GAP-CLOSE-PWR

PG4910

12

GAP-CLOSE-PWR

PG4911

12

GAP-CLOSE-PWR

PG4912

12

GAP-CLOSE-PWR

PG4913

12

GAP-CLOSE-PWR

PG4914

12

GAP-CLOSE-PWR

PG4915

12

GAP-CLOSE-PWR

PG4916

12

GAP-CLOSE-PWR

PG4917

12

GAP-CLOSE-PWR

PG4918

12

GAP-CLOSE-PWR

PG4919

12

GAP-CLOSE-PWR

PG4920

12

GAP-CLOSE-PWR

PC4909

SC4D7U25V5KX-GP

12

PR4912

DY

2D2R5F-2-GP

TPS51216_PHS_SET

12

PC4922

PC4922 SC330P50V2KX-3GP

SC330P50V2KX-3GP

+PWR_SRC_1D35V

PC4911

12

DY

SC4D7U25V5KX-GP

PL4902

1 2

COIL-D68UH-5-GP

68.R6810.20B

PM_SLP_S4#[17,24]

12

PC4912

SC10U25V5KX-GP

1 2

PWR_1D35V_VDDQS

PC4913

PC4913 SCD1U50V3KX-GP

SCD1U50V3KX-GP

1 2

DY

PG4907

GAP-CLOSE-PWR-3-GP

PC4914

12

SC4D7U25V5KX-GP

Design Current=8.65A

12.97A<OCP>15.57A

1D35V_PWR

12

PC4921

PC4920

SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP

PR4907

1 2

0R0402-PAD

12

PC4924

PC4923

SC22U6D3V5MX-2GP

PWR_1D35V_EN

PC4906

12

DY

PC4925

SC22U6D3V5MX-2GP

12

PC4926

SC22U6D3V5MX-2GP

EC4601

DY

EC4601 SCD1U50V3KX-GP

SCD1U50V3KX-GP

DY

5V_S5

678

DDD

12

SSS

123

8

D

SSS

123

PC4904

SIS412DN-T1-GE3-GP

SIS780DN-T1-GE3-GP

1D35V_PWR

SC1U10V3KX-3GP

12

84.00412.037

DY

3D3V_S0

12

PR4904

DY

20KR2F-L-GP

DDR_VTT_PG_CTRL_R

12

30K1R2F-L-GP

PR4901

PR4601_1

12

0R0402-PAD

PR4908

1 2

PWR_1D35V_VREF

12

1KR2F-3-GP

PR4902

PWR_1D35V_EN

PWR_1D35V_REFIN

PWR_1D35V_MODE

PWR_1D35V_TRIP

PWR_1D35V_VTTREF

12

133KR2F-GP

PC4918

PC4918 SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

PU4901

20

PGOOD

17

S3

16

S5

6

VREF

8

REFIN

19

MODE

18

TRIP

5

VTTREF

21

GND

7

GND

TPS51716RUKR-GP

74.51716.073

+0D675V_DDR_P

VBST

DRVH

DRVL

PGND

VDDQSNS

VLDOIN

VTTSNS

VTTGND

PG4901

GAP-CLOSE-PWR

PG4902

GAP-CLOSE-PWR

V5IN

SW

VTT

0D675V_S0

12

PWR_1D35V_VBST

15

PWR_1D35V_DRVH

14

PWR_1D35V_SW

13

PWR_1D35V_DRVL

11

10

PWR_1D35V_VDDQS

9

2

3

1

4

12

PC4901

SC1U10V3KX-3GP

PR4905

1 2

12

PC4915SCD1U16V2KX-3GP PC4915SCD 1U16V2KX-3GP

PC4916

PWR_1D35V_VTTREF

PR4605_2

2D2R3-1-U-GP

+0D675V_DDR_P

12

PC4917

SC10U6D3V3MX-GP

DDR_VREF_S3

PR4911

1 2

0R0603-PAD-1-GP-U

PC4919

PC4919 SCD1U50V3KX-GP

SCD1U50V3KX-GP

1 2

84.00780.037

12

DY

PU4902

65BOM charger

GD

4 5

567

DDD

PU4903

65BOM charger

G

4

D D

C C

DCBATOUT

1D35V_VTT_PWRGD[36]

DDR_VTT_PG_CTRL[12]

SCD1U16V2KX-3GP

B B

A A

State S3 S5 VDDR VTTREF VTT

S3S0Lo

S4/S5

5

HiLoOnOnOn

Hi

On

Off

On

Off(Hi-Z)

OffLo

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP IND 0.1UH M PCMC063T-R10MN 1.5~1.7mohm Isat =60Arms 68.R1010.10T O/P cap: CHIP CAP POL 330U 2.5V M 6.3*4.5 2.3Arms Matsuti/77.53371.18L MOS: FET MOS FDMS3664S NC POWER56 / 84.03664.037 / Q1: 8.5~11mohm @Vgs=4.5V Q2: 2.6~3.2mohm @Vgs=4.5V

4

3

SCD1U16V2KX-3GP

Wistron Corporation

21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

21F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51716_1D35V_S3

Size Document Number Rev

C

Janus HSW 40/50/70

Date: Sheet of

2

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

49 104Monday, February 10, 2014

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

A3

Reserved

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

50 104Friday, February 07, 2014

1

A00

5

SSID = PWR.Plane.Regulator_1p5v

4

3

2

1

3D3V_S5

D D

TLV70215 for 1D5V_S0

PC5119

SC1U10V2KX-1GP

PC5119

SC1U10V2KX-1GP

12

Design Current = 150mA

PU5101

1

IN

2

PWR_1D5V_EN

PM_SLP_S3#[1 7,24,36,48,49]

C C

DCBATOUT

B B

PWR_DCBATOUT_VRAM_PW R

PG5101

1 2

GAP-CLOSE-PWR

PG5102

1 2

GAP-CLOSE-PWR

PG5103

1 2

GAP-CLOSE-PWR

1D35V_VGA_EN[83 ]

PWR_DCBATOUT_VRAM_PW R

1D5V_VGA_S0

470KR2F-GP

Check GPU power sequence.

A A

1D5V_VGA_S0: for DDR3 VRAM only

5

1 2

0R0402-PAD

PC5115

12

1D5V_VGA_S0

PR5111

0R2J-2-GP

1D5V_VGA_S0

PR5110

SC4D7U25V5KX-GP

PR5114

PC5113

12

1D5V_VGA_S0

SC4D7U25V5KX-GP

TP5101TP5101

1

PWR_VRAM_PW R_ILIM VRAM_PWR_BYP

12

PWR_VRAM_PW R_EN

12

PR5104

PR5104 1MR2J-1-GP

1MR2J-1-GP

DY

GND EN3NC#4

TLV70215DBVR-GP

74.70215.03F

SY8208D for 1D35V_VGA_S0(1D5V)

PU5102_PG

4

5

OUT

4

PU5102

1D5V_VGA_S0

8

IN

2

PG

3

ILMT

1

EN

9

GND

SY8208DQNC-GP-U

74.08208.K73

LDO

BYP

12

6

BS

10

LX

4

FB

7

5

PG5105

1 2

GAP-CLOSE-PWR

PC5120

SC1U10V2KX-1GP

PC5120

SC1U10V2KX-1GP

1D5V_VGA_S0

VRAM_PWR_BS

VRAM_PWR_PH

VRAM_PWR_FB

VRAM_PWR_LDO

PC5112

SC2D2U6D3V2MX-GP

1D5V_S01D5V_PWR

PR5102

1 2

0R3J-0-U-GP

1 2

1D5V_VGA_S0

IND-1 UH-20 6-GP

PR5112

0R2J-2-GP

1D5V_VGA_S0

12

1D5V_VGA_S0

Vo=0.6x(1+R1/R2) =0.6x(1+150/100) =1.5V

3

VRAM_PWR_BS_R

PL5101

3D3V_S5

12

PC5109

12

SC1U10V2KX-1GP

1D5V_VGA_S0

PC5110

1 2

1D5V_VGA_S0

SCD1U50V3KX-GP

GAP-CLOSE-PWR-3-GP

1 2

12

1D5V_VGA_S0

PG5104

VRAM_PWR_FBH

PR5113

PR5113 150KR2F-L-GP

150KR2F-L-GP

PR5103

PR5103 100KR2F-L1-GP

100KR2F-L1-GP

1D5V_VGA_S0

Design Current=3.4A OCP=8A

12

PC5101

DY

SC22U6D3V5MX-2GP

12

PC5111

PC5111 SC220P50V2KX-3GP

SC220P50V2KX-3GP

1D5V_VGA_S0

2

1D35V_VGA_S0

1D5V_VGA_S0

12

PC5108

SC22U6D3V5MX-2GP

Title

TLV70215_1D5V / SY8208D_1D5V(VGA)

Size Document Number Rev

A3

Date: Sheet of

PC5116

SC22U6D3V5MX-2GP

DY

1D5V_VGA_S0

12

PC5118

PC5117

SC22U6D3V5MX-2GP

Janus HSW 40/50/70

PC5114

PC5114 SCD1U50V3KX-GP

SCD1U50V3KX-GP

1D5V_VGA_S0

SC22U6D3V5MX-2GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

51 104Friday, February 07, 2014

1

A00

5

LCD1

41

1

2 3 4 5 6 7 8 9 10 11

D D

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

42

ACES-CON40-18-GP

20.K0678.040

C C

LCD_BRIGHTNESS BLON_OUT_C LCD_TST_C EDP_AUX EDP_AUX# EDP_TX0# EDP_TX0 EDP_TX1# EDP_TX1 DMIC_CLK_C DMIC_DATA_C USB_CAMERA# USB_CAMERA 3D3V_CAMERA_S0

EDP_HPD_CONN LCDVDD_LCD DCBATOUT_LCD TP_RS

TP_RESET

B B

DCBATOUT_LCD

Trace width = 80mil

DBC_EN_R EDP_HPD_CONN LCD_TST_C EDP_AUX EDP_AUX#

EDP_TX0# EDP_TX0

EDP_TX1# EDP_TX1

LCD_BRIGHTNESS BLON_OUT_C PANEL_SIZE_ID_CONN

DMIC_CLK_EDP DMIC_DATA_EDP

USB_CAMERA_EDP# USB_CAMERA_EDP

3D3V_CAMERA_S0

USB_PN6_TPNL USB_PP6_TPNL

TP_RS TP_RESET

TPAN_VDD

AFTP5203AFTP5203

1

AFTP5205AFTP5205

1

AFTP5207AFTP5207

1

AFTP5206AFTP5206

1

AFTP5208AFTP5208

1

AFTP5213AFTP5213

1

AFTP5210AFTP5210

1

AFTP5211AFTP5211

1

AFTP5212AFTP5212

1

AFTP5222AFTP5222

1

AFTP5228AFTP5228

1

AFTP5225AFTP5225

1

AFTP5226AFTP5226

1

AFTP5227AFTP5227

1

AFTP5201AFTP5201

1

AFTP5202AFTP5202

1

AFTP5204AFTP5204

1

AFTP5209AFTP5209

1

AFTP5214AFTP5214

1

12

MIC_GND

Brightness

C5201 SCD1U16V2KX-3GPC5201 SCD1U16V2KX-3GP

EDP_TX0_DN[8] EDP_TX0_DP[8]

EDP_TX1_DN[8] EDP_TX1_DP[8]

EDP_AUX_DN[8] EDP_AUX_DP[8]

L_BKLT_CTRL[15]

LCDVDD_LCD

C5206

C5206 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2

R5201

1 2

0R0402-PAD

LCD

Camera

Touch Panel

LCDVDD_LCD

R5211

TP_RS

TP_RESET

1 2

DBC_EN_R

12

DY

C5208

C5208 SC10P50V2JN-4GP

SC10P50V2JN-4GP

12

DY

C5214

C5214 SC10P50V2JN-4GP

SC10P50V2JN-4GP

USB_PN6_TPNL

USB_PP6_TPNL

1 2

0R0402-PAD

R5205

1 2

0R0402-PAD

R5212

1 2

0R0402-PAD

EDP_TX0# EDP_TX0

EDP_TX1# EDP_TX1

EDP_AUX# EDP_AUX

eDP_BKLT_CTRL

EE note: Never change R5211 to short pad after MP

C5203 SCD1U16V2KX-3GPC5203 SCD1U16V2KX-3GP

1 2

C5210 SCD1U16V2KX-3GPC5210 SCD1U16V2KX-3GP

1 2

C5211 SCD1U16V2KX-3GPC5211 SCD1U16V2KX-3GP

1 2

C5213 SCD1U16V2KX-3GPC5213 SCD1U16V2KX-3GP

1 2

C5209 SCD1U16V2KX-3GPC5209 SCD1U16V2KX-3GP

1 2

C5212 SCD1U16V2KX-3GPC5212 SCD1U16V2KX-3GP

1 2

R5206

1 2

0R0402-PAD

LCDVDD

0R5J-5-GP

R5224

LCD_TST_C LCD_BRIGHTNESS BLON_OUT_C

EDP_HPD_CONN

4

DBC_EN [20]

TOUCH_PANEL_INTR# [24]

PLT_RST# [17,24,30,36,58,65,73,96]

R5203

1 2

0R0402-PAD

R5204

1 2

0R0402-PAD

RN5203

1 2 3 4 5

SRN100KJ-5-GP

RN5201

1 2 3 4 5

SRN100J-4-GP

1 2

INVERTER POWER

USB_PN6 [16]

USB_PP6 [16]

BKLT_CTRL

8

BLON_OUT_C

7

EDP_HPD

6

8 7 6

BKLT_CTRL

R5233100R2J-2-G P R5233100R2J-2-GP

LCD_TST [24]

BLON_OUT [24]

EDP_HPD [15]

12

R5231

DY

TPAN_VDD_F

3

DCBATOUT_LCDDCBATOUT

F5201

1 2

POLYSW-1D1A24V-2-GP

69.60040.001

For ESD

R5210

1 2

100R2J-2-GP

5V_S03D3V_S0

12

0R3J-0-U-GPDYR5231

0R3J-0-U-GP

R5230

R5230 0R0603-PAD-1-GP-U

0R0603-PAD-1-GP-U

EE note: Never change R5232 to short pad after MP Reserved for one time fuse: 69.43001.201

800mA

C5205

SCD1U50V3KX-GP

3D3V_S0

12

R5208

R5208 10KR2J-3-GP

10KR2J-3-GP

PANEL_SIZE_IDPANEL_SIZE_ID_CONN

For AUDIO Grade B or C selection.

12

R5209

R5209 0R2J-2-GP

0R2J-2-GP

DY

R5222 0R2J-2-GP

1 2

DY

D5202

1

3

2

EC (BIST MODE)

BAT54C-7-F-3-GP

75.00054.E7D

2nd = 83.R2003.W81

3rd = 75.00054.A7D

3rd = 75.00054.A7D 4th = 83.R2003.V81

4th = 83.R2003.V81

69.60040.001

F5203

POLYSW-1D1A24V-2-GP

1 2

DY

R5232 0R3J-0-U-GPR5232 0R3J-0-U-GP

12

DY

1 2

eDP_BKLT_CTRL

EC_BRIGHTNESS [24]

TPAN_VDD

C5202

12

SC1KP50V2KX-1GP

PANEL_SIZE_ID [20]

CAM1

DMIC_CLK_C DMIC_DATA_C

DMIC_CLK_EDP DMIC_DATA_EDP

LCDVDD

2

EE note: Never change R5229 to short pad after MP Reserved for one time fuse: 69.43001.201

R5229

1 2

0R3J-0-U-GP

3D3V_CAMERA_S0

CCD1

9

1

Notice:20.F2191.008

DY

2

DMIC_CLK_C

3

DMIC_DATA_C

4 5 6 7 8

10

DM-ACES-CON8-44-GP-01

ZZ.F2191.00801

RN5202

1 2 3

DY

SRN33J-5-GP-U

RN5204

2 3 1

CAM_EDP

SRN33J-5-GP-U

4

USB_CAMERA# USB_CAMERA

EC5205

12

DY

SC6D8P50V2DN-GP

CAM1_MIC_GND

EC5206

12

DY

SC6D8P50V2DN-GP

DMIC_CLK [27] DMIC_DATA [27]

Layout Note: Reduce the stubs.

D5201

EDP_VDD_EN[15]

LCD_TST_EN[24]

Layout Note:

Trace width = 80mil

1

2

BAT54C-7-F-3-GP

75.00054.E7D

2nd = 83.R2003.W81

3rd = 75.00054.A7D

4th = 83.R2003.V81

3

R5202

R5202 100KR2J-1-GP

100KR2J-1-GP

LCDVDD

1 2

EC5210

LCDVDD_EN

3D3V_CAMERA_S03D3V_S0

12

DY

SC33P50V2JN-3GP

CAM1_MIC_GND

USB_CAMERA#

USB_CAMERA

USB_CAMERA_EDP#

12

C5207

C5207 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

1 2

R5207 0R2J-2-GP

DY

TR5208

3 4

69.10103.041 DY

FILTER-4P-6-GP

TR5209

3 4

69.10103.041 CAM_EDP

FILTER-4P-6-GP

U5201

1

EN

VIN#5

2

GND

3

VOUT

VIN#4

RT9724GB-GP

74.09724.09F

5

4

USB_PN4_CAM#

USB_PP4_CAM

12

USB_PN4_EDP

USB_PP4_EDPUSB_CAMERA_EDP

12

Layout Note: Reduce the stubs.

3D3V_S0

12

C5204

C5204 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

1

RN5205

2 3 1

DY

SRN0J-6-GP

CAM_EDP

RN5206

1 2 3

SRN0J-6-GP

4

USB_PN4 [16] USB_PP4 [16]

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

LCD/Inverter CONN

Size Document Number Rev

A2

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

1

A00

52 104Monday, February 10, 2014

A00

5

D D

4

3

2

1

(Blanking)

C C

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

53 104Friday, February 07, 2014

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

HDMI Level Shifter/Connector

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

54 104

1

X02

5

CRT Board Connector

5V_CRT_S0_R

C5519SCD01U16V2KX-L1-GPDYC5519SCD01U16V2KX-L1-GP

DY

CRT_DDCDATA_CON

3D3V_S0

CRT_DDCCLK_CON

CRT_R CRT_G CRT_B

CRT_VSYNC_CON CRT_HSYNC_CON

R5504

1 2

0R0603-PAD-1-GP-U

R5503

1 2

0R0603-PAD-1-GP-U

D D

C C

B B

CRT1

9

12

VCC_CRT

12

DDCDATA_ID1

15

DDCCLK_ID3

1

CRT_RED

2

CRT_GREEN

3

CRT_BLUE

14

VSYNC

13

HSYNC

D-SUB 15P

D-SUB-15-252-GP

020.20020.0015

DP_CRT_G CRT_G

DP_CRT_B

R551375R2F-2-GP R551375R2F-2-GP

R550175R2F-2-GP R550175R2F-2-GP

12

AVCC33

C5523

C5523 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

1 2

VDD_DAC_33

C5521

C5521 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

1 2

4

NC#4

11

NC#11

5

GND

6

GND

7

GND

8

GND

10

GND

16

GND

17

GND

C5506

SC4D7P50V2BN-GP

C5506

SC4D7P50V2BN-GP

C5512

SC4D7P50V2BN-GP

C5512

SC4D7P50V2BN-GP

C5509

12

R551475R2F-2-GP R551475R2F-2-GP

12

C5509

12

Layout note: All cap need close to chip

PCH_DPB_AUXP[15] PCH_DPB_AUXN[15]

PCH_DPB_P0[8] PCH_DPB_N0[8]

PCH_DPB_P1[8] PCH_DPB_N1[8]

CLK_DP2VGA[18]

L5503

1 2

68.00084.A11

2nd = 68.00245.011

L5501

1 2

68.00084.A11

2nd = 68.00245.011

L5502

1 2

SC4D7P50V2BN-GP

68.00084.A11

2nd = 68.00245.011

4

5V_CRT_S0_R 5V_CRT_S0

POLYSW-1D1A6V-9-GP-U

2ND = 69.50011.081

2ND = 69.50011.081 3RD = 69.50013.101

3RD = 69.50013.101

BLM18BB220SN-GP

C5514

SC4D7P50V2BN-GP

C5514

SC4D7P50V2BN-GP

C5510

12

C5527 SCD1U16V2KX-3GPC5527 SCD1U16V2KX-3GP

1 2

C5528 SCD1U16V2KX-3GPC5528 SCD1U16V2KX-3GP

1 2

C5529 SCD1U16V2KX-3GPC5529 SCD1U16V2KX-3GP

1 2

C5526 SCD1U16V2KX-3GPC5526 SCD1U16V2KX-3GP

1 2

C5530 SCD1U16V2KX-3GPC5530 SCD1U16V2KX-3GP

1 2

C5525 SCD1U16V2KX-3GPC5525 SCD1U16V2KX-3GP

1 2

R5506

1 2

0R2J-2-GP

F5501

1 2

69.48001.081

CRT_RDP_CRT_R

CRT_B

C5518

SC4D7P50V2BN-GP

C5518

SC4D7P50V2BN-GP

12

PCH_DPC_AUXP_U PCH_DPC_AUXN_U

PCH_DPC_P0_U PCH_DPC_N0_U

PCH_DPC_P1_U PCH_DPC_N1_U

CRT_DEBUG

C5515

SC100P50V2JN-L-GPDYC5515

SC100P50V2JN-L-GP

12

DY

CRT_DDCDATA_CON

CRT_DDCCLK_CON

12

C5517SCD 1U16V2KX-3GP C5517SCD1U16V2KX-3GP

12

C5503SCD 1U16V2KX-3GP C5503SCD1U16V2KX-3GP

12

C5520SCD 1U16V2KX-3GP C5520SCD1U16V2KX-3GP

12

C5522SCD 1U16V2KX-3GP C5522SCD1U16V2KX-3GP

12

C5501SCD 1U16V2KX-3GP C5501SCD1U16V2KX-3GP

12

VDD_DAC_33

C5504SC2D2U 10V3KX-1GP C5504SC2D2U10V3KX-1GP

12

C5524SCD 1U16V2KX-3GP C5524SCD1U16V2KX-3GP

12

C5502SC10U6D 3V3MX-GP C5502SC10U6D3V3MX-GP

LDO_EN

XICLK_DP2VGA

DY

SRN2K2J-1-GP

AVCC33

VCCK_12

3D3V_S0 3D3V_S0

VCCK_12

RRX

12

R5505

R5505 12KR2F-L-GP

12KR2F-L-GP

83.R5003.H8H

CRT_DDCDATA_CON

CRT_HSYNC_CON

C5513

SC18P50V2JN-1-GPDYC5513

SC18P50V2JN-1-GP

12

RN5501

24

25

5

20

19

9

21

26 27

29 30

31 32

17 18

28

D5501

K A

RB551V30-GP

CRT_VSYNC_CON

C5507

SC18P50V2JN-1-GPDYC5507

SC18P50V2JN-1-GP

12

DY

5V_CRT_S0

4

1

2 3

U5502

AVCC_33

AVCC_12

DVCC_33 DVCC_33

VCCK_12

VDD_DAC_33

LDO_EN

AUX_P AUX_N

LANE0P LANE0N

LANE1P LANE1N

XI/CKIN XO

RRX

RTD2168-CGT-GP

071.02168.0003

5V_S0

Hsync & Vsync level shift

CRT_DDCCLK_CON

12

C5511

C5511 SC100P50V2JN-L-GP

SC100P50V2JN-L-GP

DP_CRT_HSYNC_CON

DP_CRT_VSYNC_CON

CRT_PCH_HPD

1

HPD

2

SMB_SCL

3

SMB_SDA

CRT_DDCCLK_CON

4

VGA_SCL

CRT_DDCDATA_CON

6

VGA_SDA

DP_CRT_VSYNC_CON

7

VSYNC

DP_CRT_HSYNC_CON

8

HSYNC

15

RED_P

16

RED_N

12

GREEN_P

13

GREEN_N

10

BLUE_P

11

BLUE_N

22

POL1_SDA

23

POL2_SCL

14

GND_DAC

33

GND

3

14

4

U5501B

5 6

DY

TC74VHCT125AFTQK2M-GP

7

DP_CRT_R

DP_CRT_G

DP_CRT_B

POL1_SDA POL2_SCL

CRT RGB CRT H/VSYNC CRT SMBUS

5V_CRT_S0

12

DY

14

1

U5501A

2 3

DY

TC74VHCT125AFTQK2M-GP

7

R5511 33R2J-2-GPR5511 33R2J-2-GP

1 2

R5507 33R2J-2-GPR5507 33R2J-2-GP

1 2

CRT_PCH_HPD

PCH_SMBCLK [12,18,62,96] PCH_SMBDATA [12,18,62,96]

C5516

SCD01U16V2KX-3GP

HSYNC_5

VSYNC_5

12

R5510

R5510 100KR2J-4-GP

100KR2J-4-GP

SRN0J-6-GP

1

DY

2 3

RN5502

CRT_PCH_HPD [15]

CRT_HSYNC_CON

4

CRT_VSYNC_CON

2

5V_CRT_S0

14

13

U5501D

12 11

DY

TC74VHCT125AFTQK2M-GP

7

5V_CRT_S0

14

10

U5501C

9 8

DY

TC74VHCT125AFTQK2M-GP

7

1

3D3V_S0 3D3V_S0

R5515

EEPROM

1 2

POL1_SDA

ROM

1 2

R5515

4K7R2J-2-GP

EEPROM/ROM

R5516

4K7R2J-2-GP

5

DY

1 2

POL2_SCL

1 2

R5509

4K7R2J-2-GP

R5508

4K7R2J-2-GP

A A

4

R5502

4K7R2J-2-GP

R5512

4K7R2J-2-GP

U5504

1

A0

1 2

LDO_EN

DY

1 2

2 3

3

A1

CRT_DEBUG

A2 VSS4SDA

CAT24C128WI-GT3-GP

72.24128.J01

3D3V_S03D3V_S0

8

VCC

7

WP

SCL

POL2_SCL

6

POL1_SDA

5

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)DP to VGA Converter

Size Document Number Rev

A2

Janus HSW 40/50/70

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

1

X02

55 104Friday, February 07, 2014

X02

SSID = SATA

SATA HDD Connector

HDD1

P1

V33

P2

V33

P3

V33

5V_S0

SATA_TXP0_R

C5602SCD01U50V2KX-1GP C5602SCD01U50V2KX-1GP

1 2 1 2

12

SATA_TXN0_R

C5603SCD01U50V2KX-1GP C5603SCD01U50V2KX-1GP

12

SATA_RXP0_R

C5615SCD01U50V2KX-1GP C5615SCD01U50V2KX-1GP

SATA_RXN0_R

C5616SCD01U50V2KX-1GP C5616SCD01U50V2KX-1GP

SATA3_PTX_HDDRX_P0[19] SATA3_PTX_HDDRX_N0[19]

SATA3_PRX_HDDTX_P0[19] SATA3_PRX_HDDTX_N0[19]

P7

V5

P8

V5

P9

V5

P13

V12

P14

V12

P15

V12

S2

TX+

S3

TX-

S6

RX+

S5

RX-

SATA_HDD

SKT-SATA7P-15P-159-GP

022.10019.0001

2ND = 022.10019.0021

ME Note: New HDD conn symbol is not ready, we will use original OAK HDD conn (22.10300.991) and shift to the correct position.

NP1 NP2

GND GND GND GND GND GND GND GND

DAS/DSS

23

24

NP1 NP2

S1 S4 S7 P4 P5 P6 P10 P12

P11

5V_S0

DY

SC10U10V5KX-2GP

1A

12

C5605

C5606

SCD1U16V2KX-3GP

SATA_RXN0_R SATA_RXN0_R SATA_RXP0_R SATA_RXP0_R

Layout Note: Place near HDD1

U5602

1

LINE_1

2

LINE_2

3

GND

4

LINE_3

5

LINE_4

AZ1045-04F-R7G-GP

75.01045.073

Swap based on the swap report.

DY

NC#10

NC#9

GND NC#7 NC#6

10 9 8 7 6

SATA_TXP0_RSATA_TXP0_R SATA_TXN0_RSATA_TXN0_R

Close to HDD1

ODD Connector

ODD1

14 NP1

6 5 4 3 2

1

S7 S6 S5 S4 S3 S2 S1

NP2

SKT-SATA7P+6P-57-GP-U

20.81152.013

15

SATA_ODD_DA#_C

SATA_RXP2_R SATA_RXN2_R

SATA_TXN2_R SATA_TXP2_R

1 2

SATA_ODD_PRSNT#

C5608 SCD01U50V2KX-1GPC5608 SCD01U50V2KX-1GP C5607 SCD01U50V2KX-1GPC5607 SCD01U50V2KX-1GP

C5611 SCD01U50V2KX-1GPC5611 SCD01U50V2KX-1GP C5612 SCD01U50V2KX-1GPC5612 SCD01U50V2KX-1GP

R5602

1 2 1 2

0R0402-PAD

ODD_PWR_5V

SATA_ODD_DA# [20]

SATA_ODD_PRSNT# [19]

SATA_PRX_ODDTX_P2 [19]

SATA_PRX_ODDTX_N2 [19]

SATA_PTX_ODDRX_N2 [19]

SATA_PTX_ODDRX_P2 [19]

12

R5604

R5604 10KR2J-3-GP

10KR2J-3-GP

DY

C5609

SC10U10V5KX-2GP

3D3V_S0

5V_S0

12

DY

R5607

1 2

100KR2J-1-GP

SATA_ODD_PWRGT[20]

Current limit Active High typ =>2.5A

SATA Zero Power ODD

SATA_ODD_PWRGT

U5601

2

IN#2

3

IN#3

4

EN/EN#

5

FLT#

TPS2001CDGNR-GP

74.02001.079

2nd = 74.02311.079

OUT#6 OUT#7 OUT#8

GND GND

6 7 8

1 9

ODD_PWR_5V

SC10U10V5KX-2GP

2.5A

ODD_PWR_5V

100 mil

C5610

12

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet of

HDD/ODD

Janus HSW 40/50/70

ODD_PWR_5V5V_S0

R5603

1 2

DY

0R5J-5-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

56 104

A00

5

4

3

2

1

SSID = ESATA

D D

C C

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

ESATA

57 104Friday, February 07, 2014

1

A00

5

4

3

2

1

SSID = Wireless

D D

R5806

0R2J-2-GP

C C

BT_ACT

BLUETOOTH_EN[20]

1 2

DY

3D3V_S0

1.1A

B B

3D3V_S0

WIFI_RF_EN[24]

5V_S0

E51_TXD[24]

R5805 0R0402-PADR5805 0R0402-PAD

1 2

DY

R5801 0R2J-2-GP

DY

Mini Card Connector(802.11a/b/g)

WLAN1

3D3V_S0

WLAN_ACT

TP5801TP5801

TP5802TP5802 R5804 0R2J-2-GP

R5804 0R2J-2-GP

+5V_MINI_DEBUG

TP5804TP5804 TP5803TP5803

1

1 2

DY

CARD_WLAN_OUT#

1

CARD_WPAN_OUT#

1

BT_ACT

E51_RX E51_TX

R5807

0R2J-2-GP

1 2

DY

DEBUG

6

1.5V

2

3.3V/MS_V3

28

+1.5V

48

+1.5V

52

+3.3V/MS_V3

24

+3.3VAUX/MS_V3

3

RESERVED#3

5

RESERVED#5

8

RESERVED#8

10

RESERVED#10

12

RESERVED#12

14

RESERVED#14

16

RESERVED#16

17

RESERVED#17

19

RESERVED#19

20

RESERVED#20

37

RESERVED#37

39

RESERVED#39/MS_V3

41

RESERVED#41/MS_V3

43

RESERVED#43

45

RESERVED#45

47

RESERVED#47

49

RESERVED#49

51

RESERVED#51

42

LED_WWAN#

44

LED_WLAN#

46

LED_WPAN#

MINI_PCI 52P

SKT-MINI52P-81-GP-U1

62.10043.C81

REFCLK+

REFCLK-

MS_TX+/PERN0

MS_TX-/PERP0

MS_RX-/PETN0

MS_RX+/PETP0

USB_D-

USB_D+

SMB_CLK

SMB_DATA

WAKE#

CLKREQ#

PERST#

NP1

NP2

NP1

NP2

GND GND GND GND GND GND GND GND GND GND GND GND GND GND

13 11

23 25

31 33

36 38

30 32

1 7 22

4 9 15 18 21 26 27 29 34 35 40 50 53 54

USB_PN5_R USB_PP5_R

CLK_PCIE_WLAN_P3 [18] CLK_PCIE_WLAN_N3 [18]

PCIE_PRX_WLANTX_N3 [16] PCIE_PRX_WLANTX_P3 [16]

PCIE_PTX_WLANRX_N3_C [16] PCIE_PTX_WLANRX_P3_C [16]

CLK_PCIE_WLAN_REQ3# [15,18] PLT_RST# [17,24,30,36,52,65,73,96]

12

C5802

A A

5

12

SCD1U16V2KX-3GP

DY

C5803

12

SC10U10V5KX-2GP

WLAN_ACT

C5807

SCD1U16V2KX-3GP

C5804

SCD1U16V2KX-3GP

USB_PN5_R

USB_PP5_R

4

R5802 0R0402-PADR5802 0R0402-PAD

1 2

R5803 0R0402-PADR5803 0R0402-PAD

1 2

3

USB_PN5 [16]

USB_PP5 [16]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Mini Card (WLAN)

Size Document Number Rev

A4

Date: Sheet of

2

Mini Card (WLAN)

Janus HSW 40/50/70

58 104Friday, February 07, 2014

1

A00

A

4 4

B

C

D

E

(Blanking)

3 3

2 2

Wistron Corporation

1 1

Title

Size Document Number Rev

A4

Date: Sheet of

A

B

C

Date: Sheet of

D

Janus HSW 40/50/70

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

59 104Friday, February 07, 2014

E

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

(Reserved)

Janus HSW 40/50/70

60 104Friday, February 07, 2014

1

A00

5

4

3

2

1

SSID = User.Interface

Power button

SW1

D D

R6102

KBC_PWRBTN#[24]

C C

Battery LED1

(AMBER_LED)

1 2

AFTP6801AFTP6801

100R2J-2-GP

1

KBC_PWRBTN#_C

12

EC6104

SCD1U25V2KX-GP

DY

Low actived from KBC GPIO

5V_S5

Q6104

R2

R6104

CHG_AMBER_LED#[24]

B B

BATT_WHITE_LED#[24]

1 2

0R0402-PAD

R6105

1 2

0R0402-PAD

CHG_AMBER_LED_R#

DDTA144VCA-7-F-GP

BATT_WHITE_LED_R#

DDTA144VCA-7-F-GP

B

84.00144.N11

B

84.00144.N11

R1

Q6103

R1

E

C

12

EC6105

DY

SC220P50V2KX-3GP

5V_S5

R2

E

C

12

EC6103

DY

SC220P50V2KX-3GP

R6103

499R2F-2-GP

R6101

330R2J-3-GP

BAT_AMBERAMBER_LED_BAT

12

AMBER

BAT_AMBER [63]

BAT_WHITE [63]

BAT_WHITEWHITE_LED_BAT

12

WHITE

SW1

6

4 3 2

1

5

ETY-CON4-34-GP

20.K0465.004

2nd = 20.K0422.004

3RD = 20.K0382.004

AFTP6802AFTP6802

1

Wistron Corporation

A A

Battery LED2

Low actived from KBC GPIO

5

4

(WHITE_LED)

3

Title

LED Bard/Power Button

Size Document Number Rev

Size Document Number Rev A4

A4

Date: Sheet of

Janus HSW 40/50/70

Friday, February 07, 2014

2

LED Bard/Power Button

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

61 104

1

A00

5

Internal Keyboard Connector (DVC40)

AFTP6202AFTP6202

KB_DET#[20]

AFTP6221AFTP6221 AFTP6222AFTP6222 AFTP6230AFTP6230 AFTP6218AFTP6218

R6202

1 2

0R0402-PAD

AFTP6214AFTP6214 AFTP6227AFTP6227 AFTP6234AFTP6234 AFTP6228AFTP6228 AFTP6215AFTP6215 AFTP6224AFTP6224 AFTP6213AFTP6213 AFTP6223AFTP6223 AFTP6231AFTP6231 AFTP6208AFTP6208 AFTP6206AFTP6206 AFTP6226AFTP6226 AFTP6207AFTP6207 AFTP6233AFTP6233 AFTP6225AFTP6225 AFTP6229AFTP6229 AFTP6203AFTP6203 AFTP6216AFTP6216 AFTP6219AFTP6219 AFTP6220AFTP6220 AFTP6232AFTP6232

AFTP6201AFTP6201

CAP_LED_R#

D D

C C

KROW[0..7][24]

KCOL[0..16][24]

CAP LED Control

LOW actived from KBC G PIO

CAP_LED#[24]

1

KROW7

1

KROW6

1

KROW4

1

KROW2

1

KROW5

1

KROW1

1

KROW3

1

KROW0

1 1 1 1 1 1 1 1 1 1

KCOL12

1

KCOL16

1

KCOL15

1

KCOL13

1

KCOL14

1 1

KCOL11

1

KCOL10

1

CAP_LED

1

Q6201

B

R1

DDTA144VCA-7-F-GP

84.00144.N11

KCOL5 KCOL4 KCOL7 KCOL6 KCOL8 KCOL3 KCOL1 KCOL2 KCOL0

KCOL9

R2

E

C

KB1

32 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2

1

31

ACES-CON30-10-GP

5V_S0

Internal Keyboard Connector (DVC50/DVC70)

KB2

32

KB_DET#[20]

B B

KROW7 KROW6 KROW4 KROW2 KROW5 KROW1 KROW3 KROW0

KCOL5 KCOL4 KCOL7 KCOL6 KCOL8 KCOL3 KCOL1 KCOL2

KCOL0 KCOL12 KCOL16 KCOL15 KCOL13 KCOL14

KCOL9 KCOL11 KCOL10 CAP_LED

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2

1

31

ACES-CON30-10-GP

20.K0592.030

2nd = 20.K0565.030

2nd = 20.K0565.030 3rd = 20.K0621.030

3rd = 20.K0621.030

Keyboard Backlight (DVC70)

4

20.K0592.030

2nd = 20.K0565.030

3rd = 20.K0621.030

R6201

1 2

1KR2J-1-GP

CAP_LEDCAP_LED_Q

F6201

1 2

DY

POLYSW-D5A6V-1-GP

1 2

KBBL

R6205 0R3J-0-U-GP

69.50007.921

KB_LED_BL_DET[20]

SMBUS

KB Backlight Power Consumption: 285mA max.

KB_BL_CTRL[24]

SSID = Touch.PadSSID = KBC

PCH_SMBCLK[12,18,96]

PCH_SMBDATA[12,18,96]

12

C6202

SCD1U16V2KX-3GP

R6206

1 2

KBBL

51KR2J-1-GP

R6207

DY

100KR2J-1-GP

12

R6208

DY

100KR2J-1-GP

TPCLK[24]

TPDATA[24]

I2C1_S CL[20]

I2C1_S DA[20]

+5V_KB_BL5V_S0

12

PS2

I2C

Need to check with SW.

KBBL

12

KBBL

SC33P50V2JN-3GP

KB_LED_DET_C

C6203

SCD1U16V2KX-3GP

KBBL

G

TP_VDD

1

23

4

EC6201

1

2 3 4

KB_BL_CTRL#

ACES-CON4-56-GP

20.K0800.004

2ND = 20.K0841.004

DS

Q6202

Q6202 DMN3404L-7-GP

DMN3404L-7-GP

84.03404.C31

+5V_KB_BL KB_LED_DET_C KB_BL_CTRL#

3

TP_ON#[24]

RN6201

RN6201 SRN10KJ-5-GP

SRN10KJ-5-GP

12

DY

KBLIT1

KBBL

2

3D3V_S5

BDW: Support PTP

C6204

SCD1U16V2KX-3GP

1 2

1KR2J-1-GP

1KR2J-1-GP R6214

R6214

TP_ON#

RN6202

RN6203

EC6202

SC33P50V2JN-3GPDYEC6202

SC33P50V2JN-3GP

EC6204

SC33P50V2JN-3GPDYEC6204

SC33P50V2JN-3GP

EC6203

SC33P50V2JN-3GPDYEC6203

SC33P50V2JN-3GP

12

DY

EC6206

SC33P50V2JN-3GPDYEC6206

SC33P50V2JN-3GP

EC6205

SC33P50V2JN-3GPDYEC6205

SC33P50V2JN-3GP

12

DY

5

6

1

AFTP6245AFTP6245

1

AFTP6248AFTP6248

1

AFTP6246AFTP6246

1

AFTP6247AFTP6247

1 2

SRN33J-5-GP-U

1 2 3

2 3 1

HSW

SRN33J-5-GP-U

1 2

DY

1 2

DY

TP_ON#_GATE

Q6203

Q6203 DMP2130L-7-GP

DMP2130L-7-GP

84.02130.031

2ND = 84.03413.A31

TPCLK_C

4

TPDATA_C

I2C1_S CL_R I2C1_S DA_R

4

I2C1_S CL_R

R62040R 2J-2-GP

I2C1_S DA_R

R62100R 2J-2-GP

I2C1_S CL

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

I2C1_S DA

G

Q6204_G

2N7002KDW-G P

R6213

0R2J-2-GP

BDW

G

D

0R2J-2-GP

1

2

3 4

S

0R2J-2-GP

R6216

BDW

Q6204

Q6203_S

12

R6209

3D3V_S0

12

R6212

R6212 0R2J-2-GP

0R2J-2-GP

HSW

TP_VDD

R6215

TP_LID_CLOSE#

12

DY

10KR2J-3-GP

DY

1 2

TP_VDD

3D3V_S05V_S0

12

R6217

R6217 0R2J-2-GP

0R2J-2-GP

DY

6

5

Touch Pad Connector

SCD1U16V2KX-3GP

R6211

4K7R2J-2-GP

INT_T P#[15,20,24] TP_LID_CLOSE#[24]

TP_VDD

1

23

RN6204

RN6204 SRN10KJ-5-GP

SRN10KJ-5-GP

4

I2C1_S CL_R

I2C1_S DA_R

12

TP_LID_CLOSE# TPDATA_C

TPCLK_C

AFTP6235AFTP6235

TP_VDD

C6201

12

I2C1_S DA_R I2C1_S CL_R

TPAD1

10

8 7 6 5 4 3 2

1

9

ETY-CON10-22-GP-U

20.K0665.008

1

2nd = 20.K0667.008

Need to check if it is Active High or Active Low and check if there is PH on TPAD side.

TP_VDD

TP side has pull high

R6203

12

10KR2J-3-GP

TP_VDD TPCLK_C TPDATA_C I2C1_S CL_R I2C1_S DA_R INT_T P# TP_LID_CLOSE#

AFTP6239AFTP6239

1

AFTP6238AFTP6238

1

AFTP6236AFTP6236

1

AFTP6237AFTP6237

1

AFTP6240AFTP6240

1

AFTP6241AFTP6241

1

AFTP6242AFTP6242

1

Pin number

1

2

3

4

5

6

7

8

INT_T P#

1

Pin name

VDD

DAT(I2C)

CLK(I2C)

GND

ATTN

GPIO

DAT(PS2)

CLK(PS2)

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Friday, February 07, 2014

Friday, February 07, 2014 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Key Board/Touch Pad

Janus HSW 40/50/70

1

62 104

A00

5

D D

CON1

17

C C

18

PTWO-CON16-2-GP

20.K0382.016

B B

The maximum range of the PMOS output current in RTS5170 (Card Reader IC) is 400mA

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

USB20_VCCB

3D3V_S0

USB_PN2_IOBD1 USB_PP2_IOBD1

USB_PN7_IOBD1 USB_PP7_IOBD1

4

BAT_AMBER [61] BAT_WHITE [61]

USB2.0 Port3

Card Reader

LED

3

USB_PN2_IOBD1

69.10103.041

USB_PP2_IOBD1

USB_PN7_IOBD1

USB_PP7_IOBD1

69.10103.041

2

TR6301

3 4

FILTER-4P-6-GP

TR6302

3 4

FILTER-4P-6-GP

1

USB_PN2 [16]

12

USB_PP2 [16]

USB_PN7 [16]

USB_PP7 [16]

USB20_VCCB

12

TC6301

DY

SC100U6D3V6MX-GP

78.10710.52L

Wistron Corporation

A A

Title

IO Board Connector

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Janus HSW 40/50/70

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

63 104Friday, February 07, 2014

1

5

4

SSID = User.Interface

3

2

1

D D

100KR2J-1-GP

LID_CLOSE#[24]

C C

3D3V_S5

R6401

DY

1 2

12

C6401

C6401 SCD047U25V2KX-GP

SCD047U25V2KX-GP

LID_CLOSE#

3D3V_S5

SCD1U16V2KX-3GP

C6402

12

LIDSW1

1

VSS

2

VDD

3

OUT

S-5712ACDL1-M3T1U-GP

74.05712.0BB

B B

Wistron Corporation

A A

Title

Hall Sensor

Size Document Number Rev

Size Document Number Rev A4

A4

Friday, February 07, 2014

Date: Sheet of

5

4

3

Date: Sheet of

2

Hall Sensor

Janus HSW 40/50/70

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

64 104

1

5

4

3

2

1

SSID = DEBUG PORT

D D

Debug Connector

Layout Note:

Place near trace separated point

LPC_AD[3..0][18,24]

LPC_FRAME#[18,24] PLT_RST#[17,24,30,36,52,58,73,96]

C C

LPC_AD[3..0]

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

R6501 0R2J-2-GP

R6501 0R2J-2-GP R6502 0R2J-2-GP

R6502 0R2J-2-GP

RN6501

RN6501 SRN0J-7-GP-U

SRN0J-7-GP-U

1 2 3

DEBUG

4 5

1 2

DEBUG

1 2

DEBUG

8 7 6

LPC_LAD0_R LPC_LAD1_R LPC_LAD2_R LPC_LAD3_R

LPC_FRAME#_DEBUG PLT_RST#_DEBUG

CLK_PCI_LPC[18]

20.D0075.110: Dummy Pad with solder mask is ZZ.00PAD.Y41 DB1 Optional: New one smaller LPC connector is 20.F1180.010.

3D3V_S0

DB1

11

1

2 3 4 5 6 7 8

9 10 12

PAD-10P-177042-GP

ZZ.00PAD.Y41

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Janus HSW 40/50/70

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Dubug connector

65 104Friday, February 07, 2014

1

A00

5

D D

4

3

2

1

(Blanking)

C C

B B

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Janus HSW 40/50/70

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

66 104Friday, February 07, 2014

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

67 104Friday, February 07, 2014

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

RESERVED

Size Document Number Rev

A3

Date: Sheet of

RESERVED

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

68 104Friday, February 07, 2014

1

A00

5

D D

C C

4

3

2

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

USB3.0 PORT

69 104Friday, February 07, 2014

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

70 104Friday, February 07, 2014

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

71 104Friday, February 07, 2014

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

72 104Friday, February 07, 2014

A00

5

dGPU Reset

DGPU_HOLD_RST#[15]

PLT_RST#[17,24,30,36,52,58,65,96]

D D

PEG_CLKREQ#[18]

C C

1

2

73.01G08.EHG

2ND = 73.7SZ08.EAH

3RD = 73.01G08.L04

R7304 0R2J-2-GP

1 2

Q7301

D

2N7002K-2-GP

84.2N702.J31

0R2J-2-GP

U7301

A

VCC

OPS

B

GND3Y

DY

OPS

1 2

DY

R7305

3V3_AON_S0

5

U74LVC1G08G-AL5-R-GP-U

4

3V3_AON_S0

G

OPS

1 2

S

R7303

R7303 10KR2J-3-GP

10KR2J-3-GP

CPU_RXP_C_dGPU_TXP0[16] CPU_RXN_C_dGPU_TXN0[1 6]

dGPU_RXP_C_CPU_TXP0[16] dGPU_RXN_C_CPU_TXN0[16]

CPU_RXP_C_dGPU_TXP1[16] CPU_RXN_C_dGPU_TXN1[1 6]

dGPU_RXP_C_CPU_TXP1[16] dGPU_RXN_C_CPU_TXN1[16]

CPU_RXP_C_dGPU_TXP2[16] CPU_RXN_C_dGPU_TXN2[1 6]

dGPU_RXP_C_CPU_TXP2[16] dGPU_RXN_C_CPU_TXN2[16]

CPU_RXP_C_dGPU_TXP3[16] CPU_RXN_C_dGPU_TXN3[1 6]

dGPU_RXP_C_CPU_TXP3[16] dGPU_RXN_C_CPU_TXN3[16]

12

OPS

GPIO5

GPIO0

B B

GPIO6

GPIO8

GPIO21

PEX_RST#

A A

5

4

3V3_AON_S0

12

R7312

R7312 10KR2J-3-GP

10KR2J-3-GP

GC6_20

GPU_PEX_RST#

SYS_PEX_RST_MON# [76]

R7306

R7306 100KR2F-L1-GP

100KR2F-L1-GP

SYS_PEX_RST_MON# GPU_PEX_RST#GPU_PEX_RST#

R7308

1 2

0R2J-2-GP

GC6_20

To GPIO8

CLK_PCIE_VGA[18] CLK_PCIE_VGA#[18]

OPS

C7301 SCD22U10V2KX-1GP

1 2

OPS

C7302 SCD22U10V2KX-1GP

1 2

OPS

C7303 SCD22U10V2KX-1GP

1 2

OPS

C7304 SCD22U10V2KX-1GP

1 2

OPS

C7305 SCD22U10V2KX-1GP

1 2

OPS

C7306 SCD22U10V2KX-1GP

1 2

OPS

C7307 SCD22U10V2KX-1GP

1 2

OPS

C7308 SCD22U10V2KX-1GP

1 2

GPIO45 (PCH)

GPIO47 (PCH)

4

R7313

NON_GC6

1 2

0R2J-2-GP

GPU_PEX_RST_D#

dGPU_TXP_CPU_RXP0 dGPU_TXN_CPU_RXN0

dGPU_TXP_CPU_RXP1 dGPU_TXN_CPU_RXN1

dGPU_TXP_CPU_RXP2 dGPU_TXN_CPU_RXN2

dGPU_TXP_CPU_RXP3 dGPU_TXN_CPU_RXN3

GPIO51(PCH)

GPIO96(KBC)

GPIO51(KBC)

GPIO54(PCH)

D7301

3

BAT54A-1-GP

75.00054.X7D

2nd = 75.00054.R7D

3rd = 75.BAT54.07D

4th = 75.00054.Y7D

GPU_CLKREQ#

3

PDP-06877-006

1

GC6_20

SYS_PEX_RST_MON#

2

GPU_PEX_RST# [76]

GPU1A

1/14 PCI_EXPRESS

AB6

PEX_WAKE#

AC7

PEX_RST#

AC6

PEX_CLKREQ#

AE8

PEX_REFCLK

AD8

PEX_REFCLK#

AC9

PEX_TX0

AB9

PEX_TX0#

AG6

PEX_RX0

AG7

PEX_RX0#

AB10

PEX_TX1

AC10

PEX_TX1#

AF7

PEX_RX1

AE7

PEX_RX1#

AD11

PEX_TX2

AC11

PEX_TX2#

AE9

PEX_RX2

AF9

PEX_RX2#

AC12

PEX_TX3

AB12

PEX_TX3#

AG9

PEX_RX3

AG10

PEX_RX3#

AB13

PEX_TX4

AC13

PEX_TX4#

AF10

PEX_RX4

AE10

PEX_RX4#

AD14

PEX_TX5

AC14

PEX_TX5#

AE12

PEX_RX5

AF12

PEX_RX5#

AC15

PEX_TX6

AB15

PEX_TX6#

AG12

PEX_RX6

AG13

PEX_RX6#

AB16

PEX_TX7

AC16

PEX_TX7#

AF13

PEX_RX7

AE13

PEX_RX7#

AD17

PEX_TX8

AC17

PEX_TX8#

AE15

PEX_RX8

AF15

PEX_RX8#

AC18

PEX_TX9

AB18

PEX_TX9#

AG15

PEX_RX9

AG16

PEX_RX9#

AB19

PEX_TX10

AC19

PEX_TX10#

AF16

PEX_RX10

AE16

PEX_RX10#

AD20

PEX_TX11

AC20

PEX_TX11#

AE18

PEX_RX11

AF18

PEX_RX11#

AC21

PEX_TX12

AB21

PEX_TX12#

AG18

PEX_RX12

AG19

PEX_RX12#

AD23

PEX_TX13

AE23

PEX_TX13#

AF19

PEX_RX13

AE19

PEX_RX13#

AF24

PEX_TX14

AE24

PEX_TX14#

AE21

PEX_RX14

AF21

PEX_RX14#

AG24

PEX_TX15

AG25

PEX_TX15#

AG21

PEX_RX15

AG22

PEX_RX15#

N14M-GE-S-A2-GP

71.0N14M.B0U

N15V-GM-S-A2: 071.0N15V.0A0U N15V-GM-S is GF117. N15S-GT is GM108.

From GPIO21

GPU_PEX_RST_HOLD [76]

GK208/GF117/GF119

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

OPS

GF117GF119

GF117GF119 GK208

GK208

3

1 OF 14

PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

PEX_PLL_HVDD PEX_PLL_HVDD

PEX_SVDD_3V3

VDD_SENSE

GND_SENSE

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT#

PEX_PLLVDD PEX_PLLVDD

TESTMODE

PEX_TERMP

Place close VDD ball

C7312

AA22 AB23 AC24 AD25 AE26 AE27

AA10 AA12 AA13 AA16 AA18 AA19 AA20

C7311

AA21 AB22 AC23 AD24 AE25 AF26 AF27

3.3V +/- 5% 210mA

AA8 AA9

AB8

Place close Chip

F2

F1

PEXTSTCLK_OUT

AF22

PEXTSTCLK_OUT#

AE22

VCC1R05VIDEO_PEX_PLLVDD

AA14 AA15

TESTMODE

AD9

10KR2F-2-GP

PEX_TERMP

AF25

2K49R2F-GP

Place close Chip

12

OPS

C7313

SC1U10V2KX-1GP

C7310

12

OPS

C7323

SC4D7U6D3V3KX-GP

OPS

SC10U6D3V3MX-GP

Place close ChipPlace close VDD ball

12

C7316SCD1U16V2KX-3GP

C7309

OPS

SC4D7U6D3V3KX-GP

12

C7315

SC4D7U6D3V3KX-GP

12

C7320

OPS

SC10U6D3V3MX-GP

12

OPS

C7324

VGACORE_VDD_SENSE_1 [82]

VGACORE_GND_SENSE_1 [82]

OPS

C7314

SC1U10V2KX-1GP

OPS

R7307

200R2F-L-GP

1 2

DY

Place close VDD ball Place close Chip

C7318

12

OPS

R7302

1 2

OPS

R7301

1 2

OPS

SCD1U16V2KX-3GP

C7322

C7321

3V3_AON_S0

12

OPS

SC4D7U6D3V3KX-GP

OPS

SC10U6D3V3MX-GP

OPS

SC10U6D3V3MX-GP

2

1D05V_VGA_S0

12

C7325

C7327

OPS

SC10U6D3V3MX-GP

12

OPS

SC10U6D3V3MX-GP

12

C7326

OPS

SC10U6D3V3MX-GP

1D05V_VGA_S0

12

C7328

OPS

SC10U6D3V3MX-GP

1.05V +/- 30mV

3.3A

12

1

POWER IC

L7301

1D05V_VGA_S0

MHC1608S121PBP-GP

OPS

1 2

68.00335.151

12

C7317

C7319

SC4D7U6D3V3KX-GP

OPS

SC4D7U6D3V3KX-GP

OPS

SC1U10V2KX-1GP

2

68.00335.151

12

OPS

1.05V +/- 30mV 150mA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_PCIE/STRAPPING(1/5)

Size Document Number Rev

Size Document Number Rev A2

A2

Friday, February 07, 2014

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

73 104

1

A00

5

4

3

2

1

LVDS Interface

7 OF 14

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

DVI/HDMI

I2CW_SDA

I2CW_SDA I2CW_SCL

I2CW_SCL

GF119/GK208

TXC

TXC TXC

TXC

TXD0

TXD0 TXD0

TXD0

TXD1

TXD1 TXD1

TXD1

TXD2

TXD2 TXD2

TXD2

7 OF 14

AC4

IFPA_TXC#

AC3

IFPA_TXC

Y3

IFPA_TXD0#

Y4

IFPA_TXD0

AA2

IFPA_TXD1#

AA3

IFPA_TXD1

AA1

IFPA_TXD2#

AB1

IFPA_TXD2

AA5

IFPA_TXD3#

AA4

IFPA_TXD3

AB4

IFPB_TXC#

AB5

IFPB_TXC

AB2

IFPB_TXD4#

AB3

IFPB_TXD4

AD2

IFPB_TXD5#

AD3

IFPB_TXD5

AD1

IFPB_TXD6#

AE1

IFPB_TXD6

AD5

IFPB_TXD7#

AD4

IFPB_TXD7

GM108

B3

GPIO14

8 OF 14

IFPC

DP

IFPC_AUX_I2CW_SDA#

IFPC_AUX_I2CW_SCL

IFPC_L3#

IFPC_L3

IFPC_L2#

IFPC_L2

IFPC_L1#

IFPC_L1

IFPC_L0#

IFPC_L0

GM108

GPIO15

9 OF 14

GF119/GK208

IFPD_AUX_I2CX_SDA#

IFPD_AUX_I2CX_SCL

TXC

TXC TXC

TXC

TXD0

TXD0 TXD0

TXD0

TXD1

TXD1 TXD1

TXD1

TXD2

TXD2 TXD2

TXD2

GF119/GK208

I2CY_SDA

I2CY_SDA I2CY_SCL

I2CY_SCL

TXC

TXC TXCTXC

TXCTXC

TXD0

TXD0 TXD0

TXD0

TXD1NC

TXD1NC TXD1

TXD1

TXD2

TXD2 TXD2

TXD2

HPD_E

GF119/GK208

I2CZ_SDA

I2CZ_SDA I2CZ_SCL

I2CZ_SCL

TXC

TXC TXC

TXC

TXD0

TXD0 TXD0

TXD0

TXD1

TXD1 TXD1

TXD1

TXD2

TXD2 TXD2

TXD2

NC FOR GK208

HPD_F

9 OF 14

DP

P4 P3

R5

IFPD_L3#

R4

IFPD_L3

T5

IFPD_L2#

T4

IFPD_L2

U4

IFPD_L1#

U3

IFPD_L1

V4

IFPD_L0#

V3

IFPD_L0

GM108

D4

GPIO17

10 OF 14

DPDVI-SL/HDMI

IFPE_AUX_I2CY_SDA#

IFPE_AUX_I2CY_SCL

IFPE_L3#

IFPE_L3

IFPE_L2#

IFPE_L2

IFPE_L1#

IFPE_L1

IFPE_L0#

IFPE_L0

GM108

GPIO18

IFPF_AUX_I2CZ_SDA#

IFPF_AUX_I2CZ_SCL

IFPF_L3#

IFPF_L3

IFPF_L2#

IFPF_L2

IFPF_L1#

IFPF_L1

IFPF_L0#

IFPF_L0

GM108

GPIO19

J3 J2

J1 K1

K3 K2

M3 M2

M1 N1

C2

H4 H3

J5 J4

K5 K4

L4 L3

M5 M4

F7

GPU1I

6/14 IFPD

GF119/GK208

U6

IFPD_RSET

IFPC_ PLLVD D

4

DY

1

2 3

IFPEF _PLLV DD

N5 N4

N3 N2

R3 R2

R1 T1

T3 T2

IFPEF _IOVD D

C3

4

RN7403

RN7403 SRN10KJ-5-GP

SRN10KJ-5-GP

DY

1

2 3

IFPC_ IOVDD

RN7401

RN7401 SRN10KJ-5-GP

SRN10KJ-5-GP

T7

IFPD_PLLVDD

R7

IFPD_PLLVDD

R6

IFPD_IOVDD

GF119/GK208

N14M-GE-S-A2-GP

71.0N14M.B0U

OPS

GPU1J

7/14 IFPEF

J7

IFPEF_PLLVDD

K7

IFPEF_PLLVDD

K6

IFPEF_RSET

H6

IFPE_IOVDD

J6

IFPF_IOVDD

IFPD

GF119

IFPE

IFPF

GF117

GF117 GK208

GK208

NC

GF117

GM108

GF117

GF117 GK208

GK208

NC

GF117

NC

GM108

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

GF117

DVI-DL

GM108

I2CY_SDA

NC

I2CY_SDA

NC

I2CY_SCL

NC

I2CY_SCL

NC

TXC

NC

TXC

NC

NC TXD0

NC TXD0 NC

NC

TXD0

TXD1

NC

TXD1

NC

TXD1

NC

TXD2

NC

TXD2

NC

TXD2

NC

HPD_E

GF117

DVI-DL DP

GM108

NC

NC NC

NC

NC NC

NC

TXD3

NC

TXD3

NC

TXD3

NC

TXD4

NC

TXD4

NC

TXD4

TXD5NC

NC

TXD5

NC

TXD5

GF117

NC

DVI/HDMI

I2CX_SDA

I2CX_SDA I2CX_SCL

I2CX_SCL

NC FOR GK208

DVI-SL/HDMI

GPU1G

4/14 IFPAB

D D

IFPAB _PLLV DD

IFPAB _IOVD D

4

RN7402

RN7402 SRN10KJ-5-GP

SRN10KJ-5-GP

DY

1

C C

2 3

4/14 IFPAB

GF119/GK208

AA6

IFPAB_RSET

V7

IFPAB_PLLVDD

W7

IFPAB_PLLVDD

GF119/GK208

W6

IFPA_IOVDD

Y6

IFPB_IOVDD

IFPAB

N14M-GE-S-A2-GP

71.0N14M.B0U

OPS

GM108

GF117

NC

GM108

GF117

GM108

GF117

NC

HDMI Interface

GPU1H

5/14 IFPC

GF119/GK208

T6

IFPC_RSET

IFPD_ PLLVD D

B B

4

DY

1

2 3

IFPD_ IOVDD

RN7404

RN7404 SRN10KJ-5-GP

SRN10KJ-5-GP

M7

IFPC_PLLVDD

N7

IFPC_PLLVDD

P6

IFPC_IOVDD

N14M-GE-S-A2-GP

71.0N14M.B0U

OPS

GM108

GF117

NC

NC NC

NC NC NC

NC

GM108

GF117

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

N14M-GE-S-A2-GP

71.0N14M.B0U

OPS

A A

5

4

3

OPS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Friday, February 07, 2014

Friday, February 07, 2014 Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

GPU Memory(2/5)

Janus HSW 40/50/70

1

74 104

A00

5

GPU1B

FBA_D[0..31][78]

D D

FBA_D[32..63][79]

C C

FBA_DQM0[78] FBA_DQM1[78] FBA_DQM2[78] FBA_DQM3[78] FBA_DQM4[79] FBA_DQM5[79] FBA_DQM6[79] FBA_DQM7[79]

FBA_EDC0[78] FBA_EDC1[78] FBA_EDC2[78] FBA_EDC3[78] FBA_EDC4[79] FBA_EDC5[79] FBA_EDC6[79] FBA_EDC7[79]

FBA_DQS_RN0[78]

B B

FBA_DQS_RN1[78] FBA_DQS_RN2[78] FBA_DQS_RN3[78] FBA_DQS_RN4[79] FBA_DQS_RN5[79] FBA_DQS_RN6[79] FBA_DQS_RN7[79]

TP7503TP7503

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7

FB_VREF

1

GPU1B

E18 F18 E16

F17 D20 D21

F20

E21

E15 D15

F15

F13 C13

B13

E13 D13

B15 C16

A13

A15

B18

A18

A19 C19

B24 C23

A25

A24

A21

B21 C20 C21 R22 R24

T22 R23 N25 N26 N23 N24

V23

V22

T23 U22

Y24

AA24

Y22

AA23

AD27

AB25 AD26 AC25

AA27

AA26

W26

Y25

R26

T25 N27 R27

V26

V27 W27 W25

D19 D14 C17 C22

P24 W24

AA25

U25

E19 C15

B16

B22 R25 W23

AB26

T26

F19 C14

A16

A22

P25 W22

AB27

T27

D23

N14M-GE-S-A2-GP

71.0N14M.B0U

OPS

2/14 FBA

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FB_VREF_PROBE

GF119 GF117/GK208

FB_PLLAVDD

GF117 GF119/GK208

NC

GM108 FBA_CMD34 FBA_CMD35

FB_CLAMP

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_DEBUG0 FBA_DEBUG1

FBA_CLK0

FBA_CLK0#

FBA_CLK1

FBA_CLK1#

FBA_WCK01

FBA_WCK01#

FBA_WCK23

FBA_WCK23#

FBA_WCK45

FBA_WCK45#

FBA_WCK67

FBA_WCK67#

FB_PLLAVDD

FB_DLLAVDD

2 OF 14

F3

C27 C26 E24 F24 D27 D26 F25 F26 F23 G22 G23 G24 F27 G25 G27 G26 M24 M23 K24 K23 M27 M26 M25 K26 K22 J23 J25 J24 K27 K25 J27 J26

F22 J22

D24 D25 N22 M22

D18 C18 D17 D16 T24 U24 V24 V25

F16

P22

H22

4

FB_CLAM

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_DEBUG0 FBA_DEBUG1

FBA_CLK0P FBA_CLK0N FBA_CLK1P FBA_CLK1N

62mA

35mA

R7519

DY

1 2

0R2J-2-GP

R7518

1 2

OPS

10KR2J-3-GP

FBA_CMD0 [78]

FBA_CMD2 [78] FBA_CMD3 [78] FBA_CMD4 [78,79] FBA_CMD5 [78,79] FBA_CMD6 [78,79] FBA_CMD7 [78,79] FBA_CMD8 [78,79] FBA_CMD9 [78,79] FBA_CMD10 [78,79] FBA_CMD11 [78,79] FBA_CMD12 [78,79] FBA_CMD13 [78,79]

FBA_CMD15 [78,79] FBA_CMD16 [79]

FBA_CMD18 [79] FBA_CMD19 [79] FBA_CMD20 [78,79] FBA_CMD21 [78,79] FBA_CMD22 [78,79] FBA_CMD23 [78,79] FBA_CMD24 [78,79] FBA_CMD25 [78,79] FBA_CMD26 [78,79] FBA_CMD27 [78,79] FBA_CMD28 [78,79] FBA_CMD29 [78,79] FBA_CMD30 [78,79]

TP7504 TPAD14-OP-GPTP7504 TPAD14-OP-GP

1

R7501 60D4R2F-GP

1 2

R7503 60D4R2F-GP

1 2

FBA_CLK0P [78] FBA_CLK0N [78] FBA_CLK1P [79] FBA_CLK1N [79]

Under GPU

C7506

C7505

12

OPS

SCD1U16V2KX-3GP

DY

DY DY

DY

OPS

Near GPU

12

1

1D35V_VGA_S0

FBA_PLL_AVDD

12

C7518

OPS

SC22U6D3V5MX-2GP

GC6_FB_EN [20,24,76,83]

FBA_CMD5 FBA_CMD2 FBA_CMD3 FBA_CMD19 FBA_CMD18

TP7501 TPAD14-OP-GPTP7501 TPAD14-OP-GP

TP7505 TPAD14-OP-GPTP7505 TPAD14-OP-GP

TP7502 TPAD14-OP-GPTP7502 TPAD14-OP-GP

L7501

1 2

OPS

MHC1608S300QBP-GP

68.00335.051

2nd = 68.00334.051

30ohm@100MHZ(ESR=0.01ohm)

Sourcer suggest to change to

68.00335.051 from 68.00084.H41.

OPS

1D05V_VGA_S0

3

12

R7508

R7509

OPS

10KR2F-2-GP

1D35V_VGA_S0

12

R7511

OPS

10KR2F-2-GP

FB_CAL_PD_VDDQ

12

FB_CAL_PU_GND

FB_CAL_TERM_GND

R7506

51D1R2F-GP

12

R7512

10KR2F-2-GP

D22

C24

B25

N14M-GE-S-A2-GP

71.0N14M.B0U

OPS

4 OF 14

12/14 FBVDDQ

GM108 FBVDDQ_AON FBVDDQ_AON FBVDDQ_AON FBVDDQ_AON

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

GPU1D

FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ

R7510

OPS

10KR2F-2-GP

Under GPU

R7505

OPS

40D2R2F-GP

12

R7507

OPS

1 2

42D2R2F-GP

2

1.5V +/- 3%

4.88A

C7514

C7528

OPS

SC4D7U6D3V3KX-GP

SC1U10V2KX-1GP

12

OPS

C7517

C7527

1D35V_VGA_S0

C7520

OPS

1 2

SC10U10V5KX-2GP

12

C7515

OPS

SC1U10V2KX-1GP

OPS

SCD1U16V2KX-3GP

12

OPS

12

C7507

C7511

SC1U10V2KX-1GP

SCD1U16V2KX-3GP

OPS

12

OPS

12

Near GPU

C7513

OPS

SC4D7U6D3V3KX-GP

12

Under GPU

B26 C25 E23 E26 F14 F21 G13 G14 G15 G16 G18 G19 G20 G21 H24 H26 J21 K21 L22 L24 L26 M21 N21 R21 T21 V21 W21

C7502

C7501

12

OPS

SCD1U16V2KX-3GP

Close to DRAM

C7504

C7503

12

OPS

SCD1U16V2KX-3GP

C7525

C7526

1

12

SC22U6D3V5MX-2GP

OPS

1D35V_VGA_S0

12

C7519

C7521

C7516

OPS

SC1U10V2KX-1GP

12

OPS

C7530

12

C7531

OPS

SC1U10V2KX-1GP

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_DP/LVDS/CRT/GPIO(3/5)

Size Document Number Rev

Size Document Number Rev A2

A2

Friday, February 07, 2014

Friday, February 07, 2014 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Janus HSW 40/50/70

1

75 104

A00

5

11 OF 14

GPU1K

GM108

3/14 DACA

GF117 GF119/GK208

GF119/GK208

GF117 GF119/GK208

GF119/GK208

W5

DACA_VDD

AE2

DACA_VREF

AF2

DACA_RSET

D D

C C

B B

GC6_FB_EN[20,24,75,83]

N14M- GE- S- A2- GP

71.0N14M.B0U

OPS

TP7602TP7602 TP7605TP7605 TP7601TP7601

NC

TSEN_VREF

NC NC

1

TP7603TP7603

1

TP7604TP7604

N12P_JTAG_TCK N12P_JTAG_TMS

1

N12P_JTAG_TDI

1

N12P_JTAG_TDO

1

N12P_JTAG_TRST

4

RN7602

RN7602 SRN10KJ-5-GP

SRN10KJ-5-GP

OPS

1

2 3

R7607

R7607 40K2R2F-GP

40K2R2F-GP

STRAP_REF0_GND_N9

1 2

N15S-GT

N15V-GS supports Binary Mode. N15S-GT supports Multi-Level Strap.

GC6_FB_EN GC6_FB_EN_GPU

Reserved for GC6 1.0 (N14P-GV2)

A A

3D3V_VGA_S0

R7647

10KR2J-3-GP

DY

GC6_FB_EN_GPU

GM108

GF117

NC

NC NC

NC

P2800_VGA_DXN

P2800_VGA_DXP

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

R7623

1 2

0R2J-2-GP

1 2

5

DACA_HSYNC DACA_VSYNC

DACA_GREEN

GC6_20

I2CA_SDA

DACA_RED

DACA_BLUE

E12

F12

AE5 AD6 AE6

AF6

AG4

E10 F10

D1 D2 E4 E3 D3

C1

11 OF 14

B7

I2CA_SCL

A7

AE3 AE4

AG3

AF4

AF3

GPU1N

8/14 MISC1

THERMDN

THERMDP

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST#

N14M- GE- S- A2- GP

71.0N14M.B0U

OPS

GPU1L

10/14 MISC2

VMON_IN0 VMON_IN1

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

GF119

STRAP5

F6

MULTI_STRAP_REF0_GND

F4

MULTI_STRAP_REF1_GND

F5

MULTI_STRAP_REF2_GND

N14M- GE- S- A2- GP

71.0N14M.B0U

OPS

12

R7627

R7627 10KR2J-3-GP

10KR2J-3-GP

DY

Q7603

Q7603 2N7002KDW-GP

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.F3F

1

2

DY

3 4

I2CA_SCL I2CA_SDA

GF117/GF119/GK208

NC

NC NC

NC

GF119

6

FB_CLAMP_MON_SGC6_FB_EN

5

GF117

GF117 GK208

GK208

NC

(GPU_EVENT#/FB_CLAMP_TGL_REQ#)

3D3V_S0

RN7603

1234

DY

SRN2K2J-1-GP

GF117

NC

NC NC

NC

(GC6_FB_EN/FB_CLAMP_MON)

(3V3_MAIN_EN)

GK208

GK208 OVERT

OVERT

GF117GK208

GPIO16

NC

GPIO16

NC

GPIO20

NC

GPIO20

NC

GPIO8

NC

GPIO8

NC

GF117

GK208

NC

GF117

GF117 GK208

GK208 GF119

GF119

R7649

10KR2J-3-GP

GC6_20

GPU_EVENT_GPU#

R7650

R7650 10KR2J-3-GP

10KR2J-3-GP

DY

1 2

3V3_AON_S0

14 OF 14

I2CS_SCL I2CS_SDA

I2CC_SCL

I2CC_SDA

GF119

GF119 GK208

GK208

I2CB_SCL I2CB_SDA

GF119

GM108

12 OF 14

ROM_CS#

ROM_SI

ROM_SO

ROM_SCLK

BUFRST#

PGOOD

GF119

GPIO8

GM108

3V3_AON_S0

1 2

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13

GPIO16 GPIO20 GPIO21

CEC

SMBC_THERM_NV

D9

SMBD_THERM_NV

D8

I2CC_SCL

A9

I2CC_SDA

B9

I2CB_SCL

C9

I2CB_SDA

C8

GC6_FB_EN_GPU

C6 B2 D6 C7 F9

GPIO5_GC6_PWR_EN_GPU

A3

GPU_EVENT_GPU#

A4 B6

OVERT_GPU#

A6

GPIO9_ALERT

F8

GPIO10_FBVREF

C5 E7

PWR_LEVEL

D7 B4

D5 E6

GPU_PEX_RST_HOLD_GPU#

C4

DA-05691-001_V05 P15 GPIO20/21 NC : for ALL

ROM_CS#

D12

ROM_SI

B12

ROM_SO

A12

ROM_SCLK

C12

R7628

BUFRST#

D11

OPS

10KR2J-3-GP

D10

SYS_PEX_RST_MON_GPU#

E9

Connect to SYS_PEX_RST_MON# if GC62.0 is implemented. Leave NC for GC6 1.0.

3V3_AON_S0

Q7606

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

GC6_20

R7644

DY

10KR2J-3-GP

RN7604

DY

SRN2K2J-1-GP

DY

3V3_AON_S0

3D3V_VGA_S0

DY

1 2

12

D

12

4

3V3_AON_S0

1234

RN7605

RN7605 SRN2K2J-1-GP

SRN2K2J-1-GP

1234

GPIO5_GC6_PWR_EN_GPU

3V3_MAIN_EN is an open-drain GPIO.

R7636

1 2

GPIO5_GC6_PWR_EN [83]

0R2J-2-GP

GC6_20

VGA_CORE_VID [82]

VGA_CORE_PSI [82]

R7631 10KR2J-3-GP

1 2

GC6_20

R7630

1 2

0R2J-2-GP

R7626

R7626 10KR2J-3-GP

10KR2J-3-GP

R7629

GC6_20

1 2

0R2J-2-GP

3D3V_S0

R7648

R7648 10KR2J-3-GP

10KR2J-3-GP

GC6_20

1 2

4

1D05V_VGA_S0

L7601

1 2

OPS

MHC1608S300QBP-GP

68.00335.051

2nd = 68.00334.051

L7602

MCB1608S181FBP-GP

1 2

OPS

68.00909.261

180ohm@100MHz DCR=0.3 ohm Max current = 300mA

3V3_AON_S0

12

R7633

R7633 10KR2J-3-GP

10KR2J-3-GP

GC6_20

OPS

GPU_PEX_RST_HOLD [73]

SYS_PEX_RST_MON_GPU#

SYS_PEX_RST_MON# [73]

GPU_EVENT# [20]

30ohm@100MHz DCR=0.04 ohm Max current = 3000mA

C7605

12

OPS

SCD1U16V2KX-3GP

C7604

C7601

12

C7603

DY

OPS

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

3V3_AON_S0

12

R7605

R7605 100KR2J-1-GP

100KR2J-1-GP

D7601

KA

DY

1SS400GPT-GP

D7602

KA

OPS

1SS400GPT-GP

83.00400.C1F

2ND = 83.27101.01F

3RD = 83.01426.01F

GPIO10_FBVREF

12

OPS

3V3_AON_S0

DY

1 2

ROM_SCLK

ROM_SO

SORx_EXPOSED=0000

52mA

C7606

SC2D2U6D3V2MX-GP

111mA

C7602

12

OPS

SC10U6D3V3MX-GP

SCD1U16V2KX-3GP

83.00400.C1F

2ND = 83.27101.01F

3RD = 83.01426.01F

AC_PRESENT [17,24]

OVER_CURRENT_P8# [24]

R7610

R7610 100KR2J-1-GP

100KR2J-1-GP

R7643

R7643 10KR2J-3-GP

10KR2J-3-GP

12

R7608

DY

10KR2F-2-GP

12

R7616

4K99R2F-L-GP

N15S-GT

N15V_GM

GPU_PLL_VDD SP_PLLVDD

N6:On co-layout designs, this ball can be connected to power rail filter.

VIDEO_CLK_XTAL_SS

12

R7601

OPS

10KR2J-3-GP

C7607

SC15P50V2JN-2-GP

OPS

GPU_PEX_RST#[73]

VIDEO_THERM_OVERT#

1

TP7606TP7606

VGA_CORE IC not support ALERT#.

GPIO9_ALERT

3V3_AON_S0

0R0402-PAD

SML1_DATA[18,24,26]

SML1_CLK[18,24,26]

(RVL-06891-001)N15V-

3D3V_VGA_S0

12

DY

R7611

4K99R2F-L-GP

12

R7614

10KR2F-2-GP

R7618

R7620

R7651

4K99R2F-L-GP

N15S-GT

N15V-GM

10KR2F-2-GP

N15V_GM

No VBIOS ROM

3

GPU1M

9/14 XTAL_PLL

L6

CORE_PLLVDD

M6

SP_PLLVDD

N6

VID_PLL VDD

GF119/GK208

A10

XTAL_SSIN

C11

XTAL_IN

N14M- GE- S- A2- GP

71.0N14M.B0U

1MR2J-1-GP

OPS

27MHZ_IN

1 2

X7601

2 3

OPS

1 2

5

6

Q7602

2N7002KDW-GP

OPS

123 4

R7612

1 2

OPS

10KR2J-3-GP

R7624

Q7601_G

12

Q7601

3 4

2

1

2N7002KDW-GP

OPS

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

128Mx16 DDR3L

256Mx16 DDR3L

Multi Strap:RAM_CFG[3:0]

12

R7619

R7638

15KR2F-GP

N15S-GT_Hynix

10KR2F-2-GP

N15S-GT_Micron

N15S-GT_Samsung

12

R7640

R7641

24K9R2F-L-GP

10KR2F-2-GP

20KR2F-L-GP

N15S-GT_Hynix4Gb

N15S-GT_Micron4Gb

N15S-GT_Samsung4Gb

3

NC

GF117

XTAL_OUTBUFF

20PF 5% 50V +/-0.25PF 0402

R7603

DY

41

R7604

0R2J-2-GP

1 2

27MHZ_OUT_R

XTAL-27MHZ-85-GP-U

82.30034.641

2ND = 82.30034.651

3RD = 82.30034.681

R7613

R7613 10KR2J-3-GP

10KR2J-3-GP

1 2

DY

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

P_H_S#

5

6

GT

C7608

C7608 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

1 2

OPS

84.2N702.A3F

OPS

R7653

1 2

OPS

0R2J-2-GP

DY

3V3_AON_S0

SMBD_THERM_NV

SMBC_THERM_NV

-S DDR3L Recommended Memories

Strap

Hynix

0x9

Micron

0xA

Samsung

0xB

Hynix

0x3

Micron

0x4

Samsung K4W4G1646D-BC1A0x5

N15V-GM-S: Binary Strap for VRAMs. N15S-GT-S: PH 49.9k ohm on STRAP0.

Samsung/Hynix/H ynix4Gb/Micron4Gb

R7639

STRAP2

20KR2F-L-GP

STRAP3

STRAP4

R7642

30K1R2F-L-GP

13 OF 14

N12P_X TAL _OUT BUFF

C10

B10

XTAL_OUT

27MHZ_OUT

OPS

GM: R7604 = 64.15005.6DL GT: C7607 = 78.18034.1FL C7608 = 78.22034.1FL R7604 = 64.18015.6DL

3V3_AON_S0

12

R7645

R7645 10KR2J-3-GP

10KR2J-3-GP

OPS

R7652

1 2

OPS

12

0R2J-2-GP

C7609

C7609 SC2700P50V2KX-1-GP

SC2700P50V2KX-1-GP

PURE_HW_SHUTDOWN# [ 24,26,36]

12

C7610

C7610 SC2700P50V2KX-1-GP

SC2700P50V2KX-1-GP

3V3_AON_S0

4

RN7601

RN7601 SRN4K7J-8-GP

SRN4K7J-8-GP

OPS

1

2 3

H5TC2G63FFR-11C

MT41K128M16JT-107G:K

K4W2G1646E-BY11

H5TC4G63AFR-11C

MT41K256M16HA-107G:E

3V3_AON_S0

12

R7606

10KR2J-3-GP

Micron/Samsung/Hynix4Gb

12

R7637

R7637 10KR2J-3-GP

10KR2J-3-GP

Micron/Samsung4Gb

3V3_AON_S0

12

R7617

R7617 49K9R2F-L-GP

49K9R2F-L-GP

DY

PDP-06877-006

12

R7602

R7602 49K9R2F-L-GP

49K9R2F-L-GP

OPS

(RVL-06891-001)N15V-

OVERT_GPU#OVERT#

12

R7615

R7615 10KR2J-3-GP

10KR2J-3-GP

Hynix/Micron4Gb/Samsung4Gb

12

R7609

R7609 10KR2J-3-GP

10KR2J-3-GP

2

(DS-06814-001)

128Mx16 DDR3L

256Mx16 DDR3L

(DS-06814-001)

12

R7634

R7634 10KR2J-3-GP

10KR2J-3-GP

DY

STRAP0

STRAP1ROM_SI

12

R7632

R7632 10KR2J-3-GP

10KR2J-3-GP

OPS

2

Straps

-S DDR3L Recommended Memories

GM

Strap

Hynix

0xC

H5TC2G63FFR-11C

Micron

Hynix

Micron

Samsung

N15S-GT

12

R7646

10KR2J-3-GP

Hynix/Hynix4Gb

3V3_AON_S0

49K9R2F-L-GP

R7621

MT41K128M16JT-107G:K

0x1

K4W2G1646E-BY11

0x5

H5TC4G63AFR-11C

0x4

MT41K256M16HA-107G:E

0xD

K4W4G1646D-BC1A0x9

NPN-06912 NPN-06975

Samsung/Micro n/Micron4Gb/Samsun g4Gb

12

R7625

10KR2J-3-GP

12

1

STRAP2

STRAP3

1

0 001

01

01 0 0

11

10 0 1

12

R7635

R7635 10KR2J-3-GP

10KR2J-3-GP

DY

12

R7622

R7622 10KR2J-3-GP

10KR2J-3-GP

N15V-GM

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Monday, February 10, 2014

Date: Sheet of

1

STRAP0

STRAP1

100

0

1Samsung

0

1

Wistron Co rporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GPU_POWER(4/5)

Janus HSW 40/50/70

76 104

A00

5

Under GPU

C7708

C7722

12

DY

C7709

SC4D7U6D3V3KX-GP

DY

OPS

SC4D7U6D3V3KX-GP

C7725

12

OPS

SC4D7U6D3V3KX-GP

OPS

D D

C C

Near GPU

C7733

C7732

C7731

12

SC10U6D3V3MX-GP

DY

OPS

DY

ST330U2VDM-4-GP

SC4D7U6D3V3KX-GP

12

OPS

12

C7730

C7714

C7723

C7721

OPS

SC4D7U6D3V3KX-GP

4

VGA_CORE

GPU1E

K10

VDD

K12

VDD

K14

C7701

C7702

12

OPS

SC4D7U6D3V3KX-GP

C7720

12

OPS

SC4D7U6D3V3KX-GP

OPS

12

C7713

SCD1U16V2KX-3GP

C7726

12

OPS

SC4D7U6D3V3KX-GP

C7724

OPS

SC4D7U6D3V3KX-GP

OPS

SC4D7U6D3V3KX-GP

12

DY

12

OPS

C7712

12

C7719

SCD1U16V2KX-3GP

C7717

OPS

SC4D7U6D3V3KX-GP

OPS

SC4D7U6D3V3KX-GP

OPS

SC22U6D3V5MX-2GP

12

C7711

SCD1U16V2KX-3GP

C7710

12

OPS

SC47U6D3V5MX-1-GP

VDD

K16

VDD

K18

VDD

L11

VDD

L13

VDD

L15

VDD

L17

VDD

M10

VDD

M12

VDD

M14

VDD

M16

VDD

M18

VDD

N11

VDD

N13

VDD

N15

VDD

N17

VDD

P10

VDD

P12

VDD

P14

VDD

P16

VDD

P18

VDD

R11

VDD

R13

VDD

R15

VDD

R17

VDD

T10

VDD

T12

VDD

T14

VDD

T16

VDD

T18

VDD

U11

VDD

U13

VDD

U15

VDD

U17

VDD

V10

VDD

V12

VDD

V14

VDD

V16

VDD

V18

VDD

N14M-GE-S-A2-GP

71.0N14M.B0U

OPS

11/14 NVVDD

3

5 OF 14

GPU1F

A2 AB17 AB20 AB24

AC2 AC22 AC26

AC5

AC8 AD12 AD13

A26 AD15 AD16 AD18 AD19 AD21 AD22

AE11 AE14 AE17 AE20 AB11

AF1 AF11 AF14 AF17 AF20 AF23

AF5

AF8

AG2

AG26

AB14

B1 B11 B14 B17 B20 B23 B27

B5

B8 E11 E14 E17

E2 E20 E22 E25

E5

E8

H2 H23 H25

H5 K11 K13 K15 K17

L10 L12 L14 L16 L18

L2 L23 L25

L5

M11

N14M-GE-S-A2-GP

71.0N14M.B0U

OPS

13/14 GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

2

6 OF 14

M13

GND

M15

GND

M17

GND

N10

GND

N12

GND

N14

GND

N16

GND

N18

GND

P11

GND

P13

GND

P15

GND

P17

GND

P2

GND

P23

GND

P26

GND

P5

GND

R10

GND

R12

GND

R14

GND

R16

GND

R18

GND

T11

GND

T13

GND

T15

GND

T17

GND

U10

GND

U12

GND

U14

GND

U16

GND

U18

GND

U2

GND

U23

GND

U26

GND

U5

GND

V11

GND

V13

GND

V15

GND

V17

GND

Y2

GND

Y23

GND

Y26

GND

Y5

GND

AA7

GND

AB7

GND

1

G10,G12:

B B

GPU1C

14/14 XVDD/VDD33

AD10

(GM108:3V3_AON)

NC#AD10

AD7

(GM108:3V3_AON)

NC#AD7

B19

FBA_CMD32

NC#B19

F11

3V3AUX

V5

NC#V5

V6

NC#V6

CONFIGURABLE

POWER CHANNELS

* nc on substrate

G1

NC#G1

G2

NC#G2

G3

NC#G3

G4

NC#G4

G5

NC#G5

G6

NC#G6

G7

NC#G7

V1

A A

V2

W1 W2 W3 W4

5

NC#V1 NC#V2

NC#W1 NC#W2 NC#W3 NC#W4

N14M-GE-S-A2-GP

71.0N14M.B0U

OPS

If GC62.0 is implemented, connect to a 3V3 rail that will be on in GC6. If GC62.0 is NOT implemented, connect to the same rail as VDD33.

G10 G12 G8 G9

3V3_AON_S0

Under GPU Near GPU

C7734

C7729

12

OPS

SCD1U16V2KX-3GP

4

C7727

OPS

SCD1U16V2KX-3GP

3D3V_VGA_S0

12

C7728

OPS

SC1U10V2KX-1GP

C7703

SC4D7U6D3V3KX-GP

3 OF 14

VDD33 VDD33 VDD33 VDD33

3.3V +/- 5% 85mA

12

OPS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Do cument Number Rev

Size Do cument Number Rev Custom

Custom

Friday, February 07, 2014

Friday, February 07, 2014 Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

GPU_DPPWR/GND(5/5)

Janus HSW 40/50/70

77 104

1

A00

5

4

3

2

1

1D35V_VGA_S0

D D

C C

FBA_CLK0P[75] FBA_CLK0N[75 ]

FBA_CMD3[75]

1D35V_VGA_S0

FBA_VREF_0

R7808

1 2

OPS

243R2F-2-GP

FBA_CMD9[75,7 9] FBA_CMD11[75,79]

FBA_CMD8[75,7 9]

FBA_CMD25[75,79] FBA_CMD10[75,79] FBA_CMD24[75,79]

FBA_CMD22[75,79] FBA_CMD7[75,7 9]

FBA_CMD21[75,79]

FBA_CMD6[75,7 9] FBA_CMD29[75,79] FBA_CMD23[75,79]

FBA_CMD28[75,79]

FBA_CMD12[75,79]

FBA_CMD27[75,79] FBA_CMD26[75,79]

FBA_DQM0[75] FBA_DQM1[75]

FBA_CMD13[75,79]

FBA_CMD15[75,79]

FBA_CMD30[75,79]

FBA_ZQ0

FBA_CMD3

Check

B B

Frame Buffer Patition A-Lower Half

1D35V_VGA_S0

R7806

1K33R2F-GP

R7806

1K33R2F-GP

12

OPS

FBA_VREF_0

OPS

12

R7807

1K33R2F-GP

R7807

1K33R2F-GP

C7803

SC820P50V2KX-1GP

C7803

SC820P50V2KX-1GP

12

OPS

VRAM1

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

72.41K26.00U

M2

BA0

N8

BA1

M3

BA2

E7

LDM

D3

UDM

OPS

J7

CK

K7

CK#

K9

CKE

L3

WE#

K3

CAS#

J3

RAS#

MT41K256M16HA-107G-E-GP

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

LDQS

LDQS#

UDQS

UDQS#

ODT

CS#

RESET#

NC#J1 NC#J9 NC#L1

NC#L9 NC#M7 NC#T3 NC#T7

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBA_D0

E3

FBA_D4

F7

FBA_D2

F2

FBA_D7

F8

FBA_D1

H3

FBA_D5

H8

FBA_D3

G2

FBA_D6

H7

FBA_D10

D7

FBA_D13

C3

FBA_D8

C8

FBA_D12

C2

FBA_D11

A7

FBA_D15

A2

FBA_D9

B8

FBA_D14

A3

F3 G3

C7 B7

K1

L2 T2

J1 J9 L1 L9 M7 T3 T7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

FBA_D[0..31] [75]

FBA_EDC0 [75]

FBA_DQS_RN0 [75]

FBA_EDC1 [75]

FBA_DQS_RN1 [75]

FBA_CMD2 [75]

FBA_CMD0 [75] FBA_CMD5 [75,79]

FBA_CMD20 [75,79] FBA_CMD4 [75,79]

R7809

1 2

OPS

243R2F-2-GP

FBA_CMD9[75,7 9] FBA_CMD11[75,79]

FBA_CMD8[75,7 9]

FBA_CMD25[75,79] FBA_CMD10[75,79] FBA_CMD24[75,79]

FBA_CMD22[75,79] FBA_CMD7[75,7 9]

FBA_CMD21[75,79]

FBA_CMD6[75,7 9] FBA_CMD29[75,79] FBA_CMD23[75,79]

FBA_CMD28[75,79]

FBA_CMD12[75,79]

FBA_CMD27[75,79] FBA_CMD26[75,79]

FBA_DQM2[75] FBA_DQM3[75]

FBA_CLK0P[75] FBA_CLK0N[75 ]

FBA_CMD3[75]

FBA_CMD13[75,79]

FBA_CMD15[75,79]

FBA_CMD30[75,79]

1D35V_VGA_S0

FBA_VREF_0

FBA_ZQ1

1D35V_VGA_S0

FBA_CLK0P FBA_CLK0N

FBA_CMD3

VRAM2

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

72.41K26.00U

M2

BA0

N8

BA1

M3

BA2

OPS

E7

LDM

D3

UDM

J7

CK

K7

CK#

K9

CKE

L3

WE#

K3

CAS#

J3

RAS#

MT41K256M16HA-107G-E-GP

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

LDQS

LDQS#

UDQS

UDQS#

ODT

CS#

RESET#

NC#J1 NC#J9 NC#L1 NC#L9

NC#M7

NC#T3 NC#T7

VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBA_D21

E3

FBA_D17

F7

FBA_D20

F2

FBA_D16

F8

FBA_D22

H3

FBA_D19

H8

FBA_D23

G2

FBA_D18

H7

FBA_D30

D7

FBA_D25

C3

FBA_D31

C8

FBA_D26

C2

FBA_D29

A7

FBA_D24

A2

FBA_D28

B8

FBA_D27

A3

F3 G3

C7 B7

K1

L2 T2

J1 J9 L1 L9 M7 T3 T7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

FBA_D[0..31] [75]

FBA_EDC2 [75] FBA_DQS_RN2 [75]

FBA_EDC3 [75] FBA_DQS_RN3 [75]

FBA_CMD2 [75]

FBA_CMD0 [75] FBA_CMD5 [75,79]

FBA_CMD20 [75,79]

FBA_CMD4 [75,79]

Change to 10U 0603 for height limit issue.

C7812

SC1U6D3V3KX-2GP

C7812

OPS

SC1U6D3V3KX-2GP

OPS

12

SC1U6D3V3KX-2GP

C7810

SC1U6D3V3KX-2GP

C7810

SC1U6D3V3KX-2GP

OPS

12

Change to 10U 0603 for height limit issue.

C7817

SC1U6D3V3KX-2GP

C7817

OPS

SC1U6D3V3KX-2GP

OPS

12

SC1U6D3V3KX-2GP

C7811

SC1U6D3V3KX-2GP

C7811

SC1U6D3V3KX-2GP

OPS

12

FBCLK Termination place on VRAM side

FBA_CLK0P

R7810

R7810 162R2F-GP

162R2F-GP

OPS

1 2

FBA_CLK0N

Place close VRAM1 VDD ball

Place close VRAM2 VDD ball

OPS

12

OPS

12

C7827

C7820

1D35V_VGA_S0

OPS

SCD1U16V2KX-3GP

1D35V_VGA_S0

OPS

SCD1U16V2KX-3GP

Place close VRAM1VDDQ ball

OPS

C7813

SC10U6D3V3MX-GP

C7813

SC10U6D3V3MX-GP

C7814

12

OPS

12

C7832 SCD1U16V2KX-3GP

OPS

12

Place close VRAM1VDDQ ball

OPS

C7815

SC10U6D3V3MX-GP

C7815

SC10U6D3V3MX-GP

C7816

12

OPS

12

C7836 SCD1U16V2KX-3GP

OPS

12

OPS

12

C7804

SCD1U16V2KX-3GP

OPS

12

C7821

SCD1U16V2KX-3GP

1D35V_VGA_S0

C7829 SCD1U16V2KX-3GP

OPS

12

1D35V_VGA_S0

C7833 SCD1U16V2KX-3GP

OPS

12

C7805

SC1U6D3V3KX-2GP

C7805

SC1U6D3V3KX-2GP

12

C7822

SC1U6D3V3KX-2GP

C7822

SC1U6D3V3KX-2GP

12

C7830 SCD1U16V2KX-3GP

C7831 SCD1U16V2KX-3GP

OPS

12

C7835 SCD1U16V2KX-3GP

C7834 SCD1U16V2KX-3GP

OPS

12

Layout Note: Place in the end.

FBVREF Termination

A A

Type

FBVREF%

Un-termination

70%Termination

Voltage

0.749V50%

1.0617V

GPU_GPIO10

High

Low

20110613

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet of

GPU-VRAM1,2 (1/4)

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

78 104

1

A00

5

4

3

2

1

1D35V_VGA_S0

D D

C C

FBA_CLK1P[75] FBA_CLK1N[75 ]

B B

1D35V_VGA_S0

FBA_VREF_1

R7912

FBA_ZQ2

1 2

OPS

243R2F-2-GP

FBA_CMD9[75,7 8] FBA_CMD11[75,78]

FBA_CMD8[75,7 8]

FBA_CMD25[75,78] FBA_CMD10[75,78] FBA_CMD24[75,78]

FBA_CMD22[75,78] FBA_CMD7[75,7 8]

FBA_CMD21[75,78]

FBA_CMD6[75,7 8] FBA_CMD29[75,78] FBA_CMD23[75,78]

FBA_CMD28[75,78]

FBA_CMD12[75,78]

FBA_CMD27[75,78] FBA_CMD26[75,78]

FBA_DQM4[75]

FBA_DQM7[75]

FBA_CMD19[75]

FBA_CMD13[75,78]

FBA_CMD15[75,78]

FBA_CMD30[75,78]

FBA_CMD19

VRAM3

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

72.41K26.00U

M2

BA0

N8

BA1

M3

BA2

E7

LDM

D3

UDM

J7

OPS

CK

K7

CK#

K9

CKE

L3

WE#

K3

CAS#

J3

RAS#

MT41K256M16HA-107G-E-GP

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

LDQS

LDQS#

UDQS

UDQS#

ODT

CS#

RESET#

NC#J1 NC#J9 NC#L1 NC#L9

NC#M7

NC#T3 NC#T7

VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBA_D32

E3

FBA_D39

F7

FBA_D35

F2

FBA_D36

F8

FBA_D34

H3

FBA_D38

H8

FBA_D33

G2

FBA_D37

H7

FBA_D58

D7

FBA_D61

C3

FBA_D56

C8

FBA_D63

C2

FBA_D57

A7

FBA_D62

A2

FBA_D59

B8

FBA_D60

A3

F3 G3

C7 B7

K1

L2 T2

J1 J9 L1 L9 M7 T3 T7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

FBA_D[32..63] [75]

FBA_EDC4 [75]

FBA_DQS_RN4 [75]

FBA_EDC7 [75]

FBA_DQS_RN7 [75]

FBA_CMD18 [75]

FBA_CMD16 [75] FBA_CMD5 [75,78]

FBA_CMD20 [75,78]

FBA_CMD4 [75,78]

R7913

1 2

OPS

243R2F-2-GP

FBA_CMD9[75,7 8] FBA_CMD11[75,78]

FBA_CMD8[75,7 8]

FBA_CMD25[75,78] FBA_CMD10[75,78] FBA_CMD24[75,78]

FBA_CMD22[75,78] FBA_CMD7[75,7 8]

FBA_CMD21[75,78]

FBA_CMD6[75,7 8] FBA_CMD29[75,78] FBA_CMD23[75,78]

FBA_CMD28[75,78]

FBA_CMD12[75,78]

FBA_CMD27[75,78] FBA_CMD26[75,78]

FBA_DQM5[75]

FBA_DQM6[75]

FBA_CLK1P[75] FBA_CLK1N[75 ]

FBA_CMD19[75]

FBA_CMD13[75,78]

FBA_CMD15[75,78]

FBA_CMD30[75,78]

Frame Buffer Patition A-Lower Half

1D35V_VGA_S0

FBCLK Termination place on VRAM side

1D35V_VGA_S0

FBA_VREF_1

FBA_ZQ3

FBA_CLK1P FBA_CLK1N

FBA_CMD19

1D35V_VGA_S0

VRAM4

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

72.41K26.00U

M2

BA0

N8

BA1

M3

BA2

OPS

E7

LDM

D3

UDM

J7

CK

K7

CK#

K9

CKE

L3

WE#

K3

CAS#

J3

RAS#

MT41K256M16HA-107G-E-GP

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

LDQS

LDQS#

UDQS

UDQS#

ODT

CS#

RESET#

NC#J1

NC#J9 NC#L1 NC#L9

NC#M7

NC#T3 NC#T7

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FBA_D41

E3

FBA_D45

F7

FBA_D43

F2

FBA_D47

F8

FBA_D40

H3

FBA_D46

H8

FBA_D42

G2

FBA_D44

H7

FBA_D49

D7

FBA_D53

C3

FBA_D51

C8

FBA_D54

C2

FBA_D50

A7

FBA_D55

A2

FBA_D48

B8

FBA_D52

A3

F3 G3

C7 B7

K1

L2 T2

J1 J9 L1 L9 M7 T3 T7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

FBA_D[32..63] [75]

FBA_EDC5 [75]

FBA_DQS_RN5 [75]

FBA_EDC6 [75]

FBA_DQS_RN6 [75]

FBA_CMD18 [75]

FBA_CMD16 [75] FBA_CMD5 [75,78]

FBA_CMD20 [75,78]

FBA_CMD4 [75,78]

OPS

12

OPS

SC1U6D3V3KX-2GP

OPS

12

C7917

SC1U6D3V3KX-2GP

C7917

SC1U6D3V3KX-2GP

OPS

12

SC1U6D3V3KX-2GP

OPS

C7926

OPS

C7919

SC1U6D3V3KX-2GP

C7919

SC1U6D3V3KX-2GP

OPS

12

SC1U6D3V3KX-2GP

OPS

12

C7915

SC1U6D3V3KX-2GP

C7915

SC1U6D3V3KX-2GP

C7916

SC1U6D3V3KX-2GP

C7916

Place close VRAM3 VDD ball

Place close VRAM4 VDD ball

Place close VRAM3 VDDQ ball

C7918

SC10U10V5KX-2GP

C7918

SC10U10V5KX-2GP

OPS

12

Place close VRAM4 VDDQ ball

C7924

C7920

SC10U10V5KX-2GP

C7920

SC10U10V5KX-2GP

DY

12

C7921 SCD1U16V2KX-3GP

C7929 SCD1U16V2KX-3GPDYC7929 SCD1U16V2KX-3GP

OPS

1D35V_VGA_S0

C7910 SCD1U16V2KX-3GP

12

1D35V_VGA_S0

C7913 SCD1U16V2KX-3GP

12

1D35V_VGA_S0

C7922 SCD1U16V2KX-3GP

12

OPS

12

DY

OPS

DY

1D35V_VGA_S0

C7928 SCD1U16V2KX-3GP

12

OPS

12

OPS

C7909 SCD1U16V2KX-3GPDYC7909 SCD1U16V2KX-3GP

C7906

SC1U6D3V3KX-2GP

C7906

SC1U6D3V3KX-2GP

12

C7912 SCD1U16V2KX-3GP

OPS

C7911

SC1U6D3V3KX-2GP

C7911

SC1U6D3V3KX-2GP

12

C7923 SCD1U16V2KX-3GPDYC7923 SCD1U16V2KX-3GP

C7925 SCD1U16V2KX-3GP

OPS

12

C7930 SCD1U16V2KX-3GP

C7927 SCD1U16V2KX-3GP

OPS

12

R7903

1K33R2F-GP

R7903

1K33R2F-GP

FBA_VREF_1

OPS

12

OPS

R7904

1K33R2F-GP

R7904

1K33R2F-GP

C7902

SC820P50V2KX-1GP

C7902

SC820P50V2KX-1GP

12

OPS

1 2

FBA_CLK1P

R7914

R7914 162R2F-GP

162R2F-GP

OPS

FBA_CLK1N

Layout Note: Place in the end.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet of

GPU-VRAM3,4 (2/4)

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

79 104

1

A00

5

D D

C C

4

3

2

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet of

GPU-VRAM5,6 (3/4)

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

80 104

1

A00

5

D D

C C

4

3

2

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet of

GPU-VRAM7,8 (4/4)

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

81 104

1

A00

5

4

3

2

1

PWR_DCBATOUT _VGA_CORE2DCBATOUT

PG8201

1 2

GAP-CLOSE-PWR

PG8202

1 2

GAP-CLOSE-PWR

D D

C C

B B

GAP-CLOSE-PWR

PG8203

1 2

GAP-CLOSE-PWR

PG8204

1 2

GAP-CLOSE-PWR

PG8205

1 2

GAP-CLOSE-PWR

PG8206

1 2

GAP-CLOSE-PWR

DCBATOUT

3V3_AON_S0

VGA_CORE_VID[76]

PWR_VGA_CORE_RGND

R2

REFIN_VREF

R3

PC8202

PWR_VGA_CORE_TON_1

1 2

OPS

SCD1U25V2KX-GP

PR8202

1 2

OPS

2D2R2F-GP

PR8203

1 2

OPS

100KR2J-1-GP

DGPU_PWROK[15,24,83]

PR8207

1 2

0R0402-PAD

PC8203 SC1KP50V2KX-1GP

1 2

DY

PC8201

DY

SCD1U16V2KX-3GP

1 2

12

PR8206

7K5R2F-1-GP

OPS

PR8208

1 2

0R2J-2-GP

OPS

C

R4+R5

PR8209

7K87R2F-GP

OPS

12

PWR_VGA_CORE_RGND

PR8201

1 2

OPS

R1

12

PR8222

27KR2F-L-GP

OPS

12

OPS

PC8223

PC8223 SC5600P25V2KX-1GP

SC5600P25V2KX-1GP

PWR_VGA_CORE_RGND

GAP-CLOSE-PWR

PWR_VGA_CORE_TON

499KR2F-1-GP

PWR_VGA_CORE_EN

PWR_VGA_CORE_PSI

PWR_VGA_CORE_VID

PWR_VGA_CORE_VREF

PWR_VGA_CORE_REFIN

PWR_VGA_CORE_REFAD J

PWR_VGA_CORE_SS

12

PC8205

DY

SC1KP50V2KX-1GP

12

DY

PC8204

PC8204 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

PWR_VGA_CORE_RGND

PWR_DCBATOUT _VGA_CORE1DCBATOUT

PG8207

1 2

PG8208

1 2

PG8209

1 2

PG8210

1 2

PG8211

1 2

PG8212

1 2

DGPU_PWR_EN[15,83]

5V_S0

PU8201

9

TON

13

PGOOD

3

EN

4

PSI

5

VID

8

VREF

7

REFIN

6

REFADJ

11

SS

21

GND

RT8812AGQW-GP

OPS

74.08812.073

PR8257

VGA_CORE_PSI[76]

1 2

0R0402-PAD

3D3V_VGA_S0

PR8260

1 2

DY

13KR2F-GP

PC8226

For tuning VGA_CORE sequence.

12

PR8223

PR8223 2D2R3J-2-GP

2D2R3J-2-GP

OPS

RT8812_PVCC

18

PVCC

SCD1U25V2KX-GP

PR8256

1 2

1KR2J-1-GP

1 2

UGATE1

BOOT1

PHASE1

LGATE1

UGATE2

BOOT2

PHASE2

LGATE2

VSNS

RGND

DY

OPS

12

PC8207

OPS

SCD1U50V3KX-GP

PWR_VGA_CORE_UGATE1

2

PWR_VGA_CORE_BOOT1

1

PWR_VGA_CORE_PHASE1

20

PWR_VGA_CORE_LGATE1

19

PWR_VGA_CORE_UGATE2

14

PWR_VGA_CORE_BOOT2

15

PWR_VGA_CORE_PHASE2

16

PWR_VGA_CORE_LGATE2

17

PWR_VGA_CORE_VSNS

12

PWR_VGA_CORE_RGND

10

3V3_AON_S0

12

PR8258

PR8258 10KR2J-3-GP

10KR2J-3-GP

OPS

PWR_VGA_CORE_PSI

12

PR8259

PR8259 10KR2J-3-GP

10KR2J-3-GP

DY

SCD1U25V2KX-GP

DY

1 2

PWR_VGA_CORE_EN

PC8225

PR8224

1 2

8K06R2F-GP

PR8210

PWR_VGA_CORE_BOOT1_1

1 2

0R3J-0-U-GP

OPS

OCP setting (current limit ~ 61.5A)

OPS

OPS should be in DUMMY column.

PR8211

PWR_VGA_CORE_BOOT2_1

1 2

OPS

0R3J-0-U-GP

1 2

OPS

PC8211

PC8211 SCD1U50V3KX-GP

SCD1U50V3KX-GP

1 2

OPS

PC8216

PC8216 SCD1U50V3KX-GP

SCD1U50V3KX-GP

12

PC8219

PC8219 SC47P50V2JN-3GP

SC47P50V2JN-3GP

OPS

PU8203, PU8205, PU8207 and PU8209 manually change to 84.SRA12.037

PWR_DCBATOUT _VGA_CORE1

PC8208

12

OPS

PU8204

567

DDD

G

DY

4

567

DDD

PU8203

84.SRA12.037

84.SRA12.037 OPS(65BOM VGA)

OPS(65BOM VGA)

G

4

567

DDD

DY

G

4

567

DDD

PU8207

84.SRA12.037

84.SRA12.037 OPS(65BOM VGA)

OPS(65BOM VGA)

G

4

12

PC8222

PC8222 SC47P50V2JN-3GP

SC47P50V2JN-3GP

12

PC8217

PC8217 SC47P50V2JN-3GP

SC47P50V2JN-3GP

PU8202

SIRA14DP-T1-GE3-GP

8

D

SSS

123

PWR_VGA_CORE_UGATE1

8

D

PU8205

84.SRA12.037

SSS

123

SIRA12DP-T1-GE3-GP

PU8206

SIRA14DP-T1-GE3-GP

8

D

SSS

123

PWR_VGA_CORE_UGATE2

8

D

SSS

123

SIRA12DP-T1-GE3-GP

DY

567

8

DDD

D

DDD

D

84.A14DP.037

OPS(65BOM VGA)

G

4

SSS

123

567

8

DDD

D

DDD

D

OPS(65BOM VGA)

G

4

SSS

123

567

8

DDD

D

DDD

D

84.A14DP.037

OPS(65BOM VGA)

G

4

SSS

123

567

8

DDD

D

DDD

D

PU8209

84.SRA12.037

84.SRA12.037 OPS(65BOM VGA)

OPS(65BOM VGA)

G

4

SSS

123

VGA_CORE

12

PR8212

PR8212 100R2F-L1-GP-U

100R2F-L1-GP-U

OPS

1 2

0R0402-PAD

1 2

0R0402-PAD

12

PR8213

PR8213 100R2F-L1-GP-U

100R2F-L1-GP-U

OPS

PU8204

SIRA14DP-T1-GE3-GP

PR8221

PR8220

SIRA12DP-T1-GE3-GP

PU8208

SIRA14DP-T1-GE3-GP

SC4D7U25V5KX-GP

12

PR8216

PR8216 2D2R5F-2-GP

2D2R5F-2-GP

DY

12

PC8206

DY

SC330P50V2KX-3GP

PWR_DCBATOUT _VGA_CORE2

PC8212

12

OPS

SC4D7U25V5KX-GP

12

PR8215

PR8215 2D2R5F-2-GP

2D2R5F-2-GP

DY

12

PC8218

PC8218 SC330P50V2KX-3GP

SC330P50V2KX-3GP

SIRA12DP-T1-GE3-GP

DY

Check

PC8209

12

OPS

PC8210

SC10U25V5KX-GP

OPS

PL8201

OPS

1 2

IND- D33U H-7- GP

68.R3310.201

PWR_VGA_SNUB1

PC8213

12

OPS

PC8215

SC10U25V5KX-GP

OPS

SC4D7U25V5KX-GP

PL8202

OPS

1 2

IND- D33U H-7- GP

PWR_VGA_SNUB2

VGACORE_VDD_SENSE_1 [73]

VGACORE_GND_SENSE_1 [73]

12

SCD1U25V2KX-GP

PC8214

SC10U25V5KX-GP

OPS

SC10U25V5KX-GP

12

PC8224

OPS

1 2

VGA_CORE

12

OPS

VGA_CORE

OPS

PC8220

OPS

SCD1U25V2KX-GP

1 2

12

PT8206

SE330U2D5VM-14-GP

OPS

PC8221

PT8208

PT8207

SE330U2D5VM-14-GP

12

N15V_GM_S Config D

Design Current=33.5A

56.65A <OCP< 66.7A

N15-S-GT-S

N15V-GM-S

Component

value

R1 (PR8222)

R2 (PR8206)

R3 (PR8208)

R4+R5 (PR8209)

C (PC8223)

SE330U2D5VM-14-GP

Config D

27K

64.27025.6DL

7.5K

64.75015.6DL

0

63.R0034.1DL

7.87K

64.78715.6DL

5.6nF

78.56222.2FL

Config B

20K

64.20025.6DL

20K

64.20025.6DL

2K

64.20015.6DL

18K

64.18025.6DL

2.7nF

78.27224.2FL

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L Inductor:CHIP CHOKE 0.22UH PCMC104T-R22/ 1mohm/ Isat =60A rms /68.R2210.10C O/P cap: CHIP CAP EL 330U 2.5V M6.3*4.4 Chemi-con/79.3371V.6CL H/S: SIRA14DP-T1-GE3 / 6.8mohm/8.5mOhm@4.5Vgs/ 84.A14DP.037 L/S:SIRA06DP-T1-GE3 / 2.75mohm/3.5mOhm@4.5Vgs/ 84.SRA06.037

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8812_VGACORE

Size Document Number Rev

A2

Janus HSW 40/50/70

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

1

A00

82 104Friday, February 07, 2014

A00

5

4

3

2

1

3D3V_VGA_S0 1D05V_VGA_S0

3D3V_VGA_S0 should ramp-up before VGA_Core

VGA_Core should ramp-up before 1D5V_VGA_S0

1D35V_VGA_S0 should ramp-up before 1D05V_VGA_S0

D D

DGPU_PWROK[15,24,82 ]

NON_GC6

Cold Boot/Optimus: 3V3_AON&3V3_MAIN==>NVDD&PEX_1.05V==>FBVDD/Q

C C

GC6 2.0 Exit: 3.3V_MAIN==>NVDD&PEX1.05V

3D3V_VGA_S0

12

PR8301

PR8301 1KR2J-1-GP

1KR2J-1-GP

1D05V_S0

GC6_20

R8313

1 2

0R2J-2-GP

GC6_20

1D05V_VGA_EN

C8309

C8309 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1 2

DY

3V3_MAIN_EN is an open-drain GPIO.

GPIO5_GC6_PWR_E N[76]

Could also be used for tuning sequence.

3D3V_S0

12

C8302

SC1U10V2KX-1GP

3V3_AON_S0

5V_S0

DY

DGPU_PWR_EN[15,82]

12

C8304

1 2

1D05V_VGA_EN

SC1U10V2KX-1GP

R8315 0R2J-2-GP

DY

R8301

100KR2J-1-GP

DY

3D3V_S0 to 3D3V_VGA_S0 1D05V_S0 to 1D05V_VGA_S0

U8301

12

4

VBIAS

1

IN1#1

2

IN1#2

3

EN1

6

IN2#6

7

IN2#7

5

EN2

G5016KD1U-GP

074.05016.0093

OPS

OUT1#13 OUT1#14

OUT2#8 OUT2#9

GND GND

G

S

13 14 12

CT1

8 9 10

CT2

11 15

3D3V_S0

SCD1U16V2KX-3GP

Q8301

GC6_20

2N7002K-2-GP

VTT_C T_105VC _2

3D3V_VGA_OUT1

VTT_C T_3VC_1

C8311

12

GC6_20

D

R8302

R8302 10KR2J-3-GP

10KR2J-3-GP

GPIO5_GC6_PWR_EN#

1 2

GT: R8303 = 0 ohm (63.R0034.1DL); C8301 = 0.01u (78.10324.2FL)

OPS

R8303

GC6_20

0R2J-2-GP

C8305

12

SC470P50V2KX-3GP

GC6_20

12

C8301

C8301 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

GPIO5_GC6_PWR_E N_R#

1D05V_VGA_OUT2

GAP-CLOSE-PWR

C8316

12

SC2200P50V2KX-2GP

OPS

Q8302

DMP2130L-7-GP

S

D

G

GC6_20

G

84.02130.031

2nd = 84.00102.031

3rd = 84.03413.B31

PG8312

1 2

D

3D3V_VGA_S0

DY

12

C8307

SC10U10V5KX-2GP

12

3V3_AON_S0

C8308

12

OPS

SCD1U16V2KX-3GP

C8303

C8303 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

DY

1D05V_VGA_S0

PG8313

1 2

GAP-CLOSE-PWR

PG8314

1 2

GAP-CLOSE-PWR

PG8315

1 2

GAP-CLOSE-PWR

12

C8310

SC10U10V5KX-2GP

C8306

DY

C8306

3V3_AON_S0 3D3V_VGA_S0

R8304

1 2

0R5J-5-GP

NON_GC6

VGA_CORE&1D05V_VGA_S0 Discharge Circuit

3D3V_AUX_S5

OPS

1 2

SCD1U16V2KX-3GP

DGPU_PWR_EN#

1 2

OPS

PR8313

PR8313 100KR2J-1-GP

100KR2J-1-GP

PQ8305

2N7002KDW-GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

DGPU_PWR_EN[15,8 2]

GD S

5

6

OPS

123 4

G

SD

1D05V_VGA_S0_DISCHG

1D05V_VGA_S0

12

OPS

10R2J-2-GP

10R2J-2-GP PR8316

PR8316

PR8317

10R2J-2-GP

VGA_COR E_DISCHG

DGPU_PWR_EN#

VGA_COR E

OPS

G

12

D

PQ8307

PQ8307 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

OPS

S

1D35V_VGA_S0

B B

3D3V_AUX_KBC

2nd = 83.R2003.W81

3rd = 75.00054.A7D

A A

3rd = 75.00054.A7D

4th = 83.R2003.V81

GC6_FB_EN[20 ,24,75,76]

DGPU_PWROK[15,24,82 ]

5

GC6_20

1

2

1 2

0R2J-2-GP

NON_GC6

3D3V_AUX_S5

D8301

75.00054.E7D

BAT54C-7-F-3-GP

R8312

AO44 68, SO -8 Id=?A, Q g=9~12n C Rdson=17.4~22m ohm

1D35V_VGA_S0

SC10U6D3V3MX-GP

DY

1 2

3

1D35V_VGA_EN#

PR8314

PR8314 100KR2J-1-GP

100KR2J-1-GP

OPS

1 2

PR8311

PR8311 100KR2J-1-GP

100KR2J-1-GP

PQ8304

2N7002KDW-GP

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

1D35V_VGA_EN

1 2

R8305

GC6_20

1MR2J-1-GP

PC8303

OPS

1D35V_S3

12

SIRA06DP-T1-GE3-GP

84.SRA06.037

2nd = 84.08057.037

PC8302

SCD01U50V2KX-1GP

GD S

5

6

123 4

G

SD

1D35V_VGA_EN [51]

4

15V_S5 DCBATOUT

DY

1.35V +/- 3%.

5.6A

PQ8308

S

D

S

D

8

S

D

S

D

7

S

D

S

D

6

D

5

1D35V_VGA_S0

G

4

1D35V_ENABLE_RC

R8314

1 2

1D35V_VGA_S0

12

750KR2J-GP

1D35V_VGA_S0

PR8310

PR8310 100KR2J-1-GP

100KR2J-1-GP

1 2

1D35V_ENABLE

1 2 3

PR8312

PR8312 330KR2J-L1-GP

330KR2J-L1-GP

1D35V_VGA_S0

1 2

1D35V_VGA_S0

12

PC8307

PC8307 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

1D35V_VGA_S0

PQ8306

2N7002K-2-GP

84.2N702.J31

1D35V_VGA_S0

Discharge Circuit

DIS_1D35V_VGA_S0

1D35V_VGA_EN#

12

OPS

10R2J-2-GP

10R2J-2-GP PR8315

PR8315

D

OPS

S

G

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

DISCRETE VGA POWER

Size Document Number Rev

Custom

Janus HSW 40/50/70

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

83 104Monday, February 10, 2014

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

84 104Friday, February 07, 2014

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

85 104Friday, February 07, 2014

A00

5

SSID = Mechanical

S2

S1

S1 STF237R117H83-1-GP

STF237R117H83-1-GP

S2 STF237R117H83-1-GP

STF237R117H83-1-GP

4

H2

H2 HOLE335R115-GP

HOLE335R115-GP

H5

H5 HT85BE85R29-U-5-GP

HT85BE85R29-U-5-GP

H6

H6 HT85BE85R29-U-5-GP

HT85BE85R29-U-5-GP

3

H1

H1 HOLE335R115-GP

HOLE335R115-GP

H3

H3 HOLE335R115-GP

HOLE335R115-GP

H4

H4 HOLE256R115-GP

HOLE256R115-GP

2

1

34.4CK01.001

D D

C C

34.4CK01.001

2nd = 34.4CK01.601

3rd = 34.4CK01.501

SPR2

SPRING-102-GP

1

34.41V01.001

1

34.4CK01.001

2nd = 34.4CK01.601

3rd = 34.4CK01.501

SPR3

SPRING-102-GP

1

34.41V01.001

SPR5

SPR5 SPRING-63-GP

SPRING-63-GP

1

34.4Y806.001

1

ZZ.00PAD.D01

SPR4

SPRING-43-GP-U

1

34.15J03.001

1

ZZ.00PAD.D41

1

ZZ.00PAD.D41

1

ZZ.00PAD.D01

C1

C1 HOLE197R166-1-GP

HOLE197R166-1-GP

1

ZZ.00PAD.V71

1

ZZ.00PAD.D01

C2

C2 HOLE197R166-1-GP

HOLE197R166-1-GP

1

ZZ.00PAD.V71

1

ZZ.00PAD.D11

C3

C3 HOLE197R166-1-GP

HOLE197R166-1-GP

1

ZZ.00PAD.V71

SSID = EMI

Mind the voltage rating of the caps.

DCBATOUT

EC9709

EC9708

12

DY

12

EC9702

DY

EC9711

12

EC9703

DY

SCD1U25V2KX-GP

12

EC9712

SC1KP50V2KX-1GP

DY

SCD1U25V2KX-GP

EC9704

DY

12

EC9713

DY

SCD1U25V2KX-GP

DY

12

EC9716

DY

SC1KP50V2KX-1GP

SCD1U25V2KX-GP

12

EC9701

SCD1U25V2KX-GP

12

EC9717

SCD1U25V2KX-GP

EC9717

B B

12

EC9705

12

EC9715

DY

SCD1U25V2KX-GP

DY

12

EC9706

EC9714

12

SCD1U25V2KX-GP

SC1KP50V2KX-1GP

12

EC9707

DY

EC9709

12

EC9710

12

SC1KP50V2KX-1GP

DY

SC1KP50V2KX-1GP

DY

1D35V_VGA_S0

EC9727

12

DY

SC1U10V2KX-1GP

DY

DCBATOUT

DY

EC9725

12

EC9740

12

EC9726

EC9730

12

EC9742

12

DY

12

SC1U10V2KX-1GP

DY

EC9747

DY

1 2

SC1U10V2KX-1GP

DY

EC9741

DY

SC1KP50V2KX-1GP

1 2

EC9728

SC1U10V2KX-1GP

DY

SC1KP50V2KX-1GP

DY

EC9729

12

EC9748

12

EC9731

12

SC1U10V2KX-1GP

DY

EC9749

DY

1 2

AUD_AGND

EC9739

EC9745

12

EC9743

EC9745

12

SC1KP50V2KX-1GP

DY

SCD1U25V2KX-GP

EC9744

12

SCD1U25V2KX-GP

EC9738

SC1U10V2KX-1GP

SCD1U25V2KX-GP

5V_S53D3V_S0

DY

12

EC9734

SC1U10V2KX-1GP

DY

12

SCD1U25V2KX-GP

EC9732

SC1U10V2KX-1GP

DY

12

EC9733

SC1U10V2KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

2

Date: Sheet of

Janus HSW 40/50/70

Friday, February 07, 2014

Taipei Hsien 221, Taiwan, R.O.C.

86 104

1

A00

SCD1U25V2KX-GP

EC9735

SC1U10V2KX-1GP

3

DY

12

SCD1U25V2KX-GP

EC9736

SC1U10V2KX-1GP

DY

12

5V_S0

EC9719

EC9720

12

SC1U10V2KX-1GP

DY

A A

12

SC1U10V2KX-1GP

DY

5

EC9718

SC1U10V2KX-1GP

DY

12

EC9723

SC1U10V2KX-1GP

DY

12

EC9721

SC1U10V2KX-1GP

DY

12

EC9722

SC1U10V2KX-1GP

DY

12

EC9724

SC1U10V2KX-1GP

EC9737

12

SC1U10V2KX-1GP

DY

4

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

87 104Friday, February 07, 2014

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

88 104Friday, February 07, 2014

A00

5

D D

4

3

2

1

C C

B B

A A

5

4

(Blanking)

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A4

Date: Sheet of

2

(Reserved)Finger Print

Janus HSW 40/50/70

89 104Friday, February 07, 2014

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

Free Fall Sensor

90 104Friday, February 07, 2014

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

91 104Friday, February 07, 2014

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

92 104Friday, February 07, 2014

A00

5

D D

C C

4

3

2

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

Express Card

93 104Friday, February 07, 2014

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet of

LVDS_Switch

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

94 104

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, February 07, 2014

Date: Sheet of

CRT_Switch

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

95 104

1

A00

5

4

3

2

1

SSID = XDP

CPU XDP

D D

CFG[19:0][6]

XDP_BPM[7:0][4]

XDP_PREQ#[4]

XDP_PRDY#[4]

XDP_TDO[4]

XDP_TRST#[4]

XDP_TDI[4]

XDP_TMS[4]

DY

R9601 1KR2J-1-GP

H_VCCST_PWRGD[7]

PM_PWRBTN#[17,24]

C C

B B

PWR_DEBUG[7] SYS_PWROK[17,24]

PCH_SMBDATA[12,18,62]

PCH_SMBCLK[12,18,62]

XDP_TCLK[4]

PCIE_CLK_XDP_P[18]

PCIE_CLK_XDP_N[18]

PLT_RST#[17,24,30,36,52,58,65,73]

XDP_DBRESET#[17]

1 2

R9603 0R2J-2-GP

1 2

DY

R9604 0R2J-2-GP

1 2

DY

R9605 0R2J-2-GP

1 2

RN9601

DY

1 2 3

DY

SRN0J-6-GP

PCIE_CLK_XDP_P

PCIE_CLK_XDP_N

R96020R2J-2-GP

12

DY

SCD1U16V2KX-3GP

C9602

12

DY

VCCST_PWRGD_XDP BP_PWRGD_RST#

XDP_PW R_DEBUG XDP_SYS_PWROK

XDP_SMBDAT

4

XDP_SMBCLK

XDP_TCLK

XDP_RST

XDP_DBRESET#

1 1

1

TP9652 TPAD14-OP-GPTP9652 TPAD14-OP-GP

1

TP9651 TPAD14-OP-GPTP9651 TPAD14-OP-GP

1

TP9654 TPAD14-OP-GPTP9654 TPAD14-OP-GP

1

TP9653 TPAD14-OP-GPTP9653 TPAD14-OP-GP

1

TP9648 TPAD14-OP-GPTP9648 TPAD14-OP-GP TP9645 TPAD14-OP-GPTP9645 TPAD14-OP-GP

TP9647 TPAD14-OP-GPTP9647 TPAD14-OP-GP TP9644 TPAD14-OP-GPTP9644 TPAD14-OP-GP

TP9646 TPAD14-OP-GPTP9646 TPAD14-OP-GP TP9649 TPAD14-OP-GPTP9649 TPAD14-OP-GP

TP9650 TPAD14-OP-GPTP9650 TPAD14-OP-GP

CFG[19:0]

XDP_BPM[7:0]

XDP_PREQ#

XDP_PRDY# XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG17 CFG16 CFG8 CFG9 CFG10 CFG11 CFG19 CFG18 CFG12 CFG13 CFG14 CFG15

TP9601 TPAD14-OP-GPTP9601 TPAD14-OP-GP

1

TP9602 TPAD14-OP-GPTP9602 TPAD14-OP-GP

1

TP9624 TPAD14-OP-GPTP9624 TPAD14-OP-GP

1

TP9621 TPAD14-OP-GPTP9621 TPAD14-OP-GP

1

TP9623 TPAD14-OP-GPTP9623 TPAD14-OP-GP

1

TP9611 TPAD14-OP-GPTP9611 TPAD14-OP-GP

1

TP9612 TPAD14-OP-GPTP9612 TPAD14-OP-GP

1

TP9613 TPAD14-OP-GPTP9613 TPAD14-OP-GP

1

TP9614 TPAD14-OP-GPTP9614 TPAD14-OP-GP

1

TP9615 TPAD14-OP-GPTP9615 TPAD14-OP-GP

1

TP9616 TPAD14-OP-GPTP9616 TPAD14-OP-GP

1

TP9617 TPAD14-OP-GPTP9617 TPAD14-OP-GP

1

TP9618 TPAD14-OP-GPTP9618 TPAD14-OP-GP

1

TP9619 TPAD14-OP-GPTP9619 TPAD14-OP-GP

1

TP9626 TPAD14-OP-GPTP9626 TPAD14-OP-GP

1

TP9627 TPAD14-OP-GPTP9627 TPAD14-OP-GP

1

TP9620 TPAD14-OP-GPTP9620 TPAD14-OP-GP

1

TP9622 TPAD14-OP-GPTP9622 TPAD14-OP-GP

1

TP9630 TPAD14-OP-GPTP9630 TPAD14-OP-GP

1

TP9631 TPAD14-OP-GPTP9631 TPAD14-OP-GP

1

TP9629 TPAD14-OP-GPTP9629 TPAD14-OP-GP

1

TP9628 TPAD14-OP-GPTP9628 TPAD14-OP-GP

1

TP9634 TPAD14-OP-GPTP9634 TPAD14-OP-GP

1

TP9635 TPAD14-OP-GPTP9635 TPAD14-OP-GP

1

TP9633 TPAD14-OP-GPTP9633 TPAD14-OP-GP

1

TP9632 TPAD14-OP-GPTP9632 TPAD14-OP-GP

1

TP9637 TPAD14-OP-GPTP9637 TPAD14-OP-GP

1

TP9639 TPAD14-OP-GPTP9639 TPAD14-OP-GP

1

TP9638 TPAD14-OP-GPTP9638 TPAD14-OP-GP

1

TP9636 TPAD14-OP-GPTP9636 TPAD14-OP-GP

1

TP9640 TPAD14-OP-GPTP9640 TPAD14-OP-GP

1

TP9643 TPAD14-OP-GPTP9643 TPAD14-OP-GP

1

TP9642 TPAD14-OP-GPTP9642 TPAD14-OP-GP

1

TP9641 TPAD14-OP-GPTP9641 TPAD14-OP-GP

1

Wistron Corporation

A A

Title

CPU/PCH XDP

Size Document Number Rev

Size Document Number Rev A4

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Janus HSW 40/50/70

Friday, February 07, 2014

CPU/PCH XDP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A00

96 104

1

A00

5

4

3

2

1

Shark Bay Platform Power Sequence

(DC mode)

DC

t01

PM_PWRBTN#

>9ms

+RTC_VCC

RTC_RST#

DCBATOUT

D D

Sense the power button status

V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within

0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V.

In case of a non-Deep S4/S5 Platform timing t42 should be added to t07 which will make it 100mS minimum.

3D3V_AUX_S5

KBC_PWRBTN#

3D3V_AUX_KBC

S5_ENABLE

5V_S5

3D3V_S5

PM_RSMRST#(RSMRST#_RST)

PCH_SUSCLK_KBC

PM_PWRBTN#

PM_SLP_S4#

PM_SLP_S3#

PM_LAN_ENABLE

C C

V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V.

1D5V_S3

DDR_VREF_S3(0.75V)

5V_S0

3D3V_S0

+5VS_PCH_VCC5REF

1D5V_S0

1D8V_S0

0D75V_S0

RUNPWROK

1D05V_PCH

VCCP_CPU

1D05_VTT_PWRGD

0D85V_S0

Red Words: Controlled by EC GPIO

Press Power button

Ta+5VA_PCH_VCC5REFSUS

t05

>10ms

After Power Button

t10

>30us

Tb

Platfor m to KBC PS L_IN2

PSL_OUT#( GPIO71) kee p low

KBC GPIO34 control power on by 3V_5V_EN

5V_S5 & 3D3V_S5 need meet 0.7V difference

>100ms

t07

KBC GPIO43 to PCH

PCH to K BC GPIO00

KBC GPIO20 to PCH

PCH to K BC GPIO44

PCH to K BC GPIO01

KBC GPIO47 to LAN

Enable by PM_SLP_S4#

5V_S0 & 3D3V_S0 need meet 0.7V difference

1D8V_S0 & 1D5V_S3 power ready

D85V_PWRGD

1D8V_S0

0D85V_S0

SetVID ACK

50us< <2000us

t36

t37

<5ms

t14

t18

>0us

<650ms2ms<

t17

t13

>1ms

t19

>2ms

t20

<650ms5ms<

<100ms

1ms<

t25

KBC GPIO77 to PCH

PCH to C PU

>1ms+60us

t21+t22

PCH to a ll system

<200us

t39

D85V_PWRGD

CPU SVID BUS

VCC_CORE

VCC_GFXCORE

B B

This signal represents the Power Good for all the non-CORE and non-graphics power rails.

IMVP_PWRGD

PCH_CLOCK_OUT

ALL_SYS_PWRGD=D85V_PWRGD >99ms

PWROK(S0_PWR_GOOD)

DRAMPWROK(VDDPWRGOOD)

UNCOREPWRGOOD(H_CPUPWRGD)

SYS_PWROK

PLT_RST#

DMI

N14P-GT Power-Up/Down Sequence

DGPU_PWR_EN#(Discrete only)

3D3V_VGA_S0(VDD33)

A A

8209A_EN/DEM_VGA(Discrete only)

VGA_CORE(NVVDD)

DGPU_PWROK(Discrete only)

1D5V_VGA_S0(FBVDDQ)

1D05V_VGA_S0(PEX_VDD)

First rail to power down

Last rail to power down

3D3V_S0

tPOWER-OFF

<10ms

tNVVDD

>0ms

tNV-FBVDDQ

>0ms

tNV-PEX_VDD

For power-down, reversing the ramp-up sequence is recommended.

5

PCH GPIO54 output

RT8208 PGOOD

>0ms

VGA_CORE,1D05V_VGA_S0 1D5V_VGA_S0,3D3V_VGA_S0

4

Title

Size Document Number Rev

A1

Date: Sheet of

Friday, February 07, 2014

Date: Sheet of

Friday, February 07, 2014

Date: Sheet of

3

2

Friday, February 07, 2014

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Power Sequence

Janus HSW 40/50/70

A00

97

104

5

4

3

2

1

Wistron SHARK BAY POWER UP SEQUENCE DIAGRAM

D D

DC

Battery

-7

C C

B B

Page43

AC

Adapter in

Page42

+DC_IN

SLP_S3# de-assert, delay 20ms; PCH_PWROK assert.

BT+

SWITCH

Page44

SWITCH

Page44

Charger

BQ24715

ACOK

AD+

Page44

7

-6

AC_IN

KBC_PWRBTN#

PM_SLP_S4#

PM_SLP_S3#

6

PCH_PWROK

11

H_CPU_SVIDDAT

H_VR_ENABLE

DCBATOUT

-5

DCBATOUT

1

VDIO

VR_ON

-3

S5_ENABLE

EN1

EN2

TPS51225CRUKR

VIN

DC/DC

(3.3V/5V)

3D3V_AUX_S5

SWITCH

-4

Page24

3D3V_AUX_KBC

PSL_IN1#

KBC

PSL_IN2#

NPCE985

GPIO8

GPIO01

GPIO80

S0_PWR_GOOD

10

SLP_S3# de-assert, delay 200ms; S0_PWR_GOOD assert.

TPS51622

CSD97374

PGOOD

Page46

PWR_VCC_PWM1

VSW

Page47

VCC_CORE

Page41

GPIO34

GPIO43

GPIO20

Page24

9

8

3D3V_S5

-2

5V_S5

-3

S5_ENABLE

-1

RSMRST#_KBC

PM_PWRBTN#

2

DPWROK

Haswell ULT CPU

RSMRST#

PWRBTN#

with Lynx Point PCH

APWROK

PCH_PWROK

5

H_VCCST_PWRGD

SYS_PWROK be asserted after S0_PWR_GOOD assertion and CPU core VR power good assertion.

S0_PWR_GOOD

IMVP_PWRGD

4

PM_SLP_S3#

DDR_VTT_PG_CTRL

DDR_PG_CTL

VCCST_PWRGD

EN PGOOD

4

SYS_PWROK

PM_SLP_S4#

DCBATOUT

VIN

TPS51367

1D35V_S3

TPS51206

3

Page48

VIDSOUT

PLTRST#

VR_READY

SW

VR_EN

Page46

4a

1D05V_S0

RUNPWROK

4b

0D675V_S0

H_VR_ENABLE

H_CPU_SVIDDAT

11

12

PCI_PLTRST#

DCBATOUT

3a

VIN

TPS51367

PGOODEN

Page48

1D35V_S3

SW

RUNPWROK

4b

RUNPWROK

4b

7

RUNPWROK

3D3V_S5

SWITCH

Page36

SWITCH

Page36

Level Shifter

Page7

5V_S0

3D3V_S0

H_VCCST_PWRGD

5

4a

PM_SLP_S3#

TPS51312

EN

VIN

4

VOUT

PGOOD

Page51

1D5V_S0

RUNPWROK

4b

A A

4b 5 6 7 8 9 10 11 121 2 3a 4 4a

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

Friday, February 07, 2014

Date: Sheet of

Friday, February 07, 2014

Date: Sheet of

Friday, February 07, 2014

Taipei Hsien 221, Taiwan, R.O.C.

Power Sequence Diagram

Janus HSW 40/50/70

1

98

A00

104

5

4

3

2

1

Adapter

D D

DCBATOUT

RT8237

TPS51216RUKR AP3211

ISL95813

Charger

BQ24717

Battery

C C

+PBATT

1D05V_S0

TPS22966 SIRA06DP

1D05V_VGA_S0

TLV70215

1D5V_S0

1D35V_VGA_S0

0D675V_S01D35V_S3

VCC_CORE

VGA_CORE

TPS51125ARGER

15V_S5

3D3V_AUX_S5

5V_AUX_S5 5V_S5

AP2182SG

AP2301M8G

TPS22966

3D3V_S5

TLV70215

AO3403

USB30_VCCA

B B

USB30_VCCB

+5V_USB1

5V_S0

3D3V_S0

1D5V_S0

3D3V_LAN_S5

SY6288

ODD_PWR_5V

RT9724

LCDVDD

A A

5

4

3

TPS22966

3D3V_VGA_S0

Power Shape

Regulator LDO Switch

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Block Diagram

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Power Block Diagram

Janus HSW 40/50/70

Taipei Hsien 221, Taiwan, R.O.C.

99 104Friday, February 07, 2014

1

A00

A

B

C

D

E

PCH SMBus Block Diagram

3D3V_S5_PCH

‧

SRN2K2J-1-GP

SMBCLK

1 1

SMBDATA

SMB_CLK

SMB_DATA

‧

3D3V_S5_PCH

3D3V_S0

‧

2N7002SPT

‧

SRN2K2J-1-GP

SML0_CLK

SML0CLK

SML0_DATA

SML0DATA

3D3V_S0

‧

SRN10KJ-5-GP

DIMM 1

PCH_SMBCLK

SCL

PCH_SMBDATA

SDA

SMBus Address:0xA0/0xA1

TPAD

PCH_SMBCLK

SCL

PCH_SMBDATA

SDA

SMBus Address:0x58/0x59

PTN3355

PCH_SMBCLK

VDDA33_DP

PCH_SMBDATA

TMS

(Janus Only)

SMBus Address:0xC0H/0x40H

KBC SMBus Block Diagram

TP_VDD

‧

SRN10KJ-5-GP

TouchPad Conn.

TPDATA

TPCLK

PBAT_SMBCLK1

PBAT_SMBDAT1

TPDATA

TPCLK

Battery Conn.

CLK_SMB

SMBus address:16

DAT_SMB

HPA02224RGRR

SCL

SDA

SMBus address:12

KBC

PSDAT1

PSCLK1

GPIO17/SCL1

GPIO22/SDA1

TPDATA

TPCLK

3D3V_AUX_KBC

‧

SRN4K7J-8-GP

‧

BAT_SCL

BAT_SDA

‧

SRN33J-7-GP

NPCE285P

2 2

PCH

3D3V_S5_PCH

3D3V_S0

‧

2N7002SPT

3D3V_S0

‧

3D3V_VGA_S0

‧

SRN2K2J-8-GP

‧

SMBC_Therm_NV

SMBD_Therm_NV

THM_SML1_CLK

THM_SML1_DATA

Thermal

SCL

SDL

NCT7718W

SMBus Address:0x98/0x99

3D3V_VGA_S0

‧

SRN4K7J-8-GP

dGPU

I2CS_SCL

‧

I2CS_SDA

‧

SMBus Address:0x9E/0x9F

SRN2K2J-8-GP

SML1_CLK

SML1CLK

SML1DATA

‧

SML1_DATA

‧

SMBus Address:0x82/0x83

3 3

GPIO73/SCL2

GPIO74/SDA2

SMBus Address: 0x94/0x95/0x96/0x97

3D3V_S0

‧

2N7002DW-1-GP

3D3V_S0

‧

‧‧

DDC_DATA_HDMI

SRN2K2J-1-GP

DDPB_CTRLCLK

DDPB_CTRLDATA

4 4

PCH_HDMI_CLK DDC_CLK_HDMI

‧

PCH_HDMI_DATA

‧

A

5V_S0

‧

SRN2K2J-1-GP

B

HDMI CONN

0R2J-2-GP

DY

GPIO47/SCL4A

GPIO53/SDA4A

C

PROCHOT_EC

LCD_TST_EN

‧

0R2J-2-GP

LCD_TST

‧

D

H_PROCHOT_EC

‧

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Janus HSW 40/50/70

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

SMBUS Block Diagram

100 104Friday, February 07, 2014

E

100 104Friday, February 07, 2014

A00

5

4

3

2

1

CLK Block Diagram

Intel CPU

D D

DDR3L DIMM1

FBA_CLK0P

CK

C C

VRAM1

VRAM2

VRAM3

VRAM4

CK#

CK

CK#

CK

CK#

CK

CK#

FBA_CLK0N

FBA_CLK0P

FBA_CLK0N

FBA_CLK1P

FBA_CLK1N

FBA_CLK1P

FBA_CLK1N

‧‧‧‧

VGA N15V-GM-S-A2 GB2-64 (23x23)

FBA_CLK0

FBA_CLK0#

FBA_CLK1

FBA_CLK1#

PEX_REFCLK#

XTAL_IN

XTAL_OUT

M_A_DIMA_CLK_DDR0

CK0

M_A_DIMA_CLK_DDR#0

CK0#

M_A_DIMA_CLK_DDR1

CK1

M_A_DIMA_CLK_DDR#1

CK1# CLK_PCIE_WLAN_P3

CLK_PCIE_VGA#

CLK_PCIE_VGA

27MHZ_IN

27MHZ_OUT

B B

X1901

32.768KHz

XTAL24_IN

X1801 24MHz

XTAL24_OUT

Haswell/Broadwell ULT

SA_CLK0

SA_CLK#0

SA_CLK1

SA_CLK#1

CLKOUT_PCIE_N4

CLKOUT_PCIE_P4PEX_REFCLK

X7601 27MHz

RTC_X1

RTCX1

RTC_X2

RTCX2

XTAL24_IN

XTAL24_OUT

CLKOUT_PCIE_P2

CLKOUT_PCIE_N2

CLK_PCIE_WLAN_N3

REFCLKP0

REFCLKN0

WLAN NGFF

LAN

CLKOUT_PCIE_P3

CLKOUT_PCIE_N3

CLK_PCIE_LAN_P4

CLK_PCIE_LAN_N4

X3001 25MHz

RTL8106E/RTL8111G

REFCLK_P

REFCLK_N

LANXIN

CKXTAL1

LANXOUT

CKXTAL2

Audio

RN2102

SRN33J-5-GP-U

R1710

SUS_CLK

R1805

0R2J-2-GP

R1804

0R2J-2-GP

HDA_CODEC_BITCLK

R5815

0R2J-2-GP

R2441

‧‧‧‧

0R2J-2-GP

CLK_PCI_KBC

BITCLKHDA_BCLK/I2S0_SCLK

SUSCLK_NGFF

SUS_CLK_KBC

HDA_BITCLK

SUS_CLK_PCH

CLKOUT_LPC_1 LCLK/GPIOF5

CLKOUT_LPC_0 CLK_PCI_LPC

CLK_PCI_KBC_R

CLK_PCI_LPC_R

0R2J-2-GP

Realtek ALC3223

SUS_CLK

GPIO0/EXTCLK/F_SDIO3SUSCLK/GPIO62

LPC

NGFF

KBC NPCE285P

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

Test Point

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Janus HSW 40/50/70

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CLK Block Diagram

101 104Friday, February 07, 2014

1

A00

DELL Cedar, Janus Block Diagram

Specifications and Main Features

Frequently Asked Questions

User Manual