DELL 1330 Schematics

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Thurman UMA Schematics Document

C C

uFCPGA Mobile Merom

Intel Crestline-GM + ICH8M

B B

2007-04-23

REV : SC (DELL:X02)

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Thurman UMA

COVER PAGE

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Thermal Sensor

D D

EMC4001

C C

CRT

LCD

HDMI

28

SMBus

18

19

HDMI

18

Clock Generator CY28547LFXC

SIL 1392

6

17

SPDIF

AZALIA

SATA HDD

ODD Bay

26

PATA IDE

Headphone AMP.

LINE OUT / HP

B B

Digital MIC

19

MIC IN

LINE OUT / HP

INT. SPKR *2

31

MAX4401A

Azalia CODEC STAC 9228

Headphone AMP.

MAX9789A

31

AZALIA

30

31

RGB

LVDS

SDVO

SATA

BIOS

SPI FLASH 16Mb

4

Intel Mobile CPU

Merom 4M FSB:667/ 800 Mhz

Crestline-GM

AGTL+ CPU I/F DDR Memory I/F

EXTERNAL GRAHPICS

DMI x4

ICH8-M

Enhanced

USB 2.0/1.1 ports (10) PCI Express ports (6)

High Definition Audio

PCI/PCI BRIDGE

SPI

33

7,8

FSB 667/800MHzHOST BUS

9,10,11,12,13,14

Intel

ATA 66/ 100

SATA (3) LPC I/F

SPI

ACPI 1.1

20,21,22,23,24

SPI

LPC

EC SMSC MEC5025

3

2

Thurman UMA Block Diagram

Project code:91.4C301.001 PCB P/N :06253 REVISION :SB

200-PIN DDR2 SODIMM

DDRII 533/667MHz

C-LINK0

PCI Express (4)

USB2.0 (7)

BC

32

PCI BUS

SIO Expander SMSC ECE5021

UNBUFFERED DDR2 SODIMM Socket

Power Switch

PCIE#4 USB#6

USB#7

USB#0

USB#1

PCIE#1

USB#8 PCIE#2

PCIE#6

33

26

USB#5

15

16

Ricoh R5C833

8 in 1 card reader

1394

28

Express Card Slot 54mm

Buletooth 2.1

29

USB*1 left side

USB*1 Right side

Mini-Card WWAN

Mini-Card

802.11a/g/n

LAN BCM5906 10/100 NIC

Camera

27

25

19

1394

CONN

7 in1

8 in1 CONN

26

38

27

SIM CONN

RJ45 CONN

1

System DC/DC

TPS51120

OUTPUTSINPUTS

+PWR_SRC

+5V_ALW +5V_SUS +3.3V_SUS +3.3V_RTC_LDO

System DC/DC

TPS51124

+PWR_SRC

+1.05V_VCCP +1.5V_RUN

DDR2 DC/DC

TPS51117

+PWR_SRC

+1.8V_SUS

LDO

TPS51100

+1.8V_SUS

29

LDO

SC339SKTRT

+PWR_SRC

+0.9V_DDR_VTT V_DDR_MCH_REF

+1.25V_RUN

Battery Charger

MAX8731

INPUTS OUTPUTS

+PWR_SRC

+VCHGR

CPU DC/DC

ISL6260C

INPUTS

27

+PWR_SRC

OUTPUTS

+VCC_CORE

41

42

43

44

38

39,40

PCB LAYER

25

L1:TOP L2:GND L3:Signal L4:Signal L5:VCC L6:Signal

PS/2

BC

A A

LCD

19

Digital MIC

Camera

5

19

LCD Module

Int. KB

23

34 34

4

KBC SMSC ECE1077

34

Touch Pad

CIR

38

Biometric

Touch Pad Module

3

USB#4

Title

34

2

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

L7:GND L8:BOT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Thurman UMA

BLOCK DIAGRAM

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ICH8 SMBus Block Diagram

+3.3V_RUN

‧

+3.3V_SUS

‧

+3.3V_RUN

‧

+3.3V_WLAN

‧

+3.3V_SUS

‧

SRN2K2J-1-GP

D D

ICH8-M

SMBCLK

SMBDATA

ICH_SMBCLK ICH_SMBDATA

‧

2N7002DW-7F-GP

Express Card

ICH_SMBCLK

ICH_SMBDATA

C C

ICH_SMBCLK

ICH_SMBDATA

SMB_CLK SMB_DATA

2N7002DW-7F-GP

4

SRN4K7J-8-GP

DIMM 1

MEM_SCLK

SCL

MEM_SDATA

(Reverse Type)

SDA

SMBus Address : A0

DIMM 2

MEM_SCLK

SCL

MEM_SDATA

(Reverse Type)

SDA

SMBus Address : A4

WWAN Minicard

MEM_SCLK

SMB_CLK

MEM_SDATA

SMB_DATA

SRN2K2J-1-GP

WLAN Minicard

SMB_CLK SMB_DATA

KBC SMBus Block Diagram

KSO17/GPIOA1/AB1H_DATA

KSO16/GPIOA0/AB1H_CLK

AB1A_DATA

AB1A_CLK

SIO

MEC5025

GPIO87/AB1C_DATA

GPIO86/AB1C_CLK

CKG_SMBDAT CKG_SMBCLK

DOCK_SMBDAT DOCK_SMBCLK

PBAT_SMBDAT PBAT_SMBCLK

3

+3.3V_ALW

‧

+5V_ALW

‧

+3.3V_ALW

‧

+3.3V_ALW

‧

SRN2K2J-1-GP

SRN4K7J-8-GP

‧

SRN4K7J-8-GP

2N7002DW-7F-GP

100R2F-L1-GP-U 100R2F-L1-GP-U

‧

+3.3V_RUN

‧

+5V_RUN

‧

+3.3V_RUN

‧

SRN2K2J-1-GP

‧

+5V_RUN

‧

SRN2K2J-1-GP

‧

PBAT_SMBCLK1

PBAT_SMBDAT1

2

CLK GEN.

CLK_SDATA CLK_SCLK

SDATA SCLK

SMBus address:D2

DOCK_SMBDAT_C

DOCK_SMBCLK_C

SDATA SCLK

Battery Conn.

CLK_SMB DAT_SMB

SMBus address:16

Charger

SCL SDA

SMBus address:12

1

Capacity Button Board

SMBus address:86

LDDC_CLK LDDC_DATA

THRM_SMBCLK THRM_SMBDAT

LCD_DDCLK

LCD_DDCDAT

HDMI_SDATA

HDMI_SCLK

‧

+3.3V_ALW

SMBCLK SMDATA

Thermal

‧

SRN8K2J-3-GP

LCD_SMBCLK LCD_SMBDAT

+3.3V_RUN

‧

SMBus address:58

‧

SRN8K2J-1-GP

‧

+2.5V_RUN

‧

SRN2K2J-1-GP

‧

3

SMBus address:72

SASDA

SDASCL

SMBus address:5E

INVERTER

LVDS

Sil 1932

2

SDADDC

SCLDDC

+5V_RUN

‧

SRN1K5J-GP

‧

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

SDA

HDMI CONN

SCL

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Thurman UMA

C

Thurman UMA

SMBus Block Diagram

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GPIO90/AB1E_CLK GPIO91/AB1E_DATA

B B

AB1B_CLK/GPIOA4 AB1B_DATA/GPIOA2

A A

5

4

Crestline-GM

SDVO_CTRL_CLK

SDVO_CTRL_DATA

5

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CLOCK GEN CY28547

27M_SS/LCD96_100M SELECTION TABLE

BYTE 10

Bit5 S1 Bit4 S0 Spread Spectrum S[1:0]

00 001 1 11

D D

-0.5%(Default)

-1.0%

-1.5%

-2.0%

PIN34 FCTSEL1

PIN43 PIN44 PIN47 PIN48

SEL2 FSC

1 0

C C

0101

DOT96T

DOT96C LCD100/96T LCD100/96C

SEL1

SEL0

FSB

FSA

01 01

01

Bit2 IO_VOUT2

1 DISC.0 UMA

27M_NonSpread 27M_Spread SRCT_0 SRCC_0

CPU

100M 133M 166M 200M

BYTE 15

IO_VOUT[2,1,0]

Bit1

Bit0 IO_VOUT0

0 1

11 0

0

IO_VOUT[2,1,0]

0.8V(Default)

1

IO_VOUT1

0

1

00 0

0

1

0

11

1

FSB

X

X 667M 800M

INTEL ICH8-M STRAP PIN

Signal

HDA_SDOUT

HDA_SYNC

GNT2#

GPIO20

B B

A A

GNT3#

GNT0# SPI_CS1#

INTVRMEN

LAN100_SLP

SATALED#

SPKR

TP3

GPIO33/ HDA_DOCK_EN#

Usage/When Sampled Comment

XOR Chain Entrance/ PCIE Port Config 1 bit1, Rising Edge of PWROK

PCIE Port Config 1 bit0, Rising Edge of PWROK.

PCIE Port Config 2 bit0, Rising Edge of PWROK.

Reserved

Top-Block Swap Override. Rising Edge of PWROK.

Boot BIOS Destination Selection. Rising Edge of PWROK.

Integrated VccSus1_05 VccSus1_5 and VccCL1_5 VRM Enable/Disable.Always sampled.

Integrated VccLAN1_05 VccCL1_05 VRM enable /Disable. Always sampled.

PCIE LAN REVERSAL.Rising Edge of PWROK.

No Reboot. Rising Edge of PWROK.

XOR Chain Entrance. Rising Edge of PWROK.

Flash Descriptor Security Override Strap Rising Edge of PWROK.

5

Allows entrance to XOR Chain testing when TP3 pulled low at rising edge of PWROK.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers:offset 224h) Sets bit0 of RPC.PC(Config Registers:Offset 224h)

Sets bit2 of RPC.PC(Config Registers:Offset 224h)

Weak Internal PULL-DOWN.NOTE:This signal should not be pull HIGH.

Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.

Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

Enables integrated VccSus1_05,VccSus1_5 and VccCL1_5 VRM when sampled high

Enables integrated VccLAN1_05,VccCL1_05 VRM when sampled high

This signal has weak internal pull-up. set bit27 of MPC.LR(Device28:Function0:Offset D8)

If sampled high, the system is strapped to the "No Reboot" mode(ICH8M will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.(Offset:3410h:bit5)

This signal should not be pull low unless using XOR Chain testing.

Internal Pull-Up.If sampled low,the Flash Descriptor Security will be overidden.if high,the Security measures defined in the Flash Descriptor will be in effect. This should only be used in manufacturing environments

0.3V

0.4V

0.5V

0.6V

0.7V

0.9V

1.0V

4

INTEL CRESTLINE STRAP PIN

is Default setting

*

CFG Strap

CFG 5 CFG 6 CFG 7 CFG 9 CFG 10 CFG 11 CFG 16

FSB Dynamic ODT

CFG 18

VCC Select

CFG 19

DMI Lane Reserved

CFG 20 PCIE and SDVO

PCIE/SDVO Select

SDVO_CTRLDATA

DMI X 2 Moby Dick

DT/Transportable CPU

Reserved Lane

Reserved Calistoga

Disabled

Normal Operation

Only PCIE or SDVO is operation

No SDVO Device present

CFG[13:12]

LL

Reserved

LH

XOR Mode Enabled

HL

All Z Mode Enabled

HH

Normal Operation

Low

1.05V

3

High

DMI X 4 Calistoga Mobile CPU

Normal Operation

Mobility

*

* * *

Reserved

Enabled

1.5V

Reserved Lane

are operation simu SDVO Device present

* * * * *

*

2

PCIE Routing USB TABLE

MiniCard WWAN

LANE1

MiniCard WLAN

LANE2 LANE3

No use

LANE4

Express Card

LANE5

No use

LANE6

10/100 LOM

PCI ROUTING

INT REQ GNTIDSEL

MediaCard

AD171394/

11C

D

ICH

USB0 USB1 USB2 USB3 USB4 USB5 USB6 USB7 USB8 USB9

1

USB1 USB2

Biometric Camera Express Card BT

MINI Card WWAN

*

INTEL ICH8-M INTEGRATED PULL-UPS and PULL-DOWNS

XOR Chain Entrance Strap

ICH_RSVD

A16 swap override strap

PCI_GNT#3 low = A16 swap override enable

BOOT BIOS Strap

integrated VccSus1_05,VccSus1_5,VccCL1_5

SM_INTVRMEN

integrated VccLan1_05VccCL1_05

LAN100_SLP

DEFAULE HIGH

No Reboot Strap

SPKR LOW = Defaule

8.2K PULL HIGH

4

AZ_DOUT_ICH

tp3

0 0

11

high = default

SPI_CS#1 BOOT BIOS LocationPCI_GNT#0

0 1 SPI

01 11

High=Enable Low=Disable

High=No Reboot

Description

0 1

Normal Operation(default)

01

Set PCIE port cofig bit1

PCI LPC(Default)

3

RSVD Enter XOR Chain

SIGNAL Resistor Type/Value

HDA_BIT_CLK HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC GNT[3:0] GPIO[20] LDA[3:0]#/FHW[3:0]# LAN_RXD[2:0] LDRQ[0] LDRQ[1]/GPIO23 PME# PWRBTN# SATALED# SPI_CS1# SPI_CLK SPI_MOSI SPI_MISO TACH_[3:0] SPKR TP[3] USB[9:0][P,N] CL_RST#

2

PULL-DOWN 20K NONE PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 15K TBD

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Thurman UMA

Table of Content

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2

1

D D

CPU

ITP Conn.

TCK(PIN 5)

TCK(PIN AC5)

FBO(PIN 11)

12

R28

R28 51R2F-2-GP

51R2F-2-GP

ITP_RESET#

+1.05V_VCCP

12

R27

R27 51R2F-2-GP

51R2F-2-GP

+1.05V_VCCP

12

R24

R24 39D2R2F-L-GP

39D2R2F-L-GP

12

R23

150R2F-1-GP

70105

ITP1

1 2

3 4 5 6 7 8 9

10 11 12 13 14 15

DY

16 17 18 19 20 21 22 23 24 25 26 27 28

MLX-CON28-3-GP

20.K0116.028

29

H_CPURST# use pull-up Resistor close ITP connector 500 mil ( max )

+1.05VRUN use Decoupling Capacitor close

30

ITP connector 100 mil ( max )

150R2F-1-GP

12

+3.3V_RUN

12

R30

54D9R2F-L1-GP

R26

R26 27D4R2F-L1-GP

27D4R2F-L1-GP

R29

ITP_TCK

ITP_DBRESET#

12

1 2

R36 22D6R2F-L1-GPR36 22D6R2F-L1-GP

C C

ITP_TDI7 ITP_TMS7

ITP_TRST#7

ITP_TCK7

ITP_TDO7 CLK_CPU_ITP#6 CLK_CPU_ITP6

H_RESET#7,9

ITP_BPM#57 ITP_BPM#47 ITP_BPM#37 ITP_BPM#27

B B

ITP_BPM#17 ITP_BPM#07

ITP_DBRESET#7,22,33

ITP_TDI ITP_TMS

ITP_TRST#

ITP_TDO CLK_CPU_ITP# CLK_CPU_ITP

ITP_BPM#5 ITP_BPM#4 ITP_BPM#3 ITP_BPM#2 ITP_BPM#1 ITP_BPM#0

12

R25

680R2J-3-GP

ITP Debug Conn.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Thurman UMA

ITP Debug

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60ohm 100MHz

CLKREQ PULL HIGH

RN39

D D

SATA_CLKREQ#

MINI1CLK_REQ# CARD_CLK_REQ#

MINI2CLK_REQ#

+3.3V_RUN

C C

R199 10KR2J-3-GPR199 10KR2J-3-GP

R491 10KR2J-3-GPR491 10KR2J-3-GP

Enable TMP

B B

12

SB:70312

RN39

1 2 3 4 5 6

SRN10KJ-L3-GP

H_STP_CPU#22

Enable ITP

12

H_STP_PCI#22

12

C701

SC8P250V2CC-GP

C313

10

+3.3V_RUN

9 8

CLK_3GPLLREQ#

7

LOM_CLKREQ#

H_STP_CPU#

CLK_3GPLLREQ#10

PCI_ICH

PCI_PCCARD

H_STP_PCI#

12

C328

SC27P50V2JN-2-GP

SC8P250V2CC-GP

SC:70423SC:70423

SB:70306 delete

R206 475R2F-L1-GPR206 475R2F-L1-GP

SB:70306 delete

12

C336

SC8P250V2CC-GP

SB:70312SB:70312

3000mA 0.05ohm DC

C721

SC4D7U6D3V3KX-GP

CLK_CPU_BCLK#7 CLK_CPU_BCLK7

CLK_MCH_BCLK#9 CLK_MCH_BCLK9

12

CLK_ICH_48M22 CLK_PCI_ICH21

CLK_PCI_PCCARD28

CLK_PCI_502532

12

C340

For wireless performance Close to CLK GEN

SC12P50V2JN-3GP

C721

CLK_CPU_BCLK# CLK_CPU_BCLK

CLK_MCH_BCLK# CLK_MCH_BCLK

SATA_CLKREQ#22

LOM_CLKREQ#25

CARD_CLK_REQ#26

MINI2CLK_REQ#27 MINI1CLK_REQ#27

CLK_ICH_48M CLK_PCI_ICH

CLK_PCI_PCCARD CLK_PCI_5025

CLK_ICH_14M

4

L52

1 2

BLM21PG600SN-1GP

12

+CK_VDD_MAIN2

C319

SC10U6D3V5MX-3GP

1 2

+CK_VDD_A

RN43 SRN33J-5-GP-URN43 SRN33J-5-GP-U

RN42 SRN33J-5-GP-URN42 SRN33J-5-GP-U

12

C350

SCD047U10V2KX-2GP

4

SB:70312

X-14D31818M-25GP

C343

C343 SC33P50V2JN-3GP

SC33P50V2JN-3GP

1 2

SB:70215

CPU_BCLK# CPU_BCLK

MCH_BCLK# MCH_BCLK

12 12

1 2

1 2 3

R487 33R2J-2-GPR487 33R2J-2-GP R196 33R2J-2-GPR196 33R2J-2-GP

R203 33R2J-2-GPR203 33R2J-2-GP R207 33R2J-2-GPR207 33R2J-2-GP

Place near C10

SATA_CLKREQ# MCH_3GPLL_REQ#

LOM_CLKREQ#

CARD_CLK_REQ#

MINI2CLK_REQ# MINI1CLK_REQ#

CPU_MCH_BSEL1

FSAFSA PCI_ICH

PCI_TPM

PCI_PCCARD PCI_SIO

X2

CLK_XOUT

C346

SC27P50V2JN-2-GP

1 2

12

1 2

R219 1R3F-GPR219 1R3F-GP

1 2

R489 2R3J-2-GPR489 2R3J-2-GP

13 14 10 11

24

46 26 28 57 29 62 38 71 72

45 41 37

25 34

33 32 27

1 2

R212

SB:70215

C334

SCD1U10V2KX-4GP

C334

SCD1U10V2KX-4GP

C325

12

+CK_VDD_REF

+CK_VDD_48

U20

CPUC0 CPUT0 CPUC1 CPUT1

CPU_STP#

CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4# CLKREQ5# CLKREQ6# CLKREQ7# CLKREQ8# CLKREQ9#

FSB/TEST_MODE 48M/FSA PCIF0/ITP_SEL

PCI_STP# PCI4/FCTSEL1

PCI3 PCI2 PCI1/TME

CLK_XTAL_IN

CLK_XTAL_OUT

470R2J-2-GP

3

R502

7

40

VDDA

XOUT19XIN

65

VDD_48

VDD_SRC

1 2

2D2R3J-2-GP

49

54

30

36

VDD_PCI

VDD_SRC

REF122REF0/FSC_TEST_SEL

23

CLKREF

FSC

12

1

12

18

VDD_REF

VDD_SRC

VDD_CPU

VSS_REF21VSS_CPU15VSS_SRC4VSSA

VSS_SRC

68

R211 33R2J-2-GPR211 33R2J-2-GP

SB:70312

SCD1U10V2KX-4GP

20

C315

SC10U6D3V5MX-3GP

C315

SC10U6D3V5MX-3GP

12

PGMODE

39

9

VSS_CPU

VTT_PWRGD#/PD

SRCT_0/LCD100MT SRCC_0/LCD100MC

CPUT2_ITP/SRCT_10 CPUC2_ITP/SRCC_10

VSS_PCI

VSS_PCI35VSS_48

8

31

42

12

C347

DOT96T/27M_NSS

DOT96C/27M_SS

GND

73

ICS: 71.09333.A03 ICS9LPR333CKLFT

SB:70216

2

SCD1U10V2KX-4GP

C717

SCD1U10V2KX-4GP

C717

SCD1U10V2KX-4GP

12

CLK_PWRGD

1 2

DY

R501 10KR2J-3-GP

1 2

DY

R500 10KR2J-3-GP

SDATA

SCLK

SRCT_1 SRCC_1 SRCT_2 SRCC_2 SRCT_3 SRCC_3 SRCT_4 SCRC_4 SRCT_5 SCRC_5 SRCT_6 SRCC_6 SRCT_7 SRCC_7 SRCT_8 SRCC_8 SRCT_9 SRCC_9

CY28547LFXCT-GP

Solder Thermal Pad to GND add min 4 vias

+CK_VDD_MAIN+CK_VDD_A

C323

SCD1U10V2KX-4GP

C323

SCD1U10V2KX-4GP

C320

12

17 16

47 48 50 51 52 53 55 56 58 59 60 61 63 64 66 67 70 69 3 2 6 5

43 44

CLK_ICH_14M 22

C320

12

CLK_PWRGD 22

+3.3V_RUN

CLK_SDATA CLK_SCLK

DOT96_SSC DOT96_SSC# PCIE_SATA PCIE_SATA#

MCH_3GPLL MCH_3GPLL# PCIE_LOM PCIE_LOM# PCIE_EXPCARD PCIE_EXPCARD#

PCIE_ICH PCIE_ICH# CLK_PCIE_ICH PCIE_MINI2 PCIE_MINI2# PCIE_MINI1 PCIE_MINI1# CPU_ITP CPU_ITP#

CLK_DOTT CLK_DOTC

L55

1 2

BLM21PG600SN-1GP

SCD1U10V2KX-4GP

C708

SCD1U10V2KX-4GP

1 2

Pull low to Decide VTT_PWRGO Low active

+3.3V_RUN+3.3V_RUN

60ohm 100MHz 3000mA 0.05ohm DC

SC4D7U6D3V3KX-GP

CLK_SDATA 32

CLK_SCLK 32

2 3 1

RN112 SRN33J-5-GP-URN112 SRN33J-5-GP-U

2 3 1

RN30 SRN33J-5-GP-URN30 SRN33J-5-GP-U

2 3 1

RN31 SRN33J-5-GP-URN31 SRN33J-5-GP-U

2 3 1

RN32 SRN33J-5-GP-URN32 SRN33J-5-GP-U

2 3 1

RN33 SRN33J-5-GP-URN33 SRN33J-5-GP-U

2 3 1

RN35 SRN33J-5-GP-URN35 SRN33J-5-GP-U

1 2 3

RN38 SRN33J-5-GP-URN38 SRN33J-5-GP-U

1 2 3

RN40 SRN33J-5-GP-URN40 SRN33J-5-GP-U

1 2 3

RN41 SRN33J-5-GP-URN41 SRN33J-5-GP-U

2 3 1

RN106 SRN33J-5-GP-URN106 SRN33J-5-GP-U

61229

C699

RN44

1 2 3

SRN2K2J-1-GP

DREF_SSCLK DREF_SSCLK#

4

CLK_PCIE_SATA CLK_PCIE_SATA#

4

CLK_MCH_3GPLL CLK_MCH_3GPLL#

4

CLK_PCIE_LOM CLK_PCIE_LOM#

4

CLK_PCIE_EXPCARD CLK_PCIE_EXPCARD#

4

CLK_PCIE_ICH#

4

CLK_PCIE_MINI2

4

CLK_PCIE_MINI2# CLK_PCIE_MINI1

4

CLK_PCIE_MINI1# CLK_CPU_ITP

4

CLK_CPU_ITP# MCH_DREFCLK

MCH_DREFCLK#

4

12

4

1

+CK_VDD_REF

+CK_VDD_48

+3.3V_RUN

12

C349

C349 SCD047U10V2KX-2GP

SCD047U10V2KX-2GP

12

C317

C317 SCD047U10V2KX-2GP

SCD047U10V2KX-2GP

DREF_SSCLK 10 DREF_SSCLK# 10

CLK_PCIE_SATA 20 CLK_PCIE_SATA# 20

CLK_MCH_3GPLL 10 CLK_MCH_3GPLL# 10

CLK_PCIE_LOM 25 CLK_PCIE_LOM# 25

CLK_PCIE_EXPCARD 26 CLK_PCIE_EXPCARD# 26

CLK_PCIE_ICH 21 CLK_PCIE_ICH# 21

CLK_PCIE_MINI2 27 CLK_PCIE_MINI2# 27

CLK_PCIE_MINI1 27 CLK_PCIE_MINI1# 27

CLK_CPU_ITP 5 CLK_CPU_ITP# 5

MCH_DREFCLK 10 MCH_DREFCLK# 10

+3.3V_RUN

12

R490

R490 10KR2J-3-GP

10KR2J-3-GP

DY

12

R202

R202 10KR2J-3-GP

10KR2J-3-GP

PCI_TPM

PIN34 FCTSEL1

PIN43 PIN44 PIN47 PIN48

3

DOT96T

DOT96C LCD100/96T LCD100/96C

1 DISC.0 UMA

27M_NonSpread 27M_Spread SRCT_0 SRCC_0

2

SEL0 FSA

01

CPU_MCH_BSEL0FSA CPU_MCH_BSEL1

CPU

100M 133M 166M 200M

CPU_MCH_BSEL0 7,10 CPU_MCH_BSEL1 7,10 CPU_MCH_BSEL2 7,10

FSB

X

X 667M 800M

SE:70412 delete

4

R484 2K2R2J-2-GPR484 2K2R2J-2-GP

FSC CPU_MCH_BSEL2

R210 2K2R2J-2-GPR210 2K2R2J-2-GP

A A

SEL2 FSC

1 0

12 12

SEL1 FSB

01 01

0101

5

PIN9 PGMODE

0 1

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

PIN39 DISCRIPTION

VTT_PWRGD#/PD CKPWRGD/PD#(DEFAULT)

Thurman UMA

A3

CLK_GEN CY28547

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

SC

of

646Monday, April 23, 2007

1

5

www.kythuatvitinh.com

H_A#[ 3..35] 9

1 OF 4

U54A

J4

H_A#4 H_A#5 H_A#6

H_ADSTB#0

H_ADSTB#1

H_STPCLK#

CPU_RSVD01

1

CPU_RSVD02

1

CPU_RSVD03

1

CPU_RSVD04

1

CPU_RSVD05

1

CPU_RSVD06

1

CPU_RSVD07

1

CPU_RSVD08

1

CPU_RSVD09

1

CPU_RSVD10

1

H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_A20M#

H_FERR#

H_IGNNE#

H_INTR# H_NMI# H_SMI#

D D

H_ADSTB#09

H_REQ#[0..4]9

C C

H_ADSTB#19

H_A20M#20

H_FERR#20

H_IGNNE#20

H_STPCLK#20 H_INTR#20 H_NMI#20 H_SMI#20

TP9TP9 TP8TP8 TP3TP3 TP2TP2 TP22TP22 TP16TP16 TP12TP12 TP13TP13 TP14TP14

B B

TP11TP11

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD#M4

N5

RSVD#N5

T2

RSVD#T2

V3

RSVD#V3

B2

RSVD#B2

C3

RSVD#C3

D2

RSVD#D2

D22

RSVD#D22

D3

RSVD#D3

F6

RSVD#F6

B1

KEY_NC

SKT-CPU478P-GP

62.10079.021

ICH

RESERVED

ADS# BNR#

ADDR GROUP 0

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS0# RS1# RS2#

TRDY#

HIT#

HITM#

BPM0#

ADDR GROUP 1

BPM1# BPM2# BPM3# PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS CONTROL

XDP/ITP SIGNALS CONTROL THERMAL

THERMAL

PROCHOT#

THRMDA THRMDC

THERMTRIP#

HCLK

BCLK0 BCLK1

4

H_ADS#H_A#3

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#

G2

H_HIT#

G6

H_HITM#

E4

ITP_BPM#0

AD4

ITP_BPM#1

AD3

ITP_BPM#2

AD1

ITP_BPM#3

AC4

ITP_BPM#4

AC2

ITP_BPM#5

AC1

ITP_TCK

AC5

ITP_TDI

AA6

ITP_TDO

AB3

ITP_TMS

AB5

ITP_TRST#

AB6

ITP_DBRESET#

C20

EC_CPU_PROCHOT#

D21

H_THRMDA

A24

H_THRMDC

B25

H_THERMTRIP#

C7

R88 56R2J-4-GPR88 56R2J-4-GP

CLK_CPU_BCLK

A22

CLK_CPU_BCLK#

A21

TP10TP10

1

H_ADS# 9 H_BNR# 9

H_BPRI# 9 H_DEFER# 9

H_DRDY# 9 H_DBSY# 9

H_BR0# 9

H_INIT# 20

H_LOCK# 9

H_RESET# 5,9

H_RS#[0..2] 9

H_TRDY# 9

H_HIT# 9 H_HITM# 9

ITP_BPM#0 5 ITP_BPM#1 5 ITP_BPM#2 5 ITP_BPM#3 5 ITP_BPM#4 5

ITP_BPM#5 5 ITP_TCK 5 ITP_TDI 5

ITP_TDO 5

ITP_TMS 5 ITP_TRST# 5

ITP_DBRESET# 5,22,33

H_THERMTRIP# 24

12

CLK_CPU_BCLK 6 CLK_CPU_BCLK# 6

layout note:Zo =55 ohm , 0.5" MAX for GTLREF

+1.05V_VCCP

EC_CPU_PROCHOT# 32

+1.05V_VCCP

12

R72

56R2J-4-GP

+1.05V_VCCP

1 2

2KR2F-3-GP

1 2

DY

1 2

R377

1KR2F-3-GP

V_CPU_GTLREF

R376

3

H_THRMDA 24

C225

SC2200P50V2KX-2GP

H_THRMDC 24

TP23TP23 TP15TP15

TP77TP77 TP85TP85

CPU_MCH_BSEL06,10 CPU_MCH_BSEL16,10 CPU_MCH_BSEL26,10

TP24TP24 TP1TP1

2

H_D#[0..63] 9

2 OF 4

U54B

G22 G25

G24

H22

H23 H26

H25

M24 M23

R24

N25 M26

N24

AD26

C23 D25 C24

AF26

AF1

C21

E22 F24 E26

F23 E25

E23 K24

J24 J23

F26 K22

J26

N22 K25 P26 R23 L23

L22 P25

P23 P22 T24

L25 T25

L26

A26 B22

B23

U54B

D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0#

D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

BSEL0 BSEL1 BSEL2

SKT-CPU478P-GP

62.10079.021

DATA GRP0 DATA GRP1

DATA GRP2DATA GRP3

DSTBN2# DSTBP2#

DSTBN3# DSTBP3#

MISC

DPRSTP#

PWRGOOD

D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47#

DINV2#

D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#

DINV3# COMP0

COMP1 COMP2 COMP3

DPSLP#

DPWR#

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46

H_D#47 H_DSTBN#2H_DSTBN#2 H_DSTBP#2H_DSTBP#2 H_DIV#2H_DIV#2

H_D#48

H_D#49

H_D#50

H_D#51

H_D#52

H_D#53

H_D#54

H_D#55

H_D#56

H_D#57

H_D#58

H_D#59

H_D#60

H_D#61

H_D#62

H_D#63 H_DSTBN#3 H_DSTBP#3 H_DIV#3

COMP0

COMP1

COMP2

COMP3 H_DPRSTP#

H_DPSLP# H_DPWR#H_DPWR# H_PWRGOODH_PWRGOOD H_CPUSLP# H_PSI#

H_DSTBN#2 9 H_DSTBP#2 9 H_DIV#2 9

H_DSTBN#3 9 H_DSTBP#3 9 H_DIV#3 9

R70 27D4R2F-L1-GPR70 27D4R2F-L1-GP R67 54D9R2F-L1-GPR67 54D9R2F-L1-GP R57 27D4R2F-L1-GPR57 27D4R2F-L1-GP R60 54D9R2F-L1-GPR60 54D9R2F-L1-GP

H_DPRSTP# 10,20,39 H_DPSLP# 20

H_DPWR# 9

H_CPUSLP# 9

H_PSI# 39

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_DSTBN#09 H_DSTBP#09 H_DIV#09

H_DSTBN#19 H_DSTBP#19 H_DIV#19

1 1

H_DSTBN#0 H_DSTBP#0 H_DIV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30

H_D#31 H_DSTBN#1 H_DSTBP#1 H_DIV#1

TEST1

TEST2

TEST3

TEST4

TEST5

TEST6

CPU_MCH_BSEL0 CPU_MCH_BSEL1 CPU_MCH_BSEL2

12 12 12 12

1

+1.05V_VCCP

H_PWRGOOD 20

DY

1 2

R87

200R2F-L-GP

Use old Symbol replace New P/N

original value:SKT-CPU478P-GP

+1.05V_VCCP

H_DPSLP#

12

DY

R123 56R2J-4-GP

R123 56R2J-4-GP R115 56R2J-4-GP

R115 56R2J-4-GP

R128 56R2J-4-GPR128 56R2J-4-GP

R73 56R2J-4-GPR73 56R2J-4-GP

A A

5

DY

H_DPRSTP#

12

H_FERR#

12

EC_CPU_PROCHOT#

12

4

3

TEST3 and TEST5

For the purpose of testability, route thes signals through a ground referenced Zo=55ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection.

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Thurman UMA

CPU-FSB(1/2)

1

of

746Monday, April 23, 2007

SC

5

www.kythuatvitinh.com

4 OF 4

U54D

A4

VSS

A8

VSS

A11

VSS

A14

VSS

A16

VSS

A19

VSS

D D

C C

B B

A23

VSS

AF2

VSS

B6

VSS

B8

VSS

B11

VSS

B13

VSS

B16

VSS

B19

VSS

B21

VSS

B24

VSS

C5

VSS

C8

VSS

C11

VSS

C14

VSS

C16

VSS

C19

VSS

C2

VSS

C22

VSS

C25

VSS

D1

VSS

D4

VSS

D8

VSS

D11

VSS

D13

VSS

D16

VSS

D19

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E11

VSS

E14

VSS

E16

VSS

E19

VSS

E21

VSS

E24

VSS

F5

VSS

F8

VSS

F11

VSS

F13

VSS

F16

VSS

F19

VSS

F2

VSS

F22

VSS

F25

VSS

G4

VSS

G1

VSS

G23

VSS

G26

VSS

H3

VSS

H6

VSS

H21

VSS

H24

VSS

J2

VSS

J5

VSS

J22

VSS

J25

VSS

K1

VSS

K4

VSS

K23

VSS

K26

VSS

L3

VSS

L6

VSS

L21

VSS

L24

VSS

M2

VSS

M5

VSS

M22

VSS

M25

VSS

N1

VSS

N4

VSS

N23

VSS

N26

VSS

P3

VSS

SKT-CPU478P-GP

62.10079.021

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

4

C678

C273

SC10U6D3V5MX-3GP

C273

SC10U6D3V5MX-3GP

C275

SC10U6D3V5MX-3GP

C275

SC10U6D3V5MX-3GP

C274

SC10U6D3V5MX-3GP

C274

SC10U6D3V5MX-3GP

12

C675

SC10U6D3V5MX-3GP

C675

SC10U6D3V5MX-3GP

C271

SC10U6D3V5MX-3GP

C271

SC10U6D3V5MX-3GP

12

C677

SC10U6D3V5MX-3GPDYC677

SC10U6D3V5MX-3GP

C598

12

C598

12

DY

SC:70330

C602

SC10U6D3V5MX-3GP

C602

SC10U6D3V5MX-3GP

C676

SC10U6D3V5MX-3GPDYC676

12

SC10U6D3V5MX-3GP

12

C600

C603

SC10U6D3V5MX-3GP

12

DY

C127

C673

SC10U6D3V5MX-3GP

C673

SC10U6D3V5MX-3GP

C672

SC10U6D3V5MX-3GP

C672

SC10U6D3V5MX-3GP

C104

SC10U6D3V5MX-3GP

C104

SC10U6D3V5MX-3GP

12

10uF 0805 X5R -> 85 degree C , Or better such As X6S and X7R

12

SC10U6D3V5MX-3GP

SB:70312

C680

12

DY

C128

12

C601

12

SB:70312

C670

12

DY

3

+VCC_CORE +VCC_CORE

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GPDYC680

SC10U6D3V5MX-3GP

C679

SC10U6D3V5MX-3GPDYC679

SC10U6D3V5MX-3GP

12

DY

SC10U6D3V5MX-3GP

12

SC10U6D3V5MX-3GP

12

SC10U6D3V5MX-3GPDYC670

SC10U6D3V5MX-3GP

12

C129

C99

C671

C674

SC10U6D3V5MX-3GP

12

C272

SC10U6D3V5MX-3GP

12

C100

SC10U6D3V5MX-3GP

12

C101

SC10U6D3V5MX-3GP

12

C599

SB:70312SB:70312

SC10U6D3V5MX-3GP

12

C669

DY

SC10U6D3V5MX-3GP

12

C126

SC10U6D3V5MX-3GP

12

C103

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AC10 AB10 AB12 AB14 AB15 AB17 AB18

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7 AA9

AB9

A7 A9

B7 B9

C9

D9

E7 E9

F7 F9

3 OF 4

U54C

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

SKT-CPU478P-GP

62.10079.021

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP

VCCA VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

2

+1.05V_VCCP

C91

SCD1U10V2KX-4GP

C91

SCD1U10V2KX-4GP

C149

SCD1U10V2KX-4GP

C149

SCD1U10V2KX-4GP

C147

SCD1U10V2KX-4GP

C147

SCD1U10V2KX-4GP

C178

SCD1U10V2KX-4GP

C178

12

VID[0..6]

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

Layout note: Place R53 and R54 within 1" of CPU. Routing VCC_SENSE and VSS_SENSE at

27.4 ohms with 50 mils spacing.

VID[0..6] 39

VCCSENSE 39

R49 100R2F-L1-GP-UR49 100R2F-L1-GP-U

VSSSENSE 39

R50 100R2F-L1-GP-UR50 100R2F-L1-GP-U

SCD1U10V2KX-4GP

12

C633

SCD01U16V2KX-3GP

1 2

12

C122

SCD1U10V2KX-4GP

C122

SCD1U10V2KX-4GP

+VCC_CORE

C102

SCD1U10V2KX-4GP

C102

SCD1U10V2KX-4GP

1 2

+1.5V_RUN

C640

SC10U6D3V5MX-3GP

1 2

1

12

DY

TC2

TC2 ST220U6D3VDM-13GP

ST220U6D3VDM-13GP

Layout note: place C59 near PIN B26

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Thurman UMA

06.CPU-POWER (2/2)

846Monday, April 23, 2007

1

of

SC

5

www.kythuatvitinh.com

4

3

2

1

D D

H_D#[0..63]7

C C

B B

H_REF Decoupling Crestline close Crestline 100 mil

+1.05V_VCCP

R467

1KR2F-3-GP

1 2

R459

2KR2F-3-GP

A A

1 2

5

1 2

H_RESET#5,7 H_CPUSLP#7

H_REFH_REFH_REF

C684

SCD1U10V2KX-4GP

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

H_RESET# H_CPUSLP#

Change to 71.CREST.M02

4

M10 N12

W10

AD12

AE3 AD9 AC9

AC7 AC14 AD11 AC11

AB2

AD7

AB1

AC6

AE2

AC5

AG3

AH8

AJ14

AE9 AE11 AH12

AH5

AE7

AE5

AH2 AH13

E2 G2 G7 M6 H7 H3 G4

F3 N8 H2

N9 H5

P13

K9 M2

Y8

V4 M3

J1 N5 N3 W6 W9 N2

Y7 Y9

P4 W3 N1

Y3

AJ9

AJ5 AJ6 AJ7

AJ2 AJ3

B3 C2

W1 W2

B6

E5

B9

A9

1 OF 10

U56A

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

71.CREST.00U

CRESTLINE-GP-U

H_ADSTB#0 H_ADSTB#1

HOST

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM# H_LOCK# H_TRDY#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8

H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADS#

H_BNR#

H_HIT#

H_RS#0 H_RS#1 H_RS#2

J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19

G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7

K5 L2 AD13 AE13

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

M14 E13 A11 H13 B12

E12 D7 D8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

H_DIV#0 H_DIV#1 H_DIV#2 H_DIV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

H_A#[ 3..35] 7

H_ADS# 7 H_ADSTB#0 7 H_ADSTB#1 7

H_BNR# 7

H_BPRI# 7

H_BR0# 7

H_DEFER# 7

H_DBSY# 7

CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6

H_DPWR# 7

H_DRDY# 7

H_HIT# 7

H_HITM# 7

H_LOCK# 7 H_TRDY# 7

H_DIV#0 7 H_DIV#1 7 H_DIV#2 7 H_DIV#3 7

H_DSTBN#0 7 H_DSTBN#1 7 H_DSTBN#2 7 H_DSTBN#3 7

H_DSTBP#0 7 H_DSTBP#1 7 H_DSTBP#2 7 H_DSTBP#3 7

H_REQ#[0..4] 7

H_RS#[0..2] 7

3

H_SWING routing Trace width and Spacing use 10 / 20 mil

H_SWING Resistors and Capacitors close Caliistoga 500 mil ( MAX )

From Schematic Design Checklit v.1201

221 1% pull high 100 1% pull low

H_SCOMP and H_SCOMP# Resistors and Capacitors close Caliistoga 500 mil ( MAX ) Zo=55ohms

+1.05V_VCCP

H_RCOMP routing Trace width and Spacing use 10 / 20 mil

2

R417 54D9R2F-L1-GPR417 54D9R2F-L1-GP

R420 54D9R2F-L1-GPR420 54D9R2F-L1-GP

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

H_SWING

C683

SCD1U10V2KX-4GP

1 2

12

R463 24D9R2F-L-GPR463 24D9R2F-L-GP

A3

+1.05V_VCCP

12

R465

221R2F-2-GP

12

R464

100R2F-L1-GP-U

H_SCOMP

H_SCOMP#

H_RCOMP

12

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Thurman UMA

GMCH-FSB LIBC (1/6)

SC

of

946Monday, April 23, 2007

1

5

www.kythuatvitinh.com

is Default setting

*

CFG Strap

CFG 5 CFG 6 CFG 7 CFG 9

D D

CFG 10 CFG 11 CFG 16

FSB Dynamic ODT

CFG 18

VCC Select

CFG 19

DMI Lane Reserved

CFG 20 PCIE and SDVO

PCIE/SDVO Select

SDVO_CTRLDATA

Low DMI X 2 Moby Dick

DT/Transportable CPU

Reserved Lane

Reserved Calistoga

Disabled

1.05V

Normal Operation

Only PCIE or SDVO is operation

No SDVO Device present

High

DMI X 4 Calistoga Mobile CPU

Normal Operation

Mobility

*

Reserved

Enabled

* * *

1.5V

Reserved Lane

are operation simu SDVO Device present

*

CFG[13:12] Reserved

LL

XOR Mode Enabled

LH

All Z Mode Enabled

C C

HL

Normal Operation

HH

CFG[2..0] FSB Select

LHL

FSB 800

LHH

FSB 667 Reserved

Other

CPU_MCH_BSEL06,7 CPU_MCH_BSEL16,7 CPU_MCH_BSEL26,7

Layout Note: Location of all MCH_CFG strap resistors needs to be close to minmize stub.

B B

PM_BMBUSY#22

R58 0R2J-2-GP

SB_NB_PCIE_RST#21 PM_EXTTS#015

PLTRST#17,21,25,26,27,32

DPRSLPVR22,33,39

A A

R58 0R2J-2-GP

R63 100R2J-2-GPR63 100R2J-2-GP R145 0R0402-PADR145 0R0402-PAD

5

DY

12

12 12

+3.3V_RUN

PLTRST#C

+1.05V_VCCP

RN1 SRN10KJ-5-GPRN1 SRN10KJ-5-GP

H_DPRSTP#7,20,39 PM_EXTTS#116

ICH_PWRGD22,36

THERMTRIP_MCH#24

1

4

23

61229

4

* * * * *

*

CPU_MCH_BSEL0 CPU_MCH_BSEL1 CPU_MCH_BSEL2

PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 ICH_PWRGD

THERMTRIP_MCH#

DPRSLPVR_R

R119 56R2J-4-GPR119 56R2J-4-GP

PM_EXTTS#1 PM_EXTTS#0

12

4

2 OF 10

U56B

P36

RSVD#P36

P37

RSVD#P37

R35

RSVD#R35

N35

RSVD#N35

AR12

RSVD#AR12

AR13

RSVD#AR13

AM12

RSVD#AM12

AN13

RSVD#AN13

J12

RSVD#J12

AR37

RSVD#AR37

AM36

RSVD#AM36

AL36

RSVD#AL36

AM37

RSVD#AM37

D20

RSVD#D20

H10

RSVD#H10

B51

RSVD#B51

BJ20

RSVD#BJ20

BK22

RSVD#BK22

BF19

RSVD#BF19

BH20

RSVD#BH20

BK18

RSVD#BK18

BJ18

RSVD#BJ18

BF23

RSVD#BF23

BG23

RSVD#BG23

BC23

RSVD#BC23

BD24

RSVD#BD24

BH39

RSVD#BH39

AW20

RSVD#AW20

BK20

RSVD#BK20

B44

RSVD#B44

C44

RSVD#C44

A35

RSVD#A35

B37

RSVD#B37

B36

RSVD#B36

B34

RSVD#B34

C34

RSVD#C34

P27

CFG0

N27

CFG1

N24

CFG2

C21

CFG3

C23

CFG4

F23

CFG5

N23

CFG6

G23

CFG7

J20

CFG8

C20

CFG9

R24

CFG10

L23

CFG11

J23

CFG12

E23

CFG13

E20

CFG14

K23

CFG15

M20

CFG16

M24

CFG17

L32

CFG18

N33

CFG19

L35

CFG20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#0

J36

PM_EXT_TS#1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC#BJ51

BK51

NC#BK51

BK50

NC#BK50

BL50

NC#BL50

BL49

NC#BL49

BL3

NC#BL3

BL2

NC#BL2

BK1

NC#BK1

BJ1

NC#BJ1

E1

NC#E1

A5

NC#A5

C51

NC#C51

B50

NC#B50

A50

NC#A50

A49

NC#A49

BK2

NC#BK2

CRESTLINE-GP-U 71.CREST.00U

RSVD

CFG PM NC

SM_CK0 SM_CK1 SM_CK3 SM_CK4

SM_CK#0 SM_CK#1 SM_CK#3 SM_CK#4

SM_CKE0 SM_CKE1 SM_CKE3 SM_CKE4

SM_CS#0 SM_CS#1 SM_CS#2 SM_CS#3

DDR MUXING

SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_RCOMP

SM_RCOMP#

SM_VREF#AR49

SM_VREF#AW4

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

CLK

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2

DMI

DMI_RXP3 DMI_TXN0

DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLKREQ#

ICH_SYNC#

TEST1 TEST2

MISC ME GRAPHICS VID

3

M_CLK_DDR0

AV29

M_CLK_DDR1

BB23

M_CLK_DDR2

BA25

M_CLK_DDR3

AV23

M_CLK_DDR#0

AW30

M_CLK_DDR#1

BA23

M_CLK_DDR#2

AW25

M_CLK_DDR#3

AW23

DDR_CKE0_DIMMA

BE29

DDR_CKE1_DIMMA

AY32

DDR_CKE2_DIMMB

BD39

DDR_CKE3_DIMMB

BG37

DDR_CS0_DIMMA#

BG20

DDR_CS1_DIMMA#

BK16

DDR_CS2_DIMMB#

BG16

DDR_CS3_DIMMB#

BE13

M_ODT0

BH18

M_ODT1

BJ15

M_ODT2

BJ14

M_ODT3

BE16

SM_RCOMP_VOH

BK31

SM_RCOMP_VOL

BL31

SM_RCOMP

BL15

SM_RCOMP#

BK14 AR49

AW4

MCH_DREFCLK

B42

MCH_DREFCLK#

C42

DREF_SSCLK

H48

DREF_SSCLK#

H47

CLK_MCH_3GPLL

K44

CLK_MCH_3GPLL#

K45

DMI_MRX_ITX_N0

AN47

DMI_MRX_ITX_N1

AJ38

DMI_MRX_ITX_N2

AN42

DMI_MRX_ITX_N3

AN46

DMI_MRX_ITX_P0

AM47

DMI_MRX_ITX_P1

AJ39

DMI_MRX_ITX_P2

AN41

DMI_MRX_ITX_P3

AN45

DMI_MTX_IRX_N0

AJ46

DMI_MTX_IRX_N1

AJ41

DMI_MTX_IRX_N2

AM40

DMI_MTX_IRX_N3

AM44

DMI_MTX_IRX_P0

AJ47

DMI_MTX_IRX_P1

AJ42

DMI_MTX_IRX_P2

AM39

DMI_MTX_IRX_P3

AM43

E35 A39 C38 B39 E36

Layout Note: MCH_CLVREF ~= 0.350V Width/Spacing = 12/12

CL_CLK0

AM49

CL_DATA0

AK50

ICH_CL_PWROK

AT43

ICH_CL_RST0#

AN49

MCH_CLVREF

AM50

H35 K36

CLK_3GPLLREQ#

G39

MCH_ICH_SYNC#

G40

TEST1_GMCH

A37

TEST2_GMCH

R32

3

M_CLK_DDR0 15 M_CLK_DDR1 15 M_CLK_DDR2 16 M_CLK_DDR3 16

M_CLK_DDR#0 15 M_CLK_DDR#1 15 M_CLK_DDR#2 16 M_CLK_DDR#3 16

DDR_CKE0_DIMMA 15 DDR_CKE1_DIMMA 15 DDR_CKE2_DIMMB 16 DDR_CKE3_DIMMB 16

DDR_CS0_DIMMA# 15 DDR_CS1_DIMMA# 15 DDR_CS2_DIMMB# 16 DDR_CS3_DIMMB# 16

M_ODT0 15 M_ODT1 15 M_ODT2 16 M_ODT3 16

CLOSE PIN BL15 BK14

R367 20R2F-GPR367 20R2F-GP R366 20R2F-GPR366 20R2F-GP

12

R113

20KR2J-L2-GP

12 12

V_DDR_MCH_REF

MCH_DREFCLK 6 MCH_DREFCLK# 6 DREF_SSCLK 6 DREF_SSCLK# 6

CLK_MCH_3GPLL 6 CLK_MCH_3GPLL# 6

DMI_MRX_ITX_N0 21 DMI_MRX_ITX_N1 21 DMI_MRX_ITX_N2 21 DMI_MRX_ITX_N3 21

DMI_MRX_ITX_P0 21 DMI_MRX_ITX_P1 21 DMI_MRX_ITX_P2 21 DMI_MRX_ITX_P3 21

DMI_MTX_IRX_N0 21 DMI_MTX_IRX_N1 21 DMI_MTX_IRX_N2 21 DMI_MTX_IRX_N3 21

DMI_MTX_IRX_P0 21 DMI_MTX_IRX_P1 21 DMI_MTX_IRX_P2 21 DMI_MTX_IRX_P3 21

CL_CLK0 22 CL_DATA0 22

ICH_CL_PWROK 22,32

ICH_CL_RST0# 22

SDVO_CTRLCLK SDVO_CTRLDATA

CLK_3GPLLREQ# 6 MCH_ICH_SYNC# 22

12

R466

0R0402-PAD

2

+1.8V_SUS

C615

SCD1U10V2KX-4GP

1 2

+2.5V_RUN

2

+1.25V_RUN

12

4

RN105

SRN4K7J-8-GP

SB:70213

1

2 3

1

+1.8V_SUS

12

C570

C563

SC2D2U6D3V3MX-1-GP

1 2

C564

SC2D2U6D3V3MX-1-GP

1 2

R396

1KR2F-3-GP

R387

R387 392R2F-GP

392R2F-GP

SDVO_CTRLCLK 17 SDVO_CTRLDATA 17

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

C570

SCD01U16V2KX-3GP

1 2

C571

SCD01U16V2KX-3GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Thurman UMA

GMCH-DMI/DDR (2/6)

12

10 46Monday, April 23, 2007

1

R362

1KR2F-3-GP

R365

3K01R2F-3-GP

R363

1KR2F-3-GP

of

SC

5

www.kythuatvitinh.com

D D

4

3

2

1

DDR_A_D[0..63]15

C C

B B

DDR_A_D[0..63]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

4 OF 10

U56D

AR43

SA_DQ0

AW44

SA_DQ1

BA45

SA_DQ2

AY46

SA_DQ3

AR41

SA_DQ4

AR45

SA_DQ5

AT42

SA_DQ6

AW47

SA_DQ7

BB45

SA_DQ8

BF48

SA_DQ9

BG47

SA_DQ10

BJ45

SA_DQ11

BB47

SA_DQ12

BG50

SA_DQ13

BH49

SA_DQ14

BE45

SA_DQ15

AW43

SA_DQ16

BE44

SA_DQ17

BG42

SA_DQ18

BE40

SA_DQ19

BF44

SA_DQ20

BH45

SA_DQ21

BG40

SA_DQ22

BF40

SA_DQ23

AR40

SA_DQ24

AW40

SA_DQ25

AT39

SA_DQ26

AW36

SA_DQ27

AW41

SA_DQ28

AY41

SA_DQ29

AV38

SA_DQ30

AT38

SA_DQ31

AV13

SA_DQ32

AT13

SA_DQ33

AW11

SA_DQ34

AV11

SA_DQ35

AU15

SA_DQ36

AT11

SA_DQ37

BA13

SA_DQ38

BA11

SA_DQ39

BE10

SA_DQ40

BD10

SA_DQ41

BD8

SA_DQ42

AY9

SA_DQ43

BG10

SA_DQ44

AW9

SA_DQ45

BD7

SA_DQ46

BB9

SA_DQ47

BB5

SA_DQ48

AY7

SA_DQ49

AT5

SA_DQ50

AT7

SA_DQ51

AY6

SA_DQ52

BB7

SA_DQ53

AR5

SA_DQ54

AR8

SA_DQ55

AR9

SA_DQ56

AN3

SA_DQ57

AM8

SA_DQ58

AN10

SA_DQ59

AT9

SA_DQ60

AN9

SA_DQ61

AM9

SA_DQ62

AN11

SA_DQ63

CRESTLINE-GP-U 71.CREST.00U

SA_BS0 SA_BS1 SA_BS2

SA_CAS#

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6

SA_DQS7 SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9

SA_MA10

DDR SYSTEM MEMORRY A

SA_MA11

SA_MA12

SA_MA13

SA_MA14

SA_RAS#

SA_RCVEN#

SA_WE#

BK19 BF29

BL17 AT45

BD44 BD42 AW38 AW13 BG8 AY5 AN6

AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2

BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 BJ29

BE18 AY20

BA19

DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_DM0

DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_RAS# M_A_RCVEN#

DDR_A_WE#

DDR_A_BS0

BB19

DDR_A_BS[0..2]

DDR_A_DM[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..14]

DDR_A_RAS# 15

1

TP6TP6

DDR_A_WE# 15

DDR_A_DQS#[0..7]

DDR_A_BS[0..2] 15

DDR_A_CAS# 15

DDR_A_DM[0..7] 15

DDR_A_DQS[0..7] 15

DDR_A_DQS#[0..7] 15

DDR_A_MA[0..14] 15

5 OF 10

U56E

DDR_B_D[0..63]16

DDR_B_D[0..63]

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

U56E

AP49

SB_DQ0

AR51

SB_DQ1

AW50

SB_DQ2

AW51

SB_DQ3

AN51

SB_DQ4

AN50

SB_DQ5

AV50

SB_DQ6

AV49

SB_DQ7

BA50

SB_DQ8

BB50

SB_DQ9

BA49

SB_DQ10

BE50

SB_DQ11

BA51

SB_DQ12

AY49

SB_DQ13

BF50

SB_DQ14

BF49

SB_DQ15

BJ50

SB_DQ16

BJ44

SB_DQ17

BJ43

SB_DQ18

BL43

SB_DQ19

BK47

SB_DQ20

BK49

SB_DQ21

BK43

SB_DQ22

BK42

SB_DQ23

BJ41

SB_DQ24

BL41

SB_DQ25

BJ37

SB_DQ26

BJ36

SB_DQ27

BK41

SB_DQ28

BJ40

SB_DQ29

BL35

SB_DQ30

BK37

SB_DQ31

BK13

SB_DQ32

BE11

SB_DQ33

BK11

SB_DQ34

BC11

SB_DQ35

BC13

SB_DQ36

BE12

SB_DQ37

BC12

SB_DQ38

BG12

SB_DQ39

BJ10

SB_DQ40

BL9

SB_DQ41

BK5

SB_DQ42

BL5

SB_DQ43

BK9

SB_DQ44

BK10

SB_DQ45

BJ8

SB_DQ46

BJ6

SB_DQ47

BF4

SB_DQ48

BH5

SB_DQ49

BG1

SB_DQ50

BC2

SB_DQ51

BK3

SB_DQ52

BE4

SB_DQ53

BD3

SB_DQ54

BJ2

SB_DQ55

BA3

SB_DQ56

BB3

SB_DQ57

AR1

SB_DQ58

AT3

SB_DQ59

AY2

SB_DQ60

AY3

SB_DQ61

AU2

SB_DQ62

AT2

SB_DQ63

CRESTLINE-GP-U 71.CREST.00U

SB_BS0 SB_BS1 SB_BS2

SB_CAS#

SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6

SB_DQS7 SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9

DDR SYSTEM MEMORY B

SB_MA10

SB_MA11

SB_MA12

SB_MA13

SB_MA14

SB_RAS#

SB_RCVEN#

SB_WE#

BG18 BG36

BE17 AR50

BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3

BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 BE24

AV16 AY18

BC17

DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_DM0

DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6

DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0

DDR_B_MA1

DDR_B_MA2

DDR_B_MA3

DDR_B_MA4

DDR_B_MA5

DDR_B_MA6

DDR_B_MA7

DDR_B_MA8

DDR_B_MA9

DDR_B_MA10

DDR_B_MA11

DDR_B_MA12

DDR_B_MA13

DDR_B_MA14

DDR_B_RAS#

M_B_RCVEN#

DDR_B_WE#

DDR_B_BS0

AY17

DDR_B_BS[0..2]

DDR_B_DM[0..7]

DDR_B_DQS[0..7]

DDR_B_DQS#[0..7]

DDR_B_MA[0..14]

1

TP5TP5

DDR_B_RAS# 16

DDR_B_WE# 16

DDR_B_BS[0..2] 16

DDR_B_CAS# 16

DDR_B_DM[0..7] 16

DDR_B_DQS[0..7] 16

DDR_B_DQS#[0..7] 16

DDR_B_MA[0..14] 16

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

Thurman UMA

Taipei Hsien 221, Taiwan, R.O.C.

GMCH-DDR (3/6)

1

of

11 46Monday, April 23, 2007

SC

5

www.kythuatvitinh.com

+1.05V_VCCP

D D

C106

SC22U6D3V5MX-2GP

C106

SC22U6D3V5MX-2GP

12

FOR VCC SM

12

TC3

ST330U2D5VDM-9GP

C94

SCD1U10V2KX-4GP

C94

SCD1U10V2KX-4GP

12

+1.8V_SUS

C55

SC22U6D3V5MX-2GP

C55

SC22U6D3V5MX-2GP

12

C C

Place on the Edge

Place CAP where LVDS and DDR2 taps

B B

12

C1002

12

C1001

SC1U10V2KX-1GP

12

C1009

5

1

C1003

2

SCD47U6D3V2KX-GP

Latout notice Inside GMCH cavity for VCC_AXG

A A

+1.05V_VCCP

12

C1000

SCD1U10V2KX-4GP

12

C1008

SC22U6D3V5MX-2GP

SC10U6D3V5MX-3GP

6 OF 10

U56F

AT35

VCC

AT34

VCC

AH28

VCC

AC32

VCC

AC31

VCC

AK32

VCC

AJ31

VCC

AJ28

VCC

AH32

VCC

AH31

VCC

AH29

VCC

AF32

VCC

VCC CORE

R30

VCC

POWER

AU32

VCC_SM

AU33

VCC_SM

AU35

VCC_SM

AV33

VCC_SM

AW33

VCC_SM

AW35

VCC_SM

AY35

VCC_SM

BA32

VCC_SM

BA33

VCC_SM

BA35

VCC_SM

BB33

VCC_SM

BC32

VCC_SM

BC33

VCC_SM

BC35

VCC_SM

BD32

VCC_SM

BD35

VCC_SM

BE32

VCC_SM

BE33

VCC_SM

BE35

VCC_SM

BF33

VCC_SM

VCC SM

VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM

VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG

VCC SM

BF34 BG32 BG33 BG35 BH32 BH34 BH35

BJ32 BJ33

BJ34 BK32 BK33 BK34 BK35

BL33 AU30

R20

T14 W13 W14

Y12

AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31

AJ20

AN14

CRESTLINE-GP-U 71.CREST.00U

4

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

VCC GFX NCTF

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

VCC GFX

VCC SM LF

4

VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF

+3.3V_RUN

+1.05V_VCCP

T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31

AW45 BC39 BE39 BD17 BD4 AW8 AT6

1 2

R44 10R2J-2-GPR44 10R2J-2-GP

12

Latout notice 370 mils from edge

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

TC102

TC104

ST220U2D5VBM-2GP

12

ST220U2D5VBM-2GP

12

+VCC_MCH_L

RB751V-40-1-GP

TC105

ST220U2D5VBM-2GP

12

C110

SCD1U10V2KX-4GP

C109

12

SCD1U10V2KX-4GP

3

D5

2 1

+1.05V_VCCP

12

TC1

ST220U6D3VDM-13GP

370 mils from the Edge

Signal Group Supply Icc-max +1.05V_VCCP VCC 7.7A +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.8V_SUS +1.8V_SUS 0.2A +1.25V_RUN +1.25V_RUN

VCC_NCTF A

VTT 0.85A

VCC_PEG 1.2A

VCC_RXR_DMI 0.25A

VCC_ATX 84.15mA

VCC_SM 2.4A

VCC_SM_CK

VCCA_HPLL 0.05A

VCCA_MPLL 0.15A +1.25V_RUN +1.25V_RUN +1.25V_RUN +1.25V_RUN

VCCD_HPLL 0.25A +1.25V_RUN +1.25V_RUN +1.25V_RUN VCCA_PEG_PLL

+1.05V_VCCP

12

/VCCD_PEG_PLL

C182

SCD22U10V2KX-1GP

C182

SCD22U10V2KX-1GP

C117

SC22U6D3V5MX-2GP

C117

SC22U6D3V5MX-2GP

12

Place on the Edge

FOR VCC AXM NCTF AND VCC AXM

12

1

C93

C92

2

SCD22U10V2KX-1GP

3

12

C88

C108

C115

SC1U10V2KX-1GP

SCD47U6D3V2KX-GP

SC1U10V2KX-1GP

C119

2

1

FOR VCC CORE AND VCC NCTF

7 OF 10

U56G

AB33

VCC_NCTF

SCD1U10V2KX-4GP

SC22U6D3V5MX-2GP

SCD22U10V2KX-1GP

C647

C638

1 2

C235

SCD1U10V2KX-4GP

SCD22U10V2KX-1GP

C166

1 2

Coupling CAP

(Non-AMT)

0.735AVCCA_SM

(667MHz)

AVCCA_SM_NCTF

0.015AVCCA_SM_CK

(667MHz)

0.2AVCCA_AXD AVCCA_AXD_NCTF

0.1A

0.35AVCCA_AXF+1.25V_RUN

0.1AVCCA_DMI+1.25V_RUN

0.06AVCCD_TVDAC+1.5V_RUN

0.005AVCCA_PEG_BG+3.3V_RUN

0.1AVCC_HV+3.3V_RUN

SCD1U10V2KX-4GP

C642

SCD1U10V2KX-4GP

1 2

C132

2

C218

SCD1U10V2KX-4GP

C218

SCD22U10V2KX-1GP

SCD1U10V2KX-4GP

12

1 2

Coupling CAP Inside MCH cavity

AB36

VCC_NCTF

AB37

VCC_NCTF

AC33

VCC_NCTF

AC35

VCC_NCTF

AC36

VCC_NCTF

AD35

VCC_NCTF

AD36

VCC_NCTF

AF33

VCC_NCTF

AF36

VCC_NCTF

AH33

VCC_NCTF

AH35

VCC_NCTF

AH36

VCC_NCTF

AH37

VCC_NCTF

AJ33

VCC_NCTF

AJ35

VCC_NCTF

AK33

VCC_NCTF

AK35

VCC_NCTF

AK36

VCC_NCTF

AK37

VCC_NCTF

AD33

VCC_NCTF

AJ36

VCC_NCTF

AM35

VCC_NCTF

AL33

VCC_NCTF

AL35

VCC_NCTF

AA33

VCC_NCTF

AA35

VCC_NCTF

AA36

VCC_NCTF

AP35

VCC_NCTF

AP36

VCC_NCTF

AR35

VCC_NCTF

AR36

VCC_NCTF

Y32

VCC_NCTF

Y33

VCC_NCTF

Y35

VCC_NCTF

Y36

VCC_NCTF

Y37

VCC_NCTF

T30

VCC_NCTF

T34

VCC_NCTF

T35

VCC_NCTF

U29

VCC_NCTF

U31

VCC_NCTF

U32

VCC_NCTF

U33

VCC_NCTF

U35

VCC_NCTF

U36

VCC_NCTF

V32

VCC_NCTF

V33

VCC_NCTF

V36

VCC_NCTF

V37

VCC_NCTF

AL24

VCC_AXM_NCTF

AL26

VCC_AXM_NCTF

AL28

VCC_AXM_NCTF

AM26

VCC_AXM_NCTF

AM28

VCC_AXM_NCTF

AM29

VCC_AXM_NCTF

AM31

VCC_AXM_NCTF

AM32

VCC_AXM_NCTF

AM33

VCC_AXM_NCTF

AP29

VCC_AXM_NCTF

AP31

VCC_AXM_NCTF

AP32

VCC_AXM_NCTF

AP33

VCC_AXM_NCTF

AL29

VCC_AXM_NCTF

AL31

VCC_AXM_NCTF

AL32

VCC_AXM_NCTF

AR31

VCC_AXM_NCTF

AR32

VCC_AXM_NCTF

AR33

VCC_AXM_NCTF

CRESTLINE-GP-U 71.CREST.00U

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

VSS NCTF

VCC NCTF

POWER

VSS SCBVSS AXM

Thurman UMA

GMCH-POWER (4/6)

T27

VSS_NCTF

T37

VSS_NCTF

U24

VSS_NCTF

U28

VSS_NCTF

V31

VSS_NCTF

V35

VSS_NCTF

AA19

VSS_NCTF

AB17

VSS_NCTF

AB35

VSS_NCTF

AD19

VSS_NCTF

AD37

VSS_NCTF

AF17

VSS_NCTF

AF35

VSS_NCTF

AK17

VSS_NCTF

AM17

VSS_NCTF

AM24

VSS_NCTF

AP26

VSS_NCTF

AP28

VSS_NCTF

AR15

VSS_NCTF

AR19

VSS_NCTF

AR28

VSS_NCTF

A3

VSS_SCB

B2

VSS_SCB

C1

VSS_SCB

BL1

VSS_SCB

BL51

VSS_SCB

A51

VSS_SCB

+1.05V_VCCP

AT33

VCC_AXM

AT31

VCC_AXM

AK29

VCC_AXM

AK24

VCC_AXM

AK23

VCC_AXM

AJ26

VCC_AXM

AJ23

VCC_AXM

VSS AXM NCTF

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

12 46Monday, April 23, 2007

1

of

SC

5

www.kythuatvitinh.com

4

3

2

1

L116

C162

1 2

C143

SC22U6D3V5MX-2GP

SC1U10V2KX-1GP

10uH 60mA

12

1 2

L-10UH-11-GP

+VCCA_CRTDAC_R

+VCC_TVBG_R

+VCCA_DPLLA +VCCA_DPLLB

+VCC_TX_LVDS

C142

SC22U6D3V5MX-2GP

+VCC_TVDACA_R +VCC_TVDACB_R +VCC_TVDACC_R

+VCCD_TVDAC_R

+VCCQ_TVDAC_R

+VCCD_LVDS

C130

SC10U6D3V5MX-3GP

AM2

AW18

AV19 AU19 AU18 AU17

AT22 AT21 AT19 AT18 AT17 AR17 AR16

BC29 BB29

H49 AL2

B41

K50 K49

U51

C25 B25 C27 B27 B28 A28

M32

N28 AN2 U48

H42

12

J32 A33

B33

A30 B32

B49

A41

L29

J41

+3.3V_RUN

C1080

12

TC100

C1086

ST330U2D5VDM-9GP

SCD1U10V2KX-4GP

C270

12

C569

C154

SC4D7U6D3V3KX-GP

SC1U10V2KX-1GP

SCD1U10V2KX-4GP

C95

12

SC22U6D3V5MX-2GP

+VCCA_PEG_PLL

12

C644

SCD1U10V2KX-4GP

C1083

+VCC_TVDACB_R

C1084

+1.25V_RUN

0.1Caps should be placed 200 mils with in its pins.

1 2

C1091 SC1KP50V2KX-1GPC1091 SC1KP50V2KX-1GP

12

L111

+3.3V_RUN

D D

180ohm 100MHz 200mA 0.2ohm DC

BLM18PG181SN-3GP

12

C1081

SCD1U10V2KX-4GP

R1084 0R0603-PADR1084 0R0603-PAD

1 2

45mA MAX.

+1.25V_RUN

1 2

BLM18AG121SN-1GP

+1.25V_RUN

BLM18AG121SN-1GP

C C

+1.25V_RUN

BLM21PG221SN1D-1GP

B B

120ohm 100MHz

A A

200mA 0.2ohm DC

+VCC_TVBG_R

BLM18AG121SN-1GP

L16

1 2

+1.5V_RUN

+3.3V_RUN

SC:70412

C565

SC2D2U6D3V3MX-1-GP

1 2

120ohm 100MHz 200mA 0.2ohm DC

L42

L41

1 2

+VCCA_MPLL_L

220ohm 100MHz 2A 0.1ohm DC

R425

1R3F-GP

R1091 0R0603-PADR1091 0R0603-PAD

+1.5V_RUN

BLM18AG121SN-1GP

R1090 0R0603-PADR1090 0R0603-PAD

5

+VCCA_HPLL

C617

SC22U6D3V5MX-2GP

1 2

120ohm 100MHz 200mA 0.2ohm DC

R382

D5R3F-1-GP

+VCCA_PEG_PLL

12

+VCCA_PEG_PLL_L

C632

SC10U6D3V5MX-3GP

1 2

12

SCD1U10V2KX-4GP

R1130 100R2J-2-GPR1130 100R2J-2-GP

L118

12

SCD1U10V2KX-4GP

12

SCD1U10V2KX-4GP

C618

SCD1U10V2KX-4GP

1 2

+VCCA_MPLL

12

C604

SC22U6D3V5MX-2GP

1 2

C641

SCD1U10V2KX-4GP

1 2

C1089

1 2

12

C1090

SCD1U10V2KX-4GP

C1085

1 2

C1082

1 2

+1.25V_RUN

C610

SCD1U10V2KX-4GP

1 2

+1.25V_RUN

1 2

+VCC_TVDAC

22nF & 0.1uF for VCC_TVDACA:C_R should be placed with in 250 mils from Crestline.

+VCCA_CRTDAC_R+VCCA_CRTDAC_R1

12

10uH 60mA

L115

1 2

L-10UH-11-GP

0.1Caps should be placed 200 mils with in its pins.

12

TC17

ST100U6D3VBM-9GP

12

C70

SC1U10V2KX-1GP

+1.25V_RUN

C112

SCD1U10V2KX-4GP

12

C1092

SC1U10V2KX-1GP

R1093 0R0603-PADR1093 0R0603-PAD

R1086 0R0603-PADR1086 0R0603-PAD

SCD1U10V2KX-4GP

12

+3.3V_RUN

SCD1U10V2KX-4GP

1 2

12

C52

12

C73

SC1U10V2KX-1GP

12

+VCC_TVDACA_R

12

SCD1U10V2KX-4GP

12

SCD1U10V2KX-4GP

4

+VCCA_DPLLB

12

TC101

C1087

ST330U2D5VDM-9GP

SCD1U10V2KX-4GP

8 OF 10

U56H

VCC_SYNC VCCA_CRT_DAC

VCCA_CRT_DAC

VCCA_DAC_BG VSSA_DAC_BG

VCCA_DPLLA

0.1A

VCCA_DPLLB VCCA_HPLL VCCA_MPLL

VCCA_LVDS VSSA_LVDS

VCCA_PEG_BG

0.005A

VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM

VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM_NCTF VCCA_SM_NCTF

0.035A

VCCA_SM_CK VCCA_SM_CK

VCCA_TVA_DAC VCCA_TVA_DAC VCCA_TVB_DAC VCCA_TVB_DAC VCCA_TVC_DAC VCCA_TVC_DAC

VCCD_CRT VCCD_TVDAC

0.06A

VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS

VCCD_LVDS

CRESTLINE-GP-U 71.CREST.00U

0.25A

0.15A

0.01A

A LVDS PLL CRT

A PEG

0.1A

0.04A

0.25A

0.1A

LVDS TV/CRT

+VCC_TVDAC

3

0.08A

0.85A

VTT

POWER

VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD

AXD

0.515A

VCC_AXD

VCC_AXD_NCTF

VCC_AXF VCC_AXF

AXF

VCC_AXF

0.495A1.2A

VCC_DMI

0.735A

TV A CK A SM

0.15A

0.1A

VCC_SM_CK

0.35A

VCC_SM_CK VCC_SM_CK VCC_SM_CK

SM CK

VCC_TX_LVDS

VCC_HV

HV

VCC_HV

0.1A

VCC_PEG VCC_PEG VCC_PEG

PEG

VCC_PEG VCC_PEG

VCC_RXR_DMI VCC_RXR_DMI

DMI

0.25A

VTTLF

+1.8V_SUS

+1.8V_RUN

R1089 0R0603-PADR1089 0R0603-PAD

U13

VTT

U12

VTT

U11

VTT

U9

VTT

U8

VTT

U7

VTT

U5

VTT

U3

VTT

U2

VTT

U1

VTT

T13

VTT

T11

VTT

T10

VTT

T9

VTT

T7

VTT

T6

VTT

T5

VTT

T3

VTT

T2

VTT

R3

VTT

R2

VTT

R1

VTT

AT23 AU28 AU24 AT29 AT25 AT30

AR29

B23 B21 A21

AJ50

BK24 BK23 BJ24 BJ23

A43

C40 B40

AD51 W50 W51 V49 V50

AH50 AH51

A7

VTTLF

F2

VTTLF

AH1

VTTLF

R1121 0R0402-PADR1121 0R0402-PAD

R1122 0R2J-2-GP

12

C1088

SCD1U10V2KX-4GP

+TTLF1 +TTLF2 +TTLF3

-1:70423

1 2

DY

+VCC_TVDACC_R

1 2

12

+3.3V_RUN

1

C622

SCD47U6D3V2KX-GP

2

C116

C116 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

12

C174

SC4D7U6D3V3KX-GP

Place on the edge

+VCC_AXD

12

C123

SC1U10V2KX-1GP

+1.25V_RUN

C105

SCD1U10V2KX-4GP

1 2

+VCC_TX_LVDS

12

C1093

SC1KP50V2KX-1GP

C293

SCD1U10V2KX-4GP

1 2

+VCC_RXR_DMI +1.05V_VCCP

C626

SC10U6D3V5MX-3GP

1

C686

SCD47U6D3V2KX-GP

2

+VCCD_LVDS

1 2

2

1

C666

SCD47U6D3V2KX-GP

2

R45 0R0603-PADR45 0R0603-PAD

C53

SC22U6D3V5MX-2GP

1 2

C688

SC10U6D3V5MX-3GP

1 2

1uH 300mA

L6

1 2

12

IND-1UH-36-GP

C61

SC22U6D3V5MX-2GP

1 2

IND-91NH-1-GP

12

TC11

ST220U2D5VBM-2GP

1

12

1

C158

C158 SCD47U6D3V2KX-GP

SCD47U6D3V2KX-GP

2

+1.25V_RUN

C226

SC2D2U6D3V3MX-1-GP

1 2

STUFF R86 0 ohm OR 5.6nH

Place caps close to VCC_AXD

+1.25V_RUN

12

C623

SC1U10V2KX-1GP

+VCC_SM_CK

L10

+VCC_TX_LVDS_R

1 2

R1125 0R0402-PADR1125 0R0402-PAD

1 2

DY

R1126 0R2J-2-GP

12

C281

SC4D7U6D3V3KX-GP

91nH 1.5A

Title

Size Document Number Rev

A3

Date: Sheet

Date: Sheet of

Thurman UMA

GMCH-POWER/FILTER (5/6)

+1.05V_VCCP

12

TC14

ST220U2D5VBM-2GP

1uH 300mA

1 2

IND-1UH-36-GP

C287

SC4D7U6D3V3KX-GP

1 2

C60

SC22U6D3V5MX-2GP

12

TC18

ST220U2D5VBM-2GP

1

12

R47

1R3F-GP

+VCC_SM_CK_L

C54

SC10U6D3V5MX-3GP

1 2

+1.8V_RUN

L49

1 2

IND-91NH-1-GP

91nH 1.5A

13 46Monday, April 23, 2007

C572

SCD1U10V2KX-4GP

1 2

+1.8V_SUS

+VCC_PEG

12

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

L4

of

+1.8V_SUS

+1.05V_VCCP

SC

5

www.kythuatvitinh.com

RN85

1

+3.3V_RUN

VGA_BLU18 VGA_GRN18

VGA_RED18

VGA_VSYNC18 VGA_HSYNC18

2 3

SRN2K2J-1-GP

4

LCTLA_CLK

12

LCTLA_DATA

12

+3.3V_RUN

D D

R1129 0R0402-PADR1129 0R0402-PAD R1128 0R0402-PADR1128 0R0402-PAD

C C

B B

SB:70116

G_CLK_DDC218 G_DAT_DDC218

A A

LCD_DDCLK

4

LCD_DDCDAT

SRN10KJ-5-GP

DY

RN108

61229

R160 150R2F-1-GPR160 150R2F-1-GP R353 150R2F-1-GPR353 150R2F-1-GP R159 150R2F-1-GPR159 150R2F-1-GP

R1095 39D2R2F-L-GPR1095 39D2R2F-L-GP R1082 1K3R2F-1-GPR1082 1K3R2F-1-GP R1080 39D2R2F-L-GPR1080 39D2R2F-L-GP

LCD_ACK-R

R100 0R0402-PADR100 0R0402-PAD

LCD_ACK+R

R97 0R0402-PADR97 0R0402-PAD

LCD_A0-

LCD_A0+

5

BIA_PWM19

PANEL_BKEN33

1 23

LCD_DDCLK19 LCD_DDCDAT19

ENVDD19

R1083 3K3R2F-2-GPR1083 3K3R2F-2-GP

SB:70125

12 12 12

12

R1096

0R2J-2-GP

12

SB:70215

LCD_DDCLK LCD_DDCDAT

12

LCD_ACK-R

LCD_ACK+R

12

DY

BIA_PWM PANEL_BKEN LCTLA_CLK LCTLA_DATA

ENVDD

L_IBG

LCD_A0LCD_A1LCD_A2-

LCD_A0+ LCD_A1+ LCD_A2+

VGA_VSYNC_C

CRT_IREF

VGA_HSYNC_C

12

C1079

SC8P250V2CC-GP

DY

SB:70215

C809

C809 SC3D3P50V2CN-GP

SC3D3P50V2CN-GP

1 2

J40 H39 E39 E40 C37 D35 K40

L41

L43 N41 N40 D46 C45 D44 E42

G51 E51

F49 C48

G50 E50

F48 D47

G44 B47 B45

E44 A47 A45

E27 G27 K27

F27

J27

L27 M35

P33

H32 G32 K29

J29

F29 E29

K33 G35 E33 C32

F33

LCD_ACK- 19

LCD_ACK+ 19

4

3 OF 10

U56C

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN

LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2

TVA_DAC TVB_DAC TVC_DAC

TVA_RTN TVB_RTN TVC_RTN

TV_DCONSEL0 TV_DCONSEL1

CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#

CRT_DDC_CLK CRT_DDC_DATA CRT_VSYNC CRT_TVO_IREF CRT_HSYNC

CRESTLINE-GP-U 71.CREST.00U

LCD_A0- 19

LCD_A0+ 19

4

PEG_COMPI

PEG_COMPO

LVDS

TV VGA

PCI_EXPRESS GRAPHICS

LCD_A1-

LCD_A1+

LCD_A2-

LCD_A2+

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

3

+VCC_PEG

12

R94

24D9R2F-L-GP

PEG_COMP_GMCH

N43 M43

J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41

J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42

N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44

M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43

SDVOB_INT-

SDVOB_INT+

NB_SDVOB_R- SDVOB_RNB_SDVOB_G- SDVOB_GNB_SDVOB_B- SDVOB_BNB_SDVOB_C- SDVOB_C-

NB_SDVOB_R+ SDVOB_R+ NB_SDVOB_G+ SDVOB_G+ NB_SDVOB_B+ SDVOB_B+ NB_SDVOB_C+ SDVOB_C+

SB:70215

C1095 SCD1U10V2KX-4GPC1095 SCD1U10V2KX-4GP C1097 SCD1U10V2KX-4GPC1097 SCD1U10V2KX-4GP C1098 SCD1U10V2KX-4GPC1098 SCD1U10V2KX-4GP C1100 SCD1U10V2KX-4GPC1100 SCD1U10V2KX-4GP

C1094 SCD1U10V2KX-4GPC1094 SCD1U10V2KX-4GP C1096 SCD1U10V2KX-4GPC1096 SCD1U10V2KX-4GP C1099 SCD1U10V2KX-4GPC1099 SCD1U10V2KX-4GP C1101 SCD1U10V2KX-4GPC1101 SCD1U10V2KX-4GP

C810

DY

SC3D3P50V2CN-GP

1 2

C811

DY

SC3D3P50V2CN-GP

1 2

SDVOB_INT- 17

SDVOB_INT+ 17

12 12 12 12

LCD_A1- 19

LCD_A1+ 19

LCD_A2- 19

LCD_A2+ 19

3

SDVOB_R- 17 SDVOB_G- 17 SDVOB_B- 17

SDVOB_C- 17

SDVOB_R+ 17 SDVOB_G+ 17 SDVOB_B+ 17 SDVOB_C+ 17

AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13

AC39 AC43 AC47

AD21 AD26 AD29

AD41 AD45 AD49

AD50 AE10

AE14 AF20

AF23 AF24 AF31

AG2 AG38 AG43 AG47 AG50

AH40 AH41

AJ11

AJ13

AJ21

AJ24

AJ29

AJ32

AJ43

AJ45

AJ49 AK20 AK21 AK26 AK28 AK31 AK51

AM11 AM13

AM3

AM4 AM41 AM45

AN38 AN39 AN43

AP48 AP50 AR11

AR39 AR44 AR47

AT10 AT14 AT41 AT49

AU23 AU29

AU36 AU49 AU51 AV39 AV48

AW1

AW12 AW16

AC3

AD1

AD3

AD5 AD8

AE6

AH3

AH7 AH9

AN1

AN5 AN7 AP4

AR2

AR7

AU1

AU3

A13 A15 A17 A24

AL1

2

9 OF 10

U56I

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

CRESTLINE-GP-U

71.CREST.00U

2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41

1

10 OF 10

U56J

C46

VSS

C50

VSS

C7

VSS

D13

VSS

D24

VSS

D3

VSS

D32

VSS

D39

VSS

D45

VSS

D49

VSS

E10

VSS

E16

VSS

E24

VSS

E28

VSS

E32

VSS

E47

VSS

F19

VSS

F36

VSS

F4

VSS

F40

VSS

F50

VSS

G1

VSS

G13

VSS

G16

VSS

G19

VSS

G24

VSS

G28

VSS

G29

VSS

G33

VSS

G42

VSS

G45

VSS

G48

VSS

G8

VSS

H24

VSS

H28

VSS

H4

VSS

H45

VSS

J11

VSS

J16

VSS

J2

VSS

J24

VSS

J28

VSS

J33

VSS

J35

VSS

J39

VSS

K12

VSS

K47

VSS

K8

VSS

L1

VSS

L17

VSS

L20

VSS

L24

VSS

L28

VSS

L3

VSS

L33

VSS

L49

VSS

M28

VSS

M42

VSS

M46

VSS

M49

VSS

M5

VSS

M50

VSS

M9

VSS

N11

VSS

N14

VSS

N17

VSS

N29

VSS

N32

VSS

N36

VSS

N39

VSS

N44

VSS

N49

VSS

N7

VSS

P19

VSS

P2

VSS

P23

VSS

P3

VSS

P50

VSS

R49

VSS

T39

VSS

T43

VSS

T47

VSS

U41

VSS

U45

VSS

U50

VSS

V2

VSS

V3

VSS

CRESTLINE-GP-U

71.CREST.00U

Title

Size Document Number Rev

A3

Date: Sheet of

Date: Sheet

Thurman UMA

GMCH-GND/LVDA/VGA (6/6)

W11

VSS

W39

VSS

W43

VSS

W47

VSS

W5

VSS

W7

VSS

Y13

VSS

Y2

VSS

Y41

VSS

Y45

VSS

Y49

VSS

Y5

VSS

Y50

VSS

Y11

VSS

P29

VSS

T29

VSS

T31

VSS

T33

VSS

R28

VSS

AA32

VSS

AB32

VSS

AD32

VSS

AF28

VSS

AF29

VSS

AT27

VSS

AV25

VSS

H50

VSS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

14 46Monday, April 23, 2007

1

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