Dell 1220 Schematics

1

2

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4

5

6

7

8

12.1" AM3 Low Rider Block Diagram

M/B PCBM/B PCB

A A

VER : C3A

FAN & THERMAL

EMC1423-1-AIZL-TR

CLOCK

SLG8SP513V (QFN-64)

LVDS

PG 29

PG 17

POWER

AC/BATT CONNECTOR

PG 39

SYSTEM RESET CIRCUIT

BATT CHARGER

RUN POWER SW

+3.3V_SUS +5V/+3.3V/+1.8V

PG 32

PG 33

PG 38

Penryn

(478 Pin)

PG 3,4

1066 MHz FSB

Cantiga

B B

DDR2-SODIMM*2

667/800 MHZ DDR II

1299 uFCBGA

VGA

POWER

+1.5V_RUN/+1.05V_VCCP

REGULATOR

+1.8V_SUS /+0.9V_DDR_VTT

PG 34

CPU VRREGULATOR

REGULATOR

+3.3V_ALW/+5V_SUS/+15V_ALW

PG 35

Panel Connector (WXGA)

CRT CONN.

MAX17021

PG 37

PG 36

PG 18

PG 19

PG 15,16

PG 5,6,7,8,9,10

DMI interface

SATA-ODD

PG 26

SATA

SATA-HDD

CCD

C C

Bluetooth

AUDIO/AMP

CX20583-10z

PG 26

PG 18

PG 24

PG 30

USB 2.0

USB 2.0 IHDA

MODEM (AMOM)

CX20548-11Z

PG 30

ICH9-M

676 BGA

PG 11,12,13,14

LPC

USB2.0

KBC

ITE8502

Audio SPK conn 2Wx1

Audio Jacks x2

RJ-11conn

Board to board

SPI PS/2

PG 22

18X8

TPM 1.2 SB19NP18ER28PVLR

PG 24

USB2.0

PCIE

RTL8111DL

(10/100/1000)

PCIE USB2.0

3-in-1 Card Reader

RTS5158E

SD/MMC memory Card

PG 31 PG 31

PG 20

FingerPrintReader VFS300

PG 27

USB x 3 port (2 on IO board)

PG 25

RJ45/Magnetics

Express Card(34mm)

MINI-CARD

WLAN/BT

PG 24

Card Reader CONN.

PG 21

PG 20

PG 30PG 30

D D

USER INTERFACE /Dash board

PG 28

1

2

FLASH 2M bytes

PG 23 PG 27

3

KeyboardTouchpad

PG 27

Title

Size Document Number Rev

Date: Sheet

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Date: Sheet

QUANTA

QUANTA COMPUTER

COMPUTER

Schematic Block Diagram

AM3 1A

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Table of Contents Power States

PAGE DESCRIPTION

1

Schematic Block Diagram

2

Front Page Penryn

3-4

Cantiga

5-10

ICH9M

A A

B B

C C

11-14 15-16

DDRII SO-DIMM(200P)

17

Clock Generator LCD Conn.

18 19

CRT Conn

20

RTS5158

21

Express card

22

SIO (ITE8502)

23

FLASH/RTC/TPM

24

Mini Card / BT

25

USB

26

SATA Conn HDD and ODD

27

TP / KEYBOARD / FP

28

SWITCH /LED

29

FAN & Thermal

30

Audio CODEC(CX20583)/Phone Jack/Modem

31

LAN / TRANSFORM System Reset Circuit

32

Battery Selector & Charger

1.05VCCP / 1.5VRUJN

34

DDR2_1.8VSUS, 0.9V

35

MAX17020 (+5V/+3V ALW)

36

MAX17021 V_CORE

37

RUN Power Switch

38

DCIN,Batt

39

PAD& SCREW

40

EMI CAP

41

SMBUS BLOCK

42

Power Block Dianram

43

POWER PLANE

+PWR_SRC +RTC_CELL +3.3V_ALW +15V_ALW +3.3V_LAN +5V_SUS +3.3V_SUS +1.8V_SUS +0.9V_DDR_VTT +5V_RUN +3.3V_RUN +1.5V_RUN +1.05V_VCCP +VCC_CORE +LCDVCC33 +PBATT +SBATT

10V~+19V

+3.0V~+3.3V

+3.3V +15V +3.3V +5V +3.3V +1.8V +0.9V +5V +3.3V +1.5V +1.05V

+0.7V~+1.77V

+3.3V +10V~+17V +10V~+17V

GND PLANE PAGE

4,26,32,34,46,48,49,51,52,56

11,14,31,32 3,31,32,34,36,37,38,44,46,49,52,53,54

26,36,37,52,53 42,43 14,38,51,53 3,11,12,13,14,26,30,37,38,43,48,49,51,53 6,8,9,15,48,49,53 16,49,53

14,18,27,36,37,38,39,40,41,53

4,9,14,30,33,34,48,53,56 3,4,5,6,8,9,11,14,48,56 4,51,56 26

DESCRIPTION

MAIN POWER RTC 8051 POWER LARGE POWER LAN POWER SLP_S5# CTRLD POWER SLP_S5# CTRLD POWER SODIMM POWER SODIMM POWER SLP_S3# CTRLD POWER SLP_S3# CTRLD POWER CALISTOGA/ICH8 POWER CPU/CALISTOGA/ICH8 POWER CPU CORE POWER LCD Power MAIN BATTERY SECOND BATTERY

CONTROL SIGNAL

ALWON +5V_ALW AUX_ON SUS_ON

3.3V_SUS_ON DDR_ON

0.9V_DDR_VTT_ON RUN_ON

3.3V_RUN_ON

1.5V_RUN_ON

1.05V_RUN_ON IMVP_VR_ON

LCDVCC_TST_EN & ENVDD

CHG_PBATT CHG_SBATT

ACTIVE INVOLTAGE PAGE

S0~S5 S0~S5 S0~S5 S0~S5

GND

D D

1

2

3

ALL

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

Date: Sheet

4

5

6

Date: Sheet

COMPUTER

Index & Power Status

AM3 1A

7

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H_A#[3..16]5

A A

H_ADSTB#05 H_REQ#[0..4]5

H_A#[17..35]5

B B

H_ADSTB#15

H_A20M#11

H_FERR#11

H_IGNNE#11 H_STPCLK#11

H_INTR11 H_NMI11 H_SMI#11

C C

H_A#[3..16]

H_REQ#[0..4]

H_A#[17..35]

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

U13A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

Quard Core Only

F6

TDI_1/RSV

D3

TDO_2/RSV

N5

BMP_1#[0]/RSV

M4

BMP_1#[1]/RSV

B2

BMP_1#[2]/RSV

AE8

BMP_1#[3]/VSS

D8

DCLKPH_1/VSS

F8

ACLKPH_1/VSS

D22

GTLREF_2/RSV

T2

THRMDA_1/RSV

V3

THRMDC_1/RSV

AA8

HFPLL_1/VSS

AC8

SPARE_1[4]/VSS

AA7

BR1#/VCC

Penryn Ball-out Rev 1a

ADDR GROUP 0 ADDR GROUP 1

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

CONTROL XDP/ITP SIGNALS

IERR#

INIT#

LOCK#

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

RSVD[06]

H1 E2 G5

H5 F21 E1

F1 D20

B3 H4 C1

F3 F4 G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6

TDI

AB3 AB5 AB6 C20

D21 A24 B25

C7

A22 A21

D2

R33 56R33 56

H_IERR#

1 2

ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_DBRESET#

R3256R32

56

1 2

H_PROCHOT# H_THERMDA H_THERMDC

H_THERM

R8856R88

56

1 2

C323 *2200P_NC

H_THERMDA H_THERMDC

1 2

50

H_ADS# 5 H_BNR# 5 H_BPRI# 5

H_DEFER# 5 H_DRDY# 5 H_DBSY# 5 H_BR0# 5

+1.05V_VCCP

H_INIT# 11 H_LOCK# 5 H_RESET# 5

H_RS#0 5 H_RS#1 5 H_RS#2 5 H_TRDY# 5

H_HIT# 5 H_HITM# 5

T25PAD T25PAD T30PAD T30PAD T102PAD T102PAD T29PAD T29PAD T101PAD T101PAD

ITP_DBRESET# 13

+1.05V_VCCP

T9PAD T9PAD

H_THERMDA 29

H_THERMDC 29

+1.05V_VCCP

CLK_CPU_BCLK 17 CLK_CPU_BCLK# 17

T23PAD T23PAD

Layout Note: Place voltage divider within

0.5" of GTLREF pin

+1.05V_VCCP

R216

R216 1K/F

1K/F

1 2 12

R217

R217 2K/F

2K/F

H_D#[0..63]5

H_DSTBN#05 H_DSTBP#05 H_DINV#05

H_D#[0..63]5

H_DSTBN#15 H_DSTBP#15 H_DINV#15

R34 *1K/F_NCR34 *1K/F_NC R35 *1K/F_NCR35 *1K/F_NC

CPU_MCH_BSEL06,17 CPU_MCH_BSEL16,17 CPU_MCH_BSEL26,17

H_D#[0..63] H_D#[0..63]

H_D#[0..63]

12 12

T87PAD T87PAD T86PAD T86PAD T103PAD T103PAD T84PAD T84PAD T22PAD T22PAD

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

V_CPU_GTLREF CPU_TEST1 CPU_TEST2 CPU_TEST3 CPU_TEST4 CPU_TEST5 CPU_TEST6 CPU_TEST7

U13B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

C3

TEST7

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Penryn Ball-out Rev 1a

DATA GRP 0

DATA GRP 1

MISC

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]#

DATA GRP 2

D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

DATA GRP 3

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

FSB

H_D#[0..63]

Note: H_DPRTSTP need to daisy chain from ICH9 to IMVP6 to CPU.

BCLK 667 800

200

H_D#[0..63] 5

H_DSTBN#2 5 H_DSTBP#2 5 H_DINV#2 5

H_D#[0..63] 5

H_DSTBN#3 5 H_DSTBP#3 5 H_DINV#3 5

H_DPRSTP# 6,11,37 H_DPSLP# 11 H_DPWR# 5 H_PWRGOOD 11 H_CPUSLP# 5 H_PSI# 37

BSEL2 BSEL1 BSEL0

1

1166

0

00

1

0002661066

Populate ITP700Flex for bringup

Change ITP_DBRESET# design circuit No2 1/5

ITP_DBRESET#

ITP_BPM#5 ITP_TDO ITP_TMS ITP_TDI

D D

R94 54.9/FR94 54.9/F

R95 54.9/FR95 54.9/F

1

R36 150R36 150

1 2

R96 54.9/FR96 54.9/F R98 54.9/FR98 54.9/F R97 54.9/FR97 54.9/F R99 54.9/FR99 54.9/F

ITP_TCK

ITP_TRST#

2

+3.3V_RUN

+1.05V_VCCP

Layout Note: Place R92~R97 close to CPU

3

H_THERM

Q4

MMST3904-7-F

+3.3V_RUN

2

R92

R92 10M

10M

2

12

C169

0.1U

1 3

10

31

H_THERMTRIP# 36

Q5

Q5 2N7002W-7-F

2N7002W-7-F

ITP disable guidelines

Signal Resistor Value Connect To

TDI TMS TRST# TCK TDO

150 ohm +/- 5% 39 ohm +/- 5% 680 ohm +/- 5% 27 ohm +/- 5% Open

VTT VTT GND GND VTT

ITP_EN R268 Depop +3VRUN

4

5

Resistor Placement Within 2.0" of the ITP Within 2.0" of the ITP Within 2.0" of the ITP Within 2.0" of the ITP Within 2.0" of the ITP Close to CK410M Pin8

Title

Size Document Number Rev

Date: Sheet

6

Date: Sheet

COMP0 COMP1 COMP2 COMP3

R100

R37

R101

54.9/F

1 2

Comp0,2 connect with Zo=27.4ohm,Comp1,3 connect with Zo=55ohm, make those traces length shorter than 0.5".Trace should be at least 25 mils away from any other toggling signal.

QUANTA

QUANTA COMPUTER

COMPUTER

Penryn Processor (HOST BUS)

AM3 1A

7

R37

R38

27.4/F

1 2

R38

54.9/F

27.4/F

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+VCC_CORE +VCC_CORE

+VCC_CORE

A A

+VCC_CORE

All use 10U 4V(+-20%,X6S,0805)Pb-Free.

12

C150

C150 10U

10U

805

805 4

4

C119

C119 10U

10U

805

805 4

4

12

C146

C146 10U

10U

805

805 4

4

C115

C115 10U

10U

805

805 4

4

12

C136

C136 10U

10U

805

805 4

4

12

C103

C103 10U

10U

805

805 4

4

12

C131

C131 10U

10U

805

805 4

4

12

C151

C151 10U

10U

805

805 4

4

8 inside cavity, north side, secondary layer.

+VCC_CORE

12

B B

+VCC_CORE

12

C133

C133 10U

10U

805

805 4

4

C348

C348 10U

10U

805

805 4

4

12

C110

C110 10U

10U

805

805 4

4

C352

C352 10U

10U

805

805 4

4

12

C148

C148 10U

10U

805

805 4

4

C118

C118 10U

10U

805

805 4

4

12

C338

C338 10U

10U

805

805 4

4

12

C345

C345 10U

10U

805

805 4

4

8 inside cavity, south side, secondary layer.

+VCC_CORE

12

C154

C154 10U

10U

805

805 4

4

12

C346

C346 10U

10U

805

805 4

4

12

C152

C152 10U

10U

805

805 4

4

12

C143

C143 10U

10U

805

805 4

4

4 inside cavity, north side, primary layer.

+VCC_CORE

C C

12

C353

C353 10U

10U

805

805 4

4

12

C349

C349 10U

10U

805

805 4

4

12

C347

C347 10U

10U

805

805 4

4

12

C342

C342 10U

10U

805

805 4

4

4 inside cavity, south side, primary layer.

+1.05V_VCCP

12

Layout out: Place these inside socket cavity on North side secondary.

D D

1

C141

0.1U

10

12

C98

0.1U

10

12

C123

0.1U

10

12

2

C142

0.1U

10

12

C100

0.1U

10

12

C124

0.1U

10

3

+PWR_SRC

+

C316

C316 *100U_NC

*100U_NC

25

Layout Note: Need to add 100uF cap on PWR_SRC for cap singing. Place on PWR_SRC near +VCC_CORE.

Add C315 for Acoustic No1 0220

U13C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Penryn Ball-out Rev 1a

+

4

C315

C315 100U

100U

25

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

.

+

C314

C314 *100U_NC

*100U_NC

25

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

VCCSENSE

VSSSENSE

5

+1.05V_VCCP

C500

C501

33P

1 2

33P

1 2

50

Add those caps for EMI solution No3 0318

+1.05V_VCCP

12

+

C313

C313 220U

220U

3528

3528 4

4

Close to CPU socket

+1.5V_RUN

C324

0.01U

25

+VCC_CORE

12

6

12

R74

R74 100/F

100/F

R79

R79 100/F

100/F

C320

C320 10U

10U

805

805 4

4

VID0 37 VID1 37 VID2 37 VID3 37 VID4 37 VID5 37 VID6 37

VCCSENSE 37

VSSSENSE 37

12

Layout Note: Place C363 near PIN B26.

VCCSENSE VSSSENSE

Layout Note: Route VCCSENSE and VSSSENSE traces at 27.4ohms and length matched to within 25 mil. Place PU and PD within 2 inch of CPU.

Title

Size Document Number Rev

Date: Sheet

U13D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn Ball-out Rev 1a

QUANTA

QUANTA COMPUTER

COMPUTER

Penryn Processor (POWER)

AM3 1A

7

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110]

VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128]

VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146]

VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5

AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6

AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4

AE11 AE14 AE16 AE19

.

. AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

445Wednesday, March 25, 2009

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8

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1

2

3

4

5

6

7

8

U12A

AD14

AA13 AA11

AD11 AD10 AD13 AE12

AE14

AE11

AG2 AD6

M11

N12

P13

N10

Y10 Y12 Y14

AA8

AA9

AE9 AA2 AD8 AA3 AD3 AD7

AF3 AC1 AE3 AC3

AE8

C12 E11

A11 B11

F2

G8

F8

E6 G2 H6 H2

F6 D4 H3 M9

J1

J2

J6

P2

L2 R2 N9

L6 M5

J3 N2 R1 N5 N6

N8

L7 M3

Y3

Y6

Y7 W2

Y9

C5

E3

U12A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

CANTIGA_1p0

4

H_ADSTB#_0 H_ADSTB#_1

HOST

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

H_A#3

A14

H_A#4

C15

H_A#5

F16

H_A#6

H13

H_A#7

C18

H_A#8

M16

H_A#9

J13

H_A#10

P16

H_A#11

R16

H_A#12

N17

H_A#13

M13

H_A#14

E17

H_A#15

P17

H_A#16

F17

H_A#17

G20

H_A#18

B19

H_A#19

J16

H_A#20

E20

H_A#21

H16

H_A#22

J20

H_A#23

L17

H_A#24

A17

H_A#25

B17

H_A#26

L16

H_A#27

C21

H_A#28

J17

H_A#29

H20

H_A#30

B18

H_A#31

K17

H_A#32

B20

H_A#33

F21

H_A#34

K21

H_A#35

L20 H12

B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

5

H_D#[0..63]

H_SWING H_RCOMP

H_RESET#3

H_CPUSLP#3

H_REF

12

C163

0.1U

10

Layout Note: Place the 0.1 uF decoupling capacitor within 100 mils from GMCH pins.

3

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

C166

0.1U

1 2

10

+1.05V_VCCP

H_D#[0..63]3

R233

R233 1K/F

1K/F

1 2

12

R232

R232 2K/F

2K/F

A A

+1.05V_VCCP

12

R84

R84 221/F

221/F

H_SWING

12

R85

R85 100/F

100/F

B B

H_RCOMP

R78

24.9/F

Layout Note:

1 2

H_RCOMP trace should be 10-mil wide with 20-mil spacing.

C C

D D

1

2

H_A#[3..35]

H_ADS# 3 H_ADSTB#0 3 H_ADSTB#1 3 H_BNR# 3 H_BPRI# 3 H_BR0# 3 H_DEFER# 3 H_DBSY# 3 CLK_MCH_BCLK 17 CLK_MCH_BCLK# 17 H_DPWR# 3 H_DRDY# 3 H_HIT# 3 H_HITM# 3 H_LOCK# 3 H_TRDY# 3

H_DINV#0 3 H_DINV#1 3 H_DINV#2 3 H_DINV#3 3

H_DSTBN#0 3 H_DSTBN#1 3 H_DSTBN#2 3 H_DSTBN#3 3

H_DSTBP#0 3 H_DSTBP#1 3 H_DSTBP#2 3 H_DSTBP#3 3

H_REQ#0 3 H_REQ#1 3 H_REQ#2 3 H_REQ#3 3 H_REQ#4 3

H_RS#0 3 H_RS#1 3 H_RS#2 3

6

H_A#[3..35] 3

+1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP

C138

C127

C127 *0.1U_NC

*0.1U_NC

1 2

10

+1.05V_VCCP +1.05V_VCCP +1.05V_VCCP

C134

C134 *0.1U_NC

*0.1U_NC

1 2

10

Layout Note: These 7 caps should be near belwo pin.

1. should be near AB1,AB2,AC2,Y3

2. should be near AD2,AE2,AG3,AE3

3. should be near AC5,AC6,AD7,AC7,AC9,AD9,AD11,AC11,AD12,AD13,AC14

4. should be near E2,F3,H2,H3,G4,H5,G7,H7

5. should be near M6,L7,K9,M7,N8,N9,M10,M11,N12,P13

6. should be near H13,J13,L13,M14,L16,K16,J17,H17

7. should be near E13,G17,F16,C15,B14,C11,B11,A11,B12

Title

Size Document Number Rev

Date: Sheet

C144

C144 *0.1U_NC

*0.1U_NC

1 2

10

C129

C129 *0.1U_NC

*0.1U_NC

1 2

10

QUANTA

QUANTA COMPUTER

COMPUTER

Cantiga (HOST)

AM3 1A

7

C125

C125 *0.1U_NC

*0.1U_NC

1 2

10

C128

C128 *0.1U_NC

*0.1U_NC

1 2

10

C138 *0.1U_NC

*0.1U_NC

1 2

10

545Wednesday, March 25, 2009

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8

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5

U12B

AH10 AH12 AH13

AK34 AN35 AM35

AY21

BG23 BF23 BH18 BF18

BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43

M36 N36 R33 T33 AH9

K12

AL34

T24 B31

AJ6

M1

A47

T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28

R29 N33

P32 AT40 AT11

T20

R32

BH6

BH5 BG4

BH3

BF3

BH2 BG2

BE2 BG1

BF1

BD1

BC1

U12B

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14

RSVD15 RSVD16 RSVD17

RSVD20

RSVD21 RSVD22 RSVD23 RSVD24 RSVD25

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_SYNC#

B7

PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24

F1

NC_25

CANTIGA_1p0

+1.8V_SUS +VCC_PEG

R55

R55 1K/F

1K/F

12

C76

2.2U

805

805 10

10

12

C75

2.2U

805

805 10

10

56

1 2 12

R45

3.01K/F

R44

R44 1K/F

1K/F

1 2

PM_EXTTS #0 PM_EXTTS #1

THERMTRIP_MCH#

PM_EXTTS #0 PM_EXTTS #1

PLTRST#_R THERMTRIP_MCH#

R228 *0_NCR228 *0_NC

R226 100R226 100

PLTRST#_R

12

SM_RCOMP_VOH

12

C83

0.01U

25

D D

C C

B B

A A

25

SM_RCOMP_VOL

12

C70

0.01U

25

+3.3V_RUN

R65 10KR65 10K

1 2

R64 10KR64 10K

1 2

+1.05V_VCCP

R6256R62

1 2

Layout Note: Location of all MCH_CFG strap resistors needs to be close to minmize stub.

CPU_MCH_BSEL03,17 CPU_MCH_BSEL13,17 CPU_MCH_BSEL23,17

PM_BMBUSY#13

H_DPRSTP#3,11,37 PM_EXTTS#015 PM_EXTTS#115 ICH_PWRGD13,32

DPRSLPVR13,37

SB_NB_PCIE_RST#12

PLTRST#12,21,22,24,31

4

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

RSVD

SM_RCOMP_VOH SM_RCOMP_VOL

DDR CONTROL/COMPENSATION

SM_DRAMRST# DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

CFG

DMI

PM

GRAPHICS VID

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

NC

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

SB_CKE_1 SA_CS#_0

SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

CLKREQ#

ICH_SYNC#

TSATN

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

BB36 BA17

AY16 AV16 AR13

BD17 AY17 BF15 AY13

BG22 BH21

BF28 BH28

AV42 AR36 BF17 BC36

B38 A38 E41 F41

F43 E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

AE35 AE43 AE46 AH42

AD35 AE44 AF46 AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35 AH34

N28 M28 G36 E36 K36 H36

B12

B28 B30 B29 C29 A28

M_CLK_DDR0 15 M_CLK_DDR1 15 M_CLK_DDR3 15 M_CLK_DDR4 15

M_CLK_DDR#0 15 M_CLK_DDR#1 15 M_CLK_DDR#3 15 M_CLK_DDR#4 15

DDR_CKE0_DIMMA 15,16 DDR_CKE1_DIMMA 15,16 DDR_CKE3_DIMMB 15,16 DDR_CKE4_DIMMB 15,16

DDR_CS0_DIMMA# 15,16 DDR_CS1_DIMMA# 15,16 DDR_CS2_DIMMB# 15,16 DDR_CS3_DIMMB# 15,16

M_ODT0 15,16 M_ODT1 15,16 M_ODT2 15,16 M_ODT3 15,16

SMRCOMPP SMRCOMPN

SM_RCOMP_VOH SM_RCOMP_VOL

R47 499/FR47 499/F

1 2

T10 PADT10 PAD

MCH_DREFCLK 17 MCH_DREFCLK# 17 DREF_SSCLK 17 DREF_SSCLK# 17

CLK_MCH_3GPLL 17 CLK_MCH_3GPLL# 17

DMI_MRX_ITX_N0 12 DMI_MRX_ITX_N1 12 DMI_MRX_ITX_N2 12 DMI_MRX_ITX_N3 12

DMI_MRX_ITX_P0 12 DMI_MRX_ITX_P1 12 DMI_MRX_ITX_P2 12 DMI_MRX_ITX_P3 12

DMI_MTX_IRX_N0 12 DMI_MTX_IRX_N1 12 DMI_MTX_IRX_N2 12 DMI_MTX_IRX_N3 12

DMI_MT X_IRX_P0 12 DMI_MT X_IRX_P1 12 DMI_MT X_IRX_P2 12 DMI_MT X_IRX_P3 12

T100 PADT100 PAD T18 PADT18 PAD T21 PADT21 PAD T26

T26

T93

CL_CLK0 13 CL_DATA0 13 ICH_CL_PWROK 13,22

ICH_CL_RST0# 13

MCH_CLVREF

T15 PADT15 PAD T16 PADT16 PAD T20 PADT20 PAD T28 PADT28 PAD

CLK_3GPLLREQ# 17 MCH_ICH_SYNC# 13

R231 56R231 56

T98 PADT98 PAD T91 PADT91 PAD T97 PADT97 PAD T99

T99

3

+3.3V_RUN

R66 10K/FR66 10K/F R89 10K/FR89 10K/F

+3.3V_RUN

R70 2.2KR70 2.2K R73 2.2KR73 2.2K

V_DDR_MCH_REF

VGA_BLU VGA_GRN VGA_RED

R77

R72

R76

150/F

1 2

PAD

+1.05V_VCCP

Non-iAMT

MCH_CLVREF

C122

0.1U

1 2

10

12

+1.05V_VCCP

PAD

10

LCD_DDCCLK

12

LCD_DDCDAT

12

1 2

+1.8V_SUS

R51

80.6/F

SMRCOMPP SMRCOMPN

R52

80.6/F

Layout Note: Place 150 ohm termination resistors close to GMCH.

R60

R60 1K/F

1K/F

1 2 12

R59

R59 499/F

499/F

CFG5

CFG9

CFG16

CFG19

CFG20

SDVO_CRTL_DATA

L_IBG

R83

2.4K/F

12

DMI X2 Select PCI Express

Graphic Lane FSB Dynamic

ODT DMI Lane

Reversal

SDVO/PCIE Concurrent Operation

SDVO Present.

BIA_PWM18 PANEL_BKEN22

LCD_DDCCLK18 LCD_DDCDAT18

ENVDD18

LCD_ACLK-18 LCD_ACLK+18

LCD_A0-18 LCD_A1-18 LCD_A2-18

LCD_A0+18 LCD_A1+18 LCD_A2+18

VGA_BLU19 VGA_GRN19 VGA_RED19

G_CLK_DDC219 G_DAT_DDC219

VGAHSYNC19 VGAVSYNC19

Low=DMIx2 High=DMIx4(Default)

Low= Reveise Lane High=Normal operation

Low=Dynamic ODT Disable High=Dynamic ODT Enable(default).

Low=Normal(default). High=Lane Reversed

Low=Only SDVO or PCIEx1 is operational (defaults) High=SDVO and PCIEx1 are operating simultaneously via PEG port

Low=No SDVO Device Present (default) High=SDVO Device Present

2

T94PA D T94PAD

T92PA D T92PAD T88PA D T88PAD

T96PA D T96PAD T19PA D T19PAD T24PA D T24PAD

T95PA D T95PAD T17PA D T17PAD T27PA D T27PAD

R80 75/F_4R80 75/F_4 R68 75/F_4R68 75/F_4 R69 75/F_4R69 75/F_4

VGA_BLU VGA_GRN VGA_RED

R75 30/FR75 30/F

1 2

R82 1K/FR82 1K/F

1 2

R71 30/FR71 30/F

1 2

L_CTRL_CLK L_CTRL_DATA

LCD_DDCCLK LCD_DDCDAT

L_IBG

L32 G32 M32

M33

K33

J33

M29

C44

B43

E37

E38

C41

C40

B37

A37

H47

E46 G40

A40

H48

D45

F40

B40

A41

H38 G37

J37

B42 G38

F37

K37

F25

H25

K25

H24

C31

E32

E28 G28

J28 G29

H32

J32

J29

E29

L29

U12C

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK

L_CTRL_DATA L_DDC_CLK L_DDC_DATA

L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

TVA_DAC TVB_DAC TVC_DAC

TV_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK

CRT_DDC_DATA CRT_HSYNC CRT_TVO_ IREF CRT_VSYNC

CANTIGA_1p0

LVDS

TV

PCI-EXPRESS GRAPHICS

VGA

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

T37 T36

H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39

H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40

J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46

J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46

1

VCC3G_PCIE_R

R63 49.9/FR63 49.9/F

12

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Cantiga (VGA,DMI)

Size Document Number Rev

AM3 1A

Date: Sheet

5

4

3

2

Date: Sheet

1

of

645Wednesday, March 25, 2009

http://laptop-motherboard-schematic.blogspot.com/

1

2

3

4

5

6

7

8

DDR_A_D[0..63]15

A A

B B

C C

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AJ38

AJ41 AN38 AM38

AJ36

AJ40

AM44 AM42

AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36

AW36

BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12

BB9 BA9

AU10

AV9

BA11

BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5

AN10

AM11

AM5

AN12

AM13

AJ11

AJ12

AJ9 AJ8

U12D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

CANTIGA_1p0

DDR_A_BS0

BD21

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13

DDR SYSTEM MEMORY A

SA_MA_14

BG18 AT25

BB20 BD20 AY20

AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

DDR_A_BS1 DDR_A_BS2

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 15,16 DDR_A_BS1 15,16 DDR_A_BS2 15,16

DDR_A_RAS# 15,16 DDR_A_CAS# 15,16

DDR_A_WE# 15,16

DDR_A_DM[0..7] 15

DDR_A_DQS[0..7] 15

DDR_A_DQS#[0..7] 15

DDR_A_MA[0..14] 15,16

DDR_B_D[0..63]15

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AK47 AH46 AP47 AP46

AJ46 AJ48

AM48

AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44

BG43

BF43 BE45 BC41 BF40 BF41

BG38

BF38 BH35

BG35

BH40 BG39 BG34

BH34

BH14 BG12

BH11

BG8 BH12 BF11

BG7

BC5

BC6

AY3

AY1

BA1

BD3

AV2

AU3

AR3

AN2

AY2

AV1

AP3

AR1

AH1

AM2

AM3

AH3

BF8

BF6 BF5

AL1 AL2 AJ1

AJ3

U12E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CANTIGA_1p0

DDR_B_BS0

BC16

SB_BS_0 SB_BS_1 SB_BS_2

SB_RAS# SB_CAS#

SB_WE#

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13

DDR SYSTEM MEMORY B

SB_MA_14

BB17 BB33

AU17 BG16 BF14

AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

DDR_B_BS1 DDR_B_BS2

DDR_B_RAS#

DDR_B_CAS# DDR_B_WE#

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS0 15,16 DDR_B_BS1 15,16 DDR_B_BS2 15,16

DDR_B_RAS# 15,16 DDR_B_CAS# 15,16 DDR_B_WE# 15,16

DDR_B_DM[0..7] 15

DDR_B_DQS[0..7] 15

DDR_B_DQS#[0..7] 15

DDR_B_MA[0..14] 15,16

D D

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

Date: Sheet

1

2

3

4

5

6

Date: Sheet

COMPUTER

Cantiga (DDR2)

AM3 1A

7

745Wednesday, March 25, 2009

of

8

http://laptop-motherboard-schematic.blogspot.com/

5

U12G

AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32

AW32

AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29

AW29

AV29 AU29 AT29 AR29 AP29

BA36 BB24 BD16

BB21 AW16 AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21 AG21 AE21 AC21 AA21

AH20 AF20 AE20 AC20 AB20 AA20

AM15

AL15 AE15

AJ15 AH15 AG15 AF15 AB15 AA15

U15

AN14

AM14

U14

AJ14 AH14

Y26

Y24

Y21

T17 T16

Y15 V15

T14

5

U12G

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35

VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42

VCC_AXG_SENSE VSS_AXG_SENSE

CANTIGA_1p0

POWER

VCC SMVCC GFX

VCC GFX NCTF

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

+1.8V_SUS

D D

C C

+1.05V_VCCP

B B

T13 PADT13 PAD T14 PADT14 PAD

A A

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

4

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

4

3

+3.3V_RUN

R90 10R90 10

+VCC_GMCH_L

1 2

+1.05V_VCCP

+

C351

C351 *220U_NC

Layout Note: 370 mils from edge. Close to NB

Layout Note: Inside GMCH cavity for VCC_AXG.

12

C145

0.1U

10

12

C120

0.1U

10

C132

C132 10U

10U

603

6.3

*220U_NC

12

C147

C104

1U

10U

603

10

6.3

+1.8V_SUS

12

Layout Note: Place C195 where LVDS and DDR2 taps.

1 2

Layout Note: Inside GMCH cavity.

12

C93

0.1U

10

C149

C149 10U

10U

603

6.3

C114

0.47U

603

603 10

10

12

C137

0.22U

603

603 10

10

+

C65

C65 220U

220U

7343

2.5

Close to NB

12

C105

0.22U

603

603 10

10

+1.05V_VCCP

12

Layout Note: Place on the edge.

Change C65 PN No1 0220

C80

0.1U

10

12

C108

C79

0.1U

0.22U

603

10

12

C90

0.22U

603

603 10

10

C107

0.47U

603

603 10

10

3

12

C94

C87

1U

603

10

D7

RB751V-40

12

C111

0.1U

10

C97

C97 10U

10U

603

6.3

2

21

VCC_SM

12

C89

C89 10U

10U

603

6.3

2

1

U12F

AG34

VCC_1

AC34

VCC_2

AB34

VCC_3

AA34

VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7

AM33

VCC_8

AK33

VCC_9

AJ33

VCC_10

AG33

VCC_11

AF33

VCC_12

AE33

VCC_13

AC33

VCC_14

AA33

VCC_15

Y33

VCC_16

W33

VCC_17

V33

VCC_18

U33

VCC_19

AH28

VCC_20

AF28

VCC_21

AC28

VCC_22

AA28

VCC_23

AJ26

VCC_24

AG26

VCC_25

AE26

VCC_26

AC26

VCC_27

AH25

VCC_28

AG25

VCC_29

AF25

VCC_30

AG24

VCC_31

AJ23

VCC_32

AH23

VCC_33

AF23

VCC_34

T32

VCC_35

CANTIGA_1p0

Title

Size Document Number Rev

Date: Sheet

VCC CORE

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5

POWER

VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31

VCC NCTF

VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

QUANTA

QUANTA COMPUTER

COMPUTER

Cantiga (VCC,NCTF)

AM3 1A

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

845Wednesday, March 25, 2009

1

+1.05V_VCCP

of

http://laptop-motherboard-schematic.blogspot.com/

5

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC

L32 BLM18PG181SN1D

+3.3V_RUN

D D

Non-iAMT

+1.05V_VCCP

L10 BLM11A05S

L8 BLM11A05S

+VCCA_MPLL_L

12

C C

+1.05V_VCCP

B B

L32 BLM18PG181SN1D

603

R234 0R234 0

1 2

45mA MAx.

FB_120ohm+-25%_100mHz _200mA_0.2ohm DC

+VCCA_HPLL

603

R58

1 2

C344

C344 22U

22U

1206

1206 10

10

FB_220ohm+-25%_100MHz _2A_0.1ohm DC

C126

4.7U

603

1 2

6.3

+VCCA_MPLL

0.5/F

603

L27

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC

L31

+3.3V_RUN

+1.5V_RUN

A A

BLM18PG181SN1D

L31 BLM18PG181SN1D

BLM18PG181SN1D

603

R237 0R237 0

1 2

L33

603

+VCCA_CRTDAC

12

C130

0.1U

10

12

C113

0.1U

10

BLM21P221SGPT

805

12

C367

0.1U

10

12

C368

0.1U

10

5

C366

0.01U

25

+VCCA_DAC_BG

C363

0.1U

10

+VCCA_PEG_PLL

12

R229

R229 1/F

1/F

603

12

C343

C343 10U

10U

603

6.3

+VCC_TVDACA

C361

0.01U

25

+VCCD_TVDAC

C155

0.01U

25

+VCCD_QDAC

C159

0.01U

25

12

C360

0.1U

10

C364

0.01U

25

+1.05V_VCCP

L30 10uH

L11 10uH

0.1Caps should be placed 200 mils with in its pins.

+1.05V_VCCP

12

C365

0.1U

10

10uH+-20%_100mA

12

805

12

805

R57 0

603

L9

L9 1uH/300mA

1uH/300mA

+1.05V_VCCP

FB_220ohm+-25%_100MHz _2A_0.1ohm DC

4

40mA MAx.

+VCCA_DPLLA

C164

C164 10U

10U

1 2

603

6.3

+VCCA_DPLLB

C161

C161 10U

10U

1 2

603

6.3

C106

4.7U

603

1 2

6.3

12

C112

C112 10U

10U

603

1 2

6.3

+1.8V_SUS

L28

4

12

C162

0.1U

10

12

C160

0.1U

10

C85

C85 10U

10U

603

1 2

6.3

12

C117

C117 1U

1U

603

603 10

10

BLM21P221SGPT

805

+1.5V_RUN

12

1 2

12

C121 0.1U 10C121 0.1U 10

C350 0.1U 10C350 0.1U 10

1 2

R81 0R81 0

+VCCD_PEG_PLL

12

R230

R230 1/F

1/F

603

12

C354

C354 10U

10U

603

6.3

C358

C358 1000P 50

1000P 50

C341

0.1U

10

C99

C99 10U

10U

603

6.3

C102

C102 1U

1U

603

603 10

10

12 12

+VCCD_LVDS

12

C157

C157 1U

1U

603

603 10

10

+VCCA_CRTDAC

+VCCA_DAC_BG

+VCCA_DPLLA +VCCA_DPLLB +VCCA_HPLL +VCCA_MPLL

+VCC_TX_LVDS

12

+VCCA_PEG_PLL

+VCCA_SM

12

+VCC_TVDACA

+VCC_HDA

+VCCD_TVDAC +VCCD_QDAC +VCCA_MPLL +VCCD_PEG_PLL

C96

C96 1U

1U

603

603 10

10

+VCCA_SM_CK

C95

0.1U

10

12

C158

C158 *10U_NC

*10U_NC

603

6.3

+VTTLF1 +VTTLF2 +VTTLF3

12

B27 A26

A25 B25

F47

L48 AD1 AE1

AD48

AA48

AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16

AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25

AL25

AM24

AL24

AM23

AL23

B24

A24

A32

M25

L28 AF1

AA47

M38

L37

C135

0.47U

603

603 10

10

J48 J47

U12H

CANTIGA_1p0

3

VCCA_CRT_DAC_1 VCCA_CRT_DAC_2

VCCA_DAC_BG VSSA_DAC_BG

VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL

VCCA_LVDS VSSA_LVDS

VCCA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9

VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8

VCCA_TV_DAC_1 VCCA_TV_DAC_2

VCC_HDA

VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL

VCCD_LVDS_1 VCCD_LVDS_2

12

C359

0.47U

603

603 10

10

3

CRTPLLA PEGASM

A LVDS

POWER

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_SM_CK_1

ACK

VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1

DMI

VCC_HV_2 VCC_HV_3

HV

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4

PEG

VCC_PEG_5

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

VTTLF

TV

HDA

LVDS

12

C165

0.47U

603

603 10

10

D TV/CRT

Close to pin C35, B35 and A35

VTT_10 VTT_11 VTT_12 VTT_13 VTT_14

VTT

VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

VTTLF1 VTTLF2 VTTLF3

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47 C35

B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

A8 L1 AB2

2

12

C116

2.2U

603

6.3

Close to VTT

+VCC_AXF

+VCC_SM_CK

+VCC_TX_LVDS

+3.3V_RUN

+VCC_RXR_DMI

+VTTLF1 +VTTLF2 +VTTLF3

+1.05V_VCCP

21

+1.05V_HV_MCH

R23610R236 10

1 2 12

C362

0.1U/10V

2

D23

D23 RB751V-40

RB751V-40

+3.3V_RUN

1

+1.05V_VCCP

12

C109

4.7U

603

6.3

12

C167

C167 1U

1U

603

603 10

10

12

C73

0.1U

10

C357

12

1000P

50

+VCC_PEG

12

C337

C337 10U

10U

603

6.3

Title

Size Document Number Rev

Date: Sheet

C139

C140

4.7U

0.47U

6.3

603

6.3

1 2

L12 0L12 0

Reserved L81 pad for

12

inductor.

C168

C168 10U

10U

603

6.3

12

R39

R39 1/F

1/F

603

+VCC_SM_CK_L

12

C69

C69 10U

10U

603

6.3

L29

1uH/300MA

805

C355

C355 10U

10U

1 2

603

6.3

L26

L26 91nH/1.5A

91nH/1.5A

QUANTA

QUANTA COMPUTER

COMPUTER

Cantiga (POWER)

AM3 1A

L5 1uH/300MA

1uH/300MA

+1.8V_SUS

R61 0 1206R61 0 1206

1 2

12

C356

4.7U

603

6.3

12

+1.05V_VCCP

805L5

805

+1.8V_SUS

+1.05V_VCCP

1

945Wednesday, March 25, 2009

of

http://laptop-motherboard-schematic.blogspot.com/

5

U12I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

D D

C C

B B

A A

5

AF47 AD47 AB47

BD46 BA46 AY46 AV46 AR46

AM46

BF44 AH44 AD44 AA44

M44

BC43 AV43 AU43

AM43

C43 BG42 AY42 AT42 AN42

AJ42

AE42

N42 BD41

AU41

AM41

AH41 AD41 AA41

U41

M41

G41 BG40

BB40 AV40 AN40

H40 AT39

AM39

AJ39

AE39

N39

BH38 BC38 BA38 AU38 AH38 AD38 AA38

U38

C38 BF37 BB37

AW37

AT37 AN37

AJ37

H37

C37 BG36 BD36 AK15 AU36

Y47 T47 N47 L47 G47

V46 R46 P46 H46 F46

Y44 U44 T44

F44

L42

Y41 T41

B41

E40

L39 B39

Y38 T38 F38

J43

J38

VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

CANTIGA_1p0

VSS

4

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23

3

U12J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17 M17 H17 C17

BA16

AU16 AN16

N16

K16

G16

E16 BG15 AC15

W15

A15 BG14

AA14

C14 BG13 BC13

BA13

AN13

AJ13

AE13

N13

L13

G13

E13 BF12 AV12 AT12

AM12

AA12

J12

A12

BD11

BB11 AY11

AN11 AH11

Y11

N11 G11 C11

BG10

AV10 AT10

AJ10 AE10 AA10

M10 BF9 BC9 AN9

AM9

AD9

G9

B9 BH8 BB8 AV8 AT8

3

VSS_230 VSS_231 VSS_232 VSS_233

VSS_235 VSS_237

VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252

VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273

VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

CANTIGA_1p0

VSS

VSS NCTF

VSS SCB

NC

VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 VSS_SCB_6

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42

2

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 B2 A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

QUANTA

QUANTA COMPUTER

COMPUTER

Cantiga (VSS)

AM3 1A

1

10 45Wednesday, March 25, 2009

of

1

of

http://laptop-motherboard-schematic.blogspot.com/

1

+RTC_CELL

12

R1151MR115 1M

R108 10MR108 10M

12

W2

1 4 2 3

32.768KHZ

R272

R119

20K

1 2

12

C225 0.01U/16VC225 0.01U/16V C224 0.01U/16VC224 0.01U/16V

C226 0.01U/16VC226 0.01U/16V C227 0.01U/16VC227 0.01U/16V

C198

C198 1U/10V

1U/10V

ICH_RTCRST# ICH_SRTCRST# ICH_INTRUDER#

12

C385

C385 1U/10V

1U/10V

32.768KHZ

C185

C185 15P

15P

50V

A A

Change C178, C185 value to from 12P to 15P No1 12/15

ICH_AZ_CODEC_BITCLK30

B B

ICH_AZ_CODEC_SYNC30 ICH_AZ_CODEC_RST#22,30 ICH_AZ_CODEC_SDOUT30

Place all series terms close to ICH9 except for SDIN input lines,which should be close to source.

C C

SATA_TX0-26 SATA_TX0+26

SATA_TX1-26 SATA_TX1+26

2

ICH_RTCX2ICH_RTCX1

R153 33R153 33

1 2

R166 33R166 33

1 2

R151 33R151 33

1 2

R159 33R159 33

1 2

SATA_TX0-_C SATA_TX0+_C

SATA_TX1-_C SATA_TX1+_C

C178

C178 15P

15P

50V

L19

L19 *22uH_NC

*22uH_NC

402

C266

C266 *27P/50V_NC

*27P/50V_NC

3

+RTC_CELL +RTC_CELL

12

ICH9M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN

ACZ_BIT_CLK

ACZ_SYNC ACZ_RST# ACZ_SDOUT

Reserved for Intel Nineveh design.

Master HDD

SATA ODD

Low = Internal VR Disabled High = Internal VR Enabled(Default)

T34 PADT34 PAD

T56 PADT56 PAD T58 PADT58 PAD T82 PADT82 PAD T55 PADT55 PAD T57 PADT57 PAD T53 PADT53 PAD

+3.3V_SUS

+1.5V_PCIE_ICH

ICH_AZ_CODEC_SDIN030

T70

T76

T68

SATA_ACT#28

SATA_RX0-26 SATA_RX0+26

SATA_RX1-26 SATA_RX1+26

4

R275

R275 332K/F

332K/F

ICH_INTVRMEN ICH_LAN100_SLP

ICH9M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP

U16A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD0

D12

LAN_TXD1

E13

LAN_TXD2

B10

GLAN_DOCK#/GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9M REV 1.0

R140 *10K_NCR140 *10K_NC

R102 24.9/FR102 24.9/F

1 2

PAD

PAD PAD

PAD

ICH_RTCX1 ICH_RTCX2

ICH_RTCRST# ICH_SRTCRST# ICH_INTRUDER#

ICH_INTVRMEN ICH_LAN100_SLP

GLAN_CLK

LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2

12

GLAN_COMP ACZ_BIT_CLK

ACZ_SYNC ACZ_RST#

ACZ_SDOUT

SATA_ACT#

SATA_TX0-_C SATA_TX0+_C

SATA_TX1-_C SATA_TX1+_C

5

12

R278

R278 332K/F

332K/F

Low = Internal VR Disabled High = Internal VR Enabled(Default)

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

LDRQ1#/GPIO23

RTCLAN / GLAN

LPCCPU

RTCLAN / GLAN

LPCCPU

CPUPWRGD

THRMTRIP#

IHDA

SATA_CLKN

SATA_CLKP

SATA

SATARBIAS#

SATARBIAS

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

IGNNE#

INIT# INTR

RCIN#

SMI#

STPCLK#

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

6

K5 K4 L6 K2

K3 J3

J1

SIO_A20GATE

N7 AJ27

H_DPRSTP#

AJ25

H_DPSLP#

AE23

H_FERR#_L

AJ26 AD22 AF25 AE22

AG25 L3

AF23

NMI

AF24 AH27 AG26 AG27

TP9

AH11 AJ11 AG12 AF12

AH9 AJ9 AE10 AF10

AH18 AJ18

AJ7 AH7

R250 56R250 56

SIO_RCIN#

THERMTRIP#_ICH

SATABIAS

1 2

LPC_LAD0 22,23,24 LPC_LAD1 22,23,24 LPC_LAD2 22,23,24 LPC_LAD3 22,23,24

LPC_LFRAME# 22,23,24

SIO_A20GATE 22 H_A20M# 3

H_DPRSTP# 3,6,37 H_DPSLP# 3

H_FERR#

12

H_PWRGOOD 3 H_IGNNE# 3

H_INIT# 3 H_INTR 3

SIO_RCIN# 22

H_NMI 3 H_SMI# 3

H_STPCLK# 3

T106PAD T106PAD

T59PAD T59PAD T61PAD T61PAD

T62PAD T62PAD T63PAD T63PAD

CLK_PCIE_SATA# 17 CLK_PCIE_SATA 17

R14224.9/F R14224.9/F

Place within 500mils of ICH9 ball

7

T78PAD T78PAD T125PAD T125PAD

H_FERR# 3

H_FERR#

SIO_A20GATE SIO_RCIN# SATA_ACT#

THERMTRIP#_ICH

8

+1.05V_VCCP

R25156R251 56

1 2

+3.3V_RUN

R178

R137

10K

R145

8.2K

1 2

+1.05V_VCCP

100K

R10956R109 56

1 2

+3.3V_RUN

R160

1 2

R160 *1K_NC

*1K_NC

R290

R290 *1K_NC

*1K_NC

ACZ_SDOUT

ICH_RSVD 13

5

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

Date: Sheet

6

Date: Sheet

COMPUTER

ICH9-M (CPU,SATA,LPC,LAN,CODEC)

AM3 1A

7

11 45Wednesday, March 25, 2009

of

8

XOR Chain Entrance Strap

ICH RSVD

D D

1

2

HDA SDOUT

0 0 1 1

3

Description

0

RSVD

1

Enter XOR Chain

0

Normal Operation (Default)

1

Set PCIE port config bit 1

4

http://laptop-motherboard-schematic.blogspot.com/

1

Place TX DC blocking caps close ICH9.

C172 0.1U 10C172 0.1U 10

PCIE_TX2-24 PCIE_TX2+24

A A

PCIE_TX4-21 PCIE_TX4+21

PCIE_TX6-/GLAN_TX-31 PCIE_TX6+/GLAN_TX+31

1 2

C173 0.1U 10C173 0.1U 10

1 2

C181 0.1U 10C181 0.1U 10

1 2

C184 0.1U 10C184 0.1U 10

1 2

C174 0.1U 10C174 0.1U 10

1 2

C175 0.1U 10C175 0.1U 10

1 2

Boot BIOS Strap

GNT0# SPI_CS1#

B B

11LPC PCI SPI1001

OC7# OC6#

OC4#

+3.3V_SUS

OC10# OC11# USB_OC1_3#

C C

D D

1

No stuff No stuff Stuff

6 7 8 9

10

R144 10KR144 10K R163 10KR163 10K R156 10KR156 10K

No stuff Stuff No stuff

RP28

10KX8

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

2

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN4_C PCIE_TXP4_C

GLAN_TXN_C GLAN_TXP_C

USB_OC_0#25

USB_OC1_3#25

Update USB OC circuit No24 11/17

+3.3V_SUS

5

OC9#

4

OC2#OC5#

3

USB_OC_0#

2

OC8#

1

12

+3.3V_SUS

12 12

U16B

D11

AD0

E12

E10

G11 F11

F10 D10

C8 D9

E9

C9

B7 C7 C5

F8

E7

A3 D2

D5

B3

F7 C3

F3

F4 C1 G7 H7 D1 G5 H6 G1 H3

J5

E1

J6

PCI

AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

Interrupt I/F

PIRQA# PIRQB# PIRQC# PIRQD#C4PIRQH#/GPIO5

ICH9M REV 1.0

2

REQ0#

GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2 PIRQF#/GPIO3

PIRQG#/GPIO4

3

MiniWWAN

PCIE_RX2-24 PCIE_RX2+24

Express Card

PCIE_RX4-21 PCIE_RX4+21

T104 PADT104 PAD T105 PADT105 PAD T107 PADT107 PAD T31 PADT31 PAD

PCIE_RX6-/GLAN_RX-31 PCIE_RX6+/GLAN_RX+31

Giga Bit LOM

T32 PADT32 PAD T83 PADT83 PAD T37 PADT37 PAD

T33 PADT33 PAD T35 PADT35 PAD

R176 22.6/FR176 22.6/F

1 2

Places within 500 mils of the ICH9

PCI_REQ0#

F1 G4

PCI_REQ1#

B6 A7

PCI_REQ2#

F13 F12

SB_LOM_PCIE_RST#

E6 F6

D8 B4 D6 A5

PCI_IRDY#

D3 E3

PAR

R1

PCI_DEVSEL#

C6

PCI_PERR#

E4

PCI_PLOCK#

C2

PCI_SERR#

J4

PCI_STOP#

A4

PCI_TRDY#

F5

PCI_FRAME#

D7 C14

CLK_PCI_ICH

D4 R2

PCI_PIRQE#

H4

SB_WLAN_PCIE_RST#

K6

SB_NB_PCIE_RST#

F2

ICH_IRQH_GPIO5

G2

3

U16D

N29

PERN1

N28

PERP1

P27

PETN1

P26

PETP1

L29

PERN2

L28

PERP2

M27

PETN2

M26

PETP2

J29

PERN3

J28

PERP3

K27

PETN3

K26

PETP3

G29

PERN4

G28

PERP4

H27

PETN4

H26

PETP4

E29

PERN5

E28

PERP5

F27

PETN5

F26

PETP5

C29

PERN6/GLAN_RXN

C28

PERP6/GLAN_RXP

D27

PETN6/GLAN_TXN

D26

PETP6/GLAN_TXP

D23

SPI_CLK

D24

SPI_CS0#

F23

SPI_CS1#/GPIO58/CLGPIO6

D25

SPI_MOSI

E23

SPI_MISO

N4

OC0#/GPIO59

N5

OC1#/GPIO40

N6

OC2#/GPIO41

P6

OC3#/GPIO42

M1

OC4#/GPIO43

N2

OC5#/GPIO29

M4

OC6#/GPIO30

M3

OC7#/GPIO31

N3

OC8#/GPIO44

N1

OC9#/GPIIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47

AG2

USBRBIAS

AG1

USBRBIAS#

ICH9M REV 1.0

USB_OC_0#

USB_OC1_3#

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN4_C PCIE_TXP4_C

GLAN_TXN_C GLAN_TXP_C

SPI_CLK_R SPI_CS#0_R ICH_SPI_CS1#_R

SPI_MOSI SPI_MISO

OC2# OC4#

OC5# OC6# OC7# OC8# OC9# OC10# OC11#

USBRBIAS

SB_LOM_PCIE_RST# 31

Add SB_LOM_PCIE_RST# No25 11/18

PCI_RST# 23

PLTRST# 6,21,22,24,31

CLK_PCI_ICH 17

SB_WLAN_PCIE_RST# 24 SB_NB_PCIE_RST# 6

T77PAD T77PAD

4

DMI0RXN DMI0RXP DMI0TXN

DMI0TXP

DMI1RXN DMI1RXP DMI1TXN

DMI1TXP

DMI2RXN DMI2RXP DMI2TXN

DMI2TXP

DMI3RXN DMI3RXP DMI3TXN

DMI3TXP

DMI_CLKN

PCI-Express

DMI_CLKP

DMI_ZCOMP

Direct Media Interface

DMI_IRCOMP

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P

SPI

USBP5N USBP5P USBP6N

USB

USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P

4

5

V27 V26 U29 U28

Y27 Y26 W29 W28

AB27 AB26 AA29 AA28

AD27 AD26 AC29 AC28

T26 T25

AF29

DMI_COMP

AF28 AC5

AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2

CLK_PCI_ICH

R161

R161 *10_NC

*10_NC

1 2

C265

*8.2P_NC

1 2

16

Reserved for EMI.Place resister and cap close to ICH.

16

A16 away override strap.

SB_NB_PCIE_RST#

5

6

DMI_MTX_IRX_N0 6 DMI_MTX_IRX_P0 6

DMI_MRX_ITX_N0 6 DMI_MRX_ITX_P0 6

DMI_MTX_IRX_N1 6 DMI_MTX_IRX_P1 6

DMI_MRX_ITX_N1 6 DMI_MRX_ITX_P1 6

DMI_MTX_IRX_N2 6 DMI_MTX_IRX_P2 6

DMI_MRX_ITX_N2 6 DMI_MRX_ITX_P2 6

DMI_MTX_IRX_N3 6 DMI_MTX_IRX_P3 6

DMI_MRX_ITX_N3 6 DMI_MRX_ITX_P3 6

CLK_PCIE_ICH# 17 CLK_PCIE_ICH 17

1 2

R249 24.9/FR249 24.9/F

ICH_USBP0- 25 ICH_USBP0+ 25 ICH_USBP1- 25 ICH_USBP1+ 25

ICH_USBP3- 25 ICH_USBP3+ 25 ICH_USBP4- 24 ICH_USBP4+ 24

ICH_USBP6- 24 ICH_USBP6+ 24 ICH_USBP7- 21 ICH_USBP7+ 21

ICH_USBP9- 20

ICH_USBP9+ 20 ICH_USBP10- 27 ICH_USBP10+ 27

ICH_USBP11- 18

ICH_USBP11+ 18

Low = A16 swap override enabled. High = Default.

+1.5V_PCIE_ICH

Side pair Top / left Side pair bottom / right

T75PAD T75PAD T71PAD T71PAD

T73PAD T73PAD T69PAD T69PAD

Pair 1 top / left Pair 1 bottom / right

Mini Card (WLAN)

Bluetooth Express Card

T79PAD T79PAD T74PAD T74PAD

Card reader Biometric Camera

6

7

Place within 500mils of ICH9

PCI Pullups

PCI_FRAME# PCI_TRDY# PCI_DEVSEL# PCI_REQ1#

+3.3V_RUN

PCI_IRDY# PCI_PIRQC# PCI_PIRQE# PCI_PIRQB#

+3.3V_RUN

PCI_REQ2#

SB_WLAN_PCIE_RST# SB_NB_PCIE_RST# SB_LOM_PCIE_RST#

BIOS should not enable the internal GPIO pull up resistor.

Title

ICH9-M (USB,DMI,PCIE,PCI)

Size Document Number Rev

AM3 1A

Date: Sheet

6 7 8 9

10

6 7 8 9

10

R139 8.2KR139 8.2K

QUANTA

QUANTA COMPUTER

COMPUTER

7

RP26RP26

RP27RP27

R148 20KR148 20K R182 20KR182 20K R152 20KR152 20K

5 4 3 2 1

12

8

+3.3V_RUN

PCI_PLOCK# PCI_STOP# PCI_PIRQD# PCI_PERR#

+3.3V_RUN

PCI_PIRQA# PCI_REQ0# ICH_IRQH_GPIO5 PCI_SERR#

+3.3V_RUN

12 12 12

12 45Wednesday, March 25, 2009

8

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1

+3.3V_SUS

RP25

1 3

2.2KX2

+3.3V_SUS

RP24

1

A A

3

100KX2

+3.3V_RUN

R181

8.2K

1 2

B B

Option to " Disable " clkrun. Pulling it down will keep the clks running.

PCIE_MCARD1_DET#24

CLKRUN#

Non-iAMT

ICH_SMBDATA

2

ICH_SMBCLK

4

ICH_SMLINK0

2

ICH_SMLINK1

4

ITP_DBRESET#3

PCIE_MCARD1_DET#

Add TPM_DET No10 10/16

C C

MCH_ICH_SYNC#6

+3.3V_RUN

R180 100KR180 100K

1 2

+3.3V_RUN

D D

R146 10KR146 10K R273 10KR273 10K

+3.3V_SUS

R123 10KR123 10K R296 10KR296 10K R304 100KR304 100K

1 2

Add TPM_ID No22 11/13

PCIE_MCARD1_DET#

IRQ_SERIRQ

12

THERM_ALERT#

12

RSV_WOL_EN

12

SIO_EXT_SMI#

12

USB_MCARD1_DET#

1

2

+3.3V_SUS

R340

Change ITP_DBRESET# design circuit No2 1/5

150

1 2

ITP_DBRESET_2#

+3.3V_SUS

R131 10KR131 10K R132 10KR132 10K R138 10KR138 10K R124 1KR124 1K

Change from PCIE_WAKE# to ICH_PCIE_WAKE# No22 11/13

ICH_SMBCLK21,24 ICH_SMBDATA21,24

R339 *0_NCR339 *0_NC

PM_BMBUSY#6

USB_MCARD1_DET#24

H_STP_PCI#17 H_STP_CPU#17

CLKRUN#22 ICH_PCIE_WAKE#22

IRQ_SERIRQ22,23

IMVP_PWRGD22,32,37

SIO_EXT_WAKE#22 SIO_EXT_SMI#22 SIO_EXT_SCI#22

R179 4.7KR179 4.7K

T81 PADT81 PAD T50 PADT50 PAD T49 PADT49 PAD

T67 PADT67 PAD

12

THERM_ALERT#29

T110 PADT110 PAD

T45 PADT45 PAD T39 PADT39 PAD

T112 PADT112 PAD T51 PADT51 PAD

12

T64 PADT64 PAD T36 PADT36 PAD T130 PADT130 PAD T42 PADT42 PAD

SATA_CLKREQ#17

T46 PADT46 PAD T108 PADT108 PAD

T47 PADT47 PAD

TPM_DET23 TPM_ID23

SPKR30

ICH_RSVD11

T111 PADT111 PAD

T109 PADT109 PAD

T38 PADT38 PAD

+3.3V_RUN

No Reboot strap.

SPKR

2

12 12 12 12

12

R147

*1K_NC

Low = Default. High = No Reboot.

3

Non-iAMT

RSV_ICH_CL_RST1# ICH_RI# SIO_EXT_SCI# ICH_PCIE_WAKE#

ICH_SMBCLK ICH_SMBDATA RSV_ICH_CL_RST1# ICH_SMLINK0 ICH_SMLINK1

ICH_RI# RSV_LPCPD#

ITP_DBRESET_2#

USB_MCARD1_DET#

CLKRUN# ICH_PCIE_WAKE#

IRQ_SERIRQ THERM_ALERT#

IMVP_PWRGD

SIO_EXT_SMI# SIO_EXT_SCI#

TPM_DET TPM_ID

SPKR

TP9 TP10 TP11

SPKR

3

4

U16C

G16

SMBCLK

A13

SMBDATA

E17

LINKALERT#/GPIO60/CLGPIO4

C17

SMLINK0

B18

SMLINK1

F19

RI#

R4

SUS_STAT#/LPCPD#

G19

SYS_RESET#

M6

PMSYNC#/GPIO0

A17

SMBALERT#/GPIO11

A14

STP_PCI#/GPIO15

E19

STP_CPU#/GPIO25

L4

CLKRUN#/GPIO32

E20

WAKE#

M5

SERIRQ

AJ23

THRM#

D21

VRMPWRGD

A20

TP8

AG19

TACH1/GPIO1

AH21

TACH2/GPIO6

AG21

TACH3/GPIO7

A21

GPIO8

C12

LANPHYPC/GPIO12

C21

ENGDET/GPIO13

AE18

TACH0/GPIO17

K1

GPIO18

AF8

GPIO20

AJ22

SCLOCK/GPIO22

A9

QRT_STATE0/GPIO27

D19

QRT_STATE1/GPIO28

L1

SATACLKREQ#/GPIO35

AE19

SLOAD/GPIO38

AG22

SDATAOUT0/GPIO39

AF21

SDATAOUT1/GPIO48

AH24

GPIO49

A8

GPIO57/CLGPIO5

M7

SPKR

AJ24

MCH_SYNC#

B21

TP3

AH20

TP9

AJ20

TP10

AJ21

TP11

ICH9M REV 1.0

SMbus address D2

These are for backdrive issue.

ICH_SMBDATA21,24 MEM_SDATA 15

4

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37

SATA

GPIO

SATA

GPIO

SMB

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

SYS GPIO

Power MGTController Link

GPIO

MEM_LED/GPIO24

NETDETECT/GPIO14

MISC

+3.3V_RUN

3 1

+3.3V_RUN

3 1

CLK14

CLK48 SUSCLK SLP_S3#

SLP_S4# SLP_S5#

PWROK

BATLOW# PWRBTN# LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST0# CL_RST1#

ALERT#/GPIO10 WOL_EN/GPIO9

2

1

Q12

2N7002W-7-F

2

Q13

2N7002W-7-F

4

3

5

RP23

2.2KX2

5

AH23 AF19 AE21 AD20

CLK_ICH_14M

H1

CLK_ICH_48M

AF3

ICH_SUSCLK

P1 C16

E16 G17

C10

ICH_PWRGD

G20

DPRSLPVR

M2

ICH_BATLOW#

B13 R3

RSV_ICH_LAN_RST#

D20

ICH_RSMRST#

D22 R5

ICH_CL_PWROK

R6 B16 F24

RSV_ICH_CL_CLK1

B19 F22

RSV_ICH_CL_DATA1

C19

CL_VREF0

C25

CL_VREF1

A19 F21

CL_RST1#

D18

RSV_GPIO24

A16

RSV_GPIO10

C18

RSV_GPIO14

C11

RSV_WOL_EN

C20

Non-iAMT

+3.3V_RUN

1 2

MEM_SCLK 15ICH_SMBCLK21,24

R118

8.2K

R311 8.2KR311 8.2K

PAD

R134 8.2KR134 8.2K

6

CLK_ICH_14M 17 CLK_ICH_48M 17

T123PAD T123PAD

SIO_SLP_S3# 22

T80PAD T80PAD

SIO_SLP_S5# 22

ICH_PWRGD 6,32 DPRSLPVR 6,37

12

+3.3V_SUS

SIO_PWRBTN# 22

T40PAD T40PAD

ICH_RSMRST# 22 CLK_PWRGD 17 ICH_CL_PWROK 6,22

T116PAD T116PAD

CL_CLK0 6

T44PAD T44PAD

CL_DATA0 6

T114PAD T114PAD

T113

ICH_CL_RST0# 6

T48PAD T48PAD

T115PAD T115PAD

T43PAD T43PAD

T60PAD T60PAD

T41PAD T41PAD

12

+3.3V_SUS

6

7

Place these close to ICH9.

CLK_ICH_48M

R170

R170 *10_NC

*10_NC

1 2 12

CLK_ICH_14M

R328

R328 *10_NC

*10_NC

1 2 12

Add TPM_ID No22 11/13 Add TPM_DET pull down

Non-iAMT

TPM_ID TPM_DET ICH_PWRGD DPRSLPVR ICH_RSMRST# RSV_ICH_LAN_RST# ICH_CL_PWROK

RSV_GPIO10

Non-iAMT

CL_VREF0

12

C189

0.1U

10

R141 10KR141 10K R113 10KR113 10K R126 10KR126 10K R329 100KR329 100K

1 2

R106 10KR106 10K

R120 10KR120 10K R143 1MR143 1M

R122 10KR122 10K

+3.3V_RUN

R114

3.24K/F

1 2

12

R112

R112 453/F

453/F

12 12 12

12

CL_VREF0/1 ~=0.405V

QUANTA

QUANTA COMPUTER

COMPUTER

Title

Size Document Number Rev

Date: Sheet

COMPUTER

ICH9-M (PM,GPIO,SMB,CL)

AM3 1A

7

8

C278

C278 *4.7P_NC

*4.7P_NC

50

C463

C463 *4.7P_NC

*4.7P_NC

50

+3.3V_SUS

13 45Wednesday, March 25, 2009

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