Datasheet UMA1005T Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UMA1005T

Dual low-power frequency
synthesizer

Preliminary specification
Supersedes data of September 1992
File under Integrated Circuits, IC03

Philips Semiconductors

November 1994

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

FEATURES

• Fast locking by ‘Fractional-N’ divider

• Auxiliary synthesizer

• Digital phase comparator with proportional and integral

charge pump output

• High-speed serial input

• Low-power consumption

• Programmable charge pump currents

• Supply voltage range 2.9 to 5.5 V.

APPLICATIONS

• Mobile telephony

• Portable battery-powered radio equipment.

ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

UMA1005T SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

GENERAL DESCRIPTION

The UMA1005T is a low-power, high-performance dual
frequency synthesizer fabricated in CMOS technology.
Fractional-N division with selectable modulo 5 or 8 is
implemented in the main synthesizer.

The detectors and charge pumps are designated to
achieve 10 to 5000 kHz channel spacing using
fractional-N decreases the channel spacing by a factor
5 or 8. Together with an external standard 2, 3 or 4 ratio
prescaler the main synthesizer can operate in the GHz
frequency range.

Channel selection and programming is realized by a
high-speed 3-wire serial interface.

PACKAGE

November 1994 2

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

BLOCK DIAGRAM

1 page = 296 mm (Datasheet)

DATA

CLOCK

STROBE

INM1
INM2

INR

4
5
6

2

3

7

EM

EM + EA

PR

12

2

MAIN DIVIDERS

UMA1005T

REFERENCE DIVIDER

SERIAL INPUT + PROGRAM LATCHES

NM2

NM1

12

NR

NM3
8

NM4
4

EM

SM

2

SA

2

FMOD

MAIN

PHASE

DETECTOR

MAIN

REFERENCE

SELECT

AUXILIARY

REFERENCE

SELECT

NF

3

FRACTIONAL

ACCUMULATOR

FRD

2

222

CN

8

CL

2

CK

4

PRESCALER

FEEDBACK

NORMAL
OUTPUT
CHARGE

PUMP

SPEED-UP

OUTPUT
CHARGE

PUMP

INTEGRAL

OUTPUT
CHARGE

PUMP

27 mm

18

FB1

19

FB2

16

RF
RN

15

13

PHP

11

PHI

9

RA

EA

PA NA

12

41

AUXILIARY DIVIDER

INA

EA

8

Fig.1 Block diagram.

November 1994 3

AUXILIARY

PHASE

DETECTOR

2

V

DDDVDDA

AUXILIARY

OUTPUT
CHARGE

PUMP

20 12141

V

SS

V

SSA

10

17

PHA

LOCK

MEA668 - 1

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

PINNING

SYMBOL PIN DESCRIPTION

V

DDD

INM1 2 main divider positive input; rising edge

INM2 3 main divider negative input; falling

DATA 4 serial data input line
CLOCK 5 serial clock input line
STROBE 6 serial strobe input line
INR 7 reference divider input line; rising edge

INA 8 auxiliary divider input line; rising edge

RA 9 auxiliary current setting; resistor to V
PHA 10 auxiliary phase detector output
PHI 11 integral phase detector output
V

SSA

PHP 13 proportional phase detector output
V

DDA

RN 15 main current setting input; resistor to

RF 16 fractional compensation current setting

LOCK 17 lock detector output
FB1 18 feedback output 1 for prescaler

FB2 19 feedback output 2 for prescaler

V

SS

1 digital supply voltage

active

edge active

active

active

12 analog ground; internally connected to

V

SS

14 analog supply voltage

V

SS

input; resistor to V

SS

modulus control

modulus control

20 common ground connection

SS

1/2 page (Datasheet)

V

DDD
INM1
INM2

DATA

CLOCK

STROBE

INR
INA

PHA

RA

1
2
3
4
5

UMA1005T

6
7
8
9

10

20
19
18
17
16
15
14
13
12
11

MEA667

Fig.2 Pin configuration.

V

SS
FB2
FB1

LOCK
RF
RN

V

DDA
PHP
V

SSA
PHI

22 mm

November 1994 4

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

FUNCTIONAL DESCRIPTION
Serial programming input

The serial input is a 3-wire input (CLOCK, STROBE and
DATA) to program all counter ratios, DACs, selection and
enable bits. The programming data is structured into
24 or 32-bit words. Each word includes 1 or 4 address
bits. Figure 3 shows the timing diagram of the serial input.
When the STROBE = LOW, the clock driver is enabled
and on the positive edges of the CLOCK the signal on the
DATA input is clocked into a shift register. When the
STROBE = HIGH, the clock is disabled and the data in the
shift register remains stable. Depending on the
1 or 4 address bits the data is latched into different
working registers or temporary registers. In order to fully
program the synthesizer, 4 words must be sent:

1. D word.

2. C word.

3. B word.

4. A word.
Figure 4 shows the format and the contents of each word.

The E word is for testing purposes only. The E (test) word

is reset when programming the D word. The data for NM4,
CN and PR is stored by the B word temporary registers.
When the A word is loaded, the data of these temporary
registers is loaded together with the A word into the work
registers which avoids false temporary main divider input.
CN is only loaded from the temporary registers when a
short 24-bit A0 word is used. CN will be directly loaded by
programming a long 32-bit A1 word. The flag LONG in the
D word determines whether A0 (LONG = 0) or A1
(LONG = 1) format is applicable.

The A word contains new data for the main divider. The
A word is loaded only when a main divider synchronization
signal is also active, to avoid phase jumps when
reprogramming the main divider. The synchronization
signal is generated by the main divider. It disables the
loading of the A word each main divider cycle during
maximum 300 main divider input cycles. To make sure
that the A word will be correctly loaded the STROBE signal
must be HIGH for at least 300 main divider input cycles.
Programming the A word also means that the main charge
pumps on outputs PHP and PHI are set into the speed-up
mode as long as the STROBE remains HIGH.

handbook, full pagewidth

DATA

CLOCK

STROBE

data
valid

data

change

D0 D1 D30 D31

t

suDA

t

hDA

t

HC

clock enabled

shift in data

Fig.3 Serial input timing sequence.

t

t

LC

suST

clock disabled

store data

t

hST

V

V

V

V

V

V

MBE121

H

L

H

L

H

L

November 1994 5

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

ndbook, full pagewidth

MSB

word

D31

A1

D23

A0

0 NF NM1

B

1 NM4 CN

C

1NA0

D

1

NM2

NM3 NM2

D0

NM2

NM3 NM2

000 CK CL PR

1

000

0

010

000

NR

PA

SM SA

EM EA

F

L

M

O

O

N

D

G

LSB

D0

CN0 NF NM1

PR = ‘01’
PR ‘01’

1E111

address bits

TEST BITS

D0D23

MBE122

Fig.4 Serial input word format.

November 1994 6

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

Table 1 Description of symbols used in Fig.4

SYMBOL BITS

NM1 12 number of main divider cycles when prescaler is programmed in ratio

NM2 8 if PR = 01 number of main divider cycles when prescaler is programmed in ratio

4 if PR ≠ 01

NM3 4 if PR = 1X number of main divider cycles when prescaler is programmed in ratio

NM4 4 if PR = 11 or 00 number of main divider cycles when prescaler is programmed in ratio

PR 2 prescaler type in use:

NF 3 fractional-N increment
FMOD 1 fraction-N modulus selection flag:

LONG 1 A word format selection flag:

CN 8 binary current setting factor for main charge pumps
CL 2 binary acceleration factor for proportional charge pump current
CK 4 binary acceleration factor for integral charge pump current
EM 1 main divider enable flag
EA 1 auxiliary divider enable flag
SM 2 reference select for main phase detector
SA 2 reference select for auxiliary phase detector
NR 9 reference divider ratio
NA 9 auxiliary divider ratio
PA 1 auxiliary prescaler mode:

(1)

FUNCTION

R1 (FB1 = 1; FB2 = 0); note 2

R2 (FB1 = 0; FB2 = 0); note 2

R3 (FB1 = 0; FB2 = 1); note 2

R4 (FB1 = 1; FB2 = 1); note 2

PR = 01; modulus 2 prescaler
PR = 10; modulus 3 prescaler
PR = 11; modulus 4 prescaler
PR = 00; modulus 4 prescaler (inhibit ratio 3)

1 = modulo 8
0 = modulo 5

0 = 24-bit A0 format
1 = 32-bit A1 format

PA = 0; divide-by-4
PA = 1; divide-by-1

Notes

1. X = don’t care.

2. Not including reset cycles and fractional-N effects.

Auxiliary variable divider

The input signal on INA is amplified to a logic level by a
single ended input buffer, which accepts LOW level AC
coupled input signals. This input stage is enabled if the
serial control bit EA = 1. Disabling means that all currents

November 1994 7

in the input stage are switched off. A fixed divide by 4 is
enabled if PA = 0. This divider has been optimized to
accept a high-frequency (90 MHz at a supply voltage
range of 4.75 to 5.5 V) input signal. If PA = 1 this divider is
disabled and the input signal is fed directly to the second

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

stage, which is a 9-bit programmable divider with standard
input frequency (30 MHz). The division ratio can be
expressed as:

If PA = 0; N = 4 × NA.
If PA = 1; N = NA; with NA = 4 to 511.

Reference variable divider (Fig.5) The input signal on INR is amplified to a logic level by a

single ended input buffer, which accepts LOW level AC
coupled input signals. This input stage is enabled by the
OR function of the serial input bits EA and EM. Disabling
means that all currents in the input stage are switched off.
The reference divider consists of a programmable divider
by NR (NR = 4 to 511) followed by a 3-bit binary counter.
The 2-bit SM determines which of the 4 output pulses is
selected as main phase detector input. The 2-bit SA
determines the selection of the auxiliary phase detector
signal. To obtain the best time spacing for the main and

auxiliary reference signals, the opposite output will be
used for the auxiliary phase detector, reducing the
possibility of unwanted interactions. For this reason the
programmable divider produces a symmetric output pulse
for even ratios and a 1 input cycle asymmetric pulse for
odd ratios.

Main variable divider

The input signals on INM1 and INM2 are amplified to a
logic level by a balanced input comparator giving a
common mode rejection. This input stage is enabled when
serial control bit EM = 1. Disabling means that all currents
in the comparator are switched off. The main divider is
built-up by a 12-bit counter plus a sign bit. Depending on
the serial input values of NM1, NM2, NM3, NM4 and the
prescaler select PR, the counter will select a prescaler
ratio during a number of input cycles in accordance with
the information in Table 2.

ook, full pagewidth

reference

input

MBE123

MAIN SELECT

SM = ‘00’
SM = ‘01’

SM = ‘10’
SM = ‘11’

divide by NR

2 22

AUXILIARY SELECT

SA = ‘11’
SA = ‘10’
SA = ‘01’

SA = ‘00’

Fig.5 Reference variable divider.

main
phase
detector

auxiliary
phase
detector

November 1994 8

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

Table 2 Selection of prescaler ratio

COUNTER

STATUS

FB1 FB2 PRESCALER RATIO

(−NM1 − 1) to 0 1 0 R1
(−NM1 − 1) to −11 0R1

(2)

1 to NM2 0 0 R2
0 to NM2 0 0 R2

(2)

0 to NM3 0 1 R3; if PR = 1X
0 to NM4 1 1 R4; if PR = 11 or 00

Notes

1. X = don’t care.

2. When the fractional accumulator overflows.

The total division ratio from prescaler to the phase detector expressions are given in Table 3.

Table 3 Total division from prescaler to phase detector expressions

CONDITION EXPRESSION

PR = 01 N = (NM1 + 2) × R1 + NM2 × R2

N′ = (NM1 + 1) × R1 + (NM2 + 1) × R2; note 1

PR = 10 N = (NM1 + 2) × R1 + NM2 × R2 + (NM3 + 1) × R3

N′ = (NM1 + 1) × R1 + (NM2 + 1) × R2 + (NM3 + 1) × R3; note 1

PR = 11 N = (NM1 + 2) × R1 + NM2 × R2 + (NM3 + 1) × R3 + (NM4 + 1) × R4

N′ = (NM1 + 1) × R1 + (NM2 + 1) × R2 + (NM3 + 1) × R3 + (NM4 + 1) × R4; note 1

PR = 00 N = (NM1 + 2) × R1 + NM2 × R2 + (NM4 + 1) × R4

N′ = (NM1 + 1) × R1 + (NM2 + 1) × R2 + (NM4 + 1) × R4; note 1

(1)

Note

1. When the fractional accumulator overflows.

When the prescaler ratio is R2 = R1 + 1 the total division ratio N′ =N+1.

Table 4 Modulus prescaler

PR MODULUS PRESCALER

NM1 NM2 NM3 NM4

00 4 12 4 − 4
01 2 12 8 −−
10 3 12 4 4 −
11 4 12 4 4 4

November 1994 9

BIT CAPACITY

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

The loading of the work registers NM1, NM2, NM3, NM4
and PR is synchronized with the state of the main counter,
to avoid extra phase disturbance when switching over to
another main divider ratio as is explained in Section “Serial
programming input”.

At the completion of a main divider cycle, a main divider
output pulse is generated which will drive the main phase
comparator. Also the fractional accumulator is
incremented with NF. The accumulator works modulo Q.
Q is preset by the serial control bit FMOD to 8 when
FMOD = 1. Each time the accumulator overflows, the
feedback to the prescaler will select one cycle using
prescaler ratio R2 instead of R1.

As shown above, this will increase the overall division ratio
by 1 if R2 = R1 + 1. The mean division ratio over Q main

divider cycles will then be:

NQ N

NF

+=

-------­Q

Programming a fraction means the prescaler with main
divider will divide by N or N + 1.

The output of the main divider will be modulated with a
fractional phase ripple. This phase ripple is proportional to
the contents of the fractional accumulator FRD, which is
used for fractional current compensation.

Phase detectors (Fig.6) The auxiliary and main phase detectors are a 2 D-type

flip-flop phase and frequency detector. The flip-flops are
set by the negative edges of output signals of the dividers.
The reset inputs are activated when both flip-flops have
been set and when the reset enable signal is active (LOW).
Around zero phase error this has the effect of delaying the
reset for 1 reference input cycle. This avoids non-linearity
or dead band around zero phase error. The flip-flops drive
on-chip charge pumps. A pull-up current from the charge
pump indicates that the VCO frequency shall be increased
while a pull-down pulse indicates that the VCO frequency
shall be decreased.

Current settings

The UMA1005T has 3 current setting pins RA, RN and RF.
The active charge pump currents and the fractional
compensation currents are linearly dependent on the
current in the current setting pins. This current I

can be

R

set by an external resistor to be connected between the
current setting pin (pin 9) and V

. The typical value for R

SS

(current setting resistor) can be calculated with the

equation:

V

R

=

-------------------------------------------------------------

DDA

0.5–()237 I

–

I

R

R

The current can be set to zero by connecting the
corresponding pin to V

DDA

.

Auxiliary output charge pumps

The auxiliary charge pumps on pin PHA are driven by the
auxiliary phase detector and the current value is
determined by the external resistor (R
active charge pump current is typically: |I

) at pin RA. The

ext

|=8×IRA.

PHA

Main output charge pumps and fractional compensation currents

The main charge pumps on pins PHP and PHI are driven
by the main phase detector and the current value is
determined by the current at pin RN and via a number of
DACs which are driven by registers of the serial input. The
fractional compensation current is determined by the
current at pin RF, the contents of the fractional
accumulator FRD and a number of DACs driven by
registers from the serial input. The timing for the fractional
compensation is derived from the reference divider. The
current is on during 1 input reference cycle before and
1 cycle after the output signal to the phase comparator.
Figure 7 shows the waveforms for a typical case.

When the serial input A word is loaded, the output circuits
are in the ‘speed-up mode’ as long as the STROBE is
HIGH, else the ‘normal mode’ is active.

N

ORMAL MODE

In the ‘normal mode’ the current output at PHP is:
I

PHP(N)=Ipump10+Icomp10

.

Where:

I

pump10

I

comp10

CN IRN×

=

----------------------- -

FRD IRF×

=

---------------------------

29

128

; charge pump current.

; fractional compensation current.

In ‘normal mode’ the current at output PHI is zero.

November 1994 10

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

handbook, full pagewidth

INR

L

R

X

P

INR

L

REFERENCE

DIVIDER

AUXILIARY

AND MAIN

DIVIDER

‘1’

DCQ

R

R

‘1’

R

D
C

X

Q

V

DDA

P

N

V

SSA

P-type

charge pump

PH

N-type

charge pump

N

PH

Fig.6 Phase detector structure with timing.

November 1994 11

MBE124

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

SPEED-UP MODE
In ‘speed-up mode’ the current in output PHP is:

I

PHP(S)=IPHP(N)+Ipump11+Icomp11

Where:

I

pump11=Ipump10

I

comp11=Icomp10

× 2

× 2

(CL + 1)
(CL + 1)

current.

In ‘speed-up mode’ the current in output PHI is:
I

PHI(S)=Ipump21+Icomp21

.

Where:

I

pump21=Ipump11

I

comp21=Icomp11

× CK; charge pump current.

× CK; fractional compensation current.

Figure 7 shows that for a proper fractional compensation
the area of the fractional compensation current pulse must
be equal to the area of the charge pump ripple output. This
means that the current setting on the inputs RN and RF

must have following ratio: .

I

-------­I

Where:

Q = fractional-N modulus.
f

VCO=fi(max)1

f

i(max)1

× N; input frequency of the prescaler.

= maximum input frequency of the main divider

(pins INM1 and INM2).
f

= maximum input frequency of the reference

i(max)2

divider (pin INR).

.

; charge pump current.

; fractional compensation

RN
RF

29 Q× f

=

-----------------------------------------------­64 CN× f

×

VCO

×

imax()2

Lock detect

The output LOCK is HIGH when the auxiliary phase
detector and the main phase detector indicate a lock
condition. The lock condition is defined as a phase
difference of less than±1 cycle on the reference input INR.
The lock condition is also fulfilled when the relative counter
is disabled (EM = 0 or EA = 0 respectively) for the main or
auxiliary counter respectively.

November 1994 12

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

handbook, full pagewidth

INR

INM

detector output

contents
accumulator

fractional
compensation
current

outputs
PHP and PHI

N

pulse-width
modulation

pulse-level
modulation

N N 1NN1

2 4 1 3 0

mA

µA

MBE125

t

1

t

2

Fig.7 Waveforms for NF = 2 and fraction = 0.4.

November 1994 13

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

DDD

V

DDA

V

I

I

n

P

tot

T

stg

T

amb

DC CHARACTERISTICS

V

DDD=VDDA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

digital supply voltage −0.5 6.5 V
analog supply voltage −0.5 6.5 V
voltage on any input −0.5 VDD+ 0.5 V
DC current into any input or output −10 +10 mA
total power dissipation − 25 mW
storage temperature −65 +150 °C
operating ambient temperature −40 +70 °C

= 2.9 to 5.5 V; T

= −40 to +70 °C; unless otherwise specified.

amb

Supply

I

DDD(stb)

I

DDD

digital standby supply
current

operating digital supply

EM = EA = 0; inputs on
VDDor 0

note 1 −−5mA

current

I

DDA(stb)

I

DDA

analog standby supply
current

operating analog supply

VRA=V
VRN=V

note 1 −−0.6 mA

current

Digital inputs CLK, DATA and STROBE

V

IH

V

IL

HIGH level input voltage 0.7V
LOW level input voltage 0 − 0.3V

Digital outputs FB1, FB2 and LOCK

V

OL

V

OH

LOW level output voltage IO= 2 mA; note 2 −−0.4 V
HIGH level output voltage IO= −2 mA; note 2 VDD− 0.4 −− V

Charge pump PHA

I

 output current IRA= −62.5 µA;

PHA

V

PHA

I

RA

∆I

PHA

--------------­I

PHA

∆I

PHA M

relative output current
variation

output current matching IRA= −62.5 µA;

I

RA

notes 2 and 3

V

PHA

notes 2 and 4

; VRF=V

DDA
DDA

=1⁄2VDD; note 2
= −25 µA; V
= −62.5 µA;

=1⁄2VDD;

−−5µA

;

DDA

−−10 µA

DD

− V

DD

DD

400 500 600 µA

=1⁄2VDD160 200 240 µA

PHA

− 26 %

−−±50 µA

V
V

November 1994 14

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Charge pump PHP; normal mode (notes 5, 6 and 7); VRF=V

I

∆I

 output current IRN= −62.5 µA;

PHP(N)

V

PHP

I

RN

PHP(N)

relative output current

IRN= −62.5 µA; note 3 − 26 %

=1⁄2VDD; note 2
= −25 µA; V

DD

=1⁄2VDD175 220 265 µA

PHP

variation

∆I

PHP(N M)

output current matching IRN= −62.5 µA;

V

=1⁄2VDD;

PHP

notes 2 and 4

Charge pump PHP; speed-up mode (notes 5, 6 and 8); V

I

∆I

∆I

 output current IRN= −62.5 µA;

PHP(S)

V

PHP

I

RN

PHP(S)

PHP(S M)

relative output current
variation

output current matching IRN= −62.5 µA;

IRN= −62.5 µA;
notes 2 and 3

V

PHP

=1⁄2VDD; note 2
= −25 µA; V

=1⁄2VDD;

RF=VDD

=1⁄2VDD0.85 1.1 1.35 mA

PHP

notes 2 and 4

Charge pump PHI; speed-up mode (notes 5, 6 and 9); V

I

 output current IRN= −62.5 µA;

PHI(S)

V

=1⁄2VDD; note 2

PHI

I

= −25 µA; V

RN

∆I

PHI(S)

∆I

PHI(S M)

relative output current
variation

IRN= −62.5 µA;
notes 2 and 3

output current matching IRN= −62.5 µA;

V

=1⁄2VDD; notes 2 and 4

PHI

RF=VDD

=1⁄2V

PHI

DD

Fractional compensation PHP; normal mode (notes 5, 10 and 11); V
I

PHP(F N)

fractional compensation
output current PHP as a
function of FRD

IRF= −62.5 µA;
FRD = 1 to 7;
notes 2 and 12

I

= −25 µA; FRD=1to7;

RF

note 12

440 550 660 µA

−−±50 µA

2.20 2.75 3.30 mA

− 26 %

−−±250 µA

4.4 5.5 6.6 mA

1.75 2.2 2.65 mA

− 28 %

−−±500 µA

; V

RN=VDD

PHP

=1⁄2V

DD

−675 −500 −325 nA

−270 −200 −130 nA

Fractional compensation PHP; speed-up mode (notes 5, 11 and 13); V
I

PHP(F S)

fractional compensation
output current PHP as a
function of FRD

IRN= −62.5 µA;
FRD = 1 to 7;
notes 2 and 12

= −25 µA; FRD = 1 to 7;

I

RN

note 12

November 1994 15

; V

RN=VDD

PHP

=1⁄2V

DD

−3.35 −2.50 −1.65 µA

−1.35 −1.00 −0.65 µA

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

SYMBOL PARAMETER CONDITIONS MIN. TYP . MAX. UNIT

; V

Fractional compensation PHI; speed-up mode (notes 5, 11 and 14); V

I

PHI(F)

fractional compensation
output current PHI as a
function of FRD

IRN= −62.5 µA;
FRD = 1 to 7;
notes 2 and 12

I

= −25 µA; FRD = 1 to 7;

RN

RN=VDD

−5.4 −4.0 −2.6 µA

−2.15 −1.60 −1.05 µA

note 12

Charge pump leakage currents; charge pump not active

I

PHP(LO)

output leakage current PHP normal mode;

V

= 0.7 to V

PHP

DDA

− 10 750 nA

− 0.8 V

note 5

I

PHI(LO)

output leakage current PHI normal mode;

V

= 0.7 to V

PHI

DDA

− 10 100 nA

− 0.8 V

note 5

I

PHA(LO)

output leakage current PHA V

PHA

= 0.7 to V

− 0.8 V − 10 750 nA

DDA

Notes

1. Operational conditions:
a) Main and auxiliary divider enabled (EM = EA = 1).
b) NA = 125.
c) NR = 125.
d) NM1 = 60.
e) NM2 = 63.
f) f

i(max)1=fi(max)2

g) f

i(max)3

= 60 MHz.

= 15 MHz.

h) Lock condition.
i) Normal mode; note 5
j) IRN=IRF=IRA=25µA.
k) CN = 255.
l) PA = 0.

2. Limited supply voltage range 4.5 to 5.5 V.

3. The relative output current variation is defined as:

–

2

I

×=

----------------- ­I

2I1

+

2I1

; with V

= 0.7 V; V2=VDD− 0.8 V (see Fig.8).

1

∆I

--------­I

O

O

4. The output current matching is measured when both (positive and negative current) sections of the output charge
pumps are on.

5. When a serial ‘A’ word is programmed, the main charge pumps on PHP and PHI are in the ‘speed-up mode’ as long
as STROBE = HIGH, otherwise the main charge pumps are in the ‘normal mode’.

6. Monotonicity is guaranteed with CN = 0 to 255.

PHP

=1⁄2V

DD

7. Typical output current: ; specification condition: CN = 255.

I

PHP(N)

CN

IRN–

×=

-------- ­29

November 1994 16

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

CL 1+()

2

8. Typical output current: ; specification conditions:

I

PHP(S)

IRN– CN

××=

-------------------------------

a) CN = 255; CL = 1 or,
b) CN = 75; CL = 3.

1+

29

9. Typical output current: ; specification conditions:

I

PHI

IRN– CN× 2

CL 1+()

CK

××=

-------­29

a) CN = 160; CL = 3; CK = 1 or,
b) CN = 160; CL = 2; CK = 2 or,
c) CN = 160; CL = 1; CK = 4 or,
d) CN = 160; CL = 0; CK = 8.

10. Typical fractional compensation output current: ; specification condition: FRD = 1 to 7.

I

PHP(F N)IRF

×=

FRD

------------­128

11. The compensation current specified does not include the leakage current of this output.

12. FRD is the value of the 3-bit fractional accumulator.

CL 1+()

13. Typical fractional compensation output current: ; specification conditions:

I

PHP(F S)IRF

FRD×

2

×=

-------------------------------

1+

128

FRD=1to7; CL=1.

14. Typical fractional compensation output current: ; specification conditions:

I

PHI(F)IRF

FRD× 2

CL 1+()

×

×=

CK

---------­128

a) FRD=1to7; CL=1; CK=2 or,
b) FRD=1to7; CL=2; CK=1.

November 1994 17

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

handbook, full pagewidth

I

o

I

2

I

1

I

2

I

1

V

1

Fig.8 Relative output current variation.

VV

2

MBE126

o

AC CHARACTERISTICS

V

DDD=VDDA

= 2.9 to 5.5 V; T

= −40 to +70 °C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Main divider (inputs INM1 and INM2)

f

i(max)1

maximum input frequency 10 −− MHz

note 1 30 −− MHz

∆V

INM(p-p)

differential input signal
amplitude V

INM1

− V

INM2

600 −− mV

(peak-to-peak value)

V

CM

t

pd

common mode range for
V

and V

INM1

INM2

propagation delay time
from I

NM1

and I

NM2

to FB1

1 − VDD− 1V

−−60 ns

note 1 − 18 30 ns

and FB2

msr mark-to-space ratio for

35:65

−

65:35

differential input signals

Z

i(min)

minimum input impedance resistive; note 2 5 −− kΩ

capacitive; note 2 −−5pF

November 1994 18

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Reference divider (input INR)

f

i(max)2

V

i(p-p)

Z

i(min)

Auxiliary divider (input INA)

f

i(max)3

V

i(p-p)

Z

i(min)

maximum input frequency 15 −− MHz

note 1 30 −− MHz

input signal amplitude

300 −− mV
AC coupled (peak-to-peak
value)

minimum input impedance resistive; note 2 5 −− kΩ

capacitive; note 2 −−5pF

maximum input frequency prescaler enabled; PA = 0 35 −− MHz

prescaler enabled; PA = 0;

90 −− MHz

note 1
prescaler disabled; PA = 1 15 −− MHz
prescaler disabled; PA = 1;

30 −− MHz

note 1

input signal amplitude AC

300 −− mV
coupled (peak-to-peak
value)

minimum input impedance resistive; note 2 5 −− kΩ

capacitive; note 2 −−5pF
Serial interface (inputs DATA, CLOCK and STROBE); see Fig.3
f

clk

t

HC

t

LC

t

suDA

t

hDA

t

suST

t

hST

clock frequency −−10 MHz
clock HIGH time 30 −− ns
clock LOW time 30 −− ns
DATA set-up time 30 −− ns
DATA hold time 30 −− ns
STROBE set-up time 30 −− ns
STROBE hold time 30 −− ns

Notes

1. Limited supply voltage range 4.5 to 5.5 V.

2. Periodically sampled; not 100% tested.

November 1994 19

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

PACKAGE OUTLINE

handbook, full pagewidth

Dimensions in mm.

6.75

6.40

0.32

0.20

0.1 S

0.13 M

(20x)

S

0.6

(4x)

0.2

20 11

pin 1
index

110

0.65

1.4

1.2

0.15
0

detail A

4.5

4.3

6.6

6.2

0.8

0.3

0.6

0.5

0.20

0.13

A

0 to 10

MBC237 - 1

1.5

1.2

o

Fig.9 Plastic shrink small outline package; 20 leads; body width 4.4 mm (SSOP20; SOT266-1).

November 1994 20

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

SOLDERING
Plastic small-outline packages

YWAVE

B
During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

B

Y SOLDER PASTE REFLOW

Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be

applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

R

IRON OR PULSE

-HEATED SOLDER TOOL)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

November 1994 21

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

NOTES

November 1994 22

Philips Semiconductors Preliminary specification

Dual low-power frequency synthesizer UMA1005T

NOTES

November 1994 23

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]

Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]

Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,

Tel. [phone], Fax. [phone]

Brazil: Rua do Rocio 220 - 5

CEP: 04552-903-SÃO PAULO-SP, Brazil.
P.O. Box 7383 (01064-970).
Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

Chile: Av. Santa Maria 0760, SANTIAGO,

Tel. [phone], Fax. [phone]

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77621 BOGOTA, Tel. [phone],
Fax. [phone]

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Tel. [phone], Fax. [phone]

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92156 SURESNES Cedex,
Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone].

Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. [phone] 911, Fax. [phone]

Hong Kong: PHILIPS HONG KONG Ltd., 6/F Philips Ind. Bldg.,

24-28 Kung Yip St., KWAI CHUNG, N.T.,
Tel. [phone], Fax. [phone]

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Dr. Annie Besant Rd. Worli, Bombay 400 018
Tel. [phone], Fax. [phone]

Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,

P.O. Box 4252, JAKARTA 12950,
Tel. [phone], Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS S.r.l.,

Piazza IV Novembre 3, 20124 MILANO,
Tel. [phone], Fax. [phone]

Japan: Philips Bldg13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]

Korea: (Republic of) Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905,

Tel. [phone], Fax. [phone]

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

th

floor, Suite 51,

Pakistan: Philips Electrical Industries of Pakistan Ltd.,

Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. [phone],
Fax. [phone].

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Portugal: PHILIPS PORTUGUESA, S.A.,

Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. [phone], Fax. [phone].

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

South Africa: S.A. PHILIPS Pty Ltd.,

195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone].

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Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,

Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. [phone], Fax. [phone]

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West

Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone].

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. [phone], Fax. [phone].

Turkey:Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors LTD.,

276 Bath road, Hayes, MIDDLESEX UB3 5BX,
Tel. [phone], Fax. [phone]

United States:811 East Arques Avenue, SUNNYVALE,

CA 94088-3409, Tel. [phone], Fax. [phone]

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. [phone], Fax. [phone]

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD35 © Philips Electronics N.V. 1994

All rights are reserved. Reproduction in whole or in part is prohibited without the
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The information presented in this document does not form part of any quotation
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use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

413061/1500/02/pp24 Date of release: November 1994
Document order number: 9397 743 40011

Philips Semiconductors