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TDA1312A
Datasheet (Philips)
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Datasheet TDA1312AT, TDA1312A Datasheet (Philips)

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INTEGRATED CIRCUITS
DATA SH EET
TDA1312A; TDA1312AT
Stereo continuous calibration DAC (CC-DAC)
Preliminary specification File under Integrated Circuits, IC01
July 1993
Philips Semiconductors Preliminary specification
Stereo continuous calibration DAC (CC-DAC)

FEATURES

• 8 × oversampling (simultaneous input) possible
• Voltage output
• Space saving package SO8 or DIL8
• Low power consumption
• Wide dynamic range (16-bit resolution)
• Continuous Calibration (CC) concept
• Easy application:
– single 4 to 5.5 V rail supply – output current and bias current are proportional to the
supply voltage
– integrated current-to-voltage converter
• Internal bias current ensures maximum dynamic range
• Wide operating temperature range (−40 °C to + 85 °C)
• Compatible with most current Japanese input formats:
time multiplexed, two's complement and TTL
• No zero-crossing distortion
• Cost efficient.
TDA1312A; TDA1312AT

GENERAL DESCRIPTION

The TDA1312A; 1312AT is a voltage driven D/A converter and is a device of a new generation of digital-to-analog converters which embodies the innovative technique of Continuous Calibration (CC). The largest bit-currents are repeatedly generated by one single current reference source. This duplication is based upon an internal charge storage principle having an accuracy insensitive to ageing, temperature matching and process variations.
The TDA1312A; 1312AT is fabricated in a 1.0 µm CMOS process and features an extremely low power dissipation, small package size and easy application. Furthermore, the accuracy of the intrinsic high coarse-current combined with the implemented symmetrical offset decoding method preclude zero-crossing distortion and ensures high quality audio reproduction. Therefore, the CC-DAC is eminently suitable for use in (portable) digital audio equipment.

ORDERING INFORMATION

EXTENDED TYPE NUMBER
TDA1312A
TDA1312AT
Notes
1. SOT97-1; 1996 August 14.
2. SOT96-1; 1996 August 14.
(1)
(2)
PACKAGE
PINS PIN POSITION MATERIAL CODE
8 DIL plastic SOT97DE 8 SO8 plastic SOT96AG
Philips Semiconductors Preliminary specification
Stereo continuous calibration
TDA1312A; TDA1312AT
DAC (CC-DAC)

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DD
I
DD
V
FS
(THD+N)/S total harmonic distortion plus
S/N signal-to-noise ratio at
t
CS
BR input bit rate at data input −−18.4 Mbits/s f
BCK
TC
FS
T
amb
P
tot
supply voltage 4 5 5.5 V supply current VDD = 5 V; at code 0000H − 3.4 6.0 mA full scale output voltage VDD = 5 V 1.8 2.0 2.2 V
at 0 dB signal level −−68 −63 dB
noise
− 0.04 0.07 %
at −60 dB signal level −−30 −24 dB
− 36%
at −60 dB signal level; A-weighted
−−33 − dB
− 2 − %
A-weighted; at code 0000H 86 92 − dB
bipolar zero current settling time to ±1
− 0.2 −µs
LSB
clock frequency at clock
−−18.4 MHz
input full scale temperature
−±400 − ppm coefficient at analog outputs (IOL; IOR)
operating ambient
−40 −+85 °C temperature
total power dissipation VDD = 5 V; at code 0000H − 17 30 mW
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July 1993 4
handbook, full pagewidth
Philips Semiconductors Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
V
OL
BCK
DATAR
DATAL
WS
LEFT INPUT REGISTER
LEFT OUTPUT REGISTER
6
I / V
I
OL
1
2
3
8
LEFT BIT SWITCHES
11-BIT
PASSIVE
DIVIDER
CONTROL
AND
TIMING
32 (5-BIT)
CALIBRATED
CURRENT SOURCES
1 CALIBRATED
SPARE SOURCE
RIGHT INPUT REGISTER
RIGHT OUTPUT REGISTER
RIGHT BIT SWITCHES
32 (5-BIT)
CALIBRATED
CURRENT SOURCES
1 CALIBRATED
SPARE SOURCE
TDA1312A
TDA1312AT
11-BIT
PASSIVE
DIVIDER
REFERENCE
SOURCE
GND
7
I / V
I
OR
4
C2
100 nF
V
OR
5
V
DD
MGE225
TDA1312A; TDA1312AT
Fig.1 Block diagram.
Philips Semiconductors Preliminary specification
Stereo continuous calibration DAC (CC-DAC)

PINNING

SYMBOL PIN DESCRIPTION
BCK 1 bit clock input DATAR 2 right data input DATAL 3 left data input GND 4 ground V
DD
V
OL
V
OR
WS

FUNCTIONAL DESCRIPTION

The basic operation of the continuous calibration DAC is illustrated in Fig.3. The figure shows the calibration and operation cycle. During calibration of the MOS current source (Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value I the switch S1 is opened and S2 is switched to the other position (Fig.3b). The gate-to-source voltage V not changed because the charge on Cgs is preserved. Therefore, the drain current of M1 will still be equal to I and this exact duplicate of I terminal.
The 32 current sources and the spare current source of the TDA1312A; AT are continuously calibrated (see Fig.1). The spare current source is included to allow continuous converter operation. The output of one calibrated source is
5 positive supply voltage 6 left channel output 7 right channel output 8 word select input
of M1 is
gs
is now available at the OUT
REF
ref
REF
TDA1312A; TDA1312AT
handbook, halfpage
connected to an 11-bit binary current divider consisting of 2048 transistors. A symmetrical offset decoding principle is incorporated and arranges the bit switching in such a way that the zero-crossing is performed only by switching the LSB currents.
The TDA1312A; AT (CC-DAC) accepts serial input data formats of 16-bit word length. Left and right data words are time multiplexed. The most significant bit (bit 1) must always be first. The input data format is shown in Figs.4
,
and 5. Data is placed in the right and left input registers (see
Fig.1). The data in the input registers is simultaneously latched in the output registers which control the bit switches.
An internal offset voltage V output voltage VFS; V Where V
BCK DATAR DATAL
GND
DD1/VDD2
1 2
TDA1312
TDA1312AT
3 4
8 7 6 5
MGE224
Fig.2 Pin configuration.
is added to the full scale
OFF
and VFS are proportional to VDD:
OFF
= V
FS1/VFS2
= V
OFF1/VOFF2
WS V V V
OR OL DD
.
Philips Semiconductors Preliminary specification
Stereo continuous calibration DAC (CC-DAC)
handbook, halfpage
S1
+
C
gs
(a) (b)
OUT
M1
V
TDA1312A; TDA1312AT
OUT
S1
I
REF
+
C
gs
I
REF
S2
gs
M1
V
S2
gs
I
REF
MGE226
Fig.3 Calibration principle; (a) calibration (b) operation.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V T T T V
DD stg XTAL amb es
supply voltage − 6.0 V storage temperature −55 +150 °C maximum crystal temperature −+150 °C operating ambient temperature −40 +85 °C electrostatic handling note 1 −2000 +2000 V
note 2 −200 +200 V
Notes
1. Human body model: C = 100 pF; R = 1500 Ω; 3 zaps positive and negative.
2. Machine model: C = 200 pF; L = 0.5 µH; R = 10 Ω; 3 zaps positive and negative.

THERMAL RESISTANCE

SYMBOL PARAMETER THERMAL RESISTANCE
R
th j-a
from junction to ambient in free air
DIL8 100 K/W SO8 210 K/W
Philips Semiconductors Preliminary specification
Stereo continuous calibration
TDA1312A; TDA1312AT
DAC (CC-DAC)

CHARACTERISTICS

V
= 5 V; T
DD
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply
V
DD
I
DD
Digital inputs; pins WS, BCK and DATA
I
input leakage current LOW VI = 0 V −−10 µA
IL
input leakage current HIGH VI = 5 V −−10 µA
I
IH
f
BCK
BR bit rate data input −−18.4 Mbits/s f
WS
Timing (see Fig.4) t
r
t
f
t
CY
t
BCKH
t
BCKL
t
SU;DAT
t
HD:DAT
t
HD:WS
t
SU;WS
Analog outputs; pins V
V
FS
TC
FS
V
OFF
(THD+N)/S total harmonic distortion plus noise at 0 dB signal level;
= 25 °C; measured in Fig.1; unless otherwise specified.
amb
positive supply voltage 4.0 5.0 5.5 V supply current at code 0000H − 3.4 6.0 mA
clock frequency −−18.4 MHz
word select input frequency −−384 kHz
rise time −−12 ns fall time −−12 ns bit clock cycle time 54 −−ns bit clock pulse width HIGH 15 −−ns bit clock pulse width LOW 15 −−ns data set-up time 12 −−ns data hold time to bit clock 2 −−ns word select hold time 2 −−ns word select set-up time 12 −−ns
and V
OL
OR
full-scale voltage 1.8 2.0 2.2 V full-scale temperature coefficient −±400 − ppm offset voltage at code 1000H 0.42 0.47 0.52 V
−−68 −63 dB
note 1 at −60 dB signal level;
note 1 at −60 dB signal level;
A-weighted; note1 at 0 dB signal level;
f = 20 Hz to 20 kHz
− 0.04 0.07 %
−−30 −24 dB
− 36%
−−33 − dB
− 2 − %
−−65 −61 dB
− 0.05 0.09 %
Philips Semiconductors Preliminary specification
Stereo continuous calibration
TDA1312A; TDA1312AT
DAC (CC-DAC)
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Analog outputs; pins V
t
cs
current settling time to ±1 LSB − 0.2 −µs
α channel separation 75 80 − dB δI
unbalance between outputs note 1 − 0.2 0.3 dB
O
t
time delay between outputs −±0.2 −µs
d
S/N signal-to-noise ratio at bipolar zero A-weighted;
Note
1. Measured with 1 kHz sinewave generated at sampling rate of 192 kHz.
handbook, full pagewidth
OL
and V
OR
86 92 − dB
at code 0000H
LEFT
WS
BCK
DATAR DATAL
<12
RIGHT
t
HD; WS
t
t
BCKH
r
>15
t
CY
>54
<12
t
t
f
BCKL
>15
LSB
>2
MSB
>12
t
SU; WS
SAMPLE OUT
t
SU; DAT
>12
t
HD; DAT
>2
MGE227
Fig.4 Input signals timing.
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July 1993 9
handbook, full pagewidth
Philips Semiconductors Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
DATAR DATAL
BCK
WS
SAMPLE OUT
MSB
LSB
MGE228
TDA1312A; TDA1312AT
Fig.5 Input signals format.
Philips Semiconductors Preliminary specification
Stereo continuous calibration DAC (CC-DAC)

PACKAGE OUTLINES

DIP8: plastic dual in-line package; 8 leads (300 mil)
D
seating plane
A
L
Z
e
b
8
1
w M
b
1
b
2
5
TDA1312A; TDA1312AT

SOT97-1

M
E
A
2
A
c
(e )
1
M
H
pin 1 index
E
1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
A
A
UNIT
max.
mm
inches
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE VERSION
SOT97-1
12
min.
max.
050G01 MO-001AN
b
1.73
1.14
0.068
0.045
IEC JEDEC EIAJ
0.53
0.38
0.021
0.015
b
1
1.07
0.89
0.042
0.035
4
0 5 10 mm
scale
b
2
0.36
0.23
0.014
0.009
REFERENCES
(1) (1)
cD E e M
9.8
9.2
0.39
0.36
6.48
6.20
0.26
0.24
L
e
1
M
3.60
8.25
3.05
7.80
0.14
0.32
0.12
0.31
EUROPEAN
PROJECTION
E
10.0
0.39
0.33
H
8.3
w
max.
0.2542.54 7.62
1.154.2 0.51 3.2
0.010.10 0.30
0.0450.17 0.020 0.13
ISSUE DATE
92-11-17 95-02-04
(1)
Z
July 1993 10
Philips Semiconductors Preliminary specification
Stereo continuous calibration DAC (CC-DAC)
SO8: plastic small outline package; 8 leads; body width 3.9 mm
D
c
y
Z
8
5
TDA1312A; TDA1312AT
E
H
E
A
X
v M
A

SOT96-1

A
pin 1 index
1
e
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
mm
A
max.
1.75
0.069
A1A2A
0.25
1.45
0.10
1.25
0.010
0.057
0.004
0.049
0.25
0.01
b
3
p
0.49
0.25
0.36
0.19
0.019
0.0100
0.014
0.0075
UNIT
inches
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
4
w M
b
p
0 2.5 5 mm
scale
(1)E(2)
cD
5.0
4.8
0.20
0.19
eHELLpQZywv θ
4.0
1.27
3.8
0.16
0.050
0.15
2
A
6.2
5.8
0.244
0.228
Q
3
A
θ
0.25 0.10.25
0.010.010.041 0.004
(1)
0.7
0.3
0.028
0.012
o
8
o
0
L
p
L
0.7
0.6
0.028
0.024
(A )
1
detail X
1.0
1.05
0.4
0.039
0.016
OUTLINE VERSION
SOT96-1
IEC JEDEC EIAJ
076E03S MS-012AA
REFERENCES
July 1993 11
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04 97-05-22
Philips Semiconductors Preliminary specification
Stereo continuous calibration DAC (CC-DAC)
SOLDERING Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
“IC Package Databook”
DIP
SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
R
EPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
SO
REFLOW SOLDERING Reflow soldering techniques are suitable for all SO
packages.
(order code 9398 652 90011).
). If the
stg max
TDA1312A; TDA1312AT
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.
AVE SOLDERING
W Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.
• The longitudinal axis of the package footprint must be parallel to the solder flow.
• The package footprint must incorporate solder thieves at the downstream end.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
R
EPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
July 1993 12
Philips Semiconductors Preliminary specification
Stereo continuous calibration
TDA1312A; TDA1312AT
DAC (CC-DAC)

DEFINITIONS

Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
July 1993 13
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