Datasheet TDA1311AT, TDA1311A Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA1311A

Stereo Continuous Calibration DAC
(CC-DAC)

Preliminary specification
Supersedes data of July 1993
File under Integrated Circuits, IC01

1995 Dec 18

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

FEATURES

• Voltage output

• Space saving packages SO8 or DIP8

• Low power consumption

• Wide dynamic range (16-bit resolution)

• Continuous Calibration (CC) concept

• Easy application:

– single 4 to 5.5 V rail supply
– output current and bias current are proportional to the

supply voltage

– integrated current-to-voltage converter

• Fast settling time permits 2, 4 and 8 × oversampling
(serial input) or double-speed operation at
4 × oversampling

• Internal bias current ensures maximum dynamic range

• Wide operating temperature range (−40 °C to +85 °C)

• Compatible with most current Japanese input formats:

time multiplexed, two's complement, TTL

• No zero-crossing distortion

• Cost efficient.

TDA1311A

GENERAL DESCRIPTION

The TDA1311A; AT is a voltage-driven digital-to-analog
converter and is new generation of DAC devices which
embodies the innovative technique of Continuous
Calibration (CC). The largest bit-currents are repeatedly
generated by one single current reference source. This
duplication is based upon an internal charge storage
principle which has an accuracy insensitive to ageing,
temperature matching and process variations.

The TDA1311A; AT is fabricated in a 1.0 µm CMOS
process and features an extremely low-power dissipation,
small package size and easy application. Furthermore, the
accuracy of the intrinsic high coarse-current combined
with the implemented symmetrical offset decoding method
preclude zero-crossing distortion and ensures high quality
audio reproduction. Therefore, the CC-DAC is eminently
suitable for use in (portable) digital audio equipment.

ORDERING INFORMATION

TYPE

NUMBER

TDA1311A DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
TDA1311AT SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

NAME DESCRIPTION VERSION

PACKAGE

1995 Dec 18 2

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC

TDA1311A

(CC-DAC)

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

I

DD

V

FS

(THD+N)/S total harmonic distortion

S/N signal-to-noise ratio at

t

cs

BR input bit rate at data input −− 18.4 Mbits/s
f

BCK

TC

FS

T

amb

P

tot

supply voltage 4 5 5.5 V
supply current VDD= 5 V at code 0000H − 3.4 6.0 mA
full scale output voltage VDD= 5 V 1.8 2.0 2.2 V

at 0 dB signal level −−68 −63 dB

plus noise

− 0.04 0.07 %

at −60 dB signal level −−30 −24 dB

− 36%

at −60 dB signal level;
A-weighted

−−33 − dB

− 2 − %

A-weighted at code 0000H 86 92 − dB

bipolar zero
current settling time to ±1

− 0.2 −µs

LSB

clock frequency at clock

−− 18.4 MHz

input
full scale temperature

−±400 − ppm
coefficient at analog outputs
(IOL; IOR)

operating ambient

−40 − +85 °C
temperature

total power dissipation VDD= 5 V at code 0000H − 17 30 mW

1995 Dec 18 3

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

BLOCK DIAGRAM

handbook, full pagewidth

LEFT INPUT REGISTER

LEFT OUTPUT REGISTER

6

V

OL

BCK

WS

DATA

I/V

I

OL

1
2
3

LEFT BIT SWITCHES

11-BIT

PASSIVE

DIVIDER

CONTROL

AND TIMING

32 (5-BIT)

CALIBRATED

CURRENT
SOURCES

1 CALIBRATED

SPARE SOURCE

RIGHT INPUT REGISTER

RIGHT OUTPUT REGISTER

RIGHT BIT SWITCHES

32 (5-BIT)

CALIBRATED

CURRENT
SOURCES

1 CALIBRATED

SPARE SOURCE

REFERENCE

TDA1311A

TDA1311AT

MBG858

11-BIT

PASSIVE

DIVIDER

SOURCE

GND

TDA1311A

8

I/V

I

OR

5

4

C2
100 nF

V

OR

V

DD

PINNING

SYMBOL PIN DESCRIPTION

BCK 1 bit clock input
WS 2 word select input
DATA 3 data input
GND 4 ground
V

DD

V

OL

n.c.
V

OR

5 supply voltage
6 left channel output

not connected

7

8 right channel output

Fig.1 Block diagram.

handbook, halfpage

1

BCK

WS

2

TDA1311A

DATA

GND

TDA1311AT

3
4

MBG859

Fig.2 Pin configuration.

V

8

OR

n.c.

7

V

6

OL

V

5

DD

1995 Dec 18 4

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

FUNCTIONAL DESCRIPTION

The basic operation of the continuous calibration DAC is
illustrated in Fig.3. The figure shows the calibration and
operation cycle. During calibration of the MOS current
source (see Fig.3a) transistor M1 is connected as a diode
by applying a reference current. The voltage Vgs on the
intrinsic gate-source capacitance Cgs of M1 is then
determined by the transistor characteristics. After
calibration of the drain current to the reference value I
the switch S1 is opened and S2 is switched to the other
position (see Fig.3b). The gate-to-source voltage Vgs of
M1 is not changed because the charge on Cgs is
preserved. Therefore, the drain current of M1 will still be
equal to I

and this exact duplicate of I

REF

REF

is now

available at the OUT terminal.
The 32 current sources and the spare current source of the

TDA1311A; AT are continuously calibrated (see Fig.1).
The spare current source is included to allow continuous
converter operation. The output of one calibrated source is
connected to an 11-bit binary current divider consisting of
2048 transistors.

REF

TDA1311A

A symmetrical offset decoding principle is incorporated
that arranges the bit switching in such a way that the
zero-crossing is performed only by switching the LSB
currents.

The TDA1311A; AT (CC-DAC) accepts serial input data
formats of 16-bit word length. Left and right data words are
time multiplexed. The most significant bit (bit 1) must
always be first. The input data format is shown in Figs 4
and 5.

,

With a HIGH level on the word select input (WS), data is
placed in the left input register and with a LOW level on the
WS input, data is placed in the right input register (see
Fig.1). The data in the input registers are simultaneously
latched in the output registers which control the bit
switches.

An internal offset voltage V
output voltage VFS; VOS and VFS are proportional to VDD:
V

DD1/VDD2=VFS1/VFS2=VOS1/VOS2

is added to the full scale

OS

.

handbook, full pagewidth

(a) =calibration.
(b) =operation.

S1

C

gs

out

I

ref

S2

M1

V

gs

(a) (b)

Fig.3 Calibration principle.

1995 Dec 18 5

S1

out

I

ref

C

gs

V

gs

M1

S2

I

ref

MBG860

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC

TDA1311A

(CC-DAC)

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

T

stg

T

XTAL

T

amb

V

es

Note

1. Human body model: C = 100 pF, R = 1500 Ω, 3 pulses positive and 3 pulses negative.

2. Machine model: C = 200 pF, L = 0.5 µH, R = 10 Ω, 3 pulses positive and 3 pulses negative.

THERMAL RESISTANCE

SYMBOL PARAMETER VALUE UNIT

R

th j-a

supply voltage − 6.0 V
storage temperature −55 +150 °C
maximum crystal temperature − +150 °C
operating ambient temperature −40 +85 °C
electrostatic handling note 1 −2000 +2000 V

note 2 −200 +200 V

thermal resistance from junction to ambient in free air

DIL8 100 K/W
SO8 210 K/W

QUALITY SPECIFICATION

In accordance with SNW-FQ-0611.

CHARACTERISTICS

V

DD

=5V; T

=25°C; measured in Fig.1; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DD

I

DD

supply voltage 4.0 5.0 5.5 V
supply current at code 0000H − 3.4 6.0 mA

Digital inputs; pins WS, BCK and DATA

|I

| input leakage current LOW VI= 0.8 V −− 10 µA

IL

| input leakage current HIGH VI= 2.4 V −− 10 µA

|I

IH

f

BCK

clock frequency −− 18.4 MHz

BR bit rate data input −− 18.4 Mbits/s
f

WS

word select input frequency −− 384 kHz

1995 Dec 18 6

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC

TDA1311A

(CC-DAC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing (see Fig.4)

t

r

t

f

t

CY

t

BCKH

t

BCKL

t

SU;DAT

t

HD:DAT

t

HD:WS

t

SU;WS

Analog outputs; pins V

V

FS

TC

FS

V

os

(THD+N)/S total harmonic distortion plus

t

cs

α

cs

|δI

| unbalance between outputs note 1 − 0.2 0.3 dB

O

|t

| time delay between outputs −±0.2 −µs

d

S/N signal-to-noise ratio at

rise time −− 12 ns
fall time −− 12 ns
bit clock cycle time 54 −− ns
bit clock pulse width HIGH 15 −− ns
bit clock pulse width LOW 15 −− ns
data set-up time 12 −− ns
data hold time to bit clock 2 −− ns
word select hold time 2 −− ns
word select set-up time 12 −− ns

and V

OL

OR

full-scale voltage 1.8 2.0 2.2 V
full-scale temperature

−±400 − ppm

coefficient
offset voltage VDD=V

OL/ORmax

0.45 0.50 0.55 V

at 0 dB signal level; note 1 −−68 −63 dB

noise

− 0.04 0.07 %

at −60 dB signal level; note 1 −−30 −24 dB

− 36 %

at −60 dB signal level;
A-weighted; note 1

at 0 dB signal level; f = 20 Hz
to 20 kHz

−−33 − dB

− 2 − %

−−65 −61 dB

− 0.05 0.09 %

current settling time to ±1 LSB − 0.2 −µs
channel separation 75 80 − dB

A-weighted at code 0000H 86 92 − dB

bipolar zero

Note

1. Measured with 1 kHz sinewave generated at sampling rate of 192 kHz.

1995 Dec 18 7

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

handbook, full pagewidth

WS

BCK

DATA

t

<

12

r

t

BCKHtf

>

15

t

>

CY

54

RIGHT

t

BCKL

<

>

12

15

LSB MSB

t

HD; WS

>

2

TDA1311A

LEFT

t

SU; WS

>

12

sample out

t

SU; DAT

>

12

t

HD; DAT

>

2

MBG861

Fig.4 Timing and input signals.

1995 Dec 18 8

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

LSBMSBLSBMSBDATA

TDA1311A

MBG862

RIGHT

BCK

handbook, full pagewidth

Fig.5 Format of input signals.

LEFT

sample out

WS

1995 Dec 18 9

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC

TDA1311A

(CC-DAC)

APPLICATION INFORMATION
Basic application example

A typical example of a CD-application with the TDA1311A; AT is shown in Fig.6. It features typical decoupling
components and a third-order analog post-filter stage providing a line output.

handbook, full pagewidth

10 Ω

V

DD

100

47

nF

µF

420 pF

22 kΩ

2.2 nF

420 pF

22 kΩ

2.2 nF

22 kΩ

22 kΩ

100 pF

100 pF

MBG863

BCK

WS

DATA

1

TDA1311A

2

TDA1311AT

3

5

8

7

6

4

Fig.6 Example of a 3rd order filter application.

Attention to printed circuit board layout

The TDA1311A and even more so the TDA1311AT offers
great ease in designing-in to printed-circuit boards due to
its small size and low pin count. The TDA1311A; AT being
a mixed-signal IC in CMOS, some attention needs to be
paid to layout and topology of the application PCB.
Following some basic rules will yield the desired
performance. The most important considerations are:

1. Supply: care should be taken to supply the
TDA1311A; AT with a clean, noiseless VDD, for a good
noise performance of the analog parts of the DAC.
Supply purity can easily be achieved by using an
RC-filtered supply.

2. Grounding: preferably a ground plane should be used,
in order to have a low-impedance return available at
any point in the layout. It is advantageous to make a
partitioning of the ground plane according to the nature
of the expected return currents (digital input returns
separate from supply returns and separate from the
analog section).

3. Topology: the capacitor decoupling high-frequency
supply interference from V

to GND should be placed

DD

as close as is physically possible to the IC body,
ensuring a low-inductance path to ground. The digital
input conductors may be shielded by ground leads
running alongside. The placement of a passive ground
plane underside the entire IC surface gives `free`
additional decoupling from the IC body to ground as
well as providing a shield between the digital input pins
and the analog output pins.

Figure 7 shows recommended layouts for printed-circuit
boards for the SO8 and DIL8 versions respectively. Both
layouts use a single-interconnect layer.

1995 Dec 18 10

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

handbook, full pagewidth

C1

V

DD

C2

TDA1311A

R

V

DD

MSA739

Fig.7 Recommended printed-circuit board layouts.

Interface examples

The following figures (Figs 8 to 14) show examples of connections to commonly used decoder and digital filter ICs. The
digital interface part is shown only, for clarity. The diagrams are for guidance purposes only - no guarantee for industrial
exploitation is implied.

handbook, halfpage

SM5807

BCKO

LRCOn

DOUT

15

14

12

1

BCK

2

1

WS

3

DATA

MBG864

TDA1311A

TDA1311AT

remark: SCSLn − signal SM5807 both "L" and "H" supported
by TDA1311A and TDA1311AT

Fig.8 NPC SM5807 digital filter (4FS).

1995 Dec 18 11

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

handbook, halfpage

14

DOL

DOR

BCKO

C2IOn

13

12

76

(1)

SM5840

OMODn pin 19: "L" for 4FS operation

(1)

versions A/B/G

Fig.9 NPC SM5840 digital filter (4FS).

handbook, halfpage

1

2

3

1

BCK

WS

DATA

BCK

TDA1311A

MBG865

TDA1311A

TDA1311AT

MBG866

CXD1125

MODE SELECT:
MD1 pin 55: "L"
MD2 pin 56: "L" to use DOTX function
MD3 pin 57: "H"
PSSL pin 59: "L"
SLOB pin 58: "L"

LRCK

DATA

80

78

Fig.10 Sony CXD1125 decoder (1FS).

handbook, halfpage

9

BCK

7

8

LRCK

DATA

CXD1125

C2IOn

LRD

DATA

2

3

3

1

4

WS

DATA

1

BCK

2

WS

3

DATA

TDA1311A

TDA1311AT

MBG867

TDA1311A

TDA1311AT

remark: CXD1162 input connectable to CXD1125
in the same way as for TDA1311A; AT to CXD1125

Fig.11 Sony CXD1162 digital filter (4FS).

1995 Dec 18 12

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

handbook, halfpage

76

DA14

CXD1135

MODE SELECT:
MD1 pin 55: "L"
MD2 pin 56: "L" to use DOTX function
MD3 pin 57: "H" for 1FS; "L" for 2FS
PSSL pin 59: "L"
SLOB pin 58: "L"

Fig.12 Sony CXD1135 decoder (1FS) and digital filter (2FS).

handbook, halfpage

LRCK

DA16

DSCK

80

78

74

1

2

3

1

BCK

WS

DATA

BCK

TDA1311A

MBG868

TDA1311A

TDA1311AT

MBG869

M50423

MODE SELECT:
DOBSEL pin 7: "L"
DASEL1 pin 8: "H"
DASEL2 pin 9: "L"
DASEL3 pin 10: "H"
DASEL4 pin 11: "L"

LRCK

DO1

75

72

2

3

WS

DATA

TDA1311A

TDA1311AT

Fig.13 Mitsubishi M50423 decoder (1FS) and digital filter (4FS).

handbook, halfpage

LC7863

MODE SELECT:
DFOFF pin 27: "L"
MSBF pin 38: "H"

DACLK

LRCLK

DFOUT

35

30

34

1

BCK

2

WS

3

DATA

MBG870

TDA1311A

TDA1311AT

Fig.14 Sanyo LC7863 decoder (1FS).

1995 Dec 18 13

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC

TDA1311A

(CC-DAC)

Evaluation of audio parameters

The following measurement graphs are performed on singular engineering samples; therefore no guarantee of typical
parameter values is implied. Measurement conditions are typical, as stated in the section Characteristics, unless
otherwise indicated. The normal measurement set-up includes a 20 kHz band-limiting filter for bandwidth definition, and
an A-weighting filter where indicated.

−100

handbook, halfpage

THD
(dB)

−80

−60

−40

−20

MBG871

0

−100 −80 −60 −40 −20 0
signal level (dB)

Fig.15 Total harmonic distortion plus noise as a function of signal level (4FS).

−20 10

handbook, halfpage

THD
(dB)

−40

−60

−80

−100

10

2

10

(1)

(2)

3

10

MBG873

4

10

frequency (Hz)

10

THD

(%)

1

0.1

0.01

0.001

5

(1) Measured including all distortion plus noise at a signal level of −60 dB.
(2) Measured including all distortion plus noise at a signal level of 0 dB.

Fig.16 Total harmonic distortion plus noises as a function of frequency (4FS).

1995 Dec 18 14

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

−50

handbook, halfpage

THD
(dB)

−60

−70

−80

3

(1) Measured including all distortion plus noise within the specified operating supply voltage range.
(2) Measured including all distortion plus noise outside the specified operating supply voltage range.
(3) VFS relative to nominal.

46V

5

MBG872

(3)(2)

(1)

(V)

DD

20

THD

0

−20

−40

TDA1311A

(%)

Fig.17 Total harmonic distortion plus noise as a function of supply voltage (4FS).

1995 Dec 18 15

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

PACKAGE OUTLINES

DIP8: plastic dual in-line package; 8 leads (300 mil)

D

seating plane

A

L

Z

e

b

8

1

w M

b

1

b

2

5

TDA1311A

SOT97-1

M

E

A

2

A

c

(e )

1

M

H

pin 1 index

E

1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

A

A

UNIT

max.

mm

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

SOT97-1

12

min.

max.

050G01 MO-001AN

b

1.73

1.14

0.068

0.045

IEC JEDEC EIAJ

0.53

0.38

0.021

0.015

b

1

1.07

0.89

0.042

0.035

4

0 5 10 mm

scale

b

2

0.36

0.23

0.014

0.009

REFERENCES

(1) (1)

cD E e M

9.8

9.2

0.39

0.36

6.48

6.20

0.26

0.24

L

e

1

M

3.60

8.25

3.05

7.80

0.14

0.32

0.12

0.31

EUROPEAN

PROJECTION

E

10.0

0.39

0.33

H

8.3

w

max.

0.2542.54 7.62

1.154.2 0.51 3.2

0.010.10 0.30

0.0450.17 0.020 0.13

ISSUE DATE

92-11-17
95-02-04

(1)

Z

1995 Dec 18 16

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

SO8: plastic small outline package; 8 leads; body width 3.9 mm

D

c

y

Z

8

5

TDA1311A

SOT96-1

E

H

E

A

X

v M

A

A

pin 1 index

1

e

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

A

A1A2A3b

max.

0.25

1.75

0.10

0.010

0.069

0.004

1.45

1.25

0.057

0.049

0.25

0.01

p

0.49

0.36

0.019

0.014

0.25

0.19

0.0100

0.0075

UNIT

inches

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

4

w M

b

p

0 2.5 5 mm

scale

(1)E(2)

cD

5.0

4.8

0.20

0.19

eHELLpQZywv θ

4.0

1.27

3.8

0.16

0.050

0.15

2

A

6.2

5.8

0.244

0.228

Q

3

A

θ

0.25 0.10.25

0.010.010.041 0.004

(1)

0.7

0.3

0.028

0.012

o

8

o

0

L

p

L

0.7

0.6

0.028

0.024

(A )

1

detail X

1.0

1.05

0.4

0.039

0.016

OUTLINE
VERSION

SOT96-1

IEC JEDEC EIAJ

076E03S MS-012AA

REFERENCES

1995 Dec 18 17

EUROPEAN

PROJECTION

ISSUE DATE

95-02-04
97-05-22

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“IC Package Databook”

our

DIP

SOLDERING BY DIPPING OR BY WA VE
The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

SO

REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO

packages.

(order code 9398 652 90011).

). If the

stg max

TDA1311A

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

AVE SOLDERING

W
Wave soldering techniques can be used for all SO

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

EPAIRING SOLDERED JOINTS

R
Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

1995 Dec 18 18

Philips Semiconductors Preliminary specification

Stereo Continuous Calibration DAC

TDA1311A

(CC-DAC)

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1995 Dec 18 19

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

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th

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Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,

International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD47 © Philips Electronics N.V. 1995

All rights are reserved. Reproduction in whole or in part is prohibited without the
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Printed in The Netherlands

513061/50/02/pp20 Date of release: 1995 Dec 18
Document order number: 9397 750 00532