Datasheet STHDLS101T Datasheet (ST)

Features

■ Converts low-swing alternating current (AC)

coupled differential input to high-definition
multimedia interface (HDMI) rev 1.3 compliant

■ HDMI level shifting operation up to 2.7 Gbps

per lane

■ Integrated 50-Ω termination resistors for AC-

coupled differential inputs

■ Input/output transition minimized differential

signaling (TMDS) enable/disable

■ Output slew rate control on TMDS outputs to

minimize electromagnetic interference (EMI)

■ Fail safe outputs for backdrive protection

■ No re-timing or configuration required

■ Inter-pair output skew < 250 ps

■ Intra-pair output skew < 10 ps

■ Single power supply of 3.3 V

■ ESD protection: ±6 KV HBM on all I/O pins

■ Integrated display data channel (DDC) level

shifters. Pass-gate voltage limiters allow 3.3 V
termination on graphics and memory controller
hub (GMCH) pins and 5 V DDC termination on
HDMI connector pins

■ Level shifter and configurable output for HPD

signal from HDMI/DVI connector

■ Integrated pull-down resistor on HPD_SINK

and OE_N inputs

Applications

■ Notebooks

■ PC motherboards and graphic cards

■ Dongles/cable adapters

Table 1. Device summary

STHDLS101T

AC coupled HDMI level shifter

with configurable HPD output

QFN-48

(7 x 7 mm)

Description

The STHDLS101T is a high-speed high-definition
multimedia interface (HDMI) level shifter that
converts low-swing AC coupled differential input
to HDMI 1.3 compliant open-drain current
steering RX-terminated differential output.
Through the existing PCI-E pins in the graphics
and memory controller hub (GMCH) of PCs or
notebook motherboards, the pixel clock provides
the required bandwidth (1.65 Gbps, 2.25 Gbps)
for the video supporting 720p, 1080i, 1080p with a
total of 36-bit resolution. The HDMI is multiplexed
onto the PCIe pins in the motherboard where the
AC coupled HDMI at 1.2 V is output by GMCH.
The AC coupled HDMI is then level shifter by this
device to 3.3 V DC coupled HDMI output.

The STHDLS101T supports up to 2.7 Gbps,
which is enough for 12-bits of color depth per
channel, as indicated in HDMI rev 1.3. The device
operates from a single 3.3 V supply and is
available in a 48-pin QFN package.

Order code Package Packaging

STHDLS101TQTR QFN-48 Tape and reel

December 2008 Rev 3 1/26

www.st.com

26

Contents STHDLS101T

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 System interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1.1 Power supply and temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1.2 Differential inputs (IN_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 TMDS outputs (OUT_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 HPD input and output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4 DDC input and output chatacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.5 OE_ input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.6 HPD input resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.7 ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.1 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.2 Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3 Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2/26

STHDLS101T Contents

3/26

Block diagram STHDLS101T

1 Block diagram

Figure 1. STHDLS101T block diagram

0

VCC33

IN_D4+

IN_D4-

V

50 ±10%

Ω

OUT_D4+

OUT_D4-

RX

OE_N

IN_D3+

IN_D3-

IN_D2+

IN_D2-

0V

Ω

50 ±10%

0V

50 ±10%

Ω

0V

50

Ω±10%

10mA current

driver

OUT_D3+

OUT_D3-

RX

10mA current

driver

OUT_D2+

OUT_D2-

RX

10mA current

driver

OUT_D1+

OUT_D1-

4/26

IN_D1+

RX

IN_D1-

REXT

HPD level

shifter

HPD_SOURCE HPD_SINK

DDC_EN

SCL_SOURCE

SDA_SOURCE

HPD

160

K

10mA current

driver

SCL_SINK

SDA_SINK

STHDLS101T System interface

2 System interface

Figure 2. System inferface

PCI-Express

SDVO

Graphics chipset

(GMCH) on the

motherboard

Figure 3. Cable adapter

HDMI

Level shifter

STHDLS101T

HDMI output

connector

CS00375

$ONGLEOR

ADAPTER

CABLE

($-)$6)

34($,3

$0

4

5/26

System interface STHDLS101T

Figure 4. DP to HDMI/DVI cable adapter

HDMI/DVI

Transmitter

PC chipset

HPD

AC_TMDS

DDC

HPD_SOURCE

DP Connector

AC_TMDS

DDC

STHDLS101T

HDMI/DVI Cable

Adaptor

HPD_SINK

DC TMDS

DDC

HDMI/DVI Connector

!-6

6/26

STHDLS101T Pin configuration

3 Pin configuration

Figure 5. STHDLS101T pin configuration

FUNCTION4

GND

FUNCTION3

VCC33

DDC_EN

GND

HPD_SINK

SDA_SINK

SCL_SINK

GND

VCC33

OE_N

GND

IN_D1-

IN_D1+

VCC33

IN_D2-

IN_D2+

GND

IN_D3-

IN_D3+

VCC33

IN_D4-

IN_D4+

31

33

35

1

GND

34

2

33

VCC

4

3

FUNCTION1

FUNCTION2

36

37

38

39

40

41

42

43

44
45

46

47

48

32

QFN-48

5

6

GND

REXT

30

29

7

8

SOURCE

SDA_

HPD_SOURCE

27

28

9

RCE

SOU

SCL_

24

26

25

23

22

21

20

19

18

17

16

15

14

13

10

11

33

VCC

ANALOG2

GND

OUT_D1-

OUT_D1+

VCC33

OUT_D2-

OUT_D2+

GND

OUT_D3-

OUT_D3+

VCC33

OUT_D4-

OUT_D4+

12

GND

CS000118

7/26

Pin configuration STHDLS101T

3.1 Pin description

Table 2. Pin description

Pin

number

1GND PowerGround

2 VCC33 Power 3.3V±10% DC supply

3 FUNCTION1

4 FUNCTION2

5GND PowerGround

6 REXT Analog

7 HPD_SOURCE Output

Name Type Function

Function pins are to enable vendor-specific features or

Vendor-specific

control or test

pins

Vendor-specific

control or test

pins

test modes.
For normal operation, these pins are tied to GND or

VCC33.
For consistent interoperability, GND is the preferred

default connection for these signals

Function pins are to enable vendor-specific features or
test modes.

For normal operation, these pins are tied to GND or
VCC33.

For consistent interoperability, GND is the preferred
default connection for these signals

Connection to external resistor. Resistor value
specified by device manufacturer.

Acceptable connections to this pin are:

- Resistor to GND

- Resistor to 3.3V;

- NC (direct connections to V
0-Ù resistor for layout compatibility

Buffer from the 0 V to 5 V input signal. The output
buffer stage is configurable based on the FUNCTION3
pin settings as desribed in the table below:

or GND are through a

CC

8/26

8 SDA_SOURCE I/O

9 SCL_SOURCE Input

FUNCTION3 HPD_SINK HPD_SOURCE

Open-drain,

connected an

0Low

0 High (5 V) Low (0 V)

1 Low (0 V) Low (0 V)

1 High (5 V) High (3 V)

3.3 V DDC data I/O. Pulled-up by external termination
to 3.3 V. Connected to SDA_SINK through voltage­limiting integrated NMOS pass-gate

3.3 V DDC clock I/O. Pulled-up by external termination
to 3.3 V. Connected to SCL_SINK through voltage­limiting integrated NMOS pass-gate

external pull up to

the desired

supply

(normally 1 V)

STHDLS101T Pin configuration

Table 2. Pin description (continued)

Pin

number

10 ANALOG2 Analog

11 VCC33 Power 3.3 V ±10% DC supply

12 GND Power Ground

13 OUT_D4+ Output

14 OUT_D4- Output

15 VCC33 Power 3.3 V±10% DC supply

16 OUT_D3+ Output

17 OUT_D3- Output

18 GND Power Ground

19 OUT_D2+ Output

20 OUT_D2- Output

21 VCC33 Power 3.3 V±10% DC supply

Name Type Function

Analog connection determined by vendor.
Acceptable connections to this pin are:

- Resistor or capacitor to GND

- Resistor or capacitor to 3.3 V

- Short to 3.3 V or to GND

- NC

HDMI 1.3 compliant TMDS output.
OUT_D4+ makes a differential output signal with
OUT_D4-.

HDMI 1.3 compliant TMDS output.
OUT_D4- makes a differential output signal with
OUT_D4+.

HDMI 1.3 compliant TMDS output.
OUT_D3+ makes a differential output signal with
OUT_D3-.

HDMI 1.3 compliant TMDS output.
OUT_D3- makes a differential output signal with
OUT_D3+.

HDMI 1.3 compliant TMDS output.
OUT_D2+ makes a differential output signal with
OUT_D2-.

HDMI 1.3 compliant TMDS output.
OUT_D2- makes a differential output signal with
OUT_D2+.

22 OUT_D1+ Output

23 OUT_D1- Output

24 GND Power Ground

25 OE_N Input

26 VCC33 Power 3.3 V±10% DC supply

HDMI 1.3 compliant TMDS output. OUT_D1+ makes a
differential output signal with OUT_D1-.

HDMI 1.3 compliant TMDS output. OUT_D1- makes a
differential output signal with OUT_D1+.

Enable for level shifter path. 3.3 V tolerant low-voltage
single-ended input. Internal pull-down enables chip
when unconnected.

OE_N

1 High-Z High-Z

050Ω Active

IN_D

termination

OUT_D Outputs

9/26

Pin configuration STHDLS101T

Table 2. Pin description (continued)

Pin

number

27 GND Power Ground

28 SCL_SINK Output

29 SDA_SINK I/O

30 HPD_SINK Input

31 GND Power Ground

32 DDC_EN Input

33 VCC33 Power 3.3V±10% DC supply

34 FUNCTION3 Input

35 FUNCTION4

Name Type Function

5 V DDC Clock I/O. Pulled-up by external termination
to 5 V. Connected to SCL_SOURCE through voltage­limiting integrated NMOS pass-gate

5V DDC Data I/O. Pulled-up by external termination to
5V. Connected to SDA_SOURCE through voltage­limiting integrated NMOS pass-gate

Low-frequency, 0V to 5V (nominal) input signal. This
signal comes from the HDMI connector. Voltage high
indicates “plugged” state; voltage low indicates
“unplugged” state. HPD_SINK is pulled down by an
integrated 160KΩ pull-down resistor.

Enables bias voltage to the DDC pass-gate level shifter
gates. (May be implemented as a bias voltage
connection to the DDC pass-gate themselves).

DDC_EN Pass-gate

0 V Disabled

3.3 V Enabled

Used for polarity control of the HPD_SOURCE output.
When L, the HPD_SOURCE is an open-drain output

sand when H, the HPD_SOURCE is a buffered output

CC

)

Vendor-specific

control or test

pins

(O V to V

Function pins are to enable vendor-specific features or
test modes.

For normal operation, these pins are tied to GND or
VCC33.

For consistent interoperability, GND is the preferred
default connection for these signals

10/26

36 GND Power Ground

37 GND Power Ground

38 IN_D1- Input

39 IN_D1+ Input

40 VCC33 Power 3.3 V±10% DC supply

41 IN_D2- Input

42 IN_D2+ Input

Low-swing differential input from GMCH PCIE outputs.
IN_D1- makes a differential pair with IN_D1+.

Low-swing differential input from GMCH PCIE outputs.
IN_D1+ makes a differential pair with IN_D1-.

Low-swing differential input from GMCH PCIE outputs.
IN_D2- makes a differential pair with IN_D2+.

Low-swing differential input from GMCH PCIE outputs.
IN_D2+ makes a differential pair with IN_D2-.

STHDLS101T Pin configuration

Table 2. Pin description (continued)

Pin

number

43 GND Power Ground

44 IN_D3- Input

45 IN_D3+ Input

46 VCC33 Power 3.3 V±10% DC supply

47 IN_D4- Input

48 IN_D4+ Input

Name Type Function

Low-swing differential input from GMCH PCIE outputs.
IN_D3- makes a differential pair with IN_D3+.

Low-swing differential input from GMCH PCIE outputs.
IN_D3+ makes a differential pair with IN_D3-.

Low-swing differential input from GMCH PCIE outputs.
IN_D4- makes a differential pair with IN_D4+.

Low-swing differential input from GMCH PCIE outputs.
IN_D4+ makes a differential pair with IN_D4-.

11/26

Functional description STHDLS101T

4 Functional description

The section describes the basic functionality of the STHDLS101T device.

Power supply

The STHDLS101T is powered by a single DC power supply of 3.3 V ± 10%.

Clocking

This device does not retime any data. The device contains no state machines. No inputs or
outputs of the device are latched or clocked.

Reset

This device acts as a level shifter, reset is not required.

OE_N function

When OE_N is asserted (low level), the IN_D and OUT_D signals are fully functional. Input
termina-tion resistors are enabled and any internal bias circuits are turned on.

OE_N pin has an internal pull-down that enables the chip if left unconnected.
When OE_N is de-asserted (high level), the OUT_D outputs are in high impedance state.

The IN_D input buffers are disabled and the IN_D termination resistors are disabled.
Internal bias circuits for the differential inputs and outputs are turned off. Power consumption
of the chip is minimized.

The HPD_SINK input and HPD_SOURCE output are not affected by OE_N. The SCL and
SDA pass-gates are not affected by OE_N.

Table 3. OE_N description

OE_N Device state Comments

Asserted (low level)

or unconnected

De-asserted (high level)

Differential input buffers and
output buffers enabled. Input
impedance = 50Ù

Low-power state.

Differential input buffers and
terminations are disabled.
Differential input buffers are in
high-impedance state.

OUT_D level shifting outputs are
disabled. OUT_D level shifting
outputs are in a high-impedance
state.

Internal bias currents are turned
off.

Normal functioning state for IN_D
to OUT_D level shifting function.

Intended for lowest power
condition when:

• No display is plugged in or

• The level shifted data path is

disabled

HPD_SINK input and
HPD_SOURCE output are not
affected by OE_N.

SCL_SOURCE, SCL_SINK,
SDA_SOURCE and SDA_SINK
signals and functions are not
affected by OE_N.

12/26

STHDLS101T Functional description

Table 4. OE_N function

OE_N IN_Dx

De-asserted

(high level)

Asserted or

unconnected

(low level)

50 Ω termination Enabled

OUT_Dx

(TMDS outputs)

High-Z High-Z

Notes

Device disabled.
Low power state.
Internal bias currents are

disabled.

Level shifting mode
enabled.

13/26

Maximum ratings STHDLS101T

5 Maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.

Table 5. Absolute maximum ratings

Symbol Parameter Value Unit

V

Supply voltage to ground potential -0.5 to +4.0 V

CC

DC input voltage (TMDS and PCIe ports) -0.5 to +4.0 V

V

I

Control pins -0.5 to +4.0 V

SDA_SINK, SCL_SINK, HPD_SINK pins -0.5 to +6 V

I

DC output current 120 mA

O

Power dissipation 1 W

P

D

T

V

Storage temperature -65 to +150 °C

STG

T

Lead temperature (10 sec) 300 °C

L

Electrostatic discharge

ESD

voltage on IOs

(1)

Human body model ±6 kV

1. In accordance with the MIL standard 883 method 3015

Table 6. Thermal data

Symbol Parameter QFN-48 Unit

θ

JA

Junction-ambient thermal coefficient 48 °C/W

14/26

STHDLS101T Maximum ratings

5.1 Recommended operating conditions

5.1.1 Power supply and temperature range

Table 7. Power supply and temperature range

Symbol Parameter Comments Min Typ Max Unit

V

CC33

I

CC

3.3 V power supply 3.0 3.3 3.6 V

Maximum power supply current

Total current from V

3.3 V power supply

CC

100 mA

T Operating temperature range -40 85

5.1.2 Differential inputs (IN_D signals)

Table 8. Differential input characteristics for IN_D signals

Symbol Parameter Comments Min Typ Max Unit

Tbit Unit interval

V

RX-DIFFp-p

T

RX-EYE

V

CM-AC-pp

Z

RX-DC

V

RX-Bias

Z

RX-HIGH-Z

Differential input peak to peak voltage

Minimum eye width at IN_D input pair

AC peak common mode input voltage

DC single-ended input impedance

RX input termination voltage

Single-ended input resistance for
IN_Dx when inputs are in high-Z state

Tbit is determined by the
display mode. Nominal bit
rate ranges from 250 Mbps
to 2.5 Gbps per lane.
Nominal Tbit at

2.5 Gbps = 400 ps. 360 ps =
400 ps – 10%

V

RX-DIFFp-p

|. Applies to IN_D signals.

D-

=2*|V

RX-D+

- V

RX-

The level shifter may add a
maximum of 0.02UI jitter

VCM-AC-pp=|VRX-D+ +
VRX-D-|/2 – VRX-CM-DC.

VRX-CM-DC=DC(avg) of
|VRX-D+ + VRX-D-|/2

VCM-AC-pp includes all
frequencies above 30 kHz.

Applies to IN_D+ as well as
IN_D- pins (50 Ω ± 20%
tolerance)

Intended to limit power-up
stress on chipset’s PCIE
output buffers

Differential inputs must be in
a high impedance state

360 ps

0.175 1.2 V

0.8 Tbit

100 mV

40 50 60 Ω

02V

100 KΩ

o

C

15/26

Maximum ratings STHDLS101T

5.2 TMDS outputs (OUT_D signals)

The level shifter’s TMDS outputs are required to meet the HDMI 1.3 specifications. The
HDMI 1.3 specification is assumed to be the correct reference in instances where this
document conflicts with the HDMI 1.3 specification.

Table 9. Differential output characteristics for TMDS OUT_D signals

Symbol Parameter Comments Min Typ Max Unit

is the DC termination

AV

V

V

V

SWING

I

OFF

T

T

T

SKEW-

INTRA

Single-ended high

H

level output voltage

Single-ended low level

L

output voltage

Single-ended output
swing voltage

Single-ended current
in high-Z state

Rise time

R

Fall time

F

Intra-pair differential
skew

CC

voltage in the HDMI or DVI
sink. AV

is nominally 3.3 V

CC

The open-drain output pulls
down form AV

CC

Swing down from TMDS
termination voltage
(3.3 V ±10%)

Measured with TMDS outputs
pulled up to AV

max (3.6 V)

CC

through 50 Ω resistors

Maximum rise/fall time at

2.7 Gbps = 148ps. 125ps =
148 – 15%

Maximum rise/fall time at

2.7 Gbps = 148 ps.
125ps = 148 – 15%

This differential skew budget
is in addition to the skew
presented between D+ and D­paired input pins.

AVCC-10 mV AV

AVCC-

600 mV

AVCC-

500 mV

CC

AVCC+10 m

V

AVCC-

400 mV

400 mV 500 mV 600 mV V

10 µA

125 ps 0.4 Tbit ps

125 ps 0.4 Tbit ps

10 ps

V

V

T

SKEW-

INTER

T

16/26

Inter-pair lane to lane
output skew

Jitter added to TMDS

JIT

signals

This lane to lane skew budget
is in addition to the skew
between differential input
pairs.

Jitter budget for TMDS
signals as they pass through
the level shifter.

7.4 ps = 0.02 Tbit at 2.7 Gbps

250 ps

7.4 ps

STHDLS101T Maximum ratings

5.3 HPD input and output characteristics

Table 10. HPD_SINK input and HPS_SOURCE output

Symbol Parameter Comment Min Typ Max Unit

V

IH-HPD_SINK

V

IL-HPD_SINK

I

IN-HPD_SINK

V

OH-

HPD_SOURCE

(INV)

V

OL-

HPD_SOURCE

V

OH-

HPD_SOURCE

(INV)

V

OL-

HPD_SOURCE

T

HPD

T

RF-HPD

HPD_SINK input high level

Low speed input changes
state on cable plug/unplug

25.05.3V

HPD_SINK input low level 0 0.8 V

Measured with HPD_SINK

HPD_SINK input leakage current

HPD_SOURCE output high level
when FUNCTION3 = L

at V

HPD

V

CC

max and V

IH-HPD

min

= 3.3 V ±10%

IL-

Based on external pull-up
resistor;

50 µA

output is open drain.

HPD_SOURCE output low level
when FUNCTION3 = H

HPD_SOURCE output high level
when FUNCTION3 = L

HPD_SOURCE output low level
when FUNCTION3 = H

= 3.3 V ±10% 2.5 V

V

CC

= 3.3 V ±10%

V

CC

=1mA

I

OL

= 3.3 V ±10% 0 0.2 V

V

CC

00.2V

CC

Time from HPD_SINK
changing state to

HPD_SINK to HPD_SOURCE
propagation delay

HPD_SOURCE changing
state. Includes
HPD_SOURCE rise/fall

200 ns

time

=10 pF

C

L

Time required to transition

HPD_SOURCE rise/fall time

from V

OH-HPD_SOURCE

V

OL-HPD_SOURCE

V

OL-HPD_SOURCE

HPD_SOURCE

to
or from
to V

OH-

120ns

CL=10 pF

V

17/26

Maximum ratings STHDLS101T

5.4 DDC input and output chatacteristics

Table 11. SDA_SOURCE, SCL_SOURCE and SDA_SINK, SCL_SINK characteristics

Symb

ol

V

I

Parameter Comment Min Typ Max Unit

Input voltage on SDA_SINK, SCL_SINK pins

Voltage on the DDC pins on
connector end

05.5V

VCC=3.3V

=0.1VDD to 0.9 VDD to

V

I

Input leakage current on SDA_SINK, SCL_SINK

I

LKG

pins

isolated DDC inputs

= external pull-up

V

DD

resistor voltage on

-10 10 µA

SDA_SINK and SCL_SINK
inputs (maximum of 5.5 V)

=0.0V

V

CC

= 0.1 VDD to 0.9 VDD to

V

I

DDC sink inputs

= external pull-up

V

Power-down leakage current on SDA_SINK,

I

OFF

SCL_SINK pins

DD

resistor voltage on
SDA_SINK and SCL_SINK

-10 10 µA

inputs (maximum of 5.5 V)
SDA_SOURCE,

SCL_SOURCE = 0.0 V

=1 V, 100 KHz

Input/output capacitance

C

I/O

(switch off)

Input/output capacitance

C

I/O

(switch on)

R

Switch resistance

ON

V

I(pp)

=3.3 V, T=25C

V

CC

=1 V, 100KHz

V

I(pp)

= 3.3 V, T= 25 ° C

V

CC

I

=3 mA, VO=0.4V

O

=3.3V

V

CC

5pF

27 40 Ω

Time from DDC_SINK
changing state to
DDC_SOURCE changing

DDC_SINK to DDC_SOURCE propagation delay

T

PD

state while the pass gate is
enabled.

=10 pF

C

L

=1.5 K (min), 2.0 K

R

PU

815ns

(max)

10 pF

T

SX

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Switch time from DDC_EN to the valid state on
DDC_SOURCE

CL=10pF
RPU= 1.5 K (min), 2.0 K

(max)

815ns

STHDLS101T Maximum ratings

5.5 OE_ input characteristics

Table 12. OE_N input characteristics

Symbol Parameter Comment Min Typ Max Unit

V

IH-OE_N

V

IL-OE_N

I

IN-OE_N

Input high level 2 VCC33 V

Input low level 0 0.8 V

Measured with OE_N at

Input leakage current

VIH-OE_N max and VIL­OE_N mix

200 µA

5.6 HPD input resistor

Table 13. HDP input resistor

Symbol Parameter Comment Min Typ Max Unit

Guarantees HPD_SINK is

R

HPD

HPD_SINK input pull-down resistor

LOW when no display is
plugged in

130 K 160 K 190 K Ω

5.7 ESD performance

Table 14. ESD performance

Symbol Parameter Test condition Min Typ Max Unit

ESD MIL STD 883 method 3015 (all pins) Human Body Model (HBM) -6 +6 kV

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Application information STHDLS101T

6 Application information

6.1 Power supply sequencing

Proper power-supply sequencing is advised for all CMOS devices. It is
recommended to always apply V
or control pins.

6.2 Supply bypassing

Bypass each of the VCC pins with 0.1 µF and 1nF capacitors in parallel as close to the
device as possible, with the smaller-valued capacitor as close to the V
as possible.

6.3 Differential traces

The high-speed inputs and TMDS outputs are the most critical parts for the device. There
are several considerations to minimize discontinuities on these transmission lines between
the connectors and the device.

before applying any signals to the input/output

CC

pin of the device

CC

(a) Maintain 100 Ω differential transmission line impedance into and out of the device.
(b) Keep an uninterrupted ground plane below the high-speed I/Os.
(c) Keep the ground-path vias to the device as close as possible to allow the shortest return

current path.
(d) Layout of the TMDS differential outputs should be with the shortest stubs from the

connectors.
Output trace characteristics affect the performance of the STHDLS101T. Use controlled

impedance traces to match trace impedance to both the transmission medium impedance
and termination resistor. Run the differential traces close together to minimize the effects of
the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities
in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to
further prevent impedance discontinuities.

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STHDLS101T Package mechanical data

7 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.

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Package mechanical data STHDLS101T

Figure 6. QFN-48 (7 x 7 mm) package outline

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STHDLS101T Package mechanical data

Table 15. QFN-48 (7 x 7 mm) package mechanical data

Symbol Min Typ Max Min Typ Max

A 0.80 0.90 1.00 0.80 0.85 1.00

A1 0.02 0.05 0.01 0.05

A2 0.65 1.00 0.65

A3 0.25 0.20

b 0.18 0.23 0.30 0.18 0.23 0.30

D 6.85 7.00 7.15 6.90 7.00 7.10

D2 2.25 4.70 5.25 SEE EXPOSED PAD VARIATIONS

E 6.85 7.00 7.15 6.90 7.00 7.10

E2 2.25 4.70 5.25 SEE EXPOSED PAD VARIATIONS

e 0.45 0.50 0.55 0.45 0.50 0.55

L 0.30 0.40 0.50 0.30 0.40 0.50

ddd 0.08 0.08

Figure 7. QFN-48 tape and reel information

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Package mechanical data STHDLS101T

Figure 8. Reel information

Table 16. Reel mechanical data (dimensions in mm)

ACNT

330.2 13

±0.25 100 16.4

0084694_J

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STHDLS101T Revision history

8 Revision history

Table 17. Document revision history

Date Revision Changes

30-Jun-2008 1 Initial release.

Document status promoted from preliminary data to datasheet.

24-Sep-2008 2

01-Dec-2008 3

Modified: features section, Table 2: Pin description on page 8 and

Section 4: Functional description.

Updated: Features section andChapter 5: Maximum ratings
Added: Figure 3: Cable adapter on page 5 , Figure 4: DP to

HDMI/DVI cable adapter on page 6, Figure 8: Reel information on
page 24 and Table 16: Reel mechanical data (dimensions in mm) on
page 24

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STHDLS101T

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