Page 1
®
SP6203/6205
Low Noise, 300mA and 500mA CMOS LDO Regulators
FEATURES
■ Very Low Dropout Voltage: 0.6Ω PMOS Pass
Device
■ Accurate Output Voltage: 2% over Temperature
■ Guaranteed 500mA Output Current: SP6205
■ Ultra Low Noise Output: 12µV
with 10nF
RMS
Bypass
■ Unconditionally Stable with 2.2µF Ceramic
■ Low Quiescent Current: 45µA
■ Very Low Ground Current: 350µA at 500 mA
■ Power-Saving Shutdown Mode: < 1µA
■ Fast Turn-On and Turn-Off: 60us
■ Fast Transient Response
■ Current Limit and Thermal Shutdown Protection
■ Very Good Load/Line Regulation: 0.07/0.04%
■ Excellent PSRR: 67dB<1kHz
■ Industry Standard 5 pin SOT-23 and Small 8
pin DFN Package
■ Fixed Output Voltages: 2.5V, 2.7V, 2.8V,
2.85V, 3.0V and 3.3V
■ Adjustable Output Available
V
OUTSENSE
BYP
GND
EN
■ Cellular / GSM Phones
■ Laptop / Palmtop Computers
■ Battery-Powered Systems
■ Pagers
■ Medical Devices
■ MP3/CD Players
■ Digital Still Cameras
Fixed
V
1
SP6203
2
SP6205
3
8 Pin DFN
4
8
OUT
ADJ
1
7
NC
NC
6
GND
5
V
IN
NC
EN
SP6203
2
SP6205
3
4
Now Available in Lead Free Packaging
APPLICATIONS
Adjustable
8 Pin DFN
V
8
OUT
7
NC
NC
6
5
V
IN
DESCRIPTION
The SP6203/6205 are ultra low noise CMOS LDOs with very low dropout and ground current. The noise
performance is achieved by means of an external bypass capacitor without sacrificing turn-on and turn-off
speed critical to portable applications. Extremely stable and easy to use, these devices offer excellent PSRR
and Line/Load regulation. Target applications include battery-powered equipment such as portable and
wireless products. Regulators' ground current increases only slightly in dropout. Fast turn-on/turn-off enable
control and an internal 30Ω pull down on output allows quick discharge of output even under no load
conditions. Both LDOs are protected with current limit and thermal shutdown.
Both LDO's are availiable in fixed & adjustable output voltage versions and come in an industry standard
5 pin SOT-23 and small 8 pin DFN package. For SC-70 100mA CMOS LDO, SP6213 is available.
TYPICAL APPLICATION CIRCUIT
C
IN
2.2µF
V
IN
1
SP6203
2
5
V
OUT
C
OUT
2.2µF Ceramic
SP6205
EN
ADJUSTABLE
5-Pin
3
ADJ
4
V
C
IN
2.2µF
IN
1
SP6203
2
5
V
OUT
C
OUT
2.2µF Ceramic
SP6205
5-Pin
3
EN
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
FIXED
4
BYP
1
Page 2
ABSOLUTE MAXIMUM RATINGS
OPERATING RATINGS
Supply Input Voltage (VIN) ...................................................... -2V to 6V
Output Voltage (V
Enable Input Voltage (V
Power Dissipation (PD) ................................... Internally Limited, Note 1
Lead Temperature (soldering 5s) .............................................. +260°C
Storage Temperature .................................................. -65°C to +150°C
Junction Temperature ............................................................... +150°C
These are stress ratings only and functional operation of the device at these
ratings or any other above those indicated in the operation sections of the
specifications below is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
) ................................................. -0.6V to VIN +1V
OUT
)..................................................... -2V to 6V
EN
Input Voltage (VIN) ......................................................... +2.7V to +5.5V
Enable Input Voltage (VEN) ...................................................... 0 to 5.5V
Junction Temperature (T
Thermal Resistance, SOT-23-5 (θ
Thermal Resistance, 8 Pin DFN (θJA) .......................................... Note 1
Remark: The device is not guaranteed to function outside its operating rating.
)........................................... -40°C to +125°C
J
) ........................................... Note 1
JA
ELECTRICALCHARACTERISTICS
Unless otherwise specified: VIN=V
-40°C < T < 125°C. The ♦ denotes the specifications which apply over full operating temperature range -40°C to
+125°C, unless otherwise specified.
PARAMETER MIN TYP MAX UNITS ♦ CONDITIONS
Input Voltage 6 V ♦
Output Voltage Accuracy -2 +2 % ♦ Variation from specified V
Output Voltage 50 ppm/°C ∆V
Temperature Coefficient, Note2
Reference Voltage 1.225 1.25 1.275 V ♦ Adjustable version only
Line Regulation 0.04 0.3 %/V ∆V
Load Regulation, Note 3 0.07 0.3 % I
Dropout Voltage, Note 4 0.06 I
(For V
≥ 3.0V) 60 I
OUT
Ground Pin Current, Note 5 45 100 ♦ I
Shutdown Supply Current 0.01 1 µA ♦ VEN < 0.4V (shutdown)
Current Limit 0.33 0.50 0.8 A V
Thermal Shutdown Junction 170 °C Regulator Turns off
Temperature
Thermal Shutdown Hysteresis 12 °C Regulator turns on again at 158°C
Power Supply Rejection Ratio 67 dB f ≤ 1kHz
Output Noise Voltage, Note 6 150 C
Thermal Regulation, Note 7 0.05 %/W ∆V
Wake-Up Time (TWU), Note 8 25 50 µsV
(from shutdown mode) I
Turn-On Time (TON), Note 9 60 120 µsV
(from shutdown mode) I
Turn-Off Time (T
), 100 250 µsI
OFF
Output Discharge Resistance 30 Ω No Load
Enable Input Logic Low Voltage 0.4 V ♦ Regulator Shutdown
Enable Input Logic High Voltage 1.6 V ♦ Regulator Enabled
+ 0.5V to 6V, C
OUT
= 2.2µF ceramic, CIN = 2.2µF, I
OUT
0.13 0.5 I
120 mV I
180 300 ♦ I
300 500 ♦ I
110 I
175 µAI
235 330 ♦ I
350 490 ♦ I
0.55 0.85 1.4 V
630 C
12 µV
50 75 C
RMS
15 25 I
=100µA,
OUT
OUT
/∆T
OUT
(VIN below 6V)
OUT
= 0.1mA to 300mA (SP6203)
OUT
= 0.1mA to 500mA (SP6205)
OUT
= 0.1mA
OUT
= 100mA
OUT
= 200mA
OUT
= 300mA (SP6203)
OUT
= 500mA (SP6205)
OUT
= 0.1mA (I
OUT
= 100mA
OUT
= 200mA
OUT
= 300mA (SP6203)
OUT
= 500mA (SP6205)
OUT
= 0V (SP6203)
OUT
= 0V (SP6205)
OUT
= 0nF, I
BYP
BYP
C
BYP
BYP
OUT
IN
OUT
≥ 4V, Note 10
IN
OUT
OUT
OUT
OUT
= 0nF, I
OUT
= 10nF, I
OUT
= 10nF, I
OUT
/∆P
D
≥ 4V, Note 10
= 30mA
= 30mA
= 0.1mA, VIN ≥ 4V, Note 10
= 300mA, VIN ≥ 4V, Note 10
QUIESCENT
= 0.1mA
=300mA
= 0.1mA
= 300mA
)
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
2
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ELECTRICAL CHARACTERISTIC NOTES
Note 1: Maximum power dissipation can be calculated using the formula: PD = (T
the junction temperature, TA is the ambient temperature and θJA is the junction-to-ambient thermal resistance. θ
J(max)
is 6ºC/W for this package. Exceeding the maximum allowable power dissipation will result in excessive die
temperature and thermal shutdown protection. For 5 Pin SOT-23 θJA is 191°C/W and 59°C/W for the 8 Pin DFN. A
part mounted on a PC board will deliver improved thermal perfformance based on copper surface area.
Note 2: Output voltage temperature coefficient is defined as the worst case voltage change divided by the total
temperature range.
Note 3: Regulation is measured at constant junction temperature using low duty cycle pulse testing. Changes in
output voltage due to heating effects are covered by the thermal regulation specification.
Note 4: Dropout-voltage is defined as the input to output differential at which the output voltage drops 2% below its
nominal value measured at 1V differential.
Note 5: Ground pin current is the regulator quiescent current. The total current drawn from the supply is the sum of
the load current plus the ground pin current.
Note 6: Output noise voltage is defined within a certain bandwidth, namely 10Hz < BW < 100kHz. An external
bypass cap (10nF) from reference output (BYP pin) to ground significantly reduces noise at output.
Note 7: Thermal regulation is defined as the change in output voltage at a time “t” after a change in power
dissipation is applied, excluding load and line regulation effects.
Specifications are for a 300mA load pulse at VIN = 6V for t = 1ms.
Note 8: The wake-up time (TWU) is defined as the time it takes for the output to start rising after enable is brought
high.
Note 9: The total turn-on time is called the settling time (TS), which is defined as the condition when both the
output and the bypass node are within 2% of their fully enabled values when released from shutdown.
Note 10: For output voltage versions requiring VIN to be lower than 4V, timing (TON & T
θθ
- TA) /
θ
, where T
θθ
JA
) increases slightly.
OFF
J(max)
is
JC
FUNCTIONAL DIAGRAM
V
V
IN
EN
bandgap
reference
1.25V
current limit
&
thermal shutdown
GND
OUT
BYP
Cbyp
(optional)
V
IN
EN
bandgap
reference
1.25V
current limit
&
thermal shutdown
GND
V
R1
ADJ
R2
OUT
Low Noise Fixed Regulator - 5 Pin Low Noise Adjustable Regulator - 5 Pin
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
3
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PIN DESCRIPTION
5 PIN OPTION
PIN NUMBER NAME FUNCTION
1VINPower Supply Input
2 GND Ground Terminal
3ENEnable/Shutdown (Logic high = enable, logic
low = shutdown)
4 (Fixed) BYP Reference bypass input for ultra-quiet operation.
Connecting a 10nF cap on this pin reduces
output noise.
4 (adj.) ADJ Adjustable (Input): Adjustable regulator feed-
back input. Connect to a resistive voltagedivider network.
5V
EN
3
GND
2
OUT
V
IN
1
SIPEX
4
BYP
Fixed Voltage Regulator Adjustable Voltage Regulator
V
5
OUT
Regulator Output Voltage
3
SIPEX
4
ADJ
PINOUTS
GNDEN
V
IN
12
5
V
OUT
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
4
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V
OUT
IO (200mA/DIV)
TYPICAL PERFORMANCE CHARACTERISTICS
V
OUT
V
EN
Current Limit
V
OUT
Turn off Time, R
(AC)
V
OUT
V
EN
= 6Ω (500mA)
LOAD
Turn on Time, R
Turn off Time, R
= 50Ω (60mA)
LOAD
V
OUT
V
EN
= 30K (0.1mA)
LOAD
V
(AC)
OUT
V
IN
I
OUT
Load Regulation, IO = 100µA ~ 500mA
Line Regulation, Line Step from 4V to 6V, IO = 1mA
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
5
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TYPICAL PERFORMANCE CHARACTERISTICS: Continued
V
IN
V
EN
V
OUT
V
OUT
V
= 3.5V, IO = 500mA
IN
BYP
Start Up Waveform, V
V
IN
V
OUT
BYP
= 3.5V, IO = 500mA Start Up Waveform, Slow V
IN
Start Up Waveform, Slow V
V
IN
V
OUT
, 500mA Output Load
IN
V
IN
V
OUT
BYP
Start Up Waveform, Slow V
V
IN
V
OUT
, No Load
IN
, C
=1000µF, IO=0mA
IN
OUT
BYP
Start Up Waveform, Slow VIN, C
=1000µF, IO=500mA
OUT
BYP
Fast VIN , No Load
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
6
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TYPICAL PERFORMANCE CHARACTERISTICS: Continued
V
IN
V
OUT
BYP
Fast VIN , 500mA Output Load
V
IN
V
OUT
BYP
Fast V
, C
=1000µF, IO=500mA
IN
OUT
Fast VIN = 1000µF Output Load
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
7
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THEORY OF OPERATION
General Overview
The SP6203/6205 is intended for applications
where very low dropout voltage, low supply
current and low output noise are critical, even
with high load conditions (500mA maximum).
Unlike bipolar regulators, the SP6203/6205
(CMOS LDO) supply current increases only
slightly with load current.
The SP6203/6205 contains an internal bandgap
reference which is fed into the inverting input of
the LDO-amplifier. The output voltage is then
set by means of a resistor divider and compared
to the bandgap reference voltage. The error
LDO-amplifier drives the gate of a P-channel
MOSFET pass device that has a R
DS(ON)
of 0.6Ω
at 500mA producing a 300mV drop at the output.
Furthermore, the SP6203/6205 has its own current limit circuitry (500mA/850mA) to ensure
that the output current will not damage the
device during output short, overload or start-up.
Also, the SP6203/6205 includes thermal shutdown circuitry to turn off the device when the
junction temperature exceeds 170°C and it remains off until the temperature drops by 12°C.
Enable/Shutdown Operation
The SP6203/6205 is turned off by pulling the
VEN pin below 0.4V and turned on by pulling it
above 1.6V.
If this enable/shutdown feature is not required,
it should be tied directly to the input supply
voltage to keep the regulator output on at all
time.
While in shutdown, V
quickly falls to zero
OUT
(turn-off time is dependent on load conditions
and output capacitance on V
) and power
OUT
consumption drops nearly to zero.
Input Capacitor
A small capacitor of 2.2µF is required from V
to GND if a battery is used as the power
source. Any good quality electrolytic, ceramic
or tantalum capacitor may be used at the input.
Output Capacitor
An output capacitor is required between V
OUT
and GND to prevent oscillation. A 2.2µF output
capacitor is recommended.
Larger values make the chip more stable which
means an improvement of the regulator’s transient response. Also, when operating from other
sources than batteries, supply-noise rejection
can be improved by increasing the value of the
input and output capacitors and using passive
filtering techniques.
For a lower output current, a smaller output
capacitance can be chosen.
Finally, the output capacitor should have an
effective series resistance (ESR) of 0.5Ω or less.
Therefore, the use of good quality ceramic or
tantalum capacitors is advised.
Bypass Capacitor
A bypass pin (BYP) is provided to decouple the
bandgap reference. A 10nF external capacitor
connected from BYP to GND reduces noise
present on the internal reference, which in turn
significantly reduces output noise and also improves power supply rejection. Note that the
minimum value of C
must be increased to
OUT
maintain stability when the bypass capacitor is
used because C
reduces the regulator phase
BYP
margin. If output noise is not a concern, this
input may be left unconnected. Larger capacitor
values may be used to further improve power
supply rejection, but result in a longer time
period (slower turn on) to settle output voltage
when power is initially applied.
No Load Stability
The SP6203/6205 will remain stable and in
regulation with no external load (other than the
internal voltage driver) unlike many other voltage regulators. This is especially important in
IN
CMOS RAM battery back-up applications.
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
8
Page 9
THEORY OF OPERATION: Continued
Turn On Time
The turn on response is split up in two separate
response categories: the wake up time (T
and the settlling time (T
). The wake up time is
S
WU
defined as the time it takes for the output to rise
to 2% of its total value after being released from
shutdown (EN > 0.4V). The settling time is
defined as the condition where the output reaches
98% of its total value after being released from
shutdown. The latter is also called the turn on
time and is dependent on the output capacitor, a
little bit on load and, if present, on a bypass
capacitor.
V
ENABLE
V
OUT
Turn Off Time
2%
t(s) = T(on)
98%
t(wu)
The turn off time is defined as the condition
where the output voltage drops about 66% (θ) of
its total value. 5θ to 7θ is the constant where the
output voltage drops nearly to zero. There will
always be a small voltage drop in shutdown
because of the switch unless we short-circuit it.
The turn off time of the output voltage is dependent on load conditions, output capacitance on
V
(time constant τ = RLCL) and also on the
OUT
difference in voltage between input and output.
Thermal Considerations
T
is the maximum junction temperature of
J(max)
the die and is 125°C. T
ture. θJA is the junction-to-ambient thermal re-
)
sistance for the regulator and is layout depen-
is the ambient tempera-
A
dent. The SOT-23-5 package has a θJA of
approximately 191°C/W for minimum PCB copper footprint area.
This results in a maximum power dissipation of:
P
= [(125°C - 25°C)/(256°C/W)] = 390mW
D(max)
The actual power dissipation of the regulator
circuit can be determined using one simple
equation:
PD = (VIN - V
OUT
) * I
OUT
+ V
IN
* I
To prevent the device from entering thermal
shutdown. maximum power dissipation can not
be exceeded.
Substituting P
for PD and solving for the
D(max)
operating conditions that are critical to the application will give the maximum operating conditions for the regulator circuit. For example, if
we are operating the SP6203 3.0V at room
temperature, with a minimum footprint layout
and and output current of 300mA, the maximum
input voltage can be determined, based on the
equation below. Ground pin current can be taken
from the electrical specifications table (0.23mA
at 300mA).
390mW = (VIN-3.0V) * 300mA + VIN *0.23mA
After calculations, we find that the maximum
input voltage of a 3.0V application at 300mA of
output current in a SOT-23-5 package is 4.3V.
GND
The SP6203/6205 is designed to provide 300/
500 mA of continuous current in a tiny package.
Maximum power dissipation can be calculated
based on the output current and the voltage drop
across the part. To determine the maximum
So if the intend is to operate a 5V output version
from a 6V supply at 300mA load and at a 25°C
ambient temperature, then the actual total power
dissipation will be:
power dissipation of the package, use the junction-to-ambient thermal resistance of the device
and the following basic equation:
PD = (T
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
J(max)
- TA) / θJ
A
PD=([6V-5V]*[300mA])+(6V*0.23mA)=301.4 mW
This is well below the 390mW package maxi-
mum. Therefore, the regulator can be used.
9
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THEORY OF OPERATION: Continued
Note that the regulator cannot always be used at
its maximum current rating. For example, in a
5V input to 3.0V output application at an ambient temperature of 25°C and operating at the full
500mA (I
= 0.355mA) load, the regulator is
GND
limited to a much lower load current, determined by the following equation:
390mW = ( [5V-3V]*[ I
]) +(5V*0.355mA)
load(max)
After calculation, we find that in such an application (SP6205) the regulator is limited to
194.1mA. Doing the same calculations for the
300mA LDO (SP6203) will limit the regulator’s
output current to 194.4mA.
Also, taking advantage of the very low dropout
voltage characteristics of the SP6203/6205,
power dissipation can be reduced by using the
lowest possible input voltage to minimize the
input-to-output drop.
Adjustable Regulator Applications
The SP6203/6205 can be adjusted to a specific
output voltage by using two external resistors
(see functional diagram). The resistors set the
output voltage based on the following equation:
Layout Considerations
The primary path of heat conduction out of the
package is via the package leads. Therefore,
careful considerations have to be taken into
account:
1) Attaching the part to a larger copper footprint
will enable better heat transfer from the device,
especially on PCB’s where there are internal
ground and power planes.
2) Place the input, output and bypass capacitors
close to the device for optimal transient response and device behavior.
3) Connect all ground connections directly to
the ground plane. In case there’s no ground
plane, connect to a common local ground point
before connecting to board ground.
Such layouts will provide a much better thermal
conductivity (lower θ
) for, a higher maximum
JA
allowable power dissipation limit.
V
OUT
= V
*(R1/R2 + 1)
REF
Resistor values are not critical because ADJ
(adjust) has a high input impedance, but for best
performance use resistors of 470KΩ or less. A
bypass capacitor from ADJ to V
provides
OUT
improved noise performance.
Dual-Supply Operation
When used in dual supply systems where the
regulator load is returned to a negative supply,
the output voltage must be diode clamped to
ground.
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
10
Page 11
PACKAGE: 5 PIN SOT-23
D
e1
E1
N
E1/2
1
e
5 PIN SOT-23
JEDEC MO-178
(AA) Variation
A
A1
A2
b
c
D
E
E1
e
e1
L
L1
L2
Ø
Ø1
N/2
+1
N/22
b
Dimensions in (mm)
MIN NOM MAX
- - 1.45
0 - 0.15
0.90 1.15 1.30
0.30 - 0.50
0.08 - 0.22
2.90 BSC
2.80 BSC
1.60 BSC
0.95 BSC
1.90 BSC
0.30 0.45 0.60
0.60 REF
0.25 BSC
0º 4º 8º
5º 10º 15º
E/2
E
B
Seating Plane
Ø1
Ø1
SEE VIEW C
VIEW A-A
L1
Gauge Plane
L2
L
Ø
VIEW C
B
A
WITH PLATING
A2
A1
c
BASE METAL
Seating Plane
SIDE VIEW
b
SECTION B-B
5 PIN SOT-23
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
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Page 12
PACKAGE: 8 PIN DFN
Top View
D
D/2
E/2
Pin 1 identifier to be located within this shaded area.
Terminal #1 Index Area (D/2 * E/2)
Side View
A
A1
A3
Bottom View
D2
12
E
K
L
e
2x3 8 Pin DFN
JEDEC mo-229C
(VCED-2) Variation
Symbol
A
A1
A3
b
D
D2
e
E
E2
K
L
b
Dimensions in (mm)
MIN
0.80 0.90 1.00
0.18 0.25 0.30
1.50
1.60 1.90
0.20
0.30
E2
NOM MAX
0 0.02 0.05
0.20
-
2.00 BSC
--
0.50
3.00 BSC
0.40
-
-
1.75
-
-
-
0.50
2x3 8 Pin DFN
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
12
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ORDERING INFORMATION
Part Number Top Mark Temperature Range Package Type
SP6203EM5-2.5..................... L2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.5/TR ............... L2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.7..................... G2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.7/TR ............... G2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.8..................... Q3WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.8/TR ............... Q3WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.85................... H2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-2.85/TR ............. H2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-3.0..................... M2WW .....................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-3.0/TR ............... M2WW .....................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-3.3......................J2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-3.3/TR ................J2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-ADJ ................... Q2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203EM5-ADJ/TR ............. Q2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6203ER-2.5 .................. 620325YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.5/TR ............ 620325YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.7 .................. 620327YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.7/TR ............ 620327YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.8 .................. 620328YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.8/TR ............ 620328YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.85 ................ 620385YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-2.85/TR .......... 620385YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-3.0 .................. 620330YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-3.0/TR ............ 620330YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-3.3 .................. 620333YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-3.3/TR ............ 620333YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-ADJ ................ 6203ERYWW ................-40˚C to +125˚C......................... 8 Pin DFN
SP6203ER-ADJ/TR ..........6203ERYWW ................-40˚C to +125˚C ......................... 8 Pin DFN
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6205ER-ADJ/TR = standard; SP6205ER-L-ADJ/TR = lead free
/TR = Tape and Reel
Pack quantity is 2,500 for SOT-23 and 3,000 for DFN.
Corporation
ANALOG EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
13
Page 14
ORDERING INFORMATION
Part Number Top Mark Temperature Range Package Type
SP6205EM5-2.5..................... V2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.5/TR ............... V2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.7..................... R2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.7/TR ............... R2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.8..................... E3WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.8/TR ............... E3WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.85................... S2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-2.85/TR ............. S2WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-3.0.....................W2WW .....................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-3.0/TR ............... W2WW .....................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-3.3..................... T2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-3.3/TR ............... T2WW ......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-ADJ ................... A3WW......................-40˚C to +125˚C.................... 5 Pin SOT-23
SP6205EM5-ADJ/TR ............. A3WW ...................... -40˚C to +125˚C .................... 5 Pin SOT-23
SP6205ER-2.5 .................. 620525YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.5/TR ............ 620525YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.7 .................. 620527YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.7/TR ............ 620527YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.8 .................. 620528YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.8/TR ............ 620528YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.85 ................ 620585YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-2.85/TR .......... 620585YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-3.0 .................. 620530YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-3.0/TR ............ 620530YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-3.3 .................. 620533YWW .................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-3.3/TR ............ 620533YWW.................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-ADJ ................ 6203ERYWW ................-40˚C to +125˚C......................... 8 Pin DFN
SP6205ER-ADJ/TR ..........6203ERYWW ................-40˚C to +125˚C ......................... 8 Pin DFN
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6205ER-ADJ/TR = standard; SP6205ER-L-ADJ/TR = lead free
/TR = Tape and Reel
Pack quantity is 2,500 for SOT-23 and 3,000 for DFN.
Corporation
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 05/25/04 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2004 Sipex Corporation
14
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