Datasheet SA8016 Datasheet (Philips)

INTEGRATED CIRCUITS

SA8016

2.5GHz low voltage fractional-N
synthesizer

Product specification
Supersedes data of 1999 Mar 08




1999 Apr 16

Philips Semiconductors Product specification

TYPE NUMBER

SA80162.5GHz low voltage fractional-N synthesizer

GENERAL DESCRIPTION

The SA8016 BICMOS device integrates programmable dividers,
charge pumps and a phase comparator to implement a
phase-locked loop. The device is designed to operate from 3 NiCd
cells, in pocket phones, with low current and nominal 3 V supplies.

The synthesizer operates at VCO input frequencies up to 2.5 GHz.
The synthesizer has fully programmable main and reference
dividers. All divider ratios are supplied via a 3-wire serial
programming bus.

Separate power and ground pins are provided to the analog and
digital circuits. The ground leads should be externally short-circuited
to prevent large currents flowing across the die and thus causing
damage. V

must be greater than or equal to V

DDCP

DD

.

The charge pump current (gain) is set by an external resistance at
the RSET

pin. Only passive loop filters could be used; the charge

pump operates within a wide voltage compliance range to provide a
wider tuning range.

1

LOCK

2

TEST

3

V

DD

4

GND

5

RFin+

6

RFin–

7

GND

CP

89

PHP

Figure 1. Pin Configuration

PON

16

STROBE

15
14

DATA

13

CLOCK

12

REFin+

11

REFin–

10

RSET
V

SR01505

DDCP

FEA TURES

•Low phase noise

•Low power

•Fully programmable main divider

•Internal fractional spurious compensation

APPLICATIONS

•350–2500 MHz wireless equipment

•Cellular phones (all standards)

•WLAN

•Portable battery-powered radio equipment.

•Hardware and software power down

•Split supply for V

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

V

DDCP

I

DDCP+IDD

I

DDCP+IDD

f

VCO

f

REF

f

PC

T

A

ORDERING INFORMATION

SA8016 TSSOP16 Plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403–1

and V

DD

DDCP

Supply voltage 2.7 – 5.5 V
Analog supply voltage V

DDCP

≥ V

DD

2.7 – 5.5 V
Supply current – 8.0 9.5 mA
Total supply current in power-down mode – 1 – µA
Input frequency 350 – 2500 MHz
Crystal reference input frequency 5 – 40 MHz
Maximum phase comparator frequency – 4 MHz
Operating ambient temperature –40 – +85 °C

PACKAGE
NAME DESCRIPTION VERSION

1999 Apr 16 853–2142 21267

2

Philips Semiconductors Product specification

SA80162.5GHz low voltage fractional-N synthesizer

GND

CLOCK

DATA

STROBE

13
14

15

2–BIT SHIFT

REGISTER

ADDRESS DECODER

LOAD SIGNALS

22–BIT SHIFT

REGISTER

CONTROL

LATCH

CURRENT

PUMP

SETTING

PUMP

BIAS

4

10

RSET

9

V

DDCP

RFin+
RFin–

REF
REF

TEST

5
6

AMP

12

in+
in–

11

2

MAIN DIVIDER

LATCH

REFERENCE

DIVIDER

Figure 2. Block Diagram

PINNING

SYMBOL PIN DESCRIPTION

LOCK 1 Lock detect output
TEST 2 Test (should be either grounded or

V

DD

GND 4 Digital ground
RFin+ 5 RF input to main divider
RFin– 6 RF input to main divider
GND

CP

PHP 8 Main normal charge pump
V

DDCP

RSET 10 External resistor from this pin to ground

REFin– 11 Reference input
REFin+ 12 Reference input
CLOCK 13 Programming bus clock input
DATA 14 Programming bus data input
STROBE 15 Programming bus enable input
PON 16 Power down control

connected to VDD)

3 Digital supply

7 Charge pump ground

9 Charge pump supply voltage

sets the charge pump current

LATCH

COMP

8

PHASE

DETECTOR

3

V

DD

PHP

7

GND

1

16

CP

LOCK

PON

SR01506

1999 Apr 16

3

Philips Semiconductors Product specification

SA80162.5GHz low voltage fractional-N synthesizer

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

V

DDCP

∆V

DDCP–VDD

V

n

V

1

∆V

GND

T

stg

T

amb

T

j

Digital supply voltage –0.3 +5.5 V
Analog supply voltage –0.3 +5.5 V
Difference in voltage between V

DDCP and

Voltage at pins 1, 2, 5, 6, 11 to 16 –0.3 V
Voltage at pin 8, 9 –0.3 V
Difference in voltage between GNDCP and GND (these pins should

VDD (V

≥ VDD) –0.3 +2.8 V

DDCP

+ 0.3 V

DD
DDCP

–0.3 +0.3 V

+ 0.3 V

be connected together)
Storage temperature –55 +125
Operating ambient temperature –40 +85
Maximum junction temperature 150

C
C
C

Handling

Inputs and outputs are protected against electrostatic discharge in
normal handling. However , to be totally safe, it is desirable to take
normal precautions appropriate to handling MOS devices.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j–a

Thermal resistance from junction to ambient in free air 120 K/W

1999 Apr 16

4

Philips Semiconductors Product specification

indicative, not tested

SA80162.5GHz low voltage fractional-N synthesizer

CHARACTERISTICS

= V

= +3.0V, T

DD

V

DDCP

SYMBOL

Supply; pins 3, 9

V

DD

V

DDCP

I

DDTotal

I

Standby

Digital supply voltage 2.7 – 5.5 V
Analog supply voltage V
Synthesizer operational digital supply current V
Total supply current in power-down mode logic levels 0 or V

RFin main divider input; pins 5, 6

f

VCO

V

RFin(rms)

Z

IRFin

C

IRFin

N

main

f

PCmax

VCO input frequency 350 – 2500 MHz
AC-coupled input signal level Rin (external) = Rs = 50Ω;

Input impedance (real part) f
Typical pin input capacitance f
Main divider ratio 512 – 65535
Maximum loop comparison frequency indicative, not tested – – 4 MHz

Reference divider input; pins 11, 12

f

REFin

Input frequency range from TCXO 5 – 40 MHz

VRFin AC-coupled input signal level single-ended drive;

Z

REFin

C

REFin

R

REF

Input impedance (real part) f
Typical pin input capacitance f
Reference division ratio 4 – 1023

Charge pump current setting resistor input; pin 10

R

SET

V

SET

External resistor from pin to ground 6 7.5 15 kΩ
Regulated voltage at pin R

Charge pump outputs (including fractional compensation pump); pin 8; R

I

CP

I

MATCH

I

ZOUT

I

LPH

V

PH

Phase noise (R

Charge pump current ratio to I
Sink-to-source current matching VPH=1/2 V
Output current variation versus V
Charge pump off leakage current VPH=1/2 V
Charge pump voltage compliance 0.7 – V

SET

Synthesizer’s contribution to close-in phase noise
of 800 MHz RF signal at 1 kHz offset.

C/N

Synthesizer’s contribution to close-in phase noise
of 1800 MHz RF signal at 1 kHz offset.

Synthesizer’s contribution to close-in phase noise
of 2100 MHz RF signal at 1 kHz offset.

Interface logic input signal levels; pins 13, 14, 15, 16

V
V
I

LEAK

IH
IL

HIGH level input voltage 0.7*V
LOW level input voltage –0.3 – 0.3*V
Input leakage current logic 1 or logic 0 –0.5 – +0.5 µA

= +25°C; unless otherwise specified.

A

PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1

SET

PH

= 7.5 kΩ, CP = 00)

= V

DDCP
DD

DD

= +3.0 V – 8.0 9.5 mA

DD

2.7 – 5.5 V

– 1 µA

–18 – 0 dBm
single-ended drive;
max. limit is indicative
@ 500 to 2500 MHz

= 2.4 GHz – 210 – Ω

VCO

= 2.4 GHz – 1.0 – pF

VCO

max. limit is indicative

360 – 1300 mV

= 20 MHz – 10 – kΩ

REF

= 20 MHz – 1.0 – pF

REF

=7.5 kΩ – 1.25 – V

SET

=7.5kΩ, FC=80

SET

Current gain IPH/I

2

V

in compliance range –10 +10 %

PH

SET

DDCP

CC

–15 +15 %

–10 +10 %

–10 +10 nA

–0.8 V

DDCP

PP

– –85 – dBc/Hz

f

= 19.44MHz, TCXO,

REF

f

COMP

= 240kHz

– –78 – dBc/Hz

– –77 – dBc/Hz

DD

– VDD+0.3 V

DD

V

1999 Apr 16

5

Philips Semiconductors Product specification

SA80162.5GHz low voltage fractional-N synthesizer

SYMBOL UNITMAX.TYP.MIN.CONDITIONSPARAMETER

Lock detect output signal (in push/pull mode); pin 1

V

OL

V

OH

LOW level output voltage I
HIGH level output voltage I

NOTES:

V

SET =

SET

bias current for charge pumps.

R

SET

1. I

2. The relative output current variation is defined as:
I

OUT

I

OUT

 2

.

I(I

(I2–I1)

; with V1 0.7V, V2 V

 I1)I

2

CURRENT

I

2

–0.8V (See Figure 3.)

DDCP

= 2mA – – 0.4 V

sink

= –2mA VDD–0.4 – – V

source

I

1

V

1

I

2

I

1

V

2

VOLTAGE

SR00602

Figure 3. Relative Output Current Variation

1999 Apr 16

6

Philips Semiconductors Product specification

SA80162.5GHz low voltage fractional-N synthesizer

FUNCTIONAL DESCRIPTION
Main Fractional-N divider

The RFin inputs drive a pre-amplifier to provide the clock to the first
divider stage. For single ended operation, the signal should be fed to
one of the inputs while the other one is AC grounded. The
pre-amplifier has a high input impedance, dominated by pin and pad
capacitance. The circuit operates with signal levels from –18dBm to
0dBm, and at frequencies as high as 2.5 GHz. The divider consists
of a fully programmable bipolar prescaler followed by a CMOS
counter. Total divide ratios range from 512 to 65536.

At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator. Also,
the fractional accumulator is incremented by the value of NF. The
accumulator works with modulo Q set by FMOD. When the
accumulator overflows, the overall division ratio N will be increased
by 1 to N + 1, the average division ratio over Q main divider cycles
(either 5 or 8) will be

Nfrac  N 

The output of the main divider will be modulated with a fractional
phase ripple. The phase ripple is proportional to the contents of the

REFERENCE
INPUT

NF
Q

DIVIDE BY R /2 /2 /2 /2

fractional accumulator and is nulled by the fractional compensation
charge pump.

The reloading of a new main divider ratio is synchronized to the
state of the main divider to avoid introducing a phase disturbance.

Reference divider

The reference divider consists of a divider with programmable
values between 4 and 1023 followed by a three bit binary counter.
The 3 bit SM (SA) register (see Figure 4) determines which of the 5
output pulses are selected as the main (auxiliary) phase detector
input.

Phase detector (see Figure 5)

The reference and main (aux) divider outputs are connected to a
phase/frequency detector that controls the charge pump. The pump
current is set by an external resistor in conjunction with control bits
CP0 and CP1 in the B-word (see Charge Pump table). The dead
zone (caused by finite time taken to switch the current sources on or
off) is cancelled by forcing the pumps ON for a minimum time at
every cycle (backlash time) providing improved linearity.

SM=”000”
SM=”001”

SM=”010”
SM=”011”

SM=”100”

TO

MAIN

PHASE

DETECTOR

SA=”100”

SA=”011”

SA=”010”
SA=”001”

SA=”000”

Figure 4. Reference Divider

TO

AUXILIARY

PHASE

DETECTOR

SR01415

1999 Apr 16

7

Philips Semiconductors Product specification

SA80162.5GHz low voltage fractional-N synthesizer

V

DDCP

f

REF

R

X

f

REF

REF DIVIDER

AUX/MAIN

DIVIDER

“1”

D

R

Q

CLK

R

P

τ

“1”

X

D

CLK

R

Q

N

GND

CHARGE PUMP

CHARGE PUMP

CP

P–TYPE

I

PH

N–TYPE

P

N

I

PH

SR01451

Figure 5. Phase Detector Structure with Timing

1999 Apr 16

8

Philips Semiconductors Product specification

SA80162.5GHz low voltage fractional-N synthesizer

Main Output Charge Pumps and Fractional
Compensation Currents (see Figure 6)

The main charge pumps on pins PHP and PHI are driven by the
main phase detector and the charge pump current values are
determined by the current at pin R

in conjunction with bits CP0,

SET

CP1 in the B-word (see table of charge pump ratios). The fractional
compensation is derived from the current at R

, the contents of

SET

the fractional accumulator FRD and by the program value of the
FDAC. The timing for the fractional compensation is derived from
the main divider. The main charge pumps will enter speed up mode
after the A-word is set and strobe goes High. When strobe goes
Low, charge pump will exit speed up mode.

Principle of Fractional Compensation

The fractional compensation is designed into the circuit as a means
of reducing or eliminating fractional spurs that are caused by the
fractional phase ripple of the main divider. If I
compensation current and I

is the pump current, then for each

PUMP

charge pump:

I

PUMP_TOTAL

= I

PUMP

+ I

COMP

COMP

is the

.

The compensation is done by sourcing a small current, I
Figure 7, that is proportional to the fractional error phase. For proper
fractional compensation, the area of the fractional compensation
current pulse must be equal to the area of the fractional charge
pump ripple. The width of the fractional compensation pulse is fixed
to 128 VCO cycles, the amplitude is proportional to the fractional
accumulator value and is adjusted by FDAC values (bits FC7–0 in
the B-word). The fractional compensation current is derived from the
main charge pump in that it follows all the current scaling through
external resistor setting, R

, programming or speed-up operation.

SET

For a given charge pump,

I

COMP

= ( I

/ 128 ) * ( FDAC / 5*128) * FRD

PUMP

FRD is the fractional accumulator value.
The target values for FDAC are: 128 for FMOD = 1 (modulo 5) and

80 for FMOD = 0 (modulo 8).

COMP

, see

REFERENCE R

MAIN M
DIVIDE RATIO

DETECTOR
OUTPUT

ACCUMULATOR

FRACTIONAL
COMPENSATION
CURRENT

OUTPUT ON
PUMP

NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output.

N N N+1 N N+1

241

PULSE
WIDTH
MODULATION

PULSE LEVEL
MODULATION

Figure 6. Waveforms for NF = 2 Modulo 5 → fraction = 2/

f

RF

1930.140 MHz

MAIN DIVIDER

N = 8042

FRACTIONAL

ACCUMULATOR

3

5

0

mA

µA

SR01416

1999 Apr 16

240.016 kHz I

I

f

REF

240 kHz

PUMP

Figure 7. Current Injection Concept

9

COMP

LOOP FILTER

& VCO

SR01682

Philips Semiconductors Product specification

SA80162.5GHz low voltage fractional-N synthesizer

Charge pump currents

CP0

I

PHP

I

PHP–SU

0 3xI
1 1xl

SET

SET

15xl

5xl

SET

SET

NOTES:

1. I

SET=VSET/RSET

2. I

PHP–SU

is the total current at pin PHP during speed up condition.

bias current for charge pumps.

Lock Detect

The output LOCK maintains a logic ‘1’ when the auxiliary phase
detector ANDed with the main phase detector indicates a lock
condition. The lock condition for the main and auxiliary synthesizers
is defined as a phase difference of less than 1 period of the
frequency at the input REFin+, –. One counter can fulfill the lock
condition when the other counter is powered down. Out of lock (logic
‘0’) is indicated when both counters are powered down.

Power-down mode

The power-down signal can be either hardware (PON) or software
(PD). The PON signal is exclusively ORed with the PD bits in
B-word. If PON = 0, then the part is powered up when PD = 1. PON
can be used to invert the polarity of the software bit PD. When the
synthesizer is reactivated after power-down, the main and reference
dividers are synchronized to avoid possibility of random phase
errors on power-up.

1999 Apr 16

10

Philips Semiconductors Product specification

SA80162.5GHz low voltage fractional-N synthesizer

Serial programming bus

The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 or 3 address bits. Figure 8
shows the timing diagram of the serial input. When the STROBE
goes active HIGH, the clock is disabled and the data in the shift
register remains unchanged. Depending on the address bits, the

Serial bus timing characteristics. See Figure 8.

V

= V

DD

SYMBOL

Serial programming clock; CLK

t

r

t

f

T

cy

Enable programming; STROBE

t

START

t

W

t

SU;E

Register serial input data; DATA

t

SU;DAT

t

HD;DAT

=+3.0V; TA = +25°C unless otherwise specified.

DDCP

PARAMETER MIN. TYP. MAX. UNIT

Input rise time – 10 40 ns
Input fall time – 10 40 ns
Clock period 100 – – ns

Delay to rising clock edge 40 – – ns
Minimum inactive pulse width 1/f
Enable set-up time to next clock edge 20 – – ns

Input data to clock set-up time 20 – – ns
Input data to clock hold time 20 – – ns

data is latched into different working registers or temporary
registers. In order to fully program the synthesizer, 2 words must be
sent: B, and A. Table 1 shows the format and the contents of each
word. The D word is normally used for testing purposes. When
sending the B-word, data bits FC7–0 for the fractional compensation
DAC are not loaded immediately. Instead they are stored in
temporary registers. Only when the A-word is loaded, these
temporary registers are loaded together with the main divider ratio.

COMP

– – ns

Application information

CLK

DATA

STROBE

t

SU;DAT

t

START

T

cy

MSB LSB ADDRESS

t

HD;DAT

t

r

Figure 8. Serial Bus Timing Diagram

t

f

t

SU;E

t

w

SR01417

1999 Apr 16

11

Philips Semiconductors Product specification

SA80162.5GHz low voltage fractional-N synthesizer

Data format
Table 1. Format of programmed data

LAST IN MSB SERIAL PROGRAMMING FORMAT FIRST IN LSB

p23 p22 p21 p20 ../.. ../.. p1 p0

Table 2. A word, length 24 bits

LAST IN MSB LSB FIRST IN
Address fmod Fractional-N Main Divider ratio Spare

0 0 FM NF2 NF1 NF0 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 SP1 SP2

Default:

A word select Fixed to 00.
Fractional Modulus select FM 0 = modulo 8, 1 = modulo 5.
Fractional-N Increment NF2..0 Fractional N Increment values 000 to 111.
N-Divider N0..N15, Main divider values 512 to 65535 allowed for divider ratio.

0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0

Table 3. B word, length 24 bits

Address REFERENCE DIVIDER

0 1 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 LO MAIN CP0 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 SP3

Default: 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0

B word select Fixed to 01
R-Divider R0..R9, Reference divider values 4 to 1023 allowed for divider ration.
Charge pump current

Ratio
Lock detect output L0

Power down Main = 1: power to main divider, reference divider, main charge pumps, Main = 0 to power down.
Fractional Compensation FC7..0 Fractional Compensation charge pump current DAC, values 0 to 255.

CP0: Charge pump current ratio, see table of charge pump currents.

0 Main lock detect signal present at the LOCK pin (push/pull).
1 Main lock detect signal present at the LOCK pin (open drain).
When main loop is in power down mode, the lock indicator is low.

LOCK

PD CP FRACTIONAL COMPENSATION DAC

Table 4. D word, length 24 bits

Address SYNTHESIZER TEST

BITS

1 1 0 – – – – – Tspu – – – – – – – – – – – – – – –

Default: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Tspu: Speed up = 1 Forces the main charge pumps in speed-up mode all the time.

NOTE: All test bits must be set to 0 for normal operation.

SYNTHESIZER TEST BITS

SPARE

1999 Apr 16

12

Philips Semiconductors Product specification

SA80162.5GHz low voltage fractional-N synthesizer

800
600
400
200

0

Icp (uA)

–200
–400
–600
–800

I

= 51.67 mA

SET

I

= 103.33 mA

SET

I

= 165.33 mA

SET

I

= 206.67 mA

SET

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3

COMPLIANCE VOLTAGE (V)

I
I
I

I

SET
SET
SET

SET

Figure 9. Php Charge Pump Output vs. I

(CP = 0, TEMP = 25C)

250
200
150
100

50

0

Icp (uA)

–50

I

= 51.67 mA

–100
–150
–200
–250

SET

I

= 103.33 mA

SET

I

= 165.33 mA

SET

I

= 206.67 mA

SET

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3

COMPLIANCE VOLTAGE (V)

= 206.67 mA
= 165.33 mA
= 103.33 mA

= 51.67 mA

SET

I

= 206.67 mA

SET

I

= 165.33 mA

SET

I

= 103.33 mA

SET

I

= 51.67 mA

SET

SR01911

SR01913

600

400

200

0

Icp (uA)
–200

–400

–600

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

COMPLIANCE VOLTAGE (V)

TEMP = 85C
TEMP = 25C
TEMP = –40C

Figure 10. Php Charge Pump Output vs. Temperature

(CP = 0; VDD = 3.0 V; I

200
150
100

50

0

Icp (uA)

–50
–100
–150
–200

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

COMPLIANCE VOLTAGE (V)

= 165.33 A)

SET

TEMP = 85C
TEMP = 25C
TEMP = –40C

SR01912

SR01914

Figure 11. Php Charge Pump Output vs. I

(CP = 1; TEMP = 25C)

3500

2500

1500

500

0

Icp (uA)

–500

–1500

–2500

–3500

I

= 51.67 mA

SET

I

= 103.33 mA

SET

I

= 165.33 mA

SET

I

= 206.67 mA

SET

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3

COMPLIANCE VOLTAGE (V)

Figure 13. Php–su Charge Pump Output vs. I

(CP = 0; TEMP = 25C)

1999 Apr 16

I

= 206.67 mA

SET

I

= 165.33 mA

SET

I

= 103.33 mA

SET

I

= 51.67 mA

SET

SET

SR01915

SET

Figure 12. Php Charge Pump Output vs. Temperature

(CP = 1; VDD = 3.0 V; I

3000

2000

1000

0

Icp (uA)

–1000

–2000

–3000

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

COMPLIANCE VOLTAGE (V)

= 165.33 A)

SET

TEMP = 85C
TEMP = 25C
TEMP = –40C

Figure 14. Php–su Charge Pump Output vs. Temperature

(CP = 0; VDD = 3.0 V; I

= 165.33 A)

SET

13

SR01916

Philips Semiconductors Product specification

SA80162.5GHz low voltage fractional-N synthesizer

1500

I

= 206.67 mA

1000

500

0

Icp (uA)

–500

–1000

–1500

I

= 51.67 mA

SET

I

= 103.33 mA

SET

I

= 165.33 mA

SET

I

= 206.67 mA

SET

0 0.25 0.5 0.75 1 1.51.25 1.75 2 2.25 2.5 2.75 3

COMPLIANCE VOLTAGE (V)

SET

I

= 165.33 mA

SET

I

= 103.33 mA

SET

I

= 51.67 mA

SET

Figure 15. Php–su Charge Pump Output vs. I

(CP = 1; TEMP = 25C)

0

–5
–10
–15
–20
–25
–30
–35

MINIMUM SIGNAL INPUT LEVEL (dBm)

–40

1300 1500 1700 1900 2100 2300 2500 2700 2900

FREQUENCY (MHz)

VDD = 5.00 V
VDD = 3.75 V

VDD = 3.00 V
VDD = 2.70 V

SR01917

SET

SR01919

1000

800
600
400
200

0

Icp (uA)

–200
–400
–600
–800

–1000

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5

COMPLIANCE VOLTAGE (V)

TEMP = 85C
TEMP = 25C
TEMP = –40C

SR01918

Figure 16. Php–su Charge Pump Output vs. Temperature

(CP = 1; VDD = 3.0 V; I

0

–5
–10
–15
–20
–25
–30
–35
–40

MINIMUM SIGNAL INPUT LEVEL (dBm)

–45

1300 1500 1700 1900 2100 2300 2500 2700 2900 3100

TEMP = +85C
TEMP = +25C
TEMP = –40C

FREQUENCY (MHz)

= 165.33 A)

SET

SR01920

Figure 17. Main Divider Input Sensitivity vs. Frequency and

Supply Voltage (TEMP = 25C)

0

–5
–10
–15
–20
–25
–30
–35
–40
–45
–50

MINIMUM SIGNAL POWER LEVEL (dBm)

–55

0 5 10 15 20 25 30 35 40 45 50 55 60

FREQUENCY (MHz)

VDD = 5.00 V
VDD = 3.75 V

VDD = 3.00 V
VDD = 2.70 V

65 70

SR01921

Figure 19. Reference Divider Input Sensitivity vs. Frequency

and Supply Voltage (TEMP = 25C)

1999 Apr 16

Figure 18. Main Divider Input Sensitivity vs. Frequency and

Temperature (V

0

–5
–10
–15
–20
–25
–30
–35
–40
–45
–50

MINIMUM SIGNAL POWER LEVEL (dBm)

–55

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

FREQUENCY (MHz)

= 3.00 V)

DD

TEMP = +85C
TEMP = +25C
TEMP = –40C

Figure 20. Reference Divider Input Sensitivity vs. Frequency

and Temperature (V

= 3.00 V)

DD

14

SR01922

Philips Semiconductors Product specification

SA80162.5GHz low voltage fractional-N synthesizer

11

10.5

10

9.5

9

I TOTAL (mA)

8.5

8

7.5
2 2.5 3 3.5 4 4.5 5 5.5 6

SUPPLY VOLTAGE (V)

TEMP = +85C
TEMP = +25C
TEMP = –40C

SR01923

Figure 21. Current Supply Over V

DD

1999 Apr 16

15

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N frequency
synthesizer

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

SA8016

1999 Apr 16

16

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N frequency
synthesizer

NOTES

SA8016

1999 Apr 16

17

Philips Semiconductors Product specification

2.5GHz low voltage fractional-N frequency
synthesizer

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

SA8016

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1999

All rights reserved. Printed in U.S.A.

Date of release: 04-99

Document order number: 9397 750 05734

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

1999 Apr 16

18