The SA8702 (BMTSAC) is a Block Mode
Time Slot Allocation Circuit. The device is
used to generate 8 consecutive timeslots
in one of 4 blocks in a 32 time-slot PCM
system. Each timeslot pulse is 8 BLCK
cycles long. BCLK is the 2,048 station
clock provided by the system. An active
MRST will disable all outputs until a valid
XSYNC input is recognised. The output
TSX is delayed by half a cycle and indicates
that one of 8 timeslots is currently active.
There are 4 possible modes of operation,
selectable by means of the BL0 and BL1
pins (See Table 1).
PIN CONNECTIONS
All inputs and outputs are C-MOS
compatible. All outputs are push-pull with
the exception of TSX which is open drain.
The inputs MRST and BCLK are Schmitt
Trigger. Inputs BL0 and BL1 have pull-ups.
(See figure 1).
APPLICATIONS
■PCM Switching Systems
■PCM Transmission Systems
■Subscriber Multiplex Equipment
■PBX Systems
SA8702
sames
Figure 1.
1
02.02.93
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SA8702
Operating Modes
BL1BL0Mode of Operation
00Outputs active in timeslots 0 to 7
01Outputs active in timeslots 8 to 15
10Outputs active in timeslots 16 to 23
11Outputs active in timeslots 24 to 31
Table 1.
Input pulse XSYNC occurs periodically in every frame and is used to generate the
first of the eight timeslots and also defines the beginning of Block 0. If XSYNC fails
high then the outputs will be generated as they were before the failure occured.
Should XSYNC fail low then the outputs will be deactivated after completion of the
frame.
Maximum Ratings
All voltages measured with respect to VSS.
ParameterSymbolValueUnits
Supply voltageV
Positive voltage on any pinV
Negative voltage on any pinV
Maximum current through any pinI
Storage temperatureT
Operating temperatureT
Stresses beyond these values may cause permanent damage to the device. Exposure to
maximum rated conditions for extended periods may affect device reliability.
DD
HM
LM
HM
ST
O
+7,5V
VDD +0,3V
VSS -0,3V
±10mA
-55 to +150°C
-10 to +70°C
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Operating Conditions:
All voltages measured with respect to VSS.
Inputs must never be left open.
DC ParametersSymbolMin.Nom.Max.Unit Conditions
SA8702
Supply VoltageV
* Input Low VoltageV
* Input High VoltageV
** Output Low VoltageV
** Output High VoltageV
DD
IL
IH
OL
OH
Operating Frequency-2,048 2,273MHz4,75 ≤ V
4,755,005,25V-
--1,0VV
4,0--VV
--0,5VV
4,5--VV
I
ol
I
oh
DD
DD
DD
DD
= 5V
= 5V
= 5V
= 0,5mA
= 5V
= 0,5mA
DD
≤ 5,25
Operating Temp. range-102570°C-
* All inputs are C-MOS level compatible. Pins 6 and 7 have internal pull-up
devices.
** All outputs are push-pull except pin 1 which is open drain.
AC ParametersSymbolMin.Nom.Max.UnitConditions
XSYNC setup beforeT
s
60--ns4,75 ≤ V
BCLK goes low≤ 5,25
Output propagationT
pd
--150ns4,75 ≤ Vdd
delay from active clock≤ 5,25
edge
XSYNC hold time fromT
h
50--ns4,75 ≤ V
BCLK≤ 5,25
DD
DD
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SA8702
PIN DESCRIPTION
Pin No.I/ONameDescription
1OTSXAn open drain N-channel high impedance, but pulls
low during any active timeslot.
2IMRSTA Schmitt trigger input that asynchronously disables
all outputs.
3OFSOA timeslot output which is normally low, and goes
active-high for 8 cycles of BCLK when a valid XSYNC
is made.
4OFS1Similar to pin 3.
5OFS2Similar to pin 3.
6IBL0The input for the LSB of the 2 bit word which defines
the active block.
7IBL1The input for the MSB of the 2 bit word which defines
the active block.
8IVSSThe OV ground connection to the device.
9IBCLKThe 2,048MHz station clock input.
10IXSYNCThe input pulse XSYNC used to generate the first of
the eight timeslots and also defines the beginning of
block 0.
11OFS7Similar to pin 3.
12OFS6Similar to pin 3.
13OFS5Similar to pin 3.
14OFS4Similar to pin 3.
15OFS3Similar to pin 3.
16IVDDThe positive supply to the device.
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TIMING DIAGRAM
SA8702
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SA8702
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