Datasheet MT9122AE, MT9122AP Datasheet (MITEL)

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Page 1

CMOS

MT9122

Dual Voice Echo Canceller

Preliminary Information

Features

• Dual channel 64ms or single channel 128ms echo cancellation

• Conforms to ITU-T G.165 requirements

• ITU-T G.165/G.164 disable tone detection supported on all audio paths

• Narrow-band signal detection

• Programmable double-talk detection threshold

• Non-linear processor with adaptive suppression threshold and comfort noise insertion

• Offset nulling of all PCM channels

• Controllerless mode or Controller mode with serial interface

• ST-BUS or variable-rate SSI PCM interfaces

• Selectable µ/A-Law ITU-T G.711; µ/A-Law Sign Mag; linear 2’s complement

• Per channel selectable 12 dB attenuator

• Transparent data transfer and mute option

• 19.2 MHz master clock operation

Applications

with Tone Detection

ISSUE 5 September 1996

Ordering Information

MT9122AP 28 Pin PLCC MT9122AE 28 Pin PDIP

-40 °C to + 85 °C

Description

The MT9122 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.165 requirements. The MT9122 architecture contains two echo cancellers which can be conﬁgured to provide dual channel 64 millisecond echo cancellation or single channel 128 millisecond echo cancellation. The MT9122 supports ITU-T G.165 or G.164 tone disable requirements.

The MT9122 operates in two major modes: Controller or Controllerless. Controller mode allows access to an array of features for customizing the MT9122 operation. Controllerless mode is for applications where default register settings are sufﬁcient.

• Wireless Telephony

• Trunk echo cancellers

Sin

Rout

ENA2 ENB2

NLP REV LAW

FORMAT

TD1

TD2

µ/A-Law

Programmable Bypass

Linear/

Disable Tone

Detector

Offset

Null

Linear/

µ/A-Law

Adaptive

Echo Canceller A

Non-Linear

Processor

Filter

Control

Narrow-Band

Detector

12dB

Attenuator

Echo Canceller B

Linear/

µ/A-Law

Microprocessor

Interface

Double-Talk

Detector

Offset

Null

Disable Tone

Detector

Linear/

µ/A-Law

Sout

Rin ENA1 ENB1

CONFIG1 CONFIG2 S1/DATA1 S2/DATA2

S3/ S4/SCLK

VDD VSS PWRDN IC F0od F0i BCLK/C4i MCLK

Figure 1 - Functional Block Diagram

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MT9122 Preliminary Information

ENA1 ENB1 ENA2 ENB2

Rin Sin

VSS

MCLK

NLP REV LAW

FORMAT

PWRDN

1 2

3 4 5

PDIP

6 7 8 9

10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

CONFIG2 CONFIG1

BCLK/

C4i

F0i Rout

Sout VDD

F0od S1/DATA1 S2/DATA2 S3/

CS S4/SCLK TD1 TD2

Rin Sin

VSS

MCLK

NLP

REV

ENB2

ENB1

ENA1

ENA2

LAW

PLCC

PWRDN

FORMAT

•

5 6 7 8 9

10 11

CONFIG2

TD2

TD1

BCLK/C4i

CONFIG1

25 24 23 22 21 20 19

CS S3/

S4/SCLK

F0i Rout Sout VDD F0od S1/DATA1 S2/DATA2

Figure 2 - Pin Connections

Pin Description

Pin # Name Description

1 ENA1 SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input). This pin has dual functions

depending on whether SSI or ST-BUS is selected. For SSI, this strobe must be present f or fr ame synchronization. This is an active high channel

enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for Echo Canceller A on Rin/Sout pins. Strobe period is 125 microseconds.

For ST-BUS, this pin, in conjunction with the ENB1 pin, will select the proper ST-BUS mode f or Rin/Sout pins (see ST-BUS Operation description). The selected mode applies to both Echo Canceller A and B.

2 ENB1 SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input).This pin has dual functions

depending on whether SSI or ST-BUS is selected. For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial

PCM data transfer f orEcho Canceller B on Rin/Sout pins . Strobe period is 125 microseconds. For ST-BUS, this pin, in conjunction with the ENA1 pin, will select the proper ST-BUS mode f or

Rin/Sout pins (see ST-BUS Operation description). The selected mode applies to both Echo Canceller A and B.

3 ENA2 SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input).This pin has dual functions

depending on whether SSI or ST-BUS is selected. For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial

PCM data transfer f orEcho Canceller A on Sin/Rout pins . Strobe period is 125 microseconds. For ST-BUS, this pin, in conjunction with the ENB2 pin, will select the proper ST-BUS mode f or

Sin/Rout pins (see ST-BUS Operation description). The selected mode applies to both Echo Canceller A and B.

4 ENB2 SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input).This pin has dual functions

depending on whether SSI or ST-BUS is selected. For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial

PCM data transfer f orEcho Canceller B on Sin/Rout pins . Strobe period is 125 microseconds.

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For ST-BUS, this pin, in conjunction with the ENA2 pin, will select the proper ST-BUS mode f or Sin/Rout pins (see ST-BUS Operation description). The selected mode applies to both Echo Canceller A and B.

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Preliminary Information MT9122

Pin Description (continued)

Pin # Name Description

5 Rin Receive PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data

may be in either companded or 2’s complement linear format. Two PCM channels are timemultiplexed on this pin. These are the Receive Input reference channels for Echo Cancellers A and B. Data bits are clocked in following SSI or ST-BUS timing requirements.

6 Sin Send PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data

may be in either companded or 2’s complement linear format. Two PCM channels are timemultiplexed on this pin. These are the Send Input channels (after echo path) for Echo Cancellers A and B. Data bits are clocked in following SSI or ST-BUS timing requirements.

7 VSS Digital Ground: Nominally 0 volts. 8 MCLK Master Clock (Input): Nominal 20 MHz Master Clock input. May be connected to an

asynchronous (relative to frame signal) clock source.

9 IC Internal Connection (Input): Must be tied to Vss.

10 NLP Non-Linear Processor Control (Input):

Controllerless Mode: An active high enables the Non-Linear Processors in Echo Cancellers A and B. Both NLP’ s are disab led when lo w. Intended for conformance testing to G.165 and it is usually tied to Vdd for normal operation.

Controller Mode: This pin is ignored (tie to Vdd or Vss). The non-linear processor operation is controlled by the NLPDis bit in Control Register 2. Refer to the Register Summary.

11 REV Reversal Detection (Input):

Controllerless Mode: An active high conﬁgures all the tone detectors to trigger only when a 2100Hz disable tone with periodic phase reversal is present (per G.165). When low, the tone detectors will trigger upon detection of any 2100Hz disable tone, with or without periodic phase reversal (per G.164).

Controller Mode: This pin is ignored (tie to VDD or VSS). The operation is controlled by the PHDis bit in Control Register 2. Refer to the Register Summary.

12 LAW A/µ Law Select (Input):

An active low selects µ−Law companded PCM. When high, selects A-Law companded PCM. This control is for both echo cancellers and is valid for both controller and controllerless modes.

13 FORMAT ITU-T/Sign Mag (Input):

An active low selects sign-magnitude PCM code. When high, selects ITU-T (G.711) PCM code. This control is for both echo cancellers and is v alid f or both controller and controllerless modes.

14 PWRDN Power-down (Input): An active low resets the device and puts the MT9122 into a low-power

stand-by mode.

15 TD2 Tone Detect 2 (Output):

An active low output occurs when Echo Canceller B detects the presence of a valid 2100Hz disabling tone (G.164 or G.165) on Rin or Sin pins. This output returns to a logic high once the release criteria are met. The behavior of this pin is identical in both controller and controllerless modes.

16 TD1 Tone Detect 1 (Output):

An active low output occurs when Echo Canceller A detects the presence of a valid 2100Hz disabling tone (G.164 or G.165) on Rin or Sin pins. This output returns to a logic high once the release criteria are met. The behavior of this pin is identical in both controller and controllerless modes.

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MT9122 Preliminary Information

Pin Description (continued)

Pin # Name Description 17/18

S4/S3

Selection of Echo Canceller B Functional States (Input):

Controllerless Mode: Selects Echo Canceller B functional states according to Table 2. Controller Mode: S4 and S3 pins become SCLK and CS pins respectively.

17 18

19/20

SCLK

S2/S1

Serial Port Synchronous Clock (Input): Data clock for the serial microport interface. Chip Select (Input): Enables serial microport interface data transfers. Active low.

Selection of Echo Canceller A Functional States (Input):

Controllerless Mode: Selects Echo Canceller A functional states according to Table 2. Controller Mode: S2 and S1 pins become DATA2 and DATA1 pins respectively.

DATA2

Serial Data Receive (Input):

In Motorola/National serial microport operation, the DATA2 pin is used for receiving data. In Intel serial microport operation, the DATA2 pin is not used and must be tied to Vss or Vdd.

DATA1

Serial Data Port (Bidirectional):

In Motorola/National serial microport operation, the DAT A1 pin is used f or tr ansmitting data. In Intel serial microport operation, the DATA1 pin is used for transmitting and receiving data.

21 F0od Delayed Frame Pulse Output (Output):

In ST-BUS operation, this pin generates a delay ed frame pulse after the 4th channel time slot and is used for daisy-chaining multiple ST-BUS devices. See Figures 5 to 8.

In SSI operation, this pin outputs logic low.

22 VDD Positive Power Supply: Nominally 5 volts. 23 Sout Send PCM Signal Output (Output):

128 kbit/s to 4096 kbit/s serial PCM output stream. Data may be in either companded or 2’s complement linear PCM format. Two PCM channels are time-multiplexed on this pin. These are the Send Out signals after echo cancellation and Non-linear processing. Data bits are clocked out following SSI or ST-BUS timing requirements.

24 Rout Receive PCM Signal Output (Output):

128 kbit/s to 4096 kbit/s serial PCM output stream. Data may be in either companded or 2’s complement linear PCM format. Two PCM channels are time-multiplexed on this pin. This output pin is provided for convenience in some applications and may not always be required. Data bits are clocked out following SSI or ST-BUS timing requirements.

25 F0i Frame Pulse (input):

In ST-BUS operation, this is a frame alignment low going pulse. SSI operation is enabled by connecting this pin to Vss.

26 BCLK/C4i Bit Clock/ST-BUS Clock (Input):

In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit clock. This clock must be synchronous with ENA1, ENA2, ENB1 and ENB2 enable strobes.

In ST-BUS operation, C4i pin must be connected to the 4.096MHz (C4) system clock.

27/28 CONFIG1/

CONFIG2

Device Conﬁguration Pins (Inputs).

When CONFIG1 and CONFIG2 pins are both logic 0, the MT9122 serial microport is enabled. This conﬁguration is deﬁned as Controller Mode. When CONFIG1 and CONFIG2 pins are in any other logic combination, the MT9122 is conﬁgured in Controllerless Mode. See Table 3.

Notes:

1. All un used inputs should be connected to logic lo w or high unless otherwise stated. All outputs should be left open circuit when not used.

2. All inputs have TTL compatible logic levels except for MCLK, Sin and Rin pins which have CMOS compatible logic levels and PWRDN pin which has Schmitt trigger compatible logic levels.

3. All outputs are CMOS pins with CMOS logic levels.

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Preliminary Information MT9122

Functional Description

The MT9122 architecture contains two individually controlled echo cancellers (Echo Canceller A and B). They can be set in three distinct conﬁgurations: Normal, Back-to-Back and Extended Delay (see Figure 3). Under Normal conﬁguration, the two echo cancellers are positioned in parallel providing 64 millisecond echo cancellation in two channels simultaneously. In Back-to-Back conﬁguration, the two echo cancellers are positioned to cancel echo coming from both directions in a single channel. In Extended-Delay conﬁguration, the two echo cancellers are internally cascaded into one 128 millisecond echo canceller.

Each echo canceller contains the following main elements (see Figure 1).

• Adaptive Filter for estimating the echo channel

• Subtracter for cancelling the echo

• Double-Talk detector for disabling the ﬁlter adaptation during periods of double-talk

• Non-Linear Processor for suppression of residual echo

• Disable Tone Detectors for detecting valid disable tones at the input of receive and send paths

• Narrow-Band Detector for preventing Adaptive Filter divergence caused by narrow-band signals

• Offset Null ﬁlters for removing the DC component in PCM channels

• 12dB attenuator for signal attenuation

• Serial controller interface compatible with Motorola, National and Intel microcontrollers

• PCM encoder/decoder compatible with µ/ALaw ITU-T G.711, µ/A-Law Sign-Mag or linear 2’s complement coding

The MT9122 has two modes of operation:

Controllerless

and

Controller

. Controllerless mode is intended for applications where customization is not required. Controller mode allows access to all registers for customizing the MT9122 operation. Refer to Table 7 for a complete list. Controller mode is selected when CONFIG1 and CONFIG2 pins are both connected to Vss.

Each echo canceller in the MT9122 has four functional states: and

Enable Adaptation

Mute,Bypass,Disable Adaptation

. These are explained in the

section entitled Echo Canceller Functional States.

Sin

echo path A

Rout

echo path B

PORT 2

channel A

E.C.A

channel B

E.C.B

Adaptive

Filter (64ms)

Optional -12dB pad

Adaptive

Filter (64ms)

Optional -12dB pad

a) Normal Conﬁguration (64ms)

PORT 1

Sout

Rin

PORT 2

echo

path A

Rout

Sin

channel A

E.C.A

Adaptive Filter

(128 ms)

Optional -12dB pad

PORT 1

b) Extended Delay Conﬁguration (128ms)

PORT 2

Sin

echo path

Rout Rin

Optional -12dB pad

Adaptive

Filter (64ms)

E.C.A

Filter (64ms)

Optional -12dB pad

Adaptive

E.C.B

PORT 1

echo path

c) Back-to-Back Conﬁguration (64ms)

Sout

Rin

Sout

Figure 3 - Device Conﬁguration

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MT9122 Preliminary Information

Adaptive Filter

The adaptive ﬁlter is a 1024 tap FIR ﬁlter which is divided into two sections. Each section contains 512 taps providing 64ms of echo estimation. In Normal conﬁguration, the ﬁrst section is dedicated to channel A and the second section to channel B. In Extended Delay conﬁguration, both sections are cascaded to provide 128ms of echo estimation in channel A.

Double-Talk Detector

Double-Talk is deﬁned as those periods of time when signal energy is present in both directions simultaneously. When this happens, it is necessary to disable the ﬁlter adaptation to prevent divergence of the adaptive ﬁlter coefﬁcients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller continues to cancel echo.

A double-talk condition exists whenever the Sin signal level is greater than the expected retur n echo level. The relative signal levels of Rin (Lrin) and Sin (Lsin) are compared according to the following expression to identify a double-talk condition:

The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:

DTDT

where 0 < DTDT

= hex(DTDT

(hex)

< 1

(dec)

* 32768)

Example: For DTDT = 0.5625 (-5dB), the

hexadecimal value becomes

hex(

0.5625 * 32768) = 4800h

Non-Linear Processor (NLP)

After echo cancellation, there is always a small amount of residual echo which may still be audible. The MT9122 uses an NLP to remove residual echo signals which have a level lower than the Adaptive Suppression Threshold (TSUP in G.165). This threshold depends upon the level of the Rin (Lrin) reference signal as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR). TSUP can be calculated by the following equation:

TSUP = Lrin + 20log10(NLPTHR)

Lsin > Lrin + 20log10(DTDT)

where DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are the relative signal levels expressed in dBm0.

A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo return. During these periods, the adaptation process is slowed down but it is not halted.

Controllerless Mode

In G.165 standard, the echo return loss is expected to be at least 6dB. This implies that the Double-Talk Detector Threshold (DTDT) should be set to 0.5 (-6dB). However, in order to get additional guardband, the DTDT is set internally to 0.5625 (-5dB). In controllerless mode, the Double-Talk Detector is always active.

Controller Mode

In some applications the return loss can be higher or lower than 6dB. The MT9122 allows the user to change the detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value into the DTDT register.

where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed in dBm0.

When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal to less than -65dBm0. To prevent a perceived decrease in background noise due to the activation of the NLP, a spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP.

Controllerless Mode

The NLP processor can be disabled by connecting the NLP pin to Vss.

Controller Mode

The NLP processor can be disabled by setting the NLPDis bit to 1 in Control Register 2.

The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:

NLPTHR

= hex(NLPTHR

(hex)

(dec)

* 32768)

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Preliminary Information MT9122

where 0 < NLPTHR

(dec)

< 1

The comfort noise injection can be disabled by setting the INJDis bit to 1 in Control Register 1.

It should be noted that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled.

Disable Tone Detector

G.165 recommendation deﬁnes the disable tone as having the following characteristics: 2100 Hz (± 21Hz) sinewave, a power level between -6 to

-31dBm0, and a phase reversal of 180 degrees (±25 degrees) every 450ms (±24ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the Tone Detector will tr igger.

G.164 recommendation deﬁnes the disable tone as a 2100 Hz (±21Hz) sinewave with a power level between -6 to -31dBm0. If the disable tone is present for a minimum of one second, with or without phase reversal, the Tone Detector will tr igger.

The MT9122 has four Tone Detectors in order to monitor the occurrence of a valid disable tone on channels A and B on both Rin and Sin. Upon detection of a disable tone, output pins TD1 or TD2 will go low as illustrated in Figure 4.

Rin

Tone Detector

TD1

Sin

Tone Detector

Controllerless Mode

The selection between G.165 and G.164 tone disable is controlled by the REV pin. When the REV pin is connected to Vss, G.164 is selected. This applies to all four Tone Detectors.

In response to a valid disable tone, the MT9122 must be switched from the Enable Adaptation state to the Bypass state. In an application, the Tone Detect outputs, TD1 and TD2, may be used to switch the echo cancellers between these two states. This is achieved by connecting S1 and S3 pins to Vdd and by connecting the TD1 and TD2 outputs to the S2 and S4 input pins respectively.

Controller Mode

The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2. When the PHDis bit is set to 1, G.164 tone disable requirements are selected. This applies to all four Tone Detectors.

In response to a valid disable tone, the MT9122 must be switched from the Enable Adaptation state to the Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors internally control the switching between Enable Adaptation and Bypass states. The automatic mode can be activated by setting the AutoTD bit in Control Register 2 to high. In external mode, an external controller is needed to poll the TD bit in Status Register A or B. Following the detection of a disable tone (TD bit high), the external controller should switch the echo canceller from Enable Adaptation to Bypass state.

Echo Canceller A

Rin

Tone Detector

TD2

Sin

Tone Detector

Echo Canceller B

Figure 4 - Disable Tone Detection

Once a Tone Detector has been triggered, the MT9122 no longer needs a valid disable tone (G.164 or G.165) to maintain Tone Detector status (e.g. TD1, TD2 pins low). The Tone Detector status will only release (e.g. TD1, TD2 pins high) if the signals Rin and Sin fall below -30dBm0, in the frequency range of 390Hz to 700Hz, and below -34dBm0, in the frequency range of 700Hz to 3400Hz, for at least 400ms.

TD1 and TD2 output pins remain active, as in

The Controllerless mode, and they can be used as an interrupt to an external controller.

Narrow Band Signal Detector (NBSD)

Single or dual frequency tones (e.g. DTMF tones) present in the reference input (Rin) of the echo canceller for a prolonged period of time may cause the adaptive ﬁlter to diverge. The Narrow Band Signal Detector (NBSD) is designed to prevent this divergence by detecting single or dual tones of arbitrary frequency, phase, and amplitude. When narrow band signals are detected, the adaptation process is halted but the echo canceller continues to cancel echo.

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MT9122 Preliminary Information

Controllerless Mode

The NBSD is always active and automatically disables the ﬁlter adaptation process when narrow band signals are detected.

Controller Mode

The NBSD can be disabled by setting the NBDis bit to 1 in Control Register 2.

Offset Null Filter

Adaptive ﬁlters in general do not operate properly when a DC offset is present on either the reference signal (Rin) or the echo composite signal (Sin). To remove the DC component, the MT9122 incorporates Offset Null ﬁlters in both Rin and Sin inputs.

Controllerless Mode

The Offset Null ﬁlters are always active.

Controller Mode

The offset null ﬁlters can be disabled by setting the HPFDis bit to 1 in Control Register 2.

Echo Canceller Functional States

canceller. In this conﬁguration, muting Echo Canceller A causes quiet code to be transmitted on Rout.

Bypass: The Bypass state directly transfers PCM codes from

Rin to Rout and from Sin to Sout. When Bypass state is selected, the adaptive ﬁlter coefﬁcients are reset to zero.

Disable Adaptation: When the Disable Adaptation state is selected, the

adaptive ﬁlter coefﬁcients are frozen at their current value. In this state, the adaptation process is halted however the MT9122 continues to cancel echo.

Enable Adaptation: In Enable Adaptation state, the adaptive ﬁlter

coefﬁcients are continually updated. This allows the echo canceller to model the echo return path characteristics in order to cancel echo. This is the normal operating state.

Controllerless Mode

The four functional states can be selected via S1, S2, S3, and S4 pins as shown in the following table.

Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation.

Mute: The Mute state forces the echo canceller to

transmit quiet code and halts the ﬁlter adaptation process.

In Normal conﬁguration, the PCM output data on Rout is replaced with the quiet code according to the following table.

+Zero

(quiet code)

LINEAR

16 bits

2’s

complement

0000h 80h FFh D5h

SIGN/

MAGNITUDE

µ-Law

A-Law

CCITT (G.711)

µ-Law A-Law

Table 1 - Quiet PCM Code Assignment

In Back-to-Back conﬁguration, both echo cancellers are combined to implement a full duplex echo canceller. Therefore muting Echo Canceller A causes quiet code to be transmitted on Rout, while muting Echo Canceller B causes quiet code to be transmitted on Sout.

In Extended Delay conﬁguration, both echo cancellers are cascaded to make one 128ms echo

Echo

Canceller A

S2/S1

00 Mute 01 Bypass 10 Disable Adaptation 11 Enable Adaptation

(1) Filter coefficients are frozen (adaptation disabled) (2) The adaptive filter coefficients are reset to zero (3) The MT9122 cancels echo

Functional State

(1)

(2)

(1,3)

(3)

Echo

Canceller B

S4/S3

00 01 10 11

Table 2 - Functional States Control Pins

Controller Mode

The echo canceller functions are selected in Control Register 1 and Control Register 2 through four control bits: MuteS, MuteR, Bypass and AdaptDis. See Register Summary for details.

MT9122 Throughput Delay

The throughput delay of the MT9122 varies according to the data path and the device conﬁguration. For all device conﬁgurations, except for Bypass state, Rin to Rout has a delay of two frames and Sin to Sout has a delay of three frames.

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Preliminary Information MT9122

In Bypass state, the Rin to Rout and Sin to Sout paths have a delay of two frames. In ST-BUS operation, the D and C channels have a delay of one frame.

Power Down

Forcing the PWRDN pin to logic low, will put the MT9122 into a power down state. In this state all internal clocks are halted, the DATA1, Sout and Rout pins are tristated and the F0od, TD1, and TD2 pins output high.

The device will automatically begin the execution of its initialization routines when the PWRDN pin is returned to logic high and a clock is applied to the MCLK pin. The initialization routines execute for one frame and will set the MT9122 to default register values.

Device Conﬁguration

The MT9122 architecture contains two individually controlled echo cancellers (Echo Canceller A and B). They can be set in three distinct conﬁgurations: Normal, Back-to-Back, and Extended Delay. See Figure 3.

In SSI operation, ENA1 and ENA2 enable pins are used to strobe data on Rin/Sout and Sin/Rout respectively. In ST-BUS operation, ENA1, ENA2, ENB1 and ENB2 inputs are used to select the STBUS mode according to Table 4.

Examples of Back-to-Back conﬁguration include positioning the MT9122 between a codec and a transmission device or between two codecs for echo control on analog trunks.

Extended Delay conﬁguration: In this conﬁguration, the two echo cancellers are

internally cascaded into one 128 millisecond echo canceller. See Figure 3b. In SSI operation, ENA1 and ENA2 enable pins are used to strobe data on Rin/Sout and Sin/Rout respectively. In ST-BUS operation, ENA1, ENA2, ENB1 and ENB2 inputs are used to select the ST-BUS mode according to Table

Controllerless Mode

The three conﬁgurations can be selected through the CONFIG1 and CONFIG2 pins as shown in the following table.

CONFIG1 CONFIG2 CONFIGURATION

Normal Conﬁguration: In this conﬁguration, the two echo cancellers (Echo

Canceller A and B) are positioned in parallel, as shown in Figure 3a, providing 64 milliseconds of echo cancellation in two channels simultaneously.

In SSI operation, both channels are available in different timeslots on the same TDM (Time Division Multiplexing) bus. For Echo Canceller A, the ENA1 enable strobe pin deﬁnes the Rin/Sout (PORT1) time slot while the ENA2 enable strobe pin deﬁnes the Sin/Rout (PORT2) time slot. The ENB1 and ENB2 enable strobes perform the same function for Echo Canceller B.

In ST-BUS operation, the ENA1, ENA2, ENB1 and ENB2 pins are used to determine the PCM data format and the channel locations. See Table 4.

Back-to-Back Conﬁguration: In this conﬁguration, the two echo cancellers are

positioned to cancel echo coming from both directions in a single channel providing full duplex 64 millisecond echo-cancellation. See Figure 3c. This conﬁguration uses only one timeslot on PORT1 and PORT2, allowing a no-glue interface for applications where bidirectional echo cancellation is required.

00 0 1 Extended Delay Mode 1 0 Back-to-Back Mode 1 1 Normal Mode

(selects Controller Mode)

Table 3 - Conﬁguration in Controllerless Mode

Controller Mode

In Control Register 1, the Normal conﬁguration can be programmed by setting both BBM and ExtendedDelay bits to 0. Back-to-Back conﬁguration can be programmed by setting the BBM bit to 1 and Extended-Delay bit to 0. Extended-Delay conﬁguration can be programmed by setting the Extended-Delay bit to 1 and BBM bit to 0. Both BBM and Extended-Delay bits in Control Register 1 can not be set to 1 at the same time.

PCM Data I/O

The PCM data transfer for the MT9122 is provided through two PCM ports. PORT1 consists of Rin and Sout pins while PORT2 consists of Sin and Rout Pins. The Data is transferred through these ports according to either ST-BUS or SSI conventions. The device determines the mode of operation by monitoring the signal applied to the

F0i pin. When a

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Page 10

MT9122 Preliminary Information

valid ST-BUS frame pulse is applied to the F0i pin, the MT9122 will assume ST-BUS operation. If F0i is tied continuously to Vss the MT9122 will assume SSI operation.

ST-BUS Operation

The ST-BUS PCM interface conforms to Mitel’s STBUS standard and it is used to transport 8 bit companded PCM data (using one timeslot) or 16 bit 2’s complement linear PCM data (using two timeslots). Pins ENA1 and ENB1 select timeslots on PORT1 while pins ENA2 and ENB2 select timeslots on PORT2. See Table 4 and Figures 5 to 8.

PORT1

Rin/Sout

Enable Pins Enable Pins

ENB1 ENA1 ENB2 ENA2

00Mode 1. 8 bit companded PCM I/O on

timeslots 0 & 1.

01Mode 2. 8 bit companded PCM I/O on

timeslots 2 & 3.

10Mode 3. 8 bit companded PCM I/O on

timeslots 2 & 3. Includes D & C channel bypass in timeslots 0 & 1.

11Mode 4. 16 bit 2’s complement linear

PCM I/O on timeslots 0 - 3.

ST-BUS Mode

Selection

PORT2

Sin/Rout

and ENB2) are used for parsing input/output data and they must pulse within 125 microseconds of the rising edge of ENA1. If they are unused, they must be tied to Vss.

In SSI operation, the enable strobes may be a mixed combination of 8 or 16 BCLK cycles allowing the ﬂexibility to mix 2’s complement linear data on one port (e.g., Rin/Sout) with companded data on the other port (e.g., Sin/Rout).

Enable Strobe Pin Echo Canceller Port

ENA1 A 1 ENB1 B 1 ENA2 A 2 ENB2 B 2

Table 5 - SSI Enable Strobe Pins

PCM Law and Format Control (LAW, FORMAT)

The PCM companding/coding law used by the MT9122 is controlled through the LAW and FORMAT pins. ITU-T G.711 companding curves for µ-Law and A-Law are selected by the LAW pin. PCM coding ITU-T G.711 and Sign-Magnitude are selected by the FORMAT pin. See Table 6.

Table 4 - ST-BUS Mode Select

Note that if the device is in back-to-back or extended delay conﬁgurations, the second timeslot in any STBUS Mode contains undeﬁned data. This means that the following timeslots contain undeﬁned data: timeslot 1 in ST-BUS Mode 1; timeslot 3 in ST-BUS Modes 2 & 3 and timeslots 2 and 3 in ST-BUS Mode

SSI Operation

The SSI PCM interface consists of data input pins (Rin, Sin), data output pins (Sout, Rout), a variable rate bit clock (BCLK), and four enable pins (ENA1,ENB1, ENA2 and ENB2) to provide strobes for data transfers. The active high enable may be either 8 or 16 BCLK cycles in duration. Automatic detection of the data type (8 bit companded or 16 bit 2’s complement linear) is accomplished internally. The data type cannot change dynamically from one frame to the next.

In SSI operation, the frame boundary is determined by the rising edge of the ENA1 enable strobe (see Figure 9). The other enable strobes (ENB1, ENA2

Sign-Magnitude

FORMAT=0

PCM Code

µ/A-LAW

LAW = 0 or 1

+ Full Scale 1111 1111 1000 0000 1010 1010

+ Zero 1000 0000 1111 1111 1101 0101

- Zero 0000 0000 0111 1111 0101 0101

- Full Scale 0111 1111 0000 0000 0010 1010

ITU-T (G.711)

FORMAT=1

µ-LAW

LAW = 0

A-LAW

LAW =1

Table 6 - Companded PCM

Linear PCM

The 16-bit 2’s complement PCM linear coding permits a dynamic range beyond that which is speciﬁed in ITU-T G.711 for companded PCM. The echo-cancellation algorithm will accept 16 bits 2’s complement linear code which gives a dynamic range of +15dBm0. Note however that the tone detectors must be limited to the maximum dynamic range speciﬁed in G.711 (+3.14 or +3.17 dBm0).

8-26

Page 11

Preliminary Information MT9122

Linear PCM data must be formatted as 14-bit, 2’s complement data with three bits of sign extension in the most signiﬁcant positions (i.e.: S,S,S,12,11, ...1,0) for a total of 16 bits where “S” is the extended sign bit. When A-Law is converted to 2’s complement linear format, it must be scaled up by 6dB (i.e. left shifted one bit) with a zero inserted into the least signiﬁcant bit position. See Figure 8.

Bit Clock (BCLK/C4i)

The BCLK/C4i pin is used to clock the PCM data in both SSI (BCLK) and ST-BUS (C4i) operations.

In SSI operation, the bit rate is determined by the BCLK frequency. This input must contain either eight or sixteen clock cycles within the valid enable strobe window. BCLK may be any rate between 128 KHz to

4.096 MHz and can be discontinuous outside of the enable strobe windows deﬁned by ENA1, ENB1, ENA2 and ENB2 pins. Incoming PCM data (Rin, Sin) are sampled on the falling edge of BCLK while outgoing PCM data (Sout, Rout) are clocked out on the rising edge of BCLK. See Figure 17.

In ST-BUS operation, connect the system C4 (4.096MHz) clock to the C4i pin.

Master Clock (MCLK)

A nominal 20MHz master clock (MCLK) is required for execution of the MT9122 algor ithms. The MCLK input may be asynchronous with the 8KHz frame. If only one channel operation is required, (Echo Canceller A only) the MCLK can be as low as

9.6MHz.

Microport

The serial microport provides access to all MT9122 internal read and write registers and it is enabled when CONFIG1 and CONFIG2 pins are both set to logic 0. This microport is compatible with Intel MCS51 (mode 0), Motorola SPI (CPOL=0, CPHA=0), and National Semiconductor Microwire speciﬁcations. The microport consists of a transmit/receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (

CS) and a synchronous data clock pin (SCLK).

timing is assumed. In this case DATA1 pin is deﬁned as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK is low during CS activation, then Motorola/National timing is assumed and DATA1 is deﬁned as the data transmit pin while DATA2 becomes the data receive pin. The MT9122 supports Motorola half-duplex processor mode (CPOL=0 and CPHA=0). This means that during a write to the MT9122, by the Motorola processor, output data from the DATA1 pin must be ignored. This also means that input data on the DATA2 pin is ignored by the MT9122 during a valid read by the Motorola processor.

All data transfers through the microport are two bytes long. This requires the transmission of a Command/ Address byte followed by the data byte to be written or read from the addressed register. CS must remain low for the duration of this two-byte transfer. As shown in Figures 10 and 11, the falling edge of CS indicates to the MT9122 that a microport transfer is about to begin. The ﬁrst 8 clock cycles of SCLK after the falling edge of CS are always used to receive the Command/Address byte from the microcontroller. The Command/Address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock cycles are used to transfer the data byte between the MT9122 and the microcontroller. At the end of the two-byte transf er, CS is brought high again to terminate the session. The rising edge of CS will tri-state the DATA1 pin. The DATA1 pin will remain tristated as long as CS is high.

Intel processors utilize Least Signiﬁcant Bit (LSB) ﬁrst transmission while Motorola/National processors use Most Signiﬁcant Bit (MSB) ﬁrst transmission. The MT9122 microport automatically accommodates these two schemes for normal data bytes. However, to ensure timely decoding of the R/ information, the Command/Address byte is deﬁned differently for Intel and Motorola/National operations. Refer to the relative timing diagrams of Figures 10 and 11.

Receive data is sampled on the rising edge of SCLK while transmit data is clocked out on the falling edge of SCLK. Detailed microport timing is shown in Figure 19 and Figure 20.

W and address

The MT9122 automatically adjusts its internal timing and pin conﬁguration to conform to Intel or Motorola/ National requirements. The microport dynamically senses the state of the SCLK pin each time becomes active (i.e. high to low transition). If SCLK pin is high during CS activation, then Intel mode 0

CS pin

8-27

Page 12

MT9122 Preliminary Information

Function Controllerless

selected when pins CONFIG1 & 2 ≠00

Normal Configuration Set pins CONFIG1 to 1 and CONFIG2 1 to select this

configuration.

Back-to-Back Configuration

Extended Delay Configuration

Mute Set pins S2/S1 to 00 and S4/S3 to 00 to select for Echo

Bypass Set pins S2/S1 to 01 and S4/S3 to 01 to select for Echo

Disable Adaptation Set pins S2/S1 to 10 and S4/S3 to 10 to select for Echo

Enable Adaptation Set pins S2/S1 to 11 and S4/S3 to 11 to select for Echo

SSI Tie pin F0i to VSS to select. Tie pin F0i to VSS to select. ST-BUS Apply a valid ST-BUS frame pulse to F0i pin to select. Apply a valid ST-BUS frame pulse to F0i pin to select. 12dB Attenuator Always disabled. Set bit PAD to 1 in Control Register 1 to enable. Double-Talk

Detector Disable Tone

Detector

Disable Tone Set pin REV to 1 to select disable tone with phase

Non-Linear Processor

PCM Law Set pin LAW to 1 or 0 to select A-Law or µ-Law

PCM Format Set pin FORMAT to 0 or 1 to select Sign-Magnitude or

Narrow-Band Signal Detector

Offset Null Filter Continuously enabled which removes the DC compo-

Set pins CONFIG1 to 1 and CONFIG2 to 0 to select this configuration.

Set pins CONFIG1 to 0 and CONFIG2 to 1 to select this configuration.

Canceller A and Echo Canceller B respectively.

Canceller A and Echo Canceller B, respectively.

Continuously enabled which disables filter adaptation when double-talk is detected.

It is continuously enabled and puts TD1 orTD2 or both into active low when disable tone is detected. The TD1 and TD2 outputs have to be externally manipulated by the user to bypass the echo canceller.

reversal (G.165). Set pin NLP to 1 to enable. Set bit NLPDis to 1 to disable.

respectively.

ITU-T format respectively. Continuously enabled which disables the filter adapta-

tion when narrow band signal is detected.

nent in the PCM input.

Set bits Extended-Delay to 0 and BBM to 0 in Control Register 1 to select.

Set bit BBM to 1 in Control Register 1 to select.

Set bit Extended-Delay to 1 in Control Register 1 to select.

Set bit MuteR to 1 or MuteS to 1 in Control Register 2 to select.

Set bit Bypass to 1 in Control Register 1 to select.

Set bit AdaptDis to 1 in Control Register 1 to select.

Set bits AdaptDis to 0 and Bypass to 0 in Control Register 1 to select.

The detection threshold can be controlled via Double-Talk Detection Threshold Register 1 and 2.

Set bit TDis to 1 in Control Register 2 to disable tone detectors.

Set bit PHDis to 1 in Control Register 2 to select disable tone without phase reversal (G164).

Set pin LAW to 1or 0 to select A-Law or µ-Law respectively.

Set pin FORMAT to 0 or 1 to select Sign-Magnitude or ITU-T format respectively.

Set bit NBDis to 1 in Control Register 2 to disable.

Set bit HPFDis to 1 in Control Register 2 to disable.

selected when pins CONFIG1 & 2 = 00

Controller

8-28

Table 7 - MT9122 Function Control Summary

Page 13

Preliminary Information MT9122

C4i

F0i

F0od

PORT1 Rin

Sout

PORT2 Sin

Rout

7654

outputs=High impedance

inputs = don’t care

01 2 34

ECA

ECB

7654

ECB

7654

In ST-BUS Mode 1, both echo canceller I/O channels are assigned to ST-BUS timeslots 0 and 1. Note that the user could conﬁgure PORT1 and POR T2 into different ST-BUS modes. The pin

F0od is always delayed 4 time slots to permit

a more ﬂexible interleave of ST-BUS modes.

Figure 5 - ST-BUS 8 Bit Companded PCM I/O on Timeslots 0 & 1 (Mode 1)

C4i

F0i

F0od

PORT1 Rin

Sout

PORT2

Sin

Rout

outputs=High impedance

inputs = don’t care

01 2 34

ECA

7654

ECA

7654

ECB

7654

ECB

7654

In ST-BUS Mode 2, both echo canceller I/O channels are assigned to ST-BUS timeslots 2 and 3. Note that the user could conﬁgure PORT1 and POR T2 into different ST-BUS modes. The pin

F0od is always delayed 4 time slots to permit

a more ﬂexible interleave of ST-BUS modes.

Figure 6 - ST-BUS 8 Bit Companded PCM I/O on Timeslots 2 & 3 (Mode 2)

8-29

Page 14

MT9122 Preliminary Information

C4i

F0i

01 2 34

F0od

PORT1

Rin

7654

ECA ECB

Sout

PORT2

Sin

7654

ECA ECB

Rout

7654

outputs=High impedance

inputs = don’t care indicates that an input channel is bypassed to an output channel

7654

ST-BUS Mode 3 supports connection to 2B+D devices where timeslots 0 and 1 transport D and C channels and both echo canceller I/O channels are assigned to ST-BUS timeslots 2 and 3. Both PORT1 and PORT2 must be conﬁgured in ST-BUS Mode 3.

Figure 7 - ST-BUS 8 Bit Companded PCM I/O with D and C channels (Mode 3)

C4i

F0i

F0od

Rin PORT1

Sout

Sin PORT2

Rout

outputs=High impedance

inputs = don’t care

8 76543210

76543210

ECA

8 76543210

76543210

8 76543210

76543210

ECA

8 76543210

76543210

ST-BUS Mode 4 allows 16 bits 2’s complement linear data to be transferred using ST-BUS I/O timing. Note that PORT1 and PORT2 need not necessarily both be in mode 4.

ECB

8-30

Figure 8 - ST-BUS 16 Bit 2’s complement linear PCM I/O (Mode 4)

Page 15

Preliminary Information MT9122

BCLK

PORT1

ENA1

ENB1

Rin

Sout

PORT2

ENA2

ENB2

Sin

Rout

outputs=High impedance

inputs = don’t care

ECA ECB

8 or 16 bits

ECA ECB

8 or 16 bits

Note that the two ports are independent so that, for example, PORT1 can operate with 8 bit enable strobes and PORT2 can operate with 16 bit enable strobes.

Figure 9 - SSI Operation

COMMAND/ADDRESS DATA INPUT/OUTPUT

A0A1A2A3A4A5X

DATA 1

SCLK

➀

Delays due to internal processor timing which are transparent to the MT9122.

➁

The MT9122:

➂

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high.

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

➃ ➄

The COMMAND/ADDRESS byte contains: 1 bit - Read/

R/W

➁

➂

latches receive data on the rising edge of SCLK outputs transmit data on the falling edge of SCLK

➄

➀

0D1D2D3D4D5D6D7

6 bits - Addressing Data 1 bit - Unused

➃

Write

Figure 10 - Serial Microport Timing for Intel Mode 0

8-31

Page 16

MT9122 Preliminary Information

COMMAND/ADDRESS DATA INPUT

DATA 2 Receive

DATA 1 Transmit

➁

SCLK

➀

Delays due to internal processor timing which are transparent to the MT9122.

➁

The MT9122:

➂

The falling edge of byte is always data followed by CS returning high.

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

➃ ➄

The COMMAND/ADDRESS byte contains: 1 bit - Read/Write

R/W

High Impedance

➂

latches receive data on the rising edge of SCLK outputs transmit data on the falling edge of SCLK

CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent

➄

➀

0A1A2A3A4A5

DATA OUTPUT

6 bits - Addressing Data 1 bit - Unused

3D4D5D6D7

Figure 11 - Serial Microport Timing for Motorola Mode 00 or National Microwire

0D1D2D3D4D5D6D7

1D2

➃

8-32

Page 17

Preliminary Information MT9122

Echo Canceller A, Control Register 1 ADDRESS = 00h WRITE/READ VERIFY

CRA1

INJDis BBM PAD AdaptDis 0

BypassReset

Extended

Delay

Power Reset Value

0000 0000

76543210

Echo Canceller B, Control Register 1 ADDRESS = 20h WRITE/READ VERIFY

CRB1

INJDis BBM PAD AdaptDis 1 0

BypassReset

Power Reset Value

0000 0010

76543210

Extended- When high, Echo Cancellers A and B are internally cascaded into one 128ms echo canceller. Delay

AdaptDis When high, echo canceller adaptation is disabled.

Bypass When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout.

PAD When high, 12dB of attenuation is inserted into the Rin to Rout path.

BBM When high the Back to Back configuration is enabled.

INJDis When high, the noise injection process is disabled. When low noise injection is enabled. Reset When high, the power-up initialization is executed presetting all register bits including this bit.

Note: Bits marked as “1” or “0” are reserved bits and should be written as indicated.

When low, Echo Cancellers A and B operate independently. Do not enable both Extended-Delay and BBM configurations at the same time.

When low, the echo canceller dynamically adapts to the echo path characteristics.

When low, output data on both Sout and Rout is a function of the echo canceller algorithm.

When low the Rin to Rout path gain is 0dB.

When low the Normal configuration is enabled. Do not enable Extended-Delay and BBM configurations at the same time. Always set both BBM bits of the two echo cancellers to the same logic value to avoid conflict.

Echo Canceller A, Control Register 2 ADDRESS = 01h WRITE/READ VERIFY Echo Canceller B, Control Register 2 ADDRESS = 21h WRITE/READ VERIFY

CR2

PHDis NLPDis AutoTD

NBDisTDis

HPFDis

MuteS MuteR

Power Reset Value

0000 0000

76543210

MuteR When high, data on Rout is muted to quiet code. When low, Rout carries active code. MuteS When high, data on Sout is muted to quiet code. When low, Sout carries active code. HPFDis When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths.

NBDis When high, the narrow-band detector is disabled. When low, the narrow-band detector is enabled. AutoTD When high, the echo canceller is in Bypass mode when the tone detectors detect the presence of 2100Hz tones. See PHDis

NLPDis When high, the non-linear processor is disabled.

PHDis When high, the tone detectors will trigger upon the presence of a 2100Hz tone regardless of the presence/absence of periodic

TDis When high, tone detection is disabled entirely. When low, tone detection is enabled.

When low, the offset nulling filters are active and will remove DC offsets on PCM input signals.

for qualification of 2100Hz tones. When low, the echo canceller algorithm will remain operational regardless of the state of the 2100Hz tone detectors.

When low, the non-linear processors function normally. Useful for G.165 conformance testing.

phase reversals. When low, the tone detectors will trigger only upon the presence of a 2100Hz tone with periodic phase reversals.

Echo Canceller A, Status Register ADDRESS = 02h READ Echo Canceller B, Status Register ADDRESS = 22h READ

TD DTDet Conv Active TDG NB

Down

Power Reset Value

0000 0000

76543210

NB Logic high indicates the presence of a narrow-band signal on Rin. TDG Tone detection status bit gated with the AutoTD bit.

Active Logic high indicates that the power level on Rin is above the threshold level (i.e., low power condition). Down Decision indicator for the non-linear processor gain adjustment. Conv Decision indicator for rapid adaptation convergence. Logic high indicates a rapid convergence state. DTDet Logic high indicates the presence of a double-talk condition. TD Logic high indicates the presence of a 2100Hz tone.

Logic high indicates that AutoTD has been enabled and the tone detector has detected the presence of a 2100Hz tone.

8-33

Page 18

MT9122 Preliminary Information

Echo Canceller A, Flat Delay Register ADDRESS = 04h WRITE/READ VERIFY Echo Canceller B, Flat Delay Register ADDRESS = 24h WRITE/READ VERIFY

Power Reset Value

76543210

Echo Canceller A, Decay Step Number Register ADDRESS = 07h WRITE/READ VERIFY Echo Canceller B, Decay Step Number Register ADDRESS = 27h WRITE/READ VERIFY

76543210

Echo Canceller A, Decay Step Size Control Register ADDRESS = 06h WRITE/READ VERIFY Echo Canceller B, Decay Step Size Control Register ADDRESS = 26h WRITE/READ VERIFY

SSC

0000

SSC

SSC1SSC

76543210

00h

Power Reset Value

00h

Power Reset Value

04h

Note: Bits marked with “0” are reserved bits and should be written “0”.

Amplitude of MU

FIR Filter Length (512 or 1024 taps)

1.0 Step Size (SS)

Flat Delay (FD

-16

7-0

)

Time

Number of Steps (NS

7-0

)

The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS adaptation step-size (MU) to be programmed over the length of the FIR ﬁlter. A programmable MU proﬁle allows the performance of the echo canceller to be optimized for speciﬁc applications. For example, if the characteristic of the echo response is known to have a ﬂat delay of several milliseconds and a roughly exponential decay of the echo impulse response, then the MU proﬁle can be programmed to approximate this expected impulse response thereby improving the convergence characteristics of the adaptive ﬁlter. Note that in the following register descriptions, one tap is equivalent to 125µs (64ms/512 taps).

7-0

Flat Delay: This register deﬁnes the ﬂat delay of the MU proﬁle, (i.e., where the MU value is 2 as FD range of FD

x 8 taps. For example; if FD

7-0

is: 0 <= FD

7-0

is zero.

7-0

= 5, then MU=2

<= 64 in normal mode and 0 <= FD

7-0

-16

for the ﬁrst 40 taps of the echo canceller FIR ﬁlter. The valid

<= 128 in extended-delay mode. The default value of

7-0

-16

). The delay is deﬁned

SSC

8-34

7-0

Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay of MU. The

2-0

decay rate is deﬁned as a decrease of MU by a factor of 2 every SS taps of the FIR ﬁlter, where SS = 4 x2 example; If SSC

is 04h.

= 4, then MU is reduced by a factor of 2 every 64 taps of the FIR ﬁlter. The default value of SSC

2-0

Decay Step Number: This register defines the number of steps to be used for the decay of MU where each step has a period of SS taps (see SSC

Filter Length (512 or 1024) - [ Decay Step Number (NS

For example, if NS 256 taps for a filter length of 512 taps.

=4 and SSC

7-0

). The start of the exponential decay is defined as:

2-0

=4, then the exponential decay start value is 512 - [NS

2-0

) x Step Size (SS) ] where SS = 4 x2

7-0

SSC

2-0

x SS] = 512 - [4 x (4x24)] =

7-0

SSC

2-0

. For

2-0

Page 19

Preliminary Information MT9122

Echo Canceller A, Rin Peak Detect Register 2 ADDRESS = 0Dh READ Echo Canceller B, Rin Peak Detect Register 2 ADDRESS = 2Dh READ

Power Reset Value

76543210

Echo Canceller A, Rin Peak Detect Register 1 ADDRESS = 0Ch READ Echo Canceller B, Rin Peak Detect Register 1 ADDRESS = 2Ch READ

76543210

These peak detector registers allow the user to monitor the receive in signal (Rin) peak signal lev el. The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1.

Echo Canceller A, Sin Peak Detect Register 2 ADDRESS = 0Fh READ Echo Canceller B, Sin Peak Detect Register 2 ADDRESS = 2Fh READ

N/A

Power Reset Value

N/A

Power Reset Value

N/A

76543210

Echo Canceller A, Sin Peak Detect Register 1 ADDRESS = 0Eh READ Echo Canceller B, Sin Peak Detect Register 1 ADDRESS = 2Eh READ

Power Reset Value

N/A

76543210

These peak detector registers allow the user to monitor the send in signal (Sin) peak signal level. The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1.

Echo Canceller A, Error Peak Detect Register 2 ADDRESS = 11h READ Echo Canceller B, Error Peak Detect Register 2 ADDRESS = 31h READ

Power Reset Value

N/A

76543210

Echo Canceller A, Error Peak Detect Register 1 ADDRESS = 10h READ Echo Canceller B, Error Peak Detect Register 1 ADDRESS = 30h READ

Power Reset Value

N/A

76543210

These peak detector registers allow the user to monitor the error signal peak level. The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1.

8-35

Page 20

MT9122 Preliminary Information

Echo Canceller A, Double-Talk Detection Threshold Register 2 ADDRESS = 15h WRITE/READ VERIFY Echo Canceller B, Double-Talk Detection Threshold Register 2 ADDRESS = 35h WRITE/READ VERIFY

Power Reset Value

DTDT

DTDT15DTDT14DTDT13DTDT

DTDT

DTDT10DTDT9DTDT

76543210

Echo Canceller A, Double-Talk Detection Threshold Register 1 ADDRESS = 14h WRITE/READ VERIFY Echo Canceller B, Double-Talk Detection Threshold Register 1

DTDT

DTDT7DTDT6DTDT5DTDT

DTDT

DTDT2DTDT1DTDT

ADDRESS = 34h WRITE/READ VERIFY

76543210

This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s complement linear value defaults to 4800h= 0.5625 or -5dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in Register 1.

Echo Canceller A, Non-Linear Processor Threshold Register 2 ADDRESS = 19h WRITE/READ VERIFY Echo Canceller B, Non-Linear Processor Threshold Register 2 ADDRESS = 39h WRITE/READ VERIFY

48h

Power Reset Value

00h

Power Reset Value

NLPTHR

NLP15NLP

NLP

08h

76543210

Echo Canceller A, Non-Linear Processor Threshold Register 1 ADDRESS = 18h WRITE/READ VERIFY Echo Canceller B, Non-Linear Processor Threshold Register 1 ADDRESS = 38h WRITE/READ VERIFY

Power Reset Value

NLPTHR

NLP7NLP

NLP5NLP

NLP

00h

76543210

This register allows the user to program the lev el of the Non-Linear Processor Threshold (NLPTHR). The 16 bit 2’s complement linear value defaults to 0800h = 0.0625 or -24.1dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in Register 1.

Echo Canceller A, Adaptation Step Size (MU) Register 2 ADDRESS = 1Bh WRITE/READ VERIFY Echo Canceller B, Adaptation Step Size (MU) Register 2 ADDRESS = 3Bh WRITE/READ VERIFY

Power Reset Value

40h

76543210

Echo Canceller A, Adaptation Step Size (MU) Register 1 ADDRESS = 1Ah WRITE/READ VERIFY Echo Canceller B, Adaptation Step Size (MU) Register 1 ADDRESS = 3Ah WRITE/READ VERIFY

Power Reset Value

76543210

This register allows the user to program the level of MU. MU is a 16 bit 2’s complement value which defaults to 4000h = 1.0 The high byte is in Register 2 and the low byte is in Register 1.

8-36

00h

Page 21

Preliminary Information MT9122

echo paths

MT8910 2B1Q MT8972 Bi-Phase MT8931 S-INT

MT9122

DSTo

T R

DSTi

F0b

C4o

Sin

Rout

Sout

ENA ENB

BCLK

Rin

MT9125 ADPCM

DSTi

EN1 EN2 C20

DSTo

F0i MCLK

ADPCMo

ADPCMi

Din Dout

BCLK STB1

Dual RF Section

Figure 12 - (Basic Rate ISDN) Wireless Application Diagram

MT9122 is in SSI mode

MT9160 5V CODEC

Dout

MT9122 is in SSI mode

echo path

T R

echo path

MT8941 PLL

Din

Clockin

MT9160 5V CODEC

Clockin

F0i

Dout

Din

F0i

Figure 13 - (Analog Trunk) Wireless Application Diagram

Sin

Rout

MT9122

Sout

ENA ENB

BCLK

Rin

MT9125 ADPCM

DSTi

EN1 EN2

C20 DSTo

F0i

ADPCMo

ADPCMi

MCLK

Din Dout

BCLK STB1

Dual RF Section

8-37

Page 22

MT9122 Preliminary Information

T R

echo

path

T R

echo path

MT8941 PLL

MT9160 5V CODEC

Clockin

MT9160 5V CODEC

Clockin

F0i

Dout

Din

F0i

Dout

Din

MT9122 connected in ST-BUS mode 1

MT9122

Sin

Rout

F0i C4i

Sout

Rin

MT9125 ADPCM

DSTi

DSTo

ADPCMo

ADPCMi

C20 BCLK

EN1

F0i MCLK

Din Dout

STB1

Dual RF Section

echo path

Figure 14 - (Analog Trunk) Wireless Application Diagram

MT9122 in ST-BUS mode 1 Back-To-Back Configuration

using D&C channel bypass

MT8910 2B1Q MT8972 Bi-phase MT8931 S-INT

MT9122

C4o

DSTo

DSTi

F0b

T R

Sin

Rout Rin

F0i C4i

Sout

MT909x Digital Phone

DSTi

DSTo

F0i MCLK

Figure 15 - (Basic Rate ISDN) Wired Telephone Application Diagram

Handset

8-38

Page 23

Preliminary Information MT9122

Absolute Maximum Ratings*

Parameter Symbol Min Max Units

1 Supply Voltage VDD-V 2 Voltage on any digital pin V 3 Continuous Current on any digital pin I 4 Storage Temperature T 5 Package Power Dissipation P

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

i/o

Recommended Operating Conditions - Voltages are with respect to ground (V

-0.3 7.0 V

VSS-0.3 VDD+ 0.3 V

-65 150 °C

) unless otherwise stated.

Characteristics Sym Min Typ‡Max Units Test Conditions

1 Supply Voltage V

2 TTL Input High Voltage 2.4 V 3 TTL Input Low Voltage V 4 CMOS Input High Voltage 4.5 V 5 CMOS Input Low Voltage V 6 Operating Temperature T

‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

DC Electrical Characteristics* - Voltages are with respect to ground (V

Characteristics Sym Min Typ

4.5 5.0 5.5 V

-40 +85 °C

‡

V 400mV noise margin

0.4 V 400mV noise margin

0.5 V

) unless otherwise stated.

Max Units Conditions/Notes

±20 mA

500 mW

1 Supply Current I

2 Input HIGH voltage (TTL) V 3 Input LOW voltage (TTL) V 4 Input HIGH voltage (CMOS) V 5 Input LOW voltage (CMOS) V 6 Input leakage current IIH/I 7 High level output voltage V 8 Low level output voltage V

9 High impedance leakage I 10 Output capacitance C 11 Input capacitance C

CC DD

IH IL

IHC

ILC

2.0 V All except MCLK,Sin,Rin

3.5 V MCLK,Sin,Rin

0.9V

0.1 10 µAVIN=VSS to V

110µAVIN=VSS to V

10 pF

8pF

100 µAmAPWRDN = 0

PWRDN = 1, clocks active

0.8 V All except MCLK,Sin,Rin

1.5 V MCLK,Sin,Rin

VIOH=2.5mA

0.1V

VIOL=5.0mA

12 PWRDN

Positive Threshold Voltage Hysteresis Negative Threshold Voltage

‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * DC Electrical Characteristics are over recommended temperature and supply voltage.

V+ V

V-

3.75

1.0

1.25

V V V

8-39

Page 24

MT9122 Preliminary Information

AC Electrical Characteristics† - Serial Data Interfaces (see Figures 17 and 18)

Voltages are with respect to ground (VSS) unless otherwise stated.

Characteristics Sym Min Max Units Test Notes

1 MCLK Clock High t 2 MCLK Clock Low t 3 MCLK Frequency

Dual Channel Single Channel

4 BCLK/C4i Clock High t

5 BCLK/C4i Clock Low t

6 BCLK/C4i Period t 7 SSI Enable Strobe to Data Delay (ﬁrst

bit)

8 SSI Data Output Delay (excluding ﬁrst

bit)

9 SSI Output Active to High Impedance t

10 SSI Enable Strobe Signal Setup t

11 SSI Enable Strobe Signal Hold t

MCH MCL

DCLK

SCLK

BCH,

C4H

BLL,

C4L

BCP

AHZ

SSS

SSH

20 ns 20 ns

19.15

20.5 MHz

9.58 90 ns

90 ns

240 7900 ns

80 ns CL=150pF

10 t

BCP

-15

15 t

BCP

-10

MHz

12 SSI Data Input Setup t 13 SSI Data Input Hold t 14 F0i Setup t 15 F0i Hold t 16 ST-BUS Data Output delay t 17 ST-BUS Output Active to High

DIS

DIH F0iS F0iH DSD

ASHZ

Impedance 18 ST-BUS Data Input Hold time t 19 ST-BUS Data Input Setup time t 20 F0od Delay t 21 F0od Pulse Width Low t

† Timing is over recommended temperature and power supply voltages.

DSH DSS DFD

DFW

10 ns 15 ns 20 150 ns 20 150 ns

80 ns CL=150pF 80 ns CL=150pF

20 ns 20 ns

80 ns CL=150pF

200 ns CL=150pF

8-40

Page 25

Preliminary Information MT9122

AC Electrical Characteristics† - Microport Timing (see Figure 17)

Characteristics Sym Min Max Units Test Notes

1 Input Data Setup t 2 Input Data Hold t 3 Output Data Delay t 4 Serial Clock Period t 5 SCLK Pulse Width High t 6 SCLK Pulse Width Low t 7 CS Setup-Intel t 8 CS Setup-Motorola t 9 CS Hold t

10 CS to Output High Impedance t

† Timing is over recommended temperature range and recommended power supply voltages.

IDS

IDH

ODD

SCP

SCH

SCL

CSSI

CSSM

CSH

OHZ

100 ns

30 ns

100 ns CL=150pF 500 ns 250 ns 250 ns 200 ns 100 ns 100 ns

100 ns CL=150pF

Characteristic Symbol TTL Pin CMOS Pin Units

TTL reference level V CMOS reference level V Input HIGH level V

1.5 - V

- 0.5*V

2.4 0.9*V

V Input LOW level V Rise/Fall HIGH measurement point V Rise/Fall LOW measurement point V

Table 8 - Reference Level Deﬁnition for Timing Measurements

MCH

MCLK

(3)

Figure 16 Master Clock - MCLK

Notes: 1. CMOS output

2. TTL input compatible

3. CMOS input (see Table 8 for symbol deﬁnitions)

0.4 0.1*V

2.0 0.7*V

0.8 0.3*V

MCL

8-41

Page 26

MT9122 Preliminary Information

Bit 0 Bit 1

Sout/Rout

(1)

(2)

BCLK

ENA1/ENA2 or ENB1/ENB2

(3)

Rin/Sin

Notes: 1. CMOS output

2. TTL input compatible

3. CMOS input (see Table 8 for symbol deﬁnitions)

Sout/Rout

(1)

SSS

BCP

BCH

DIS

BCL

DIH

SSH

AHZ

Bit 0 Bit 1

Figure 17 - SSI Data Port Timing

Bit 0 Bit 1

(2)

C4i

(2)

F0i

Rin/Sin

F0od

(3)

(1)

Notes: 1. CMOS output

2. TTL input compatible

3. CMOS input (see Table 8 for symbol deﬁnitions)

F0iStF0iH

DSD

C4H

C4L

DSStDSH

Bit 0 Bit 1

Figure 18 - ST-BUS Data Port Timing

DFD

DFW

ASHZ

8-42

Page 27

Preliminary Information MT9122

(1, 2)

DATA1

SCLK

(2)

(

Notes: 1. CMOS output

2. TTL input compatible

3. CMOS input (see Table 8 for symbol deﬁnitions)

(2)

DATA2 (Input)

DATA INPUT

IDStIDH

CSSI

SCL

SCH

DATA OUTPUT

ODD

SCP

CSH

OHZ

VTT,V

Figure 19 - INTEL Serial Microport Timing

IDStIDH

SCH

SCP

(2)

SCLK

(2)

(1)

DATA1 (Output)

Notes: 1. CMOS output

2. TTL input compatible

3. CMOS input (see Table 8 for symbol deﬁnitions)

CSSM

SCL

ODD

CSH

OHZ

Figure 20 - MOTOROLA Serial Microport Timing

8-43

Page 28

MT9122 Preliminary Information

Notes:

8-44

Page 29

Package Outlines

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

n-2 n-1 n

Plastic Dual-In-Line Packages (PDIP) - E Sufﬁx

8-Pin 16-Pin 18-Pin 20-Pin

DIM

Plastic Plastic Plastic Plastic

Min Max Min Max Min Max Min Max

C D

NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.

0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95)

0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)

0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77)

0.008

(0.203)

0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9)

0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)

0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26)

0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11)

0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)

0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62)

0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81)

0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52)

0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33)

0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356)

0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92)

General-8

Page 30

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

Package Outlines

n-2 n-1 n

Plastic Dual-In-Line Packages (PDIP) - E Sufﬁx

DIM

C D

E E

22-Pin 24-Pin 28-Pin 40-Pin

Plastic Plastic Plastic Plastic

Min Max Min Max Min Max Min Max

0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35)

0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95)

0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)

0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77)

0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381)

1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2)

0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)

0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02)

0.290 (7.37) .330 (8.38)

0.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73)

0.246 (6.25) 0.254 (6.45)

0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)

0.400 BSC (10.16) 0.600 BSC (15.24) 0.600 BSC (15.24) 0.600 BSC (15.24)

0.300 BSC (7.62)

0.430 (10.92)

0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 15° 15° 15° 15°

Shaded areas for 300 Mil Body Width 24 PDIP only

Page 31

Package Outlines

e: (lead coplanarity)

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

4) For D & E add for allowable Mold Protrusion 0.010"

Dim

D/E

D1/E

D2/E

20-Pin 28-Pin 44-Pin 68-Pin 84-Pin

Min Max Min Max Min Max Min Max Min Max

0.165 (4.20)

0.090

(2.29)

0.385 (9.78)

0.350

(8.890)

0.290

(7.37)

0.026

(0.661)

0.013

(0.331)

0.020 (0.51)

0.180

(4.57)

0.120

(3.04)

0.395

(10.03)

0.356

(9.042)

0.330

(8.38)

0 0.004 0 0.004 0 0.004 0 0.004 0 0.004

0.032

(0.812)

0.021

(0.533)

0.050 BSC (1.27 BSC)

0.165

(4.20)

0.090

(2.29)

0.485

(12.32)

0.450

(11.430)

0.390

(9.91)

0.026

(0.661)

0.013

(0.331)

0.050 BSC (1.27 BSC)

0.020

(0.51)

0.180 (4.57)

0.120 (3.04)

0.495

(12.57)

0.456

(11.582)

0.430

(10.92)

0.032

(0.812)

0.021

(0.533)

0.165 (4.20)

0.090 (2.29)

0.685

(17.40)

0.650

(16.510)

0.590

(14.99)

0.026

(0.661)

0.013

(0.331)

0.050 BSC (1.27 BSC)

0.020 (0.51)

0.180

(4.57)

0.120

(3.04)

0.695

(17.65)

0.656

(16.662)

0.630

(16.00)

0.032

(0.812)

0.021

(0.533)

0.165 (4.20)

0.090 (2.29)

0.985

(25.02)

0.950

(24.130)

0.890

(22.61)

0.026

(0.661)

0.013

(0.331)

0.050 BSC (1.27 BSC)

0.020 (0.51)

0.200

(5.08)

0.130

(3.30)

0.995

(25.27)

0.958

(24.333)

0.930

(23.62)

0.032

(0.812)

0.021

(0.533)

(30.10)

(29.210)

(27.69)

(0.661)

(0.331)

0.165 (4.20)

0.090 (2.29)

1.185

1.150

1.090

0.026

0.013

0.050 BSC (1.27 BSC)

0.020 (0.51)

0.200

(5.08)

0.130

(3.30)

1.195

(30.35)

1.158

(29.413)

1.130

(28.70)

0.032

(0.812)

0.021

(0.533)

General-10

Plastic J-Lead Chip Carrier - P-Sufﬁx

Page 32

http://www.mitelsemi.com

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Tel: +1 (613) 592 2122

Fax: +1 (613) 592 6909

North America Asia/Paciﬁc Europe, Middle East,

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Fax: +1 (770) 631 8213 Fax: +65 333 6192 Tel: +44 (0) 1793 518528

Fax: +44 (0) 1793 518581

Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever. Purchasers of products are also hereby notiﬁed that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or other intellectual property rights owned by Mitel.

This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their speciﬁcations, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speciﬁc piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in signiﬁcant injury or death to the user. All products and materials are sold and services provided subject to Mitel’s conditions of sale which are available on request.

TECHNICAL DOCUMENTATION - NOT FOR RESALE

Datasheet MT9122AE, MT9122AP Datasheet (MITEL)

Specifications and Main Features

Frequently Asked Questions

User Manual