Datasheet M48T201Y-70MH1, M48T201Y, M48T201V Datasheet (SGS Thomson Microelectronics)

3.3V-5V TIMEKEEPERCONTROLLER

■ CONVERTS LOW POWER SRAMs into

NVRAMs

■ YEAR 2000 COMPLIANT

■ BATTERY LOW FLAG

■ INTEGRATED REAL TIME CLOCK,

POWER-FAIL CONTROL CIRCUIT,
BATTERY and CRYSTAL

■ WATCHDOG TIMER

■ WRITE PROTECT VOLTAGES

(V

= Power-fail Deselect Voltage):

PFD

– M48T201Y: 4.1V ≤ V
– M48T201V: 2.7V ≤ V

■ PACKAGING INCLUDESa44-LEADSOIC and

SNAPHATTOP
(to beOrdered Separately)

■ SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL

■ MICROPROCESSOR POWER-ON RESET

(Valid even during battery back-up mode)

■ PROGRAMMABLE ALARM OUTPUT ACTIVE

IN THE BATTERY BACKED-UP MODE

PFD
PFD

≤ 4.5V
≤ 3.0V

SNAPHAT (SH)

Battery/Crystal

44

1

SOH44 (MH)

Figure 1. Logic Diagram

V

CC

19

A0-A18

M48T201Y
M48T201V

8

DQ0-DQ7

DESCRIPTION

The M48T201Y/201V are self-contained devices
that include a real time clock (RTC), programma­ble alarms, a watchdog timer, and a square wave
output which provides control of up to 512K x 8 of
external low-power static RAM. Access to all RTC
functions and the external RAM is the same as
conventional bytewide SRAM. The 16 TIME­KEEPERregisters offer year, month, date, day,
hour, minute, second, calibration, alarm, century,
watchdog, andsquare waveoutput data.External­ly attached static RAMs are controlled by the
M48T201Y/201V via the G

CON

and E

CON

signals.

The 44 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con­nection to a separate SNAPHAT housing contain­ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.

WDI

W

RSTIN1

RSTIN2

IRQ/FT

M48T201Y

E

G

M48T201V

V

SS

RST

G

CON

E

CON

SQW

V

OUT

AI02240

1/24November 1999

M48T201Y, M48T201V,

Figure 2. SOIC Connections

RSTIN1
RSTIN2

RST

NC
A18
A16
A14
A12

A7
A6
A5
A4
A3
A2
A1
A0

WDI

G

CON

DQ0
DQ1
DQ2 21

V

SS

1
2
3
4
5
6
7
8
9
10
11

M48T201Y

12

M48T201V

13
14
15
16
17
18
19
20

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
2322

AI02241

V

CC

V

OUT

SQW
IRQ/FT
A17
A15
A13
A8
A9
A11
G
W
NC
A10
E
E

CON

DQ7
DQ6
DQ5
DQ4
DQ3
NC

Table 1. Signal Names

A0-A18 Address Inputs

DQ0-DQ7 Data Inputs / Outputs
RSTIN1 Reset 1 Input

RSTIN2 Reset 2 Input

RST Reset Output (Open Drain)

WDI Watchdog Input

E Chip Enable Input

G Output Enable Input

W Write Enable Input

E

CON

G

CON

IRQ/FT

SQW

V

OUT

V

CC

V

SS

RAM Chip Enable Output

RAM Enable Output

Interrupt / Frequency Test Output
(Open Drain)

Square Wave Output

Supply Voltage Output

Supply Voltage

Ground

Insertion of the SNAPHAT housing after reflow
prevents potential battery damage due to the high
temperatures required for device surface-mount­ing. TheSNAPHAT housing iskeyedto preventre­verse insertion. The SOIC and battery packages
are shipped separately in plastic anti-static tubes
or in Tape & Reel form. For the 44 lead SOIC, the
battery/crystal package (i.e. SNAPHAT) part num­ber is ”M4Txx-BR12SH1” (See Table 14).

Caution: Do not place the SANPHAT battery/crys­tal top in conductive foam,as this will drain the lith­ium button-cell battery.

Automatic backup and write protection for an ex­ternal SRAMis provided through V
G

pins. (Users are urged to insurethat voltage

CON

OUT,ECON

, and

specifications, for both the controller chip and ex­ternal SRAM chosen, are similar.) The SNAPHAT
containing the lithium energy source used to per­manently power the real time clock is also used to
retain RAM data in the absence of VCCpower

2/24

NC Not Connected Internally

through the V
RAM (E
(G

CON

) andthe output enableoutput to RAM

CON

) are controlled during power transients to

pin. The chip enable output to

OUT

prevent data corruption. The date is automatically
adjusted for months with less than 31 days and
corrects for leap years. The internal watchdog tim­er provides programmable alarm windows.

The nine clock bytes (7FFFFh-7FFF9h and
7FFF1h) are not the actual clock counters, they
are memory locations consisting of BiPORT
read/write memory cells within the static RAM ar­ray. Clock circuitry updates the clock bytes with
current informationonce per second. The informa­tion canbe accessedby theuser inthe same man­ner as any other location in the static memory
array. Byte 7FFF8h is the clock control register.
This byte controls user access to the clock infor­mation and also stores the clock calibration set­ting.

M48T201Y, M48T201V,

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A

T

STG

T

SLD

V

IO

V

CC

I

O

P

D

Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoiddamaging SNAPHATsockets.

Table 3. Operating Modes

Mode

Deselect
Write
Read
Read

Deselect
Deselect

Note: 1. X = VIHor VIL.

2. V

Ambient Operating Temperature 0 to 70 °C

Storage Temperature (VCCOff,Oscillator Off)

(2)

Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages

Supply Voltage

SNAPHAT –40 to 85 °C
SOIC –55 to 125 °C

–0.3 to V

CC

+0.3

V
M48T201Y –0.3 to 7.0 V
M48T201V –0.3 to 4.6 V

Output Current 20 mA
Power Dissipation 1 W

rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.

(1)

V

CC

4.5V to 5.5V
or

3.0V to 3.6V

to V

V

SO

PFD

≤ V

SO

= Battery Back-up Switchover Voltage. (See Tables 6A and 6B for details).

SO

(min)

(2)

(2)

E G W DQ0-DQ7 Power

V

IH

V

IL

V

IL

V

IL

X X High Z Standby
X

V

IL

V

IH

V

IL

V

IH

V

IH

D

D

OUT

IN

Active
Active

High Z Active

X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode

Byte 7FFF7h contains the watchdog timer setting.
The watchdog timer can generate either a reset or
an interrupt, depending on the state of the Watch­dog Steering bit (WDS). Bytes 7FFF6h - 7FFF2h
include bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
date, hours, minutes, and seconds of the clock
registers. Byte 7FFF1h contains century informa­tion. Byte7FFF0h containsadditionalflag informa­tion pertaining to the watchdog timer, the alarm
condition, the battery statusand square wave out­put operation. 4-bits are included within this regis-

ter (RS0-RS3) that are used to program the
Square Wave Output Frequency (see Table 11).
The M48T201Y/V also has its own Power-Fail De­tect circuit. This control circuitry constantly moni­tors the supply voltage for an out of tolerance
condition. When VCCis out of tolerance,the circuit
write protects the TIMEKEEPER register data and
external SRAM, providing data security in the
midst of unpredictable system operation. As V

CC

falls, the control circuitry automatically switchesto
the battery, maintaining data and clock operation
until valid power is restored.

3/24

M48T201Y, M48T201V,

Figure 3. Block Diagram

0.1µF

5V

32,768

Hz

CRYSTAL

LITHIUM

CELL

M48T201Y/V

V

CC

E
W
G
WDI
RSTIN1
RSTIN2
V

SS

A0-A18

IRQ/FT

DQ0-DQ7

V

OUT

ECON

GCON

RST

SQW

0.1µF

V

E
W
G

V

A0-Axx

CC

CMOS
SRAM

SS

DQ0-DQ7

AI00604

Figure 4. AC Testing Load Circuit

DEVICE
UNDER

TEST

CLincludes JIG capacitance

Note: Excluding open-drain output pin.

4/24

645Ω

CL= 100pF

1.75V

AI02330

Table 4. AC Measurement Conditions

Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref.Voltages 1.5V

Note that Output Hi-Z is defined asthe point wheredata isnolonger
driven.

Address Decoding

The M48T201Y/V accommodates 19 address
lines (A0-A18) which allow direct connection of up
to 512K bytesof static RAM. Regardless of SRAM
density used, timekeeping, watchdog, alarm, cen­tury, flag, and control registers are located in the
upper RAM locations. All TIMEKEEPER registers
reside in the upper RAM locations without conflict
by inhibiting the G

(output enable RAM) signal

CON

during clock access. TheRAM’s physical locations
are transparent to the user and the memory map
looks continuousfrom thefirst clock address to the
upper most attached RAM addresses.

M48T201Y, M48T201V,

Table 5. Capacitance

(1)

(TA=25°C, f = MHz)

Symbol Parameter Test Condition Min Max Unit

C

IN

C

IO

Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.

2. Outputs deselected.

Input Capacitance

(2)

Input / Output Capacitance

V

V

OUT

IN

=0V

=0V

10 pF
10 pF

Table 6A. DC Characteristics

(TA= 0 to 70 °C; VCC= 3.0V to 3.6V)

Symbol Parameter Test Condition Typ Min Max Unit

(1, 2)

I

LI

I

LO

I
I

I

Input Leakage Current 0V ≤ VIN≤ V

(1)

Output Leakage Current

I

Supply Current Outputs open 4 10 mA

CC

Supply Current (Standby) TTL

CC1

Supply Current (Standby) CMOS

CC2

Battery Current OSC ON 575 800 nA

BAT

Battery Current OSC OFF 100 nA

V

Input Low Voltage –0.3 0.8 V

IL

V

Input High Voltage 2.0

IH

Output Low Voltage IOL= 2.1mA 0.4 V

V

OL

Output Low Voltage (open drain)

V

V

OHB

I

OUT1

I

OUT2VOUT

V

V

V

Note: 1. Outputs deselected.

Output High Voltage

OH

(4)

VOH(Battery Back-Up) I

(5)

V

Current (Active) V

OUT

Current (Battery Back-Up) V

Power Fail Deselect 2.9 2.7 3.0 V

PFD

Battery Back-Up Switchover

SO

Battery Voltage 3.0 V

BAT

2. RSTIN1 andRSTIN2 internally pulled-up to V

3. For IRQ/FT, RST pins (Open Drain).

4. Conditioned outputs (E
Higher leakage currents will reduce battery life.

5. External SRAM must match TIMEKEEPER Controller chip V

CON

and G

(3)

) can only sustain CMOS leakage current in the battery back-up mode.

CON

CC

0V ≤ V

E=V

OUT

E=V

CC

≤ V

IH

–0.2V

CC

IOL= 10.0mA

I

= –1.0mA

OH

= –1.0µA

OUT2

OUT1>VCC

OUT2>VBAT

–0.3

–0.3 100 µA

V

–

PFD

2.4 V

2.0 3.6 V

100mV

through 100KΩ resistor. WDI internally pulled-down to VSSthrough 100KΩ resistor.

CC

specification.

CC

±1 µA
±1 µA

3mA
2mA

V

+ 0.3

CC

0.4 V

70 mA

V

V

5/24

M48T201Y, M48T201V,

Table 6B. DC Characteristics

(TA= 0 to 70 °C; VCC= 4.5V to 5.5V)

Symbol Parameter Test Condition Typ Min Max Unit

(1, 2)

I

LI

I

LO

I
I

I

Input Leakage Current

(1)

Output Leakage Current

I

Supply Current Outputs open 8 15 mA

CC

Supply Current (Standby) TTL

CC1

Supply Current (Standby) CMOS

CC2

Battery Current OSC ON 575 800 nA

BAT

Battery Current OSC OFF 100 nA

V

Input Low Voltage –0.3 0.8 V

IL

V

Input High Voltage 2.2

IH

Output Low Voltage

V

OL

Output Low Voltage (open drain)

V

V

OHB

I

OUT1

I

OUT2VOUT

V

V

V

Note: 1. Outputs deselected.

Output High Voltage

OH

(4)

VOH(Battery Back-Up) I

(5)

V

Current (Active) V

OUT

Current (Battery Back-Up) V

Power Fail Deselect 4.35 4.1 4.5 V

PFD

Battery Back-Up Switchover 3.0 V

SO

Battery Voltage 3.0 V

BAT

2. RSTIN1 andRSTIN2 internally pulled-up to V

3. For IRQ/FT, RST pins (Open Drain).

4. Conditioned outputs (E
Higher leakage currents will reduce battery life.

5. External SRAM must match TIMEKEEPER Controller chip V

CON

and G

) can only sustain CMOS leakage current in the battery back-up mode.

CON

0V ≤ V

0V ≤ V

E=V

(3)

IOL= 10.0mA

I

OUT2

OUT1>VCC

OUT2>VBAT

through 100KΩ resistor. WDI internally pulled-down to VSSthrough 100KΩ resistor.

CC

I

OL

E=V

≤ V

IN

≤ V

OUT

IH

–0.2V

CC

= 2.1mA

CC

CC

±1 µA
±1 µA

5mA
3mA

V

+ 0.3

CC

0.4 V

0.4 V

= –1.0mA

OH

2.4 V

= –1.0µA2.03.6V

–0.3

–0.3

specification.

CC

100 mA
100 µA

V

6/24

Figure 5. Power Down/Up Mode AC Waveforms

V

CC

V

(max)

PFD

V

(min)

PFD

V

SO

tF

tFB

M48T201Y, M48T201V,

tR

tRECtRB

INPUTS

OUTPUTS

RST

VALID VALID

VALID VALID

Table 7. Power Down/Up Trip Points DC Characteristics

DON’T CARE

HIGH-Z

(1)

(TA= 0 to 70 °C)

Symbol Parameter Min Max Unit

t

t

t

REC

t

FB

t

RB

F

R

V

(max) to V

PFD

V

(min) to VSSVCCFall Time

PFD

V

(min) to V

PFD

VSSto V
V

(max) to RST High

PFD

PFD

PFD

(min) VCCRise Time 5 µs

PFD

(min) VCCFallTime

(max) VCCRise Time

300 µs
M48T201Y 10 µs
M48T201V 150 µs

10 µs

40 200 ms

AI03519

7/24

M48T201Y, M48T201V,

Figure 6. G

Timing When Switching Between RTC and External SRAM

CON

ADDRESS

G

G

CON

E

00000h - 7FFEFh 7FFF0h - 7FFFFh 00000h - 7FFEFh7FFF0h - 7FFFFh

Table 8. Read Mode AC Characteristics

(TA= 0 to 70 °C)

Symbol Parameter

tAOEL

tAOEH tOERL tRO

AI02333

M48T201Y M48T201V

Unit-70 -85

Min Max Min Max

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

t

AXQX

t

AOEL

t

AOEH

t

EPD

t

OERL

t

RO

Read Cycle Time 70 85 ns
Address Valid to Output Valid 70 85 ns
Chip Enable Low to Output Valid 70 85 ns
Output Enable Low to Output Valid 25 35 ns
Chip Enable Low to Output Transition 5 5 ns
Output Enable Low to Output Transition 0 0 ns
Chip Enable High to Output Hi-Z 20 25 ns
Output Enable High to Output Hi-Z 20 25 ns
Address Transition to Output Transition 5 5 ns
External SRAM Address to G
Controller SRAM Address to G
EtoE
G Low to G
G High to G

Low or High 10 15 ns

CON

Low

CON

High

CON

Low 20 30 ns

CON

CON

High

20 30 ns

15 20 ns
10 15 ns

8/24

Figure 7. Read Cycle Timing: RTC & External RAM Control Signals

M48T201Y, M48T201V,

ADDRESS

E

G

G

CON

E

CON

tEPD

W

DQ0-DQ7

READ READ WRITE

tAVAV

tELQV

tELQX

tGLQV

DATA OUT

tAVAV tAVAV

tAVQV tWHAXtAVWL

tAXQXtGLQX

VALID

tRO

tWLWH

DATA OUT

VALID

tGHQZ

DATA IN

VALID

AI02334

READ MODE

The M48T201Y/V executes a read cycle whenev­er W (Write Enable) is high and E (ChipEnable) is
low. The unique address specified by the address
inputs (A0-A18) defines which one of the on-chip
TIMEKEEPER registers or external SRAM loca­tions is to be accessed. When the address pre­sented to the M48T201Y/V is in the range of
7FFFFh-7FFF0h, one of the on-board TIME­KEEPER registers is accessed and valid data will
be available to the eight data output drivers within
t

after the address input signal is stable, pro-

AVQV

viding that the E and G access times are also sat-

isfied. If they are not, then data access must be
measured from the latter occurring signal (E or G)
and the limiting parameter is either t
t

for G rather than the address access time.

GLQV

ELQV

forE or

When one of the on-chip TIMEKEEPER registers
is selectedfor read,the G

signal will remainin-

CON

active throughout the read cycle.
When the address value presented to the

M48T201Y/V is outside the range of TIMEKEEP­ER registers, an external SRAM location will be
selected. In this case the G signal will be passed
to the G
t

or t

AOEL

pin, with the specified delay times of

CON

.

OERL

9/24

M48T201Y, M48T201V,

Figure 8. Write Cycle Timing: RTC & External RAM Control Signals

ADDRESS

tAVEL

E

E

CON

G

G

CON

tAVWL

W

DQ0-DQ7

DATA OUT

VALID

WRITE WRITE READ

tAVAV

tAVEH

tELEH tEHAX

tEPD

tEPD

tRO

tWLWH

tEHQZ tDVEH

tEHDX

DATA IN

VALID

tAVAV tAVAV

tAVWH

tWHAX

tDVWH

DATA IN

VALID

tWHQX

tWHDX

tAVQV

tGLQV

DATA OUT

tWLQZ

VALID

AI02336

WRITE MODE

The M48T201Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are low
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W orE. A write is terminated bythe
earlier rising edge of W or E. The addresses must
be heldvalid throughout thecycle. E or Wmust re­turn high fora minimumof t
or t

fromWrite Enable priorto the initiation of

WHAX

fromChip Enable

EHAX

another read or write cycle. Data-in must be valid
t
t

10/24

priorto the end of write and remainvalid for

DVWH

afterward. G should be kept high during

WHDX

write cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and Ga lowon Wwill disable the outputs t

WLQZ

af-

ter W falls.
When the address value presented to the

M48T201Y/V during the write is in the range of
7FFFFh-7FFF0h, one of the on-board TIME­KEEPER registers will beselectedand data will be
written into the device. When the address value
presented to M48T201Y/V is outside the range of
TIMEKEEPER registers, an external SRAM loca­tion is selected.

Table 9. Write Mode AC Characteristics

(TA= 0 to 70 °C)

M48T201Y M48T201V

Symbol Parameter

Min Max Min Max

t

AVAV

t

AVWL

t

AVEL

t

WLWH

t

ELEH

t

WHAX

t

EHAX

t

DVWH

t

DVEH

t

WHDX

t

EHDX

t

WLQZ

t

AVWH

t

AVEH

t

WHQX

Note: 1. CL= 5pF.

2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

Write Cycle Time 70 85 ns
Address Valid to Write Enable Low 0 0 ns
Address Valid to Chip Enable Low 0 0 ns
Write Enable Pulse Width 45 55 ns
Chip Enable Low to Chip Enable High 50 60 ns
Write Enable High to Address Transition 0 0 ns
Chip Enable High to Address Transition 0 0 ns
Input Valid to Write Enable High 25 30 ns
Input Valid to Chip Enable High 25 30 ns
Write Enable High to Input Transition 0 0 ns
Chip Enable High to Input Transition 0 0 ns

(1, 2)

Write Enable Low to Output Hi-Z 20 25 ns
Address Valid to Write Enable High 55 65 ns

Address Valid to Chip Enable High 55 65 ns

(1, 2)

Write Enable High to Output Transition 5 5 ns

M48T201Y, M48T201V,

Unit-70 -85

DATA RETENTION MODE

With valid VCCapplied, the M48T201Y/V can be
accessed as described above with read or write
cycles. Should the supply voltage decay, the
M48T201Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
VCCfalls between V

(max) and V

PFD

PFD

(min).
This is accomplished by internally inhibiting ac­cess to the clock registers via the E signal. At this
time, the Reset pin (RST) is driven active and will
remain active until VCCreturns to nominal levels.
External RAM access isinhibited in a similar man­ner by forcing E
within 0.2V of the V

to a high level. This level is

CON

BAT.ECON

will remain at this
level aslong as VCCremains at anout-of tolerance
condition. When VCCfalls below the level of the
battery (V

), power input is switched from the

BAT

VCCpin to the SNAPHAT battery and the clock
registers are maintainedfrom the attached battery
supply. External RAM is also powered by the
SNAPHAT battery. All outputs except G
E

, RST, IRQ/FT and V

CON

, become high im-

OUT

CON

pedance. The V

pin is capable of supplying

OUT

100µA of current tothe attached memory with less
than 0.3V drop under this condition. On power up,
when VCCreturnsto anominal value, writeprotec­tion continues for200ms (max) by inhibitingE
The RST signal also remains active during this
time (see Figure 5).

Note: Most low power SRAMs on the market to­day can be used with the M48T201Y/V TIME­KEEPER Controller. There are, however some
criteria which should be used in making the final
choice of an SRAM to use.

The SRAM must be designed in a way where the
chip enable input disables all other inputs to the
SRAM. This allowsinputs to the M48T201Y/V and
SRAMs to be Don’t Care once VCCfalls below
V

(min). The SRAM should also guarantee

PFD

data retention down to VCC= 2.0V. The chip en­able access time must be sufficient to meet the
system needswith the chip enable (andoutput en-

,

able) output propagation delays included.

CON

11/24

.

M48T201Y, M48T201V,

Figure 9. Alarm Interrupt Reset Waveforms

A0-A18

ACTIVE FLAG BIT

IRQ/FT

Table 10. Alarm Repeat Modes

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Activated

1 1 1 1 1 Once per Second
1 1 1 1 0 Once per Minute
1 1 1 0 0 Once per Hour
1 1 0 0 0 Once per Day of Month
1 0 0 0 0 Once per Month

ADDRESS 7FFF0h

15ns Min

HIGH-Z

AI02331

If data retention lifetime is a critical parameter for
the system, it isimportant to review the datareten­tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention currentat 3.0V. Manufacturers gen­erally specify a typical condition for room temper­ature along with a worst case condition (generally
at elevated temperatures). The system level re­quirements will determine the choice of which val-

12/24

ue to use. The data retention current value of the
SRAMs can then be added to the I

value of the

BAT

M48T201Y/V to determine the total current re­quirements for data retention. The available bat­tery capacity for the SNAPHAT of your choice can
then be divided by this current to determine the
amount of data retention available (see Table 14).

For a further more detailed review of lifetime calcu­lations, please see Application Note AN1012.

Figure 10. Back-Up Mode Alarm Waveform

V

CC

V

(max)

PFD

V

(min)

PFD

V

SO

AFE bit/ABE bit

AF bit in Flags Register

IRQ/FT

M48T201Y, M48T201V,

tREC

HIGH-Z

TIMEKEEPER REGISTERS

The M48T201Y/V offers 16 internal registers
which contain TIMEKEEPER, Alarm, Watchdog,
Interrupt, Flag, and Control data. These registers
are memory locations whichcontain external (user
accessible) andinternal copies ofthe data (usually
referred to as BiPORT TIMEKEEPER cells). The
external copies are independent of internal func­tions except that they are updated periodically by
the simultaneoustransfer of the incremented inter­nal copy. TIMEKEEPER and Alarm Registers
store data in BCD. Control, Watchdog and Flags
(bits D0 to D3) Registers store data in Binary For­mat.

CLOCK OPERATIONS
Reading the Clock

Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME­KEEPER cells in the RAM array areonly data reg­isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.

Updating is halted when a ’1’ is written to the
READ bit, D6 in theControl Register (7FFF8h). As

HIGH-Z

AI03520

long as a ’1’ remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and timethat were
current at the moment the halt command was is­sued.

All of the TIMEKEEPER registers are updated si­multaneously. A halt will not interrupt an update in
progress. Updating occurs approximately 1 sec­ond after the READ bit is reset to a ‘0’.

Setting the Clock

Bit D7 of the Control Register (7FFF8h) is the
WRITE bit. Setting the WRITE bit to a ’1’, like the
READ bit, halts updates to the TIMEKEEPER reg­isters. The user can then load them with the cor­rect day, date, and time data in 24 hour BCD
format (see Table 12).

Resetting the WRITE bit to a ’0’ then transfers the
values of all time registers (7FFFFh-7FFF9h,
7FFF1h)to theactual TIMEKEEPER counters and
allows normal operation to resume. After the
WRITE bit is reset,the next clock updatewill occur
approximately one second later.

Note: Upon power-up following a power failure,
both the WRITE bit and the READ bit will be reset
to ’0’.

13/24

M48T201Y, M48T201V,

Table 11. Square Wave Output Frequency

(TA= 0 to 70°C)

Square Wave Bits Square Wave

RS3 RS2 RS1 RS0 Frequency Units

0 0 0 0 Hi-Z ­0 0 0 1 32.768 kHz
0 0 1 0 8.192 kHz
0 0 1 1 4.096 kHz
0 1 0 0 2.048 kHz
0 1 0 1 1.024 kHz
0 1 1 0 512 Hz
0 1 1 1 256 Hz
1 0 0 0 128 Hz
1 0 0 1 64 Hz
1 0 1 0 32 Hz
1 0 1 1 16 Hz
11008Hz
11014Hz
11102Hz
11111Hz

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, theoscillator can be turned off to
minimize current drain on the battery. The STOP
bit is located at Bit D7 within the Seconds Register
(7FFF9h). Setting it to a ’1’ stops the oscillator.
When reset to a ’0’, the M48T201Y/V oscillator
starts within one second.

Note: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).

SETTING ALARM CLOCK

Registers 7FFF6h-7FFF2h contain the alarm set­tings. The alarm can be configured to go off at a
prescribed time on a specific month, day of month,
hour, minute, or second or repeat every month,
day of month, hour, minute, or second.

It can also be programmed to go off while the
M48T201Y/V is in the battery back-up to serve as
a system wake-up call.

Bits RPT5-RPT1 putthe alarm in the repeat mode
of operation. Table 10 shows the possible config­urations. Codesnot listedin thetabledefault tothe

once per second mode to quickly alert the user of
an incorrect alarm setting.

Note: Usermust transition address (or toggle chip
enable) to see Flag bit change.

When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi­tion activates the IRQ/FT pin. To disable alarm,
write ’0’ to the Alarm-Date register and RPT1-4.
The IRQ/FT output is cleared by a read to the
Flags register asshown in Figure 9. A subsequent
read of the Flags register will reset the Alarm Flag
(D6; Register 7FFF0h).

The IRQ/FT pin can also be activated in the bat­tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable)and AFE areset. The ABE
and AFE bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. Theuser can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T201Y/V was in the deselect mode
during power-up. Figure 10 illustrates the back-up
mode alarm timing.

14/24

M48T201Y, M48T201V,

Table 12. Register Map

Address

Data

D7 D6 D5 D4 D3 D2 D1 D0

7FFFFh 10 Years Year Year 00-99

7FFFEh 0 0 0 10 M Month Month 01-12
7FFFDh 0 0 10 Date Date: Dayof Month Date 01-31
7FFFCh 0 FT 0 0 0 Day Day 01-07
7FFFBh 0 0 10 Hours Hours (24 Hour Format) Hour 00-23

7FFFAh 0 10 Minutes Minutes Minutes 00-59

7FFF9h ST 10 Seconds Seconds Seconds 00-59

7FFF8h W R S Calibration Control

7FFF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

7FFF6h AFE SQWE ABE Al.10M Alarm Month Al. Month 01-12

7FFF5h RPT4 RPT5 Al. 10 Date Alarm Date Al. Date 01-31

7FFF4h RPT3 0 Al. 10 Hours Alarm Hours Al. Hours 00-23

7FFF3h RPT2 Alarm 10 Minutes Alarm Minutes Al. Minutes 00-59

7FFF2h RPT1 Alarm 10 Seconds Alarm Seconds Al. Seconds 00-59

7FFF1h 1000 Years 100 Years Century 00-99

7FFF0h WDF AF 0 BL RS3 RS2 RS1 RS0 Flags

Function/Range

BCD Format

Keys: S = SIGN Bit

FT =FREQUENCY TEST Bit
R = READ Bit
W = WRITEBit
ST = STOP Bit
0 = Must be set to zero
Z = ’0’and are Read only
WDS = Watchdog Steering Bit
AF = Alarm Flag

WATCHDOG TIMER

The watchdog timer can be used to detect an out­of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address
7FFF7h. BitsBMB4-BMB0store abinarymultiplier
and the two lower order bits RB1-RB0 select the
resolution, where 00 = 1/16 second, 01 = 1/4 sec­ond, 10 = 1 second, and 11 = 4 seconds. The
amount of time-out is then determined to be the
multiplication ofthe fivebit multiplier value withthe
resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).

Note: Accuracy of timer is within ± the selected
resolution.

If the processor does notreset the timer withinthe
specified period, the M48T201Y/V sets the WDF
(Watchdog Flag) and generates a watchdog inter-

BL = Battery Low
SQWE = Battery Low Flag
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable
ABE = Alarm in Battery Back-up Mode Enable
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog Flag
RS0-RS3 = SQW Frequency

rupt or a microprocessor reset. WDF is reset by
reading the Flag Register (Address 7FFF0h).

The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a ’0’, the watchdog will activate the IRQ/FT pin
when timed-out. When WDS is set to a ’1’, the
watchdog will output a negative pulse on the RST
pin for 40 to 200 ms. The Watchdog register and
the FT bit will reset to a ’0’ at the end of a Watch­dog time-out when the WDS bit is set to a ’1’.

The watchdog timer can be reset by two methods:

1) a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or 2) the
microprocessor can perform a write of the Watch­dog Register. The time-out period then starts over.
The WDI pin should be tied to VSSif not used. The
watchdog will be reset on each transition (edge)
seen by the WDI pin.

15/24

M48T201Y, M48T201V,

Figure 11. Calibration Waveform

NORMAL

POSITIVE
CALIBRATION

NEGATIVE
CALIBRATION

AI00594B

In order to perform a software reset of the watch­dog timer, the original time-out period can be writ­ten into the Watchdog Register, effectively
restarting the count-down cycle.

Should the watchdog timertime-out, and the WDS
bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also dis­able the watchdog function until it is again pro­grammed correctly. A read of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
7FFF0h).

The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is setto output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test functionis denied.

Square Wave Output

The M48T201Y/V offers the user a programmable
square wave function which is output on the SQW
pin. RS3-RS0 bitslocated in 7FFF0h establish the
square waveoutput frequency. These frequencies
are listed in Table 11. Once the selection of the
SQW frequency has been completed, the SQW
pin can be turned on and off under software con­trol withthe squarewave enable bit (SQWE)locat­ed in Register 7FFF6h.

POWER-ON RESET

The M48T201Y/V continuously monitors VCC.
When VCCfalls to the power fail detect trip point,
the RST pulls low (opendrain) and remains low on
power-up for 40 to 200ms after VCCpasses V

PFD

The RST pin isanopen drain output andan appro­priate pull-up resistor to VCCshould be chosen to
control rise time.

Reset Inputs (RSTIN1 & RSTIN2)

The M48T201Y/V provides two independent in­puts which can generate an output reset. The du­ration and function of these resets is identical to a
reset generated by a power cycle. Table 13 and
Figure 12 illustrate the AC reset characteristics of
this function. Pulses shorter than tR1and tR2will
not generate a reset condition. RSTIN1 and
RSTIN2 are each internally pulled up to V

CC

through a 100KΩ resistor.

Calibrating the Clock

The M48T201Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are factory calibrated at 25°C and
tested for accuracy. Clock accuracy will not ex­ceed ±35 ppm (parts per million) oscillator fre­quency error at 25°C, which equates to about
±1.53 minutes per month. When the Calibration
circuit is properlyemployed, accuracyimproves to
better than ±2 ppm at 25°C. The oscillation rate of
crystals changes with temperature. The
M48T201Y/V design employs periodic counter
correction. The calibration circuit adds orsubtracts
counts from the oscillator divider circuit at the di­vide by 256 stage, as shown in Figure 11.

.

16/24

M48T201Y, M48T201V,

Table 13. Reset AC Characteristics

(TA = 0to 70°C, VCC= 3.0V to 3.6V or VCC= 4.5V to 5.5V)

Symbol Parameter Min Max Unit

t

R1

t

R2

t

R1HRZ

t

R2HRZ

Note: 1. 1.CL = 5pF.

Table 14. SNAPHAT Battery Table

Part Number Description Package

M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH
M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH

RSTIN1 Low to RST Low 50 200 ns
RSTIN2 Low to RST Low 20 100 ms

(1)

RSTIN1 High to RST Hi-Z 40 200 ms

(1)

RSTIN2 High to RST Hi-Z 40 200 ms

The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load­ed intothe five Calibration bits foundin theControl
Register. Adding countsspeeds the clock up, sub­tracting counts slows the clock down.

The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register 7FFF8h.
These bits can be set to represent any value be­tween 0 and 31 in binary form. Bit D5 is a Sign bit;
’1’indicates positive calibration, ’0’indicates nega­tive calibration. Calibration occurs within a 64
minute cycle. The first 62 minutes in the cycle
may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator
cycles. If a binary ’1’ is loaded into the register,
only the first 2 minutes in the 64 minute cycle will
be modified; if a binary 6 is loaded, the first 12 will
be affected, and so on.

Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra­tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which correspondstoa total range of +5.5 or–2.75
minutes per month.

Two methods are available for ascertaining how
much calibration a given M48T201Y/V may re­quire. The first involves setting the clock, letting it
run for a month and comparing itto a known accu­rate reference and recording deviation overa fixed

period of time. Calibration values, including the
number of seconds lost or gained in a given peri­od, can be found in STMicroelectronics Applica­tion Note: TIMEKEEPER CALIBRATION. This
allows the designer to give the end user the ability
to calibrate the clock as the environment requires,
even if the final product is packaged in a non-user
serviceableenclosure. The designer could provide
a simple utility that accesses the Calibration byte.

The second approach is better suited to a manu­facturing environment, and involves the useof the
IRQ/FT pin. The pinwill toggle at 512Hz, when the
Stop bit (ST, D7 of 7FFF9h) is ’0’,the Frequency
Test bit (FT, D6 of 7FFFCh) is ’1’, the Alarm Flag
Enable bit (AFE, D7 of 7FFF6h) is ’0’, and the
Watchdog Steering bit (WDS, D7 of 7FFF7h) is ’1’
or the Watchdog Register (7FFF7h=0) is reset.

Note: A 4 second settling time must be allowed
before reading the 512Hz output.

Any deviation from 512Hz indicates the degree
anddirection ofoscillatorfrequency shift at the test
temperature. For example, a reading of

512.010124Hz would indicatea +20 ppmoscillator
frequency error, requiring a –12 (001100) to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does notaffect the Frequency testoutput frequen­cy.

The IRQ/FT pin is an open drain output which re­quires a pull-up resistor to VCCfor proper opera­tion. A 500-10kΩ resistoris recommended inorder
to control the rise time. The FT bit is cleared on
power-up.

17/24

M48T201Y, M48T201V,

Figure 12. RSTIN1 and RSTIN2 Timing Waveforms

RSTIN1

RSTIN2

RST

tR2

Hi-Z

Hi-Z

tR1 tR1HRZ

BATTERY LOW WARNING

The M48T201Y/V automatically performs battery
voltage monitoring upon power-up and at factory­programmed time intervals of approximately 24
hours. The Battery Low (BL) bit, Bit D4 of Flags
Register 7FFF0h, will be asserted if the battery
voltage is found to be less than approximately

2.5V. The BL bit will remain asserted until comple­tion of battery replacement and subsequent bat­tery low monitoring tests, either during the next
power-up sequenceorthe next scheduled24-hour
interval.

If a battery lowis generatedduring a power-up se­quence, this indicates that the battery is below ap­proximately 2.5V and may not be able to maintain
data integrityin theSRAM. Datashould beconsid­ered suspect and verified as correct. A fresh bat­tery should be installed.

If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-

tR2HRZ

AI01679

tery is near end of life. However, data is not com­promised due to the fact that a nominal VCCis
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT top
maybe replacedwhile VCCisapplied to the device
(Note, this will cause the clock to lose time during
the time interval the battery/crystal is removed).

The M48T201Y/201V only monitors the battery
when a nominal VCCis applied to the device. Thus
applications which require extensive durations in
the battery back-up mode should be powered-up
periodically (at least once every few months) in or­der forthis technique tobe beneficial. Additionally,
if a battery low is indicated, data integrity should
be verified uponpower-up viaa checksum or other
technique.

18/24

M48T201Y, M48T201V,

POWER-ON DEFAULTS

Upon application of power to the device, the fol­lowing register bits are set to a ’0’ state: WDS;
BMB0-BMB4; RB0-RB1; AFE; ABE; SQWE; W;R;
FT.

(See Table 15)

POWER SUPPLY DECOUPLING
and UNDERSHOOT PROTECTION

ICCtransients,including those produced by output
switching, can produce voltage fluctuations, re­sulting in spikes on the VCCbus. These transients
can be reduced if capacitors are used to store en­ergy, which stabilizes the VCCbus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by­pass capacitor value of 0.1µF (as shownin Figure

13) is recommended in order to provide the need­ed filtering.

In addition to transients that are caused bynormal
SRAM operation,power cycling cangenerate neg­ative voltage spikes on VCCthat drive it to values
below VSSby as much as one Volt. These nega­tive spikescan cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to con­nect a schottky diode from VCCto VSS(cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.

Figure 13. Supply Voltage Protection

V

CC

V

CC

0.1µF DEVICE

V

SS

AI00605

Table 15. Default Values

Condition W R FT AFE AFE

Initial Power-up
(Battery Attach for SANPHAT)

Subsequent Power-up / RESET
Power-down

Note: 1. WDS, BMB0-BMB4, RB0, RB1.

2. State of other control bits undefined.

3. State of other control bits remains unchanged.

4. Assuming these bits set to ‘1’ prior to power-down.

(4)

(2)

(3)

WATCHDOG

Register

00000 0

00000 0
00011 0

(1)

19/24

M48T201Y, M48T201V,

Table 16. Ordering Information Scheme

Example: M48T201Y -70 MH 1 TR

Device Type

M48T

Supply Voltage and Write Protect Voltage

Y=V
V=V

Speed

-70 = 70ns (M48T201Y)

-85 = 85ns (M48T201V)

Package

MH

Temperature Range

1=0to70°C

Shipping Method for SOIC

blank tubes
TR Tape& Reel

= 4.5V to 5.5V; V

CC

= 3.0V to 3.6V; V

CC

(1)

= SOH44

= 4.1V to 4.5V

PFD

= 2.7V to 3.0V

PFD

Note: 1. The SOIC package (SOH44) requiresthe battery package (SNAPHAT) which is ordered separately underthe part number ”M4Txx-

BR12SH1” in plastic tube or ”M4Txx-BR12SH1TR” in Tape & Reel form.
Caution:Do not place the SNAPHAT battery package ”M4Txx-BR12SH1” inconductive foam since will drain the lithium button-cell

battery.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de­vice, please contact the ST Sales Office nearest to you.

20/24

M48T201Y, M48T201V,

Table 17. SOH44 - 44 lead Plastic Small Outline, 4-socket battery, SNAPHAT,
Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106

B 0.36 0.46 0.014 0.018

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 0.81 – – 0.032 – –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α 0° 8° 0° 8°

mm inches

N44 44

CP 0.10 0.004

Figure 14. SOH44 - 44 lead Plastic Small Outline, 4-socket battery, SNAPHAT, Package Outline

A2

A

C

Be

CP

eB

D

N

E

H

1

SOH-A

Drawing is not to scale.

LA1 α

21/24

M48T201Y, M48T201V,

Table18.SH - 4-pinSNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

mm inches

Figure 15. SH - 4-pinSNAPHAT Housing for48 mAh Battery & Crystal, Package Outline

A1

A

eA

D

B

eB

E

SHTK-A

Drawing is not to scale.

A2

A3

L

22/24

M48T201Y, M48T201V,

Table19.SH - 4-pinSNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 10.54 0.415
A1 8.00 8.51 0.315 .0335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 .0710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

mm inches

Figure 16. SH - 4-pinSNAPHAT Housing for120 mAh Battery & Crystal, Package Outline

A1

eA

D

A

B

eB

A3

L

E

SHTK-A

Drawing is not to scale.

A2

23/24

M48T201Y, M48T201V,

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information norforanyinfringement of patents or other rights of third parties whichmay result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces allinformation previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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24/24