Datasheet M48T18-150MH1, M48T18-120MH1, M48T18-100PC1, M48T18, M48T18-150PC1 Datasheet (SGS Thomson Microelectronics)

M48T08
M48T18

64 Kbit (8Kb x 8) TIMEKEEPER® SRAM

May 1999 1/19

INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK , PO WE R-FAIL C O NTRO L
CIRCUIT and BA T TER Y

BYTEWIDE RAM-LIKE CLOCK ACCE S S
BCD CODED YEAR, MONTH, DAY, DA TE,

HOURS, MINUTES and SECONDS
TYPICAL CLOCK A CCURA CY of ± 1 MINUTE

a MONTH, at 25°C
AUTOMATIC POWER-F AIL CHIP DES ELECT and

WRITE PROTECTION
WRITE PROTECT VOLT AGES

(V

PFD

= Power-fail Deselect Voltage):

– M48T08: 4.5V ≤ V

PFD

≤

4.75V

– M48T18: 4.2V ≤ V

PFD

≤

4.5V

SOFTWARE CONTROLLED CLOCK
CALIBRA TION for HIGH ACCURACY
APPLICATIONS

SELF-CONTAINED BA TTER Y and CRYST AL in the
CAPHA T DIP P ACKAGE

PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT

®

TOP

(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL

PIN and FUNCTION COMPATIBLE with
DS1643 and JEDEC STANDARD 8K x 8
SRAMs

AI01020

13

A0-A12

W

DQ0-DQ7

V

CC

M48T08
M48T18

G

E2

V

SS

8

E1 INT

Figure 1. Logic Diagram

A0-A12 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
INT Power Fail Interrupt (Open Drain)
E1 Chip Enable 1
E2 Chip Enable 2
G Output Enable
W Write Enable
V

CC

Supply Voltage

V

SS

Ground

T ab le 1. Signal Names

28

1

PCDIP28 (PC)

Battery/Crystal

CAPHAT

SNAPHAT (SH)

Battery/Crystal

28

1

SOH28 (MH)

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature 0 to 70 °C

T

STG

Storage T emper ature (VCC Off, Oscillator Off) –40 to 85 °C

T

SLD

(2)

Lead Solder Temperature for 10 seconds 260 °C

V

IO

Input or Output Voltages –0.3 to 7 V

V

CC

Supply Voltage –0.3 to 7 V

I

O

Output Current 20 mA

P

D

Power Dissipation 1 W

Notes:

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indi cat ed in the operati onal
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negat i ve undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

T ab le 2. Absolute Maximum Ratings

(1)

Mode V

CC

E1 E2 G W DQ0-DQ7 Power

Deselect

4.75V to 5.5V
or

4.5V to 5.5V

V

IH

X X X High Z Standby

Deselect X V

IL

X X High Z Standby

Write V

IL

V

IH

XVILD

IN

Active

Read V

IL

V

IH

V

IL

V

IH

D

OUT

Active

Read V

IL

V

IH

V

IH

V

IH

High Z Active

Deselect V

SO

to V

PFD

(min) X X X X High Z CMOS Standby

Deselect ≤ V

SO

X X X X High Z Battery Back-up Mode

Notes:

1. X = V

IH

or VIL; VSO = Battery Back-up Switchover Voltage.

T ab le 3. Operating Modes

A1
A0

DQ0

A7

A4
A3
A2

A6
A5

E2

A10

A8
A9

DQ7

W

A11
G

E1

DQ5DQ1

DQ2

DQ3V

SS

DQ4

DQ6

A12

INT V

CC

AI01182

M48T08
M48T18

8

1
2
3
4
5
6
7

9
10
11
12
13
14

16
15

28
27
26
25
24
23
22
21
20
19
18
17

Figure 2A. DIP Pin Connections

AI01021B

8

2
3
4
5
6
7

9
10
11
12
13
14

22
21
20
19
18
17
16
15

28
27
26
25
24
23

1

A1
A0

DQ0

A7

A4
A3
A2

A6
A5

E2

A10

A8
A9

DQ7

W

A11
G

E1

DQ5DQ1

DQ2

DQ3V

SS

DQ4

DQ6

A12

INT V

CC

M48T18

Figure 2B. SOIC Pin Connections

2/19

M48T08, M48T18

AI01019

5V

OUT

CL = 100pF

CL includes JIG capacitance

1.8kΩ

DEVICE
UNDER

TEST

1kΩ

Figure 4. AC Testing Load Circuit

Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data is no
longer driven.

T able 4. AC Measurement Conditions

AI01333

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

V

PFD

INTV

CC

V

SS

32,768 Hz

CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

8 x 8 BiPORT

SRAM ARRAY

8184 x 8

SRAM ARRAY

A0-A12

DQ0-DQ7

E1
E2
W
G

POWER

Figure 3. Block Diagram

DESCRIPTION

The M48T08/18 TIMEKEEPE R

®

RAM is an 8K x 8
non-volatile static RAM and real time clock which
is pin and functional compatible with the DS1643.
The monolithic chip is available in two special
packages to provide a highly integrated battery
backed-up memory and real time clock solution.

The M48T08/18 is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes t hat
can be performed.

The 28 pin 600mil DIP CAPHAT houses the
M48T08/18 silicon with a quartz crystal and a long
life lithium button cell in a single package.

The 28 pin 330mil SOIC provides s ockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery and crystal. The unique design allows the
SNAPHAT bat tery package to be mounted on t op
of the SOIC package after the completion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and
crystal damage due to the hig h temperatures re­quired for device surface-mounting. The SNAPHA T
housing is keyed to prevent reverse insertion.

3/19

M48T08, M48T18

Symbol Parameter Test Condition Min Max Unit

I

LI

(1)

Input Leakage Current 0V ≤ VIN ≤ V

CC

±1 µA

I

LO

(1)

Output Leakage Current 0V ≤ V

OUT

≤ V

CC

±5 µA

I

CC

Supply Current Outputs open 80 mA

I

CC1

(2)

Supply Current (Standby) TTL E1 = VIH, E2 = V

IL

3mA

I

CC2

(2)

Supply Current (Standby) CMOS

E1 = VCC – 0.2V,
E2 = V

SS

+ 0.2V

3mA

V

IL

(3)

Input Low Voltage –0.3 0.8 V

V

IH

Input High Voltage 2.2 VCC + 0.3 V

V

OL

Output Low Voltage IOL = 2.1mA 0.4 V
Output Low Voltage (

INT)

(4)

IOL = 0.5mA 0.4 V

V

OH

Output High Voltage IOH = –1mA 2.4 V

Notes:

1. Outputs Deselected.

2. Measured with Control Bits set as follows: R = ’1’; W, ST , FT = ’0’.

3. Negative spikes of –1V allowed for up to 10ns once per Cycle.

4. The

INT pin is Open Drain.

T ab le 6. DC Characteristics

(T

A

= 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

Symbol Parameter Test Condition Min Max Unit

C

IN

Input Capacitance VIN = 0V 10 pF

C

IO

(3)

Input / Output Capacitance V

OUT

= 0V 10 pF

Notes:

1. Effective capacitance measured with power supply at 5V .

2. Sampled only, not 100% tested.

3. Outputs deselected.

T ab le 5. Capacitance

(1, 2)

(T

A

= 25 °C, f = 1 MHz )

Symbol Parameter Min Typ Max Unit

V

PFD

Power-fail Deselect Voltage (M48T08) 4.5 4.6 4.75 V

V

PFD

Power-fail Deselect Voltage (M48T18) 4.2 4.3 4.5 V

V

SO

Battery Back-up Switchover Voltage 3.0 V

t

DR

(2)

Expected Data Retention Time 10 YEARS

Notes:

1. All voltages referenced to V

SS

.

2. At 25°C

T able 7. Power Down/Up Trip Points DC Characteristics

(1)

(T

A

= 0 to 70°C)

The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the
battery/crystal package (i.e. SNAPHAT) part num­ber is "M4T28-BR12SH1".

As Figure 3 shows, the static memory array and the
quartz controlled clock oscillator of the M48T08/18
are integrated on one silicon chip. The two circuits
are interconnected at the upper eight memory lo­cations to provide user accessible BYTEWIDE



clock information in the bytes with addresses
1FF8h-1FFFh.

DESCRIPTION

(cont’d)

4/19

M48T08, M48T18

Symbol Parameter Min Max Unit

t

PD

E1 or W at VIH or E2 at VIL before Power Down 0 µs

t

F

(1)

V

PFD

(max) to V

PFD

(min) VCC Fall Time 300 µs

t

FB

(2)

V

PFD

(min) to VSO VCC Fall Time 10 µs

t

R

V

PFD

(min) to V

PFD

(max) VCC Rise Time 0 µs

t

RB

VSO to V

PFD

(min) VCC Rise Time 1 µs

t

REC

E1 or W at VIH or E2 at VIL after Power Up 1 ms

t

PFX

INT Low to Auto Deselect 10 40 µs

t

PFH

(3)

V

PFD

(max) to INT High 120 µs

Notes

:1.V

PFD

(max) to V

PFD

(min) fall time of less than tF may result in deselection/writ e protection not occ urri ng until 200 µs after

V

CC

passes V

PFD

(min).

2. V

PFD

(min) to VSO fall time of less than tFB may cause corruption of RAM data.

3.

INT may go high anytime after VCC exceeds V

PFD

(min) and is guaranteed to go high t

PFH

after VCC exceeds V

PFD

(max).

T able 8. Power Down/Up Mode AC Characteristics

(T

A

= 0 to 70°C)

AI00566

V

CC

INPUTS

INT

(PER CONTROL INPUT)

OUTPUTS

DON'T CARE

HIGH-Z

tF

tFB

tPFX

tR

tPFH

tREC

tPD tRB

tDR

VALID VALID

NOTE

(PER CONTROL INPUT)

RECOGNIZEDRECOGNIZED

V

PFD

(max)

V

PFD

(min)

VSO

Figure 5. Power Down/Up Mode AC Waveforms

Note:

Inputs may or may not be recognized at this time. Caution should be taken to keep

E1 high or E2 low as VCC rises past V

PFD

(min).

Some systems may perform inadvertent write cycles after V

CC

rises above V

PFD

(min) but before normal system operations begin. Even

though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is runn ing.

5/19

M48T08, M48T18

Symbol Parameter

M48T08 / M48T18

Unit

-100 -150

Min Max Min Max

t

AVAV

Read Cycle Time 100 150 ns

t

AVQV

Address Valid to Output Valid 100 150 ns

t

E1LQV

Chip Enable 1 Low to Output Valid 100 150 ns

t

E2HQV

Chip Enable 2 High to Output Valid 100 150 ns

t

GLQV

Output Enable Low to Output Valid 50 75 ns

t

E1LQX

Chip Enable 1 Low to Output Transition 10 10 ns

t

E2HQX

Chip Enable 2 High to Output Transition 10 10 ns

t

GLQX

Output Enable Low to Output Transition 5 5 ns

t

E1HQZ

Chip Enable 1 High to Output Hi-Z 50 75 ns

t

E2LQZ

Chip Enable 2 Low to Output Hi-Z 50 75 ns

t

GHQZ

Output Enable High to Output Hi-Z 40 60 ns

t

AXQX

Address Transition to Output Transition 5 5 ns

T ab le 9. Read Mode AC Characteristics

(T

A

= 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

AI00962

tAVAV

tAVQV tAXQX

tE1LQV

tE1LQX

tE1HQZ

tGLQV

tGLQX

tGHQZ

VALID

A0-A12

E1

G

DQ0-DQ7

tE2HQV

tE2HQX

VALID

tE2LQZ

E2

Figure 6. Read Mode AC Waveforms

Note:

Write Enable (

W) = High.

6/19

M48T08, M48T18

Symbol Parameter

M48T08 / M48T18

Unit

-100 -150

Min Max Min Max

t

AVAV

Write Cycle Time 100 150 ns

t

AVWL

Address Valid to Write Enable Low 0 0 ns

t

AVE1L

Address Valid to Chip Enable 1 Low 0 0 ns

t

AVE2H

Address Valid to Chip Enable 2 High 0 0 ns

t

WLWH

Write Enable Pulse Width 80 100 ns

t

E1LE1H

Chip Enable 1 Low to Chip Enable 1 High 80 130 ns

t

E2HE2L

Chip Enable 2 High to Chip Enable 2 Low 80 130 ns

t

WHAX

Write Enable High to Address Transition 10 10 ns

t

E1HAX

Chip Enable 1 High to Address Transition 10 10 ns

t

E2LAX

Chip Enable 2 Low to Address Transition 10 10 ns

t

DVWH

Input Valid to Write Enable High 50 70 ns

t

DVE1H

Input Valid to Chip Enable 1 High 50 70 ns

t

DVE2L

Input Valid to Chip Enable 2 Low 50 70 ns

t

WHDX

Write Enable High to Input Transition 5 5 ns

t

E1HDX

Chip Enable 1 High to Input Transition 5 5 ns

t

E2LDX

Chip Enable 2 Low to Input Transition 5 5 ns

t

WLQZ

Write Enable Low to Output Hi-Z 50 70 ns

t

AVWH

Address Valid to Write Enable High 80 130 ns

t

AVE1H

Address Valid to Chip Enable 1 High 80 130 ns

t

AVE2L

Address Valid to Chip Enable 2 Low 80 130 ns

t

WHQX

Write Enable High to Output Transition 10 10 ns

T ab le 10. Write Mode AC Characteristics

(T

A

= 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD
format. Corrections for 28, 29 (leap year), 30, and
31 day months are made automatically. Byte
1FF8h is the clock control register. This byte con­trols user access to the clock information and also
stores the clock calibration setting.

The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT read/write memory cells.
The M48T08/18 includes a clock control circuit
which updates the clock bytes with current informa­tion once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array.

DESCRIPTION

(cont’d)

7/19

M48T08, M48T18

AI00963

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A12

E1

W

DQ0-DQ7

VALID

E2

tAVWH

tAVE1L

tAVE2H

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

Figure 7. Write Enable Controlled, Write AC Waveforms

AI00964B

tAVAV

tE1HAX

tDVE1H
tDVE2L

A0-A12

E1

W

DQ0-DQ7

VALID

E2

tAVE1H

tAVE1L

tAVWL

tAVE2L

tE1LE1H

tE2LAX

tAVE2H tE2HE2L

tE1HDX
tE2LDX

DATA INPUT

Figure 8. Chip Enable Controlled, Write AC Waveforms

8/19

M48T08, M48T18

The M48T08/18 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When V

CC

is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpr edictable system op­eration brought on by low V

CC

. As VCC falls below
approximately 3V , the c ontrol circuitry connects the
battery which maintains data and clock operation
until valid power returns.

READ MODE

The M48T08/18 is in the Read Mode whenever

W

(Write Enable) is high,

E1 (Chip Enable 1) is low,
and E2 (Chip Enable 2) is high. The device archi­tecture allows ripple-through access of data from
eight of 65,536 locations in the static storage array.
Thus, the unique address specified by the 13 Ad­dress Inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be avail­able at the Dat a I/O pins within Address Access
time (t

AV Q V

) after the last address input signal is

stable, providing that the

E1, E2, and G ac cess

times are also satisfied. If the

E1, E2 and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access times (t

E1LQV

or t

E2HQV

) or Output Enable Access time (t

GLQV

).

The state of the eight three-state Data I/O signals
is controlled by

E1, E2 and G. If the outputs are

activated before t

AVQV

, the data lines will be driven

to an indeterminate state until t

AVQV

. If the Address

Inputs are changed while

E1, E2 and G remain
active, output data will remain valid for Output Data
Hold time (t

AXQX

) but will go indeterminate until the

next Address Access.

WRITE MODE

The M48T08/18 is in the Write Mode whenever

W,
E1, and E2 are active. The start of a write is
referenced from the latter occurring falling edge of
W or E1, or the rising edge of E2. A write is
terminated by the earlier rising edge of

W or E1, or
the falling edge of E2. The addresses must be held
valid throughout the cycle.

E1 or W must return high

or E2 low for a minimum of t

E1HA X

or t

E2LAX

from

Chip Enable or t

WHAX

from Write Enable prior to the
initiation of another read or write cycle. Data-in
must be valid t

DVWH

prior to the end of write and

remain valid for t

WHDX

afterward. G should be kept
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on

E1 and G and a high on E 2, a low on W will

disable the outputs t

WLQZ

after W falls.

DESCRIPTION

(cont’d)

Address

Data

Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

1FFFh 10 Y ears Year Year 00-99

1FFEh 0 0 0 10 M. Month Month 01-12
1FFDh 0 0 10 Date Date Date 01-31
1FFCh 0 FT 0 0 0 Day Day 01-07

1FFBh 0 0 10 Hours Hours Hour 00-23

1FFAh 0 10 Minutes Minutes Minutes 00-59

1FF9h ST 10 Seconds Seconds Seconds 00-59

1FF8h W R S Calibration Control

Keys:

S = SIGN Bit
FT = FREQUENCY TEST Bit (Set to ’0’ for normal clock operation)
R = READ Bi t
W = WRITE Bit
ST = STOP Bit
0 = Must be set to ’0’

T ab le 11. Register Map

9/19

M48T08, M48T18

DATA RETENTION MODE

With valid V

CC

applied, the M48T08/18 operates as
a conventional BYTEWIDE static RAM. Should the
supply voltage decay, the RAM will automatically
power-fail deselect, write protecting itself when V

CC

falls within the V

PFD

(max), V

PFD

(min) window. All
outputs become high impedance, and all inputs are
treated as "don’t care."

Note:

A power failure during a write cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM’s
content. At voltages below V

PFD

(min), the user can
be assured the memory w ill be in a write protected
state, provided the V

CC

fall time is not less than tF.
The M48T08/18 may respond to transient noise
spikes on V

CC

that reach into the deselect window

during the time the device is s ampling V

CC

. There­fore, decoupling of the power supply lines is rec­ommended.

When V

CC

drops below VSO, the control circuit
switches power to the internal battery which pr e­serves data and powers the clock. The internal
button cell will maintain data in the M48T08/18 for
an accumulated period of at least 10 years when
V

CC

is less than VSO. As system power returns and

V

CC

rises above VSO, the battery is disconnected,

and the power supply is switched to external V

CC

.

Write protection continues until V

CC

reaches V

PFD

(min) plus t

REC

(min). E1 should be kept high or E 2

low as V

CC

rises past V

PFD

(min) to prevent inadver­tent write cycles prior to system stabilization. Nor­mal RAM operation can resume t

REC

after V

CC

exceeds V

PFD

(max).

For more information on Battery Storage Life refer
to the Applicatio Noyte ANxxx.

POWER F AIL INTERR UPT PIN

The M48T08/18 continuously monitors V

CC

. When

V

CC

falls to the power-fail detect trip point, an
interrupt is immediately generated. An internal
clock provides a delay of between 10µs and 40µs
before automatically deselecting the M48T08/18.
The

INT pin is an open drain output and requires
an external pull up resistor, even if the interrupt
output function is not being used.

SYSTEM BATTERY LIFE

The useful life of the battery in the M48T08/18 is
expected to ultimately come to an end for one of
two reasons: either because it has been dis­charged while providing current to the RAM and
clock in the battery back-up mode, or because the
effects of aging render the cell useless before it can

AI01024

20 30 40 50 60 70 80 90

1

2

3

4

5

8
6

TEMPERATURE (Degrees Celsius)

10

20

30

40

50

YEARS

t50% (AVERAGE)

t1%

Figure 9. Predicted Battery Storage Life versus Temperature

10/19

M48T08, M48T18

actually be completely discharged. The two ef fects
are virtually unrelated, allowing discharge or Ca­pacity Consumption, and the effects of aging or
Storage Life, to be treated as two independent but
simultaneous mechanisms. The earlier occurring
failure mechanism defines the batt ery system life
of the M48T08/18.

Cell Storage Life

Storage life is primarily a function of temperature.
Figure 9 illustrates the approximate stor age life of
the M48T08/18 battery over temperature. The re­sults in Figure 9 are derived from temperature
accelerated life test studies performed at SGS­THOMSON. For the purpose of the testing, a cell
failure is defined as the inability of a cell stabilized
at 25°C to produce a 2.4V closed circuit voltage
across a 250 kΩ load resistor. The two lines, t

1%

and t

50%

, represent different failure rate dis tribu­tions for the cell’s storage life. At 70°C, for example,
the t

1%

line indicates that an M48T08/18 has a 1%
chance of having a battery failure 11 years into its
life while the t

50%

shows the part has a 50% chance

of failure at the 20 year mark. The t

1%

line repre­sents the practical onset of wear out and can be
considered the worst case Storage Life for the cell.
The t

50%

can be considered the normal or average

life.

Calculating Storage Life

The following formula can be used to predict stor­age life:

1

{[(TA1/TT)/SL1]+[(TA2/TT)/SL2]+...+[(TAN/TT)/SLN]}

where,
– T A1, TA2, T A N = time at ambient temperature

1, 2, etc.
– TT = total time = TA1+TA2+...+TAN
– SL1, SL2, SLN = storage life at temperature 1,

2, etc.
For example, an M48T08/18 is exposed to tem-

peratures of 55°C or less for 8322 hrs/yr, and
temperatures greater than 60°C but less than 70°C
for the remaining 438 hrs/yr. Reading predicted t

1%

values from Figure 9,
– SL1 = 41 yrs, SL2 = 11.4 yrs
– TT = 8760 hrs/yr
– T A1 = 8322 hrs/yr , TA2 = 438 hrs/yr
Predicted storage life

≥

1

{[ (8322/8760)/41]+[(431/8760)/11.4]}

or 36 years.

Cell Capacity Life

The M48T08/18 internal cell has a rated capacity
of 50mAh. The device places a nominal RAM and
TIMEKEEPER load of less than 520nA on the

battery at room temperature. At this rate, t he ca­pacity consumption life is 50E-3/520E-9 = 96,153
hours or about 11 years. Capacity consumption life
can be extended by applying V

CC

or turning off the

clock oscillator prior to system power down.

Calculating Capacity Life

The RAM and TIMEKEEPER load remains rela­tively constant over the operating temperature
range. Thus, worst case cell capacity life is essen­tially a function of one variable, V

CC

duty cycle. For
example, if the oscillator runs 100% of the time with
V

CC

applied 60% of the time, the capacity con-

sumption life is 10/(1-0.6), or 25 years.

Estimated System Life

Since either storage life or capacity consumption
can end the battery’s life, the system life is marked
by which ever occurs first. In the above example,
this would be 25 years.

Reference for System Life

Each M48T08/18 is marked with a nine digit manu­facturing date code in the form of H99XXYYZZ. For
example, H995B9431 is:

H = fabricated in Carrollton, TX
9 = assembled in Muar, Malaysia,
9 = tested in Muar, Malaysia,
5B = lot designator,
9431 = assembled in the year 1994, work week 31.

CLOCK OPERATIONS
Reading the Clock

Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME­KEEPER cells in the RAM array are only data
registers, and not the actual clock counters, updat­ing the registers can be halted without disturbing
the clock itself.

Updating is halted when a ’1’ is written to the READ
bit, the seventh bit in the control register. As long
as a ’1’ remains in that position, updating is halted.
After a halt is issued, t he registers reflect the count;
that is, the day, date, and the time that were current
at the moment the halt command was issued.

All of the TIMEKEEPER registers are updated si­multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.

Setting the Clock

The eighth bit of the control register is the WRI TE
bit. Setting the WRITE bit to a ’1’, like the READ bit,
halts updates to the TIMEKEEPER registers. The
user can then load them with the correct day , date,
and time data in 24 hour BCD format (on T able 1 1).

11/19

M48T08, M48T18

Resetting the WRITE bit to a ’0’ then transfers the
values of all time registers (1FF9h-1FFFh) to the
actual TIMEKEEPER counters and allows normal
operation to resume. The FT bit and the bits marked
as ’0’ in Table 11 must be written to ’0’ to allow for
normal TIMEKEEPER and RAM operation.

See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" for information on
Century Rollover.

Stopping and Starting the Oscilla tor

The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a ’1’ stops the oscillator. The M48T08/18 is shipped
from STMicroelectronics with the STOP bit set to a
’1’. When reset to a ’0’, the M48T08/18 oscillator
starts within 1 second.

Calibrating the Clock

The M48T08/18 is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz. A
typical M48T08/18 is accurate within ±1 minute per
month at 25°C without calibration. The devices are
tested not to exceed ±35 PPM (parts per million)
oscillator frequency error at 25°C, which equates
to about ± 1.53 minutes per month.

The oscillation rate of any crystal changes with
temperature. Figure 11 shows the frequency error
that can be expected at various temperatures. Most
clock chips compensate for crystal frequency and

Setting the Clock

(cont’d)

temperature shift error with cumbersome t rim ca­pacitors. The M48T08/18 design, however, em­ploys periodic counter correction. The calibration
circuit adds or subtracts counts from the oscillator
divider circuit at the divide by 256 stage, as shown
in Figure 10. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five bit Calibration byte found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.

The Calibration byte occupies the five lower order
bits in the Control register. This byte can be set to
represent any value between 0 and 31 in binary
form. The sixth bit is a sign bit; ’1’ indicates positive
calibration, ’0’ indicates negative calibration. Cali­bration occurs within a 64 minute cycle. The first 62
minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened
by 256 oscillator cycles. If a binary ’1’ is loaded into
the register, only the first 2 minutes in the 64 minute
cycle will be modified; if a binary 6 is loaded, the
first 12 will be affected, and so on.

Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles; that is
+4.068 or -2.034 PPM of adjustment per calibration
step in the calibration register. Assuming that the
oscillator is in fact running at exactly 32,768 Hz,
each of the 31 increments in the Calibration byte
would represent +10.7 or - 5.35 seconds per month
which corresponds to a total range of +5.5 or - 2.75
minutes per month.

AI00594B

NORMAL

POSITIVE
CALIBRATION

NEGATIVE
CALIBRATION

Figure 10. Clock Calibration

12/19

M48T08, M48T18

AI02124

-80

-60

-100

-40

-20

0

20

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

∆F

= -0.038 (T - T

0

)2 ± 10%

F

ppm

C

2

T0 = 25 °C

ppm

°C

Figure 11. Crystal Accuracy Across Temperature

Two methods are available for ascertaining how
much calibration a given M48T08/18 may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known
accurate reference (like WWV broadcasts). While
that may seem crude, it allows the des igner to give
the end user the ability to calibrate his clock as his
environment may require, even after the final prod­uct is packaged in a non-user serviceable enclo­sure. All the designer has to do is provide a simple
utility that accesses the Calibration byte. The utility
could even be menu driven and made foolproof.

The second approach is better suited to a manu­facturing environment, and involves the use of
some test equipment. When the Frequency Te st
(FT) bit, the seventh-most significant bit in the Day
Register, is s et to a ’1’, and the oscillator is running
at 32,768 Hz, the LSB (DQ0) of the Seconds Reg­ister will toggle at 512 Hz. Any deviation from 512
Hz indicates the degree and direction of oscillator

frequency shift at the test temperature. For exam­ple, a reading of 512.01024 Hz would indicate a
+20 PPM oscillator frequency error , r equiring a -10
(WR001010) to be loaded into the Calibration Byte
for correction. Note that setting or changing the
Calibration Byte does not affect the Frequency test
output frequency. The device must be selected and
addresses must stable at Address 1FF9h when
reading the 512 Hz on DQ0.

The FT bit must be set using the same method used
to set the clock, using the Write bit. The LSB of the
Seconds Register is monitored by holding the
M48T08/18 in an extended read of the Seconds
Register, without having the Read bit set. The FT
bit MUST be reset to ’0’ for normal clock operations
to resume.

For more information on calibration, see the Appli­cation Note AN924 "TIMEKEEPER Calibration".

13/19

M48T08, M48T18

POWER SUPPLY DECOUPLING and UNDER­SHOOT PROTECTION

I

CC

transients, including those produced by output
switching, can produce voltage fluctuations, result­ing in spikes on the V

CC

bus. These transients can
be reduced if capacitors are used to store energy,
which stabilizes the V

CC

bus. The energy stored in
the bypass capacitors will be released as low going
spikes are generated or ener gy will be absorbed
when overshoots occur. A ceramic bypass capaci­tor value of 0.1µF (as shown in Figure 12) is
recommended in order to provide the needed filter­ing.

In addition to transients that are caused by normal
SRAM operation, power cycling can generate
negative voltage spikes on V

CC

that drive it to

values below V

SS

by as much as one Volt. These
negative spikes can cause data corruption in t he
SRAM while in battery backup mode. To protect
from these voltage spikes, it is recommeded to
connect a schottky diode from V

CC

to VSS (cathode

connected to V

CC

, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.

AI02169

V

CC

0.1µF DEVICE

V

CC

V

SS

Figure 12. Supply Voltage Protection

14/19

M48T08, M48T18

ORDERING INFORMATION SCHEME

Supply Voltage and Write

Protect Voltage

08

(1)

VCC = 4.75V to 5.5V
V

PFD

= 4.5V to 4.75V

18 V

CC

= 4.5V to 5.5V

V

PFD

= 4.2V to 4.5V

Speed

-100 100ns

-150 150ns

Package

PC PCDIP28
MH

(2)

SOH28

Temp. Range

1 0 to 70 °C

Shipping Method

for SOIC

blank Tubes
TR Tape & Reel

Example: M48T18 -100 MH 1 TR

Notes:

1. The M48T08 part is offered with the PCDIP28 (i.e. CAPHAT) package only.

2. The SOIC package (SOH28) requires the battery /c rystal package (SNAPHAT) which is ordered separately under the part number
"M4T28-BR12SH1" in plasti c tube or "M4T28 -BR 12SH 1T R" in Tape & Reel form.

Caution:

Do not place the SNAPHAT battery/crystal package "M4T18-BR12SH1" in conductive foam since this will drain the lithiu m
button-cell battery.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.

15/19

M48T08, M48T18

PCDIP

A2

A1AL

B1 B e1

D

E

N

1

C

eA

e3

Symb

mm inches

Typ Min Max Typ Min Max

A 8.89 9.65 0.350 0.380
A1 0.38 0.76 0.015 0.030
A2 8.38 8.89 0.330 0.350

B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070

C 0.20 0.31 0.008 0.012
D 39.37 39.88 1.550 1.570

E 17.83 18.34 0.702 0.722
e1 2.29 2.79 0.090 0.110
e3 29.72 36.32 1.170 1.430
eA 15.24 16.00 0.600 0.630

L 3.05 3.81 0.120 0.150

N28 28

Drawing is not to scale.

PCDIP2 8 - 28 pin Plasti c D IP, battery CAPHAT

16/19

M48T08, M48T18

SOH-A

E

N

D

C

LA1 α

1

H

A

CP

Be

A2

eB

Symb

mm inches

Typ Min Max Typ Min Max

A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e1.27– –0.050– –
eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α 0° 8° 0° 8°

N28 28

CP 0.10 0.004

Drawing is not to scale.

SOH28 - 2 8 l ead Plastic Small Ou tli ne, batter y SNAPHAT

17/19

M48T08, M48T18

SHTK-A

A1

A

D

E

eA

eB

A2

B

L

A3

Symb

mm inches

Typ Min Max Typ Min Max

A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

Drawing is not to scale.

SH - SNAPHAT Housing for 28 lead Plastic Small Outline

18/19

M48T08, M48T18

Information furnished is believed to be accurate and reliable. However, STMicroelectronics as sumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and repl aces all information previously supplied. STMicroelectron ics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

© 1999 STMicroelectronics - All Rights Reserved

® TIMEKEEPER and SNAPHAT are registered trademarks of STMicroelectronics



CAPHAT, BYTEWIDE and BiPORT are trademarks of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

19/19

M48T08, M48T18