Page 1
5V, 64 Kbit (8 Kb x 8) TIMEKEEPER® SRAM
FEATURES SUMMARY
■ INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT, and BATTERY
■ BYTEWIDE™ RAM-LIKE CLOCK ACCESS
■ BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, and SECONDS
■ TYPICAL CLOCK ACCURACY OF ±1 MINUTE
A MONTH, AT 25°C
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■ WRITE PROTECT VOLTAGES
(V
= Power-fail Deselect Voltage):
PFD
– M48T08: V
4.5V ≤ V
– M48T18/T08Y: V
4.2V ≤ V
■ SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
■ SELF-CONTAINED BATTERY and CRYSTAL
IN THE CAPHAT™ DIP PACKAGE
■ PACKAGING INCLU DES A 28-LEAD SOIC and
SNAPHAT
■ (to be Ordered Separately)
■ SOIC PACKAGE PROVIDES DIR EC T
CONNECTION F OR A SNAPHAT TOP WHI CH
CONTAINS THE BATTERY and CRYSTAL
■ PIN and FUNCTION COMPATIBLE WITH
DS1643 and JEDEC STANDARD 8K x 8
SRAMs
= 4.75 to 5. 5V
CC
≤ 4.75V
PFD
≤ 4.5V
PFD
®
TOP
= 4.5 to 5.5V
CC
M48T08
M48T08Y, M48 T18
Figure 1. 28-pin PCDIP, CAPHAT™ Package
28
1
PCDIP28 (PC)
Battery/Crystal
CAPHAT
Figure 2. 28-pi n S O I C Package
SNAPHAT (SH)
Battery/Crystal
28
1
SOH28 (MH)
Rev. 4.0
1/26March 2003
Page 2
M48T08, M48T18, M48T08Y
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 5. SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 7. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. WRITE Enable Controlled, WRITE AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 10. Chip Enable Controlled, WRITE AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reading the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Setting the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Crystal Accuracy Across Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
V
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CC
Figure 14. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
Page 3
M48T08, M48T18, M48T08Y
SUMMARY DESCRIPTION
®
The M48T08/18/08Y TIMEKEEPER
RAM is an
8K x 8 non-volatile static RAM and real time clock
which is pin and functional compatible with the
DS1643. The monolithic chip is available in two
special packages to provide a highly integrated
battery backed-up memory and real time clock solution.
The M48T08/18/08Y is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
The 28-pin, 600mil DIP CAPHAT™ houses the
M48T08/18/08Y silicon with a quartz crystal and a
long- life lithium button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct connection to a separate SNAPHAT
taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and c rystal dam age due to
the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For t he 2 8 le ad S OIC , t he ba ttery/crystal package (e.g., SNAPHAT) part number is “M4T28-BR12SH” or “M4T32-BR12SH”
(see Table 17, page 24).
Figure 3. Logic Diagram Table 1. Signal Names
A0-A12 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
INT
E1
Power Fail Interrupt (Open Drain)
Chip Enable 1
A0-A12
13
V
CC
8
DQ0-DQ7
®
housing con-
W
E1 INT
E2
G
M48T08
M48T08Y
M48T18
V
SS
AI01020
E2 Chip Enable 2
G
W
V
V
CC
SS
Output Enable
WRITE Enable
Supply Voltage
Ground
3/26
Page 4
M48T08, M48T18, M48T08Y
Figure 4. DIP C on ne ctions Figure 5. SOI C Co nn e ct io ns
INT V
1
A12
2
3
A7
4
A6
5
A5
6
A4
7
A3
A2
A1
A0
DQ0
8
9
10
11
M48T08
M48T18
12
13
DQ2
14
SS
Figure 6. Block Diagram
32,768 Hz
CRYSTAL
28
CC
27
W
26
E2
25
A8
24
A9
23
A11
22
G
21
A10
20
E1
19
DQ7
18
DQ6
17
DQ5DQ1
16
DQ4
15
DQ3V
AI01182
OSCILLATOR AND
CLOCK CHAIN
INT V
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
1
2
3
4
5
6
7
8
9
10
11
M48T08Y
12
DQ2
SS
8 x 8 BiPORT
SRAM ARRAY
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI01021B
A0-A12
CC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
CC
INTV
POWER
V
PFD
8184 x 8
SRAM ARRAY
V
SS
DQ0-DQ7
E1
E2
W
G
AI01333
4/26
Page 5
M48T08, M48T18, M48T08Y
MAXIMUM RATI N G
Stressing the device ab ove the rating listed in t he
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the dev ice at
these or any other conditions above those indicated in the Operating sections of this specification is
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
A
T
STG
(1,2)
T
SLD
V
IO
V
CC
I
O
P
D
Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer
than 30 seco nd s) .
2. For SO pa ck age: Re flow at pea k temp era ture of 2 15°C t o 225° C fo r < 60 se conds (tot al t herm al bu dge t not to excee d 180 °C for
between 90 t o 120 seco nds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC t o avoid damaging SNAP HAT sockets.
Ambient Operating Temperature 0 to 70 °C
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages –0.3 to 7 V
Supply Voltage –0.3 to 7 V
Output Current 20 mA
Power Dissipation 1 W
not implied. Exposure to Absol ute Maxim um Ra ting conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and other relevant quality documents.
–40 to 85 °C
5/26
Page 6
M48T08, M48T18, M48T08Y
DC AND AC PARAMETERS
This section summarizes the operat ing and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the M easure-
Table 3. Operating and AC Measurement Conditions
Parameter M48 T08 M48T18/T08Y Unit
ment Conditions listed in the rel evant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Supply Voltage (V
Ambient Operating Temperature (T
Load Capacitance (C
CC
)
)
A
)
L
4.75 to 5.5 4.5 to 5.5 V
0 to 70 0 to 70 °C
100 100 pF
Input Rise and Fall Times ≤ 5 ≤ 5ns
Input Pulse Voltages 0 to 3 0 to 3 V
Input and Output Timing Ref. Voltages 1.5 1.5 V
Note: Output Hi-Z is defined as the point wh ere data is no l onger driv en.
Figure 7. AC Testing Load Circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
1kΩ
OUT
CL = 100pF
CL includes JIG capacitance
AI01019
Table 4. Capacitance
Symbol
C
IN
C
IO
Note: 1. Effecti ve capacit ance meas ured with po wer supp l y at 5V ; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs desele ct ed.
Input Capacitance 10 pF
(3)
Input / Output Capacitance 10 pF
Parameter
6/26
(1,2)
Min Max Unit
Page 7
Table 5. DC Characteristics
Symbol Parameter
Test Condition
(1)
M48T08, M48T18, M48T08Y
M48T08/M48T18/T08Y
Unit
Min Max
I
LI
(2)
I
LO
I
CC
(3)
I
CC1
(3)
I
CC2
(4)
V
IL
V
IH
Input Leakage Current
Output Leakage Current
Supply Current Outputs open 80 mA
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage –0.3 0.8 V
Input High Voltage 2.2
0V ≤ V
0V ≤ V
E1
E1
E2 = V
Output Low Voltage
V
OL
Output Low Voltage (INT
V
OH
Note: 1. Valid for Ambien t Operating T em perature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V ( except whe re noted).
2. Outputs desele ct ed.
3. Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0.'
4. Negative s p i k e s of –1V allo wed for up t o 10 ns once pe r Cycle.
5. The INT
Output High Voltage
pin is Open Drain.
(5)
)
≤ V
IN
CC
≤ V
OUT
= V
E2 = V
IH,
= VCC – 0.2V,
+ 0.2V
SS
I
= 2.1mA
OL
IOL = 0.5mA
I
= –1mA
OH
CC
±1 µA
±1 µA
IL
3mA
3mA
V
+ 0.3
CC
0.4 V
0.4 V
2.4 V
V
7/26
Page 8
M48T08, M48T18, M48T08Y
OPERATION MODES
As Figure 6, page 4 s hows, the static memory array and the quartz-controlled clock oscillator of the
M48T08/18/08Y are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE™ clock information in the by tes with
addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap yea r - valid until
2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This
byte controls user access to the clock information
and also stores the clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locat ions
consisting of BiPORT™ READ/WRITE memory
Table 6. Operating Modes
4.75 to 5.5V
4.5 to 5.5V
VSO to V
≤ V
V
CC
or
PFD
SO
(min)
(1)
(1)
E1 E2 G W DQ0-DQ7 Power
V
IH
V
IL
V
IL
V
IL
X X X X High Z CMOS Standby
X X X X High Z Battery Back-up Mode
X X X High Z Standby
V
IL
V
IH
V
IH
V
IH
Mode
Deselect
Deselect X
WRITE
READ
READ
Deselect
Deselect
Note: X = VIH or VIL; VSO = Batte ry Back -up Swit c h over Vol tage.
1. See Table 10, page 15 for detail s.
cells. The M48T08/18/08Y includes a clock control
circuit which updates the clock bytes with current
information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T08/18/08Y also has its own Power-fail
Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance
condition. When V
is out of tolerance, the circuit
CC
write protects the S RAM, p roviding a high degree
of data security in the midst of unpredictable s ystem operation brought on by low V
. As VCC falls
CC
below the Battery Back-up Switchover Voltage
), the control circuitry connects the battery
(V
SO
which maintains data and clock operation until valid power returns.
X X High Z Standby
X
V
IL
V
IH
V
IL
V
IH
V
IH
D
IN
D
OUT
High Z Active
Active
Active
8/26
Page 9
READ Mode
The M48T08/18/08Y i s in the READ M ode whenever W
(WRITE Enable) is high, E1 (Chip Enable
1) is low, and E2 (Chip Enable 2 ) is hi gh. The device architecture allows ripple-through access of
data from eight of 65,536 locations in the static
storage array. Thus, the unique address specified
by the 13 address inputs defines which one of the
8,192 bytes of data is to be accessed. Valid data
will be available at the Data I/O pins within address
access time (t
signal is stable, providing that the E1
) after the last address input
AVQV
, E2, and G
access times are a lso satisfied. I f the E1 , E2 and
access times are not met, valid data will be
G
Figure 8. READ Mode AC Waveforms
M48T08, M48T18, M48T08Y
available after the latter of the Chip Enable Access
times ( t
time ( t
GLQV
E1LQV
).
or t
The state of the eight t hree-s tate Da ta I/O s i gnals
is controlled by E1
tivated before t
AVQV
an indeterminate state until t
inputs are changed while E1
tive, output data will remain valid for Output Data
Hold time (t
) but will go indeterminate until the
AXQX
next address access.
tAVAV
) or Output Enable Access
E2HQV
, E2 and G. If the outputs are ac-
, the data lines will be driven to
. If the address
AVQV
, E2 and G remain ac-
A0-A12
E1
E2
G
DQ0-DQ7
Note: WRITE Enable (W) = High.
VALID
tAVQV tAXQX
tE1LQV
tE1LQX
tE2HQV
tE2HQX
tGLQX
tGLQV
tGHQZ
VALID
tE1HQZ
tE2LQZ
AI00962
9/26
Page 10
M48T08, M48T18, M48T08Y
Table 7. READ Mode AC Characteristics
M48T08/M4 8T18/ T08Y
Symbol
t
AVAV
t
AVQV
t
E1LQV
t
E2HQV
t
GLQV
t
E1LQX
t
E2HQX
t
GLQX
t
E1HQZ
t
E2LQZ
t
GHQZ
t
AXQX
Note: 1. Valid for Ambien t Operating T em perature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V ( except whe re noted).
READ Cycle Time 100 150 ns
Address Valid to Output Valid 100 150 ns
Chip Enable 1 Low to Output Valid 100 150 ns
Chip Enable 2 High to Output Valid 100 150 ns
Output Enable Low to Output Valid 50 75 ns
Chip Enable 1 Low to Output Transition 10 10 ns
Chip Enable 2 High to Output Transition 10 10 ns
Output Enable Low to Output Transition 5 5 ns
Chip Enable 1 High to Output Hi-Z 50 75 ns
Chip Enable 2 Low to Output Hi-Z 50 75 ns
Output Enable High to Output Hi-Z 40 60 ns
Address Transition to Output Transition 5 5 ns
Parameter
(1)
Min Max Min Max
Unit–100/–10 (T08Y) –150/–15 (T08Y)
10/26
Page 11
WRITE Mode
The M48T08/18/08Y is in the WRITE Mode whenever W
, E1, and E2 are active. The start of a
WRITE is referenced from the latter occurring falling edge of W
or E1, or the rising edge of E2. A
WRITE is terminated by the earlier rising edge of
or E1, or the falling edge of E2. T he addres ses
W
must be held valid throughout the cycle. E1
must return high or E2 low for a minimum of t
or t
from Chip Enable or t
E2LAX
from WRITE
WHAX
or W
E1HAX
Enable prior to the initiation of another READ or
WRITE Cycle. Data-in must be valid t
the end of WRITE and remain valid for t
terward. G
cles to avoid bus contention; however, if the output
bus has been activated by a low on E1
a high on E2, a low o n W
t
WLQZ
Figure 9. WRITE Enable Controlled, WRITE AC Waveform
tAVAV
M48T08, M48T18, M48T08Y
DVWH
should be kept high during WRITE Cy-
will disable the o utputs
after W falls.
prior to
af-
WHDX
and G and
A0-A12
E1
E2
W
DQ0-DQ7
tAVE1L
tAVE2H
tAVWL
tWLQZ
VALID
tAVWH
tWLWH
tDVWH
tWHAX
tWHQX
tWHDX
DATA INPUT
AI00963
11/26
Page 12
M48T08, M48T18, M48T08Y
Figure 10. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
A0-A12
E1
E2
W
DQ0-DQ7
VALID
tAVE1H
tAVE1L
tAVE2H tE2HE2L
tAVWL
tE1LE1H
tAVE2L
tDVE1H
tDVE2L
tE1HAX
tE2LAX
tE1HDX
tE2LDX
DATA INPUT
AI00964B
12/26
Page 13
M48T08, M48T18, M48T08Y
Table 8. WRITE Mode AC Characteristics
M48T08/M48 T18/ T08Y
Symbol
t
AVAV
t
AVWL
t
AVE1L
t
AVE2H
t
WLWH
t
E1LE1H
t
E2HE2L
t
WHAX
t
E1HAX
t
E2LAX
t
DVWH
t
DVE1H
t
DVE2L
t
WHDX
t
E1HDX
t
E2LDX
t
WLQZ
t
AVWH
t
AVE1H
t
AVE2L
t
WHQX
Note: 1. Valid for Ambien t Operating T em perature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V ( except whe re noted).
WRITE Cycle Time 100 150 ns
Address Valid to WRITE Enable Low 0 0 ns
Address Valid to Chip Enable 1 Low 0 0 ns
Address Valid to Chip Enable 2 High 0 0 ns
WRITE Enable Pulse Width 80 100 ns
Chip Enable 1 Low to Chip Enable 1 High 80 130 ns
Chip Enable 2 High to Chip Enable 2 Low 80 130 ns
WRITE Enable High to Address Transition 10 10 ns
Chip Enable 1 High to Address Transition 10 10 ns
Chip Enable 2 Low to Address Transition 10 10 ns
Input Valid to WRITE Enable High 50 70 ns
Input Valid to Chip Enable 1 High 50 70 ns
Input Valid to Chip Enable 2 Low 50 70 ns
WRITE Enable High to Input Transition 5 5 ns
Chip Enable 1 High to Input Transition 5 5 ns
Chip Enable 2 Low to Input Transition 5 5 ns
WRITE Enable Low to Output Hi-Z 50 70 ns
Address Valid to WRITE Enable High 80 130 ns
Address Valid to Chip Enable 1 High 80 130 ns
Address Valid to Chip Enable 2 Low 80 130 ns
WRITE Enable High to Output Transition 10 10 ns
Parameter
(1)
Min Max Min Max
Unit–100/–10 (T08Y) –150/–15 (T08Y)
13/26
Page 14
M48T08, M48T18, M48T08Y
Data Retention Mode
With valid V
ates as a convention al BY TEWIDE™ static RAM.
Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V
(min) window. All outputs become high impedance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently a ddressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
assured the memory will be i n a write protected
state, provided the V
The M48T08/18/08Y may respond to transient
noise spikes on V
window during the time the device is sampling
V
. Therefore, decoupling of the power supply
CC
lines is recommended.
When V
switches power to the internal battery which preserves data and powers the clock. The internal
button cell will maintain data in the M48T08/18/
08Y for an accumulated period of at least 10 years
when V
CC
applied, the M48T08/ 18/ 08Y oper-
CC
falls within the V
CC
(min), the user can be
PFD
fall time is not less than tF.
CC
that reach into the des elect
CC
drops below VSO, the control circuit
CC
PFD
(max), V
is less than VSO.
PFD
Note: Requires use of M4T32-BR12SH
SNAPHAT
As system power returns and V
V
SO
supply is switched to external V
Write protection continues until V
(min) plus t
low as V
®
top when using the SOH28 package.
rises above
CC
, the battery is disconnected and the power
.
CC
reaches V
(min). E1 should be kept high or E2
REC
rises past V
CC
PFD
CC
(min) to prevent inad-
PFD
vertent WRITE cyc les pr ior to system st abilization.
Normal RAM operation can resume t
exceeds V
PFD
(max).
REC
after V
CC
For more information on Battery Storage Life refer
to the Application Note AN1012.
Power-fail Interrupt Pin
The M48T08/18/08Y cont inuously monitors V
When V
falls to the power-fail detect trip point,
CC
CC
an interrupt is immediately generated. An internal
clock provides a delay of between 10µs and 40µ s
before automatically deselecting the M 48T08/18/
08Y. The INT
pin is an open drain output and requires an external pull up resistor, even if the interrupt output function is not being used.
.
Figure 11. Power Down/Up Mode AC Waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
VSO
tF
tPD tRB
INT
INPUTS
OUTPUTS
Note: Inp uts may or may not be rec ogni zed at th is time . Caut ion shoul d be tak en to ke ep E1 hi gh or E2 low as VCC rises past V
Some systems may perform inadvertent WRITE cycles after V
Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
VALID VALID
(PER CONTROL INPUT)
tFB
tPFX
tDR
rises above V
CC
DON'T CARE
HIGH-Z
(min) but before normal system operations begin.
PFD
tR
tPFH
NOTE
(PER CONTROL INPUT)
tREC
RECOGNIZEDRECOGNIZED
AI00566
PFD
(min).
14/26
Page 15
M48T08, M48T18, M48T08Y
Table 9. Power Down/Up AC Characteristics
Symbol
t
PD
(2)
t
F
(3)
t
FB
t
R
t
RB
t
REC
t
PFX
t
PFH
Note: 1. Valid for Ambien t Operating T em perature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V ( except whe re noted).
2. V
es V
3. V
E1 or W at VIH or E2 at VIL before Power Down
V
(max) to V
PFD
V
(min) to VSS VCC Fall Time
PFD
V
(min) to V
PFD
VSS to V
PFD
E1 or W at VIH or E2 at V
INT Low to Auto Deselect 10 40 µs
V
(max) to INT High
PFD
(max) t o V
PFD
(min).
PFD
(min) to VSS fall time of less than tFB may cause corruption of RAM data.
PFD
(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-
PFD
Parameter
(min) VCC Fall Time
PFD
(max) VCC Rise Time
PFD
(min) VCC Rise Time
Table 10. Power Down/Up Trip Points DC Characteristics
Symbol
Parameter
(1)
before Power Up
IL
(1,2)
Min Max Unit
0µs
300 µs
10 µs
0µs
1µs
1ms
120 µs
Min Typ Max Unit
V
PFD
V
SO
t
DR
Note: 1. All voltages referenced to VSS.
2. Vali d for Ambient Operating T em perature: T
3. At 55°C, V
Power-fail Deselect Voltage
Battery Back-up Switchover Voltage 3.0 V
Expected Data Retention Time
= 0V; tDR = 8.5 years (typ) at 70°C. Requires use of M4T32-BR12SH SNAPHAT® top when using the SOH28 package.
CC
M48T08 4.5 4.6 4.75 V
M48T18/T08Y 4.2 4.3 4.5 V
(3)
10
= 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V ( except whe re noted).
A
YEARS
15/26
Page 16
M48T08, M48T18, M48T08Y
CLOCK OPERATIONS
Reading the Clock
®
Updates to the TIMEKEEPER
registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT ™ TIMEKEEPER cel ls in th e RAM array a re o n ly data re g isters and not the actual clock counters, so
updating the registers can be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, the seventh bit in the control register.
As long as a '1' remains in that po sition, updating
is halted. After a halt is issued, the registers reflect
the count; tha t is, the day, dat e, and the tim e that
were current at the moment the halt command was
issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a '0.'
Table 11. Register Map
Address
D7 D6 D5 D4 D3 D2 D1 D0
1FFFh 10 Years Year Year 00 -99
Data
Setting the C l ock
The eighth bit of the control register is the WRITE
Bit. Setting the WRITE Bit to a '1,' like the RE AD
Bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (on Table 11). Resetting the WRITE Bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh)
to the actual TIMEKEEPER counters and allows
normal operation to resum e. The FT Bit and the
bits marked as '0' in Table 11 must be written to '0'
to allow for normal TIMEKEEPER and RAM operation.
See the Application Note AN923, “TIMEKEEPER
Rolling Into the 21st Century” for information on
Century Rollover.
Function/Range
BCD Format
®
1FFEh 0 0 0 10 M Month Month 01-12
1FFDh 0 0 10 Date Date Date 01-31
1FFCh 0 FT 0 0 0 Day Day 01-07
1FFBh 0 0 10 Hours Hours Hours 00-23
1FFAh 0 10 Minutes Minutes Minutes 00-59
1FF9h ST 10 Seconds Seconds Seconds 00-59
1FF8h W R S Calibration Control
Keys : S = SIG N Bit
FT = FREQUE NCY TEST Bit (Set to '0' for norm al clock operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
16/26
Page 17
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit (ST) is the MSB of the seconds register. Setting
it to a '1' stops the oscillator. The M48T08/ 18/08Y
(in the PCDIP28 package) is shipped from STMicroelectronics with the STOP Bit set to a '1.' When
reset to a '0,' the M48T08/18/08Y oscillator starts
within one second.
Note: To guarant ee oscillato r start-up af ter initial
power-up, first write the STOP Bit (ST) to '1,' then
reset to '0.'
Calib rating the C lock
The M48T08/18/08Y is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. A typical M48T08/18/08Y is accurate
within 1 minute per month at 25°C without calibration. The devices are tested not to exceed ± 35
PPM (parts per million) oscillator frequenc y error
at 25°C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T08/18/08Y improves to
better than +1/–2 PPM at 25°C.
The oscillation rate of any crystal changes with
temperature. Figure 12, page 18 shows the frequency error that can be expected at various temperatures. Most clock chips compensate for
crystal frequency and temperat ure shift error with
cumbersome “trim” capacitors. The M48T08/18/
08Y design, however, employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 13, page 18.
The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive
calibration) depends upon the value loaded into
the five-bit Calibration Byte f ound in the Control
Register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order
bits in the Control register. This byte can be set to
represent any value be tween 0 and 31 in binary
form. The sixth bit is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration.
Calibration occurs within a 64 minute cycle. The
first 62 minutes i n the cycle may, o nce per minut e,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary '1'
is loaded into the register, only the first 2 minutes
M48T08, M48T18, M48T08Y
in the 64 minute cycle will be modified; if a binary
6 is loaded, the first 12 will be affected, and so on.
Therefore, each cal ibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles; that is
+4.068 or –2.034 PPM of adjustm ent per calibration step in the cal ibration registe r. Ass um ing that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration Byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T08/18/08Y may require. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the final product is packaged in a non-user serviceable
enclosure. All the d esigner has t o do i s provide a
simple utility that accesses the Calibration Byte.
The second approach is better suit ed to a manufacturing environment, and involves the use of
standard test equipment. When the Frequency
Test (FT) Bit, the seventh-most significant bit in
the Day R egist er, is se t to a '1 ,' an d th e os cillat or
is running at 32,768 Hz, the LSB (DQ0) of the Seconds Register will toggle at 512 Hz. Any deviation
from 512 Hz indicates the degree and direction of
oscillator frequency shift at the test temperature.
For example, a reading of 512.01024 Hz would indicate a +20 PPM oscilla tor frequency e rror, requiring a –10 (WR001010) to be loaded into the
Calibration Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output frequency. The device must be selected and addresses must be stable at Address 1FF9h when
reading the 512 Hz on DQ0.
The FT Bit must be set using the same method
used to set the clo ck: using the WRITE Bit. The
LSB of the Seconds Register is monitored by holding the M48T08/18/08Y in an ext ended READ of
the Seconds Register, but without having the
READ Bit set. The FT Bit MUST be reset to '0' for
normal clock operations to resume.
For more information on calibration, see the Application Note AN934, “TIMEKEEPER
®
Calibration.”
17/26
Page 18
M48T08, M48T18, M48T08Y
Figure 12. Crystal Accuracy Across Temp eratur e
ppm
20
0
-20
-40
-60
-80
-100
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
Figure 13. Cloc k C al ib rat i on
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
∆F
= -0.038 (T - T0)2 ± 10%
F
ppm
2
C
T0 = 25 °C
°C
AI02124
AI00594B
18/26
Page 19
M48T08, M48T18, M48T08Y
VCC Noise And Negative Going Transients
transients, including those produced by output
I
CC
switching, can produce voltage fluctuations, resulting in spikes on the V
bus. These transients
CC
can be reduced if capacitors are used to store energy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure
14) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on V
below V
by as much as one volt. These negative
SS
that drive it to values
CC
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to connect a schottky diode from V
connected to V
, anode to VSS). Schottky diode
CC
to VSS (cathode
CC
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
Figure 14. Supply Voltage Protection
V
CC
V
CC
0.1µF DEVICE
V
SS
AI02169
19/26
Page 20
M48T08, M48T18, M48T08Y
PACKAGE MECHANICAL INFORMATION
Figure 15. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline
A2
A1AL
C
B1 B e1
eA
e3
D
N
E
1
Note: Drawing is not to scale.
PCDIP
Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A 8.89 9.6 5 0.350 0.380
A1 0.38 0.7 6 0.015 0.030
A2 8.38 8.8 9 0.330 0.350
B 0.38 0.5 3 0.015 0.021
mm inches
B1 1.14 1.7 8 0.045 0.070
C 0.20 0.31 0. 008 0.012
D 39.37 39.88 1.550 1.570
E 17.83 18.34 0.702 0 .722
e1 2.29 2.79 0.090 0.110
e3 29.72 36.32 1.170 1 .430
eA 15.24 16.00 0.600 0.630
L 3.05 3.81 0.120 0 .150
N28 28
20/26
Page 21
M48T08, M48T18, M48T08Y
Figure 16. SOH28 – 2 8-lea d P last ic Small Outlin e, 4- socket batt ery S NA P HAT, Package Outline
A2
A
C
Be
eB
CP
D
N
E
H
LA1 α
1
SOH-A
Note: Drawing is not to scale.
Table 13. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Mechanical Data
Symb
T yp Min Max Typ Min Max
mm inches
A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e 1.27 – – 0.050 – –
eB 3.20 3.61 0.126 0.142
H 1 1.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N 28 28
CP 0.10 0.004
21/26
Page 22
M48T08, M48T18, M48T08Y
Figure 17. SH – 4-pin S NA PH AT Housi ng for 48mAh Battery & Crystal , Package Outline
A2
A3
L
eA
D
A1
A
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 14. SH – 4-pin SN AP HAT Hous ing for 48mAh Battery & Crystal, Package M echanical Data
Symb
T yp Min Max T yp Min Max
mm inches
A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
22/26
Page 23
M48T08, M48T18, M48T08Y
Figure 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A2
A3
L
eA
D
A1
A
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
mm inches
A 10.54 0.415
A1 8.00 8.5 1 0.315 .0335
A2 7.24 8.0 0 0.285 0.315
A3 0.38 0.015
B 0.46 0.5 6 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 . 0710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.6 1 0.126 0.142
L 2.03 2.29 0.080 0 .090
23/26
Page 24
M48T08, M48T18, M48T08Y
PART NUMBERING
Table 16. Ordering Information Scheme
Example: M48T 18 –100 PC 1 TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
(1)
08
= VCC = 4.75 to 5.5V; V
18/08Y = V
= 4.5 to 5.5V; V
CC
Speed
–100 = 100ns
–150 = 150ns
–10 = 100ns (M48T08Y)
= 4.5 to 4.75V
PFD
= 4.2 to 4.5V
PFD
Package
(1)
PC
= PCDIP28
(2)
MH
= SOH28
Temperature Rang e
1 = 0 to 70°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The M48 T 08/18 part is off ered with th e PCDIP28 (e.g., CAP HA T ™ ) package only.
2. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT
“M4TXX-BR 12SH” in plastic tube or “M4TXX-BR1 2SHTR” in Tape & Reel f orm. The M48T08Y part is offered in the SOH2 8
(SNAPHAT) package only.
Caution: Do not place the SNA PH AT batter y package “M4TXX-BR12SH” in c onductive f oam as it w ill drain th e l i thium button-cell
battery.
®
) which is ordered separately under the part number
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest you.
Table 17. SNAPHAT Battery Table
Part Number Description Package
M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH
M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH
24/26
Page 25
M48T08, M48T18, M48T08Y
REVISION HIST ORY
Table 18. Document Revision History
Date Rev. # Revision Details
December 1999 1.0 First Issue
07-Feb-00 2.0
11-Jul-00 2.1
16-Jul-01 3.0
01-Aug-01 3.1 Reference to App. Note corrected in “Calibrating the Clock” section
21-Dec-01 3.2 Changes to text in document to reflect addition of M48T08Y option
06-Mar-02 3.3 Fix Ordering Information table and add to footnote (Table 16)
20-May-02 3.4 Modify reflow time and temperature footnotes (Table 2)
29-Aug-02 3.5
28-Mar-03 4.0 v2.2 template applied; updated test conditions (Table 9)
From Preliminary Data to Data Sheet; Battery Low Flag paragraph changed; 100ns
speed class identifier changed (Tables 7, 8)
changed (Table 9); Watchdog Timer paragraph changed
t
FB
Reformatted; SNAPHAT battery table added (Table 17); added temp./voltage info. to
tables (Tables 4, 5, 7, 8, 9, 10)
t
specification temperature updated (Table 10)
DR
25/26
Page 26
M48T08, M48T18, M48T08Y
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the cons equences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or o therwise under any patent or patent rights of STMicroelectron i cs. Speci fications mentioned i n this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as c ri t i cal components in life support dev i ces or systems wi thout exp ress written approval of STMicroel ectronics.
The ST log o i s registered tradema rk of STMicroelectronics
All other names are the property of their resp ective owners.
© 2003 STMicroelectronics - All Rights Reserved
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