Page 1
5 V, 64 Kbit (8 Kb x 8) TIMEKEEPER® SRAM
Features
■ Integrated ultra low power SRAM, real-time
clock, power-fail control circuit, and battery
■ BYTEWIDE
■ BCD coded year, month, day, date, hours,
minutes, and seconds
■ Typical clock accuracy of ±1 minute a month, at
25 °C
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect
V
PFD
–M48T08: V
4.5 V ≤ V
– M48T18/T08Y: V
4.2 V ≤ V
■ Software controlled clock calibration for high
accuracy applications
■ Self-contained battery and crystal in the
CAPHAT
■ Packaging includes a 28-lead SOIC and
SNAPHAT
■ SOIC package provides direct connection for a
snaphat top which contains the battery and
crystal
■ Pin and function compatible with DS1643 and
JEDEC standard 8 K x 8 SRAMs
■ RoHS compliant
– Lead-free second level interconnect
™
RAM-like clock access
= power-fail deselect voltage):
= 4.75 to 5.5 V;
CC
≤ 4.75 V
PFD
= 4.5 to 5.5 V;
CC
≤ 4.5 V
PFD
™
DIP package
®
top (to be ordered separately)
M48T08
M48T08Y, M48T18
28
1
PCDIP28
battery/crystal
CAPHAT™
SNAPHAT
battery/crystal
2
8
®
1
SOH28
June 2011 Doc ID 2411 Rev 11 1/31
www.st.com
1
Page 2
Contents M48T08, M48T08Y, M48T18
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Power-fail interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 V
noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 18
CC
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31 Doc ID 2411 Rev 11
Page 3
M48T08, M48T08Y, M48T18 List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data . . . . . . . . . . . . . 23
Table 13. SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT
Table 14. SH – 4-pin SNAPHAT
Table 15. SH – 4-pin SNAPHAT
Table 16. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. SNAPHAT® battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
®
housing for 48 mAh battery & crystal, package mech. data . . . . . 25
®
housing for 120 mAh battery & crystal, package mech. data . . . . 26
®
, package mech. data. . . . . . . 24
Doc ID 2411 Rev 11 3/31
Page 4
List of figures M48T08, M48T08Y, M48T18
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 23
Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT
Figure 15. SH – 4-pin SNAPHAT
Figure 16. SH – 4-pin SNAPHAT
Figure 17. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
®
housing for 48 mAh battery & crystal, package outline. . . . . . . . . 25
®
housing for 120 mAh battery & crystal, package outline. . . . . . . . 26
®
, package outline . . . 24
4/31 Doc ID 2411 Rev 11
Page 5
M48T08, M48T08Y, M48T18 Description
1 Description
The M48T08/18/08Y TIMEKEEPER® RAM is an 8 K x 8 non-volatile static RAM and realtime clock which is pin and function compatible with the DS1643. The monolithic chip is
available in two special packages to provide a highly integrated battery-backed memory and
real-time clock solution.
The M48T08/18/08Y is a non-volatile pin and function equivalent to any JEDEC standard
8 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing
the non-volatility of PROMs without any requirement for special WRITE timing or limitations
on the number of WRITEs that can be performed.
The 28-pin, 600 mil DIP CAPHAT™ houses the M48T08/18/08Y silicon with a quartz crystal
and a long-life lithium button cell in a single package.
The 28-pin, 330 mil SOIC provides sockets with gold-plated contacts at both ends for direct
connection to a separate SNAPHAT
design allows the SNAPHAT
®
after the completion of the surface mount process. Insertion of the SNAPHAT
reflow prevents potential battery and crystal damage due to the high temperatures required
for device surface-mounting. The SNAPHAT
The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or
in tape & reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT
®
housing containing the battery and crystal. The unique
battery package to be mounted on top of the SOIC package
®
housing is keyed to prevent reverse insertion.
®
housing after
®
)
part number is “M4T28-BR12SH” or “M4T32-BR12SH”.
Figure 1. Logic diagram
V
CC
13
A0-A12
W
E1 INT
E2
M48T08
M48T08Y
M48T18
8
DQ0-DQ7
G
V
SS
Doc ID 2411 Rev 11 5/31
AI01020
Page 6
Description M48T08, M48T08Y, M48T18
Table 1. Signal names
A0-A12 Address inputs
DQ0-DQ7 Data inputs / outputs
INT Power fail interrupt (open drain)
E1 Chip enable 1
E2 Chip enable 2
G Output enable
W WRITE enable
V
CC
V
SS
Supply voltage
Ground
Figure 2. DIP connections
Figure 3. SOIC connections
INT V
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
8
9
10
11
M48T08
M48T18
A2
A1
A0
DQ0
12
DQ2
13
14
SS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
AI01182
INT V
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
1
2
3
4
5
6
7
M48T08Y
8
9
10
11
12
DQ2
SS
13
14
6/31 Doc ID 2411 Rev 11
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
AI01021B
Page 7
M48T08, M48T08Y, M48T18 Description
Figure 4. Block diagram
32,768 Hz
CRYSTAL
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
CC
INTV
POWER
V
PFD
8 x 8 BiPORT
SRAM ARRAY
8184 x 8
SRAM ARRAY
V
SS
A0-A12
DQ0-DQ7
E1
E2
W
G
AI01333
Doc ID 2411 Rev 11 7/31
Page 8
Operation modes M48T08, M48T08Y, M48T18
2 Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz-controlled clock
oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are
made automatically. Byte 1FF8h is the clock control register. This byte controls user access
to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T08/18/08Y
includes a clock control circuit which updates the clock bytes with current information once
per second. The information can be accessed by the user in the same manner as any other
location in the static memory array.
The M48T08/18/08Y also has its own power-fail detect circuit. The control circuitry
constantly monitors the single 5 V supply for an out-of-tolerance condition. When V
of tolerance, the circuit write protects the SRAM, providing a high degree of data security in
the midst of unpredictable system operation brought on by low V
battery backup switchover voltage (V
), the control circuitry connects the battery which
SO
. As VCC falls below the
CC
maintains data and clock operation until valid power returns.
CC
is out
Table 2. Operating modes
Mode V
Deselect
Deselect X V
WRITE V
READ V
READ V
Deselect
Deselect ≤ V
1. See Table 11 on page 22 for details.
Note: X = V
IH
or V
CC
4.75 to 5.5 V
or
4.5 to 5.5 V
to
V
SO
(1)
(min)
V
PFD
(1)
SO
IL ; VSO
= Battery backup switchover voltage.
E1 E2 G W DQ0-DQ7 Power
V
IH
IL
IL
IL
X X X High Z Standby
IL
V
IH
V
IH
V
IH
X X High Z Standby
XVILD
V
IL
V
IH
V
IH
V
IH
IN
D
OUT
High Z Active
Active
Active
XXXXHigh ZCMOS standby
X X X X High Z Battery backup mode
8/31 Doc ID 2411 Rev 11
Page 9
M48T08, M48T08Y, M48T18 Operation modes
2.1 READ mode
The M48T08/18/08Y is in the READ mode whenever W (WRITE enable) is high, E1 (chip
enable 1) is low, and E2 (chip enable 2) is high. The device architecture allows ripplethrough access of data from eight of 65,536 locations in the static storage array. Thus, the
unique address specified by the 13 address inputs defines which one of the 8,192 bytes of
data is to be accessed. Valid data will be available at the data I/O pins within address access
time (t
access times are also satisfied. If the E1
be available after the latter of the chip enable access times (t
enable access time (t
The state of the eight three-state data I/O signals is controlled by E1
outputs are activated before t
until t
will remain valid for output data hold time (t
address access.
Figure 5. READ mode AC waveforms
) after the last address input signal is stable, providing that the E1, E2, and G
AVQ V
, E2 and G access times are not met, valid data will
GLQV
or t
E1LQV
).
E2HQV
) or output
, E2 and G. If the
, the data lines will be driven to an indeterminate state
. If the address inputs are changed while E1, E2 and G remain active, output data
AVQ V
AVQ V
tAVAV
) but will go indeterminate until the next
AXQX
A0-A12
E1
E2
G
DQ0-DQ7
Note: WRITE enable (W
VAL ID
tAVQV tAXQX
tE1LQV
tE1LQX
tE2HQV
tE2HQX
tGLQV
tGLQX
VAL ID
tGHQZ
) = high.
tE1HQZ
tE2LQZ
AI00962
Doc ID 2411 Rev 11 9/31
Page 10
Operation modes M48T08, M48T08Y, M48T18
Table 3. READ mode AC characteristics
M48T08/M48T18/T08Y
Symbol Parameter
(1)
Unit–100/–10 (T08Y) –150/–15 (T08Y)
Min Max Min Max
t
AVAV
t
AVQ V
t
E1LQV
t
E2HQV
t
GLQV
t
E1LQX
t
E2HQX
t
GLQX
t
E1HQZ
t
E2LQZ
t
GHQZ
t
AXQX
READ cycle time 100 150 ns
Address valid to output valid 100 150 ns
Chip enable 1 low to output valid 100 150 ns
Chip enable 2 high to output valid 100 150 ns
Output enable low to output valid 50 75 ns
Chip enable 1 low to output transition 10 10 ns
Chip enable 2 high to output transition 10 10 ns
Output enable low to output transition 5 5 ns
Chip enable 1 high to output Hi-Z 50 75 ns
Chip enable 2 low to output Hi-Z 50 75 ns
Output enable high to output Hi-Z 40 60 ns
Address transition to output transition 5 5 ns
Note: Valid for ambient operating temperature: T
(except where noted).
2.2 WRITE mode
The M48T08/18/08Y is in the WRITE mode whenever W, E1, and E2 are active. The start of
a WRITE is referenced from the latter occurring falling edge of W
E2. A WRITE is terminated by the earlier rising edge of W
The addresses must be held valid throughout the cycle. E1
for a minimum of t
initiation of another READ or WRITE cycle. Data-in must be valid t
WRITE and remain valid for t
avoid bus contention; however, if the output bus has been activated by a low on E1
and a high on E2, a low on W
E1HAX
or t
from chip enable or t
E2LAX
afterward. G should be kept high during WRITE cycles to
WHDX
will disable the outputs t
= 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V
A
or E1, or the rising edge of
or E1, or the falling edge of E2.
or W must return high or E2 low
from WRITE enable prior to the
WHAX
prior to the end of
DVW H
and G
after W falls.
WLQZ
10/31 Doc ID 2411 Rev 11
Page 11
M48T08, M48T08Y, M48T18 Operation modes
Figure 6. WRITE enable controlled, WRITE AC waveform
tAVAV
A0-A12
tAVE1L
E1
tAVE2H
E2
tAVWL
W
tWLQZ
DQ0-DQ7
VAL ID
tAVWH
tWLWH
tDVWH
Figure 7. Chip enable controlled, WRITE AC waveforms
tAVAV
tWHAX
tWHQX
tWHDX
DATA INPUT
AI00963
A0-A12
E1
E2
W
DQ0-DQ7
VAL ID
tAVE1H
tAVE1L
tAVE2H tE2HE2L
tAVWL
tE1LE1H
tAVE2L
tDVE1H
tDVE2L
tE1HAX
tE2LAX
tE1HDX
tE2LDX
DATA INPUT
AI00964B
Doc ID 2411 Rev 11 11/31
Page 12
Operation modes M48T08, M48T08Y, M48T18
Table 4. WRITE mode AC characteristics
M48T08/M48T18/T08Y
Symbol Parameter
(1)
Unit–100/–10 (T08Y) –150/–15 (T08Y)
MinMaxMinMax
t
AVAV
t
AVW L
t
AVE 1L
t
AVE 2H
t
WLWH
t
E1LE1H
t
E2HE2L
t
WHAX
t
E1HAX
t
E2LAX
t
DVW H
t
DVE1H
t
DVE2L
t
WHDX
t
E1HDX
t
E2LDX
t
WLQZ
t
AVW H
t
AVE 1H
t
AVE 2L
t
WHQX
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
WRITE cycle time 100 150 ns
Address valid to WRITE enable low 0 0 ns
Address valid to chip enable 1 low 0 0 ns
Address valid to chip enable 2 high 0 0 ns
WRITE enable pulse width 80 100 ns
Chip enable 1 low to chip enable 1 high 80 130 ns
Chip enable 2 high to chip enable 2 low 80 130 ns
WRITE enable high to address transition 10 10 ns
Chip enable 1 high to address transition 10 10 ns
Chip enable 2 low to address transition 10 10 ns
Input valid to WRITE enable high 50 70 ns
Input valid to chip enable 1 high 50 70 ns
Input valid to chip enable 2 low 50 70 ns
WRITE enable high to input transition 5 5 ns
Chip enable 1 high to input transition 5 5 ns
Chip enable 2 low to input transition 5 5 ns
WRITE enable low to output Hi-Z 50 70 ns
Address valid to WRITE enable high 80 130 ns
Address valid to chip enable 1 high 80 130 ns
Address valid to chip enable 2 low 80 130 ns
WRITE enable high to output transition 10 10 ns
12/31 Doc ID 2411 Rev 11
Page 13
M48T08, M48T08Y, M48T18 Operation modes
2.3 Data retention mode
With valid VCC applied, the M48T08/18/08Y operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
become high impedance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
user can be assured the memory will be in a write protected state, provided the V
is not less than t
. The M48T08/18/08Y may respond to transient noise spikes on VCC that
F
reach into the deselect window during the time the device is sampling V
decoupling of the power supply lines is recommended.
falls within the V
CC
PFD
(max), V
(min) window. All outputs
PFD
PFD
. Therefore,
CC
(min), the
fall time
CC
When V
drops below VSO, the control circuit switches power to the internal battery which
CC
preserves data and powers the clock. The internal button cell will maintain data in the
M48T08/18/08Y for an accumulated period of at least 10 years when V
Note: Requires use of M4T32-BR12SH SNAPHAT
As system power returns and V
power supply is switched to external V
Write protection continues until V
high or E2 low as V
rises past V
CC
rises above VSO, the battery is disconnected and the
CC
CC
.
CC
reaches V
(min) to prevent inadvertent WRITE cycles prior to
PFD
system stabilization. Normal RAM operation can resume t
For more information on battery storage life refer to the application note AN1012.
2.4 Power-fail interrupt pin
The M48T08/18/08Y continuously monitors VCC. When VCC falls to the power-fail detect trip
point, an interrupt is immediately generated. An internal clock provides a delay of between
10 µs and 40 µs before automatically deselecting the M48T08/18/08Y. The INT
open drain output and requires an external pull-up resistor, even if the interrupt output
function is not being used.
is less than VSO.
CC
®
top when using the SOH28 package.
(min) plus t
PFD
rec
(min). E1 should be kept
rec
after V
exceeds V
CC
(max).
PFD
pin is an
Doc ID 2411 Rev 11 13/31
Page 14
Clock operations M48T08, M48T08Y, M48T18
3 Clock operations
3.1 Reading the clock
Updates to the TIMEKEEPER® registers should be halted before clock data is read to
prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are
only data registers and not the actual clock counters, so updating the registers can be halted
without disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, the seventh bit in the control
register. As long as a '1' remains in that position, updating is halted. After a halt is issued,
the registers reflect the count; that is, the day, date, and the time that were current at the
moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after the bit is reset to a '0.'
3.2 Setting the clock
The eighth bit of the control register is the WRITE bit. Setting the WRITE bit to a '1,' like the
READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with
the correct day, date, and time data in 24-hour BCD format (on Ta bl e 5 ). Resetting the
WRITE bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual
TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits
marked as '0' in Ta bl e 5 must be written to '0' to allow for normal TIMEKEEPER and RAM
operation.
See the application note AN923, “TIMEKEEPER
information on century rollover.
®
rolling Into the 21st century” for
14/31 Doc ID 2411 Rev 11
Page 15
M48T08, M48T08Y, M48T18 Clock operations
Table 5. Register map
Data
Address
D7 D6 D5 D4 D3 D2 D1 D0
1FFFh 10 years Year Year 00-99
1FFEh 0 0 0 10 M Month Month 01-12
1FFDh 0 0 10 date Date Date 01-31
1FFCh 0 FT 0 0 0 Day Day 01-07
1FFBh 0 0 10 hours Hours Hours 00-23
1FFAh 0 10 minutes Minutes Minutes 00-59
1FF9h ST 10 seconds Seconds Seconds 00-59
1FF8h W R S Calibration Control
Function/range
BCD format
Keys:
S = SIGN bit
FT = FREQUENCY TEST bit (set to '0' for normal clock operation)
R = READ bit
W = WRITE bit
ST = STOP bit
0 = Must be set to '0'
3.3 Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit (ST) is the MSB of the seconds register. Setting it to a '1' stops the
oscillator. The M48T08/18/08Y (in the PCDIP28 package) is shipped from
STMicroelectronics with the STOP bit set to a '1.' When reset to a '0,' the M48T08/18/08Y
oscillator starts within one second.
Note: To guarantee oscillator startup after initial power-up, first write the STOP bit (ST) to '1,' then
reset to '0.'
3.4 Calibrating the clock
The M48T08/18/08Y is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. A typical M48T08/18/08Y is accurate within 1 minute per month at 25 °C without
calibration. The devices are tested not to exceed ± 35 ppm (parts per million) oscillator
frequency error at 25 °C, which equates to about ±1.53 minutes per month. With the
calibration bits properly set, the accuracy of each M48T08/18/08Y improves to better than
+1/–2 ppm at 25 °C.
The oscillation rate of any crystal changes with temperature. Figure 8 on page 17 shows the
frequency error that can be expected at various temperatures. Most clock chips compensate
for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The
Doc ID 2411 Rev 11 15/31
Page 16
Clock operations M48T08, M48T08Y, M48T18
M48T08/18/08Y design, however, employs periodic counter correction. The calibration
circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage,
as shown in Figure 9 on page 17. The number of times pulses are blanked (subtracted,
negative calibration) or split (added, positive calibration) depends upon the value loaded into
the five-bit calibration byte found in the control register. Adding counts speeds the clock up,
subtracting counts slows the clock down.
The calibration byte occupies the five lower order bits in the control register. This byte can
be set to represent any value between 0 and 31 in binary form. The sixth bit is the sign bit;
'1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a
64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second
either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into
the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is
loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is in
fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or
–2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M48T08/18/08Y
may require. The first involves simply setting the clock, letting it run for a month and
comparing it to a known accurate reference (like WWV broadcasts). While that may seem
crude, it allows the designer to give the end user the ability to calibrate his clock as his
environment may require, even after the final product is packaged in a non-user serviceable
enclosure. All the designer has to do is provide a simple utility that accesses the calibration
byte.
The second approach is better suited to a manufacturing environment, and involves the use
of standard test equipment. When the frequency test (FT) bit, the seventh-most significant
bit in the day register, is set to a '1,' and the oscillator is running at 32,768 Hz, the LSB
(DQ0) of the seconds register will toggle at 512 Hz. Any deviation from 512 Hz indicates the
degree and direction of oscillator frequency shift at the test temperature. For example, a
reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a
–10 (WR001010) to be loaded into the calibration byte for correction.
Note: Setting or changing the calibration byte does not affect the frequency test output frequency.
The device must be selected and addresses must be stable at address 1FF9h when reading
the 512 Hz on DQ0.
The LSB of the seconds register is monitored by holding the M48T08/18/08Y in an extended
READ of the seconds register, but without having the READ bit set. The FT bit MUST be
reset to '0' for normal clock operations to resume.
For more information on calibration, see the application note AN934, “TIMEKEEPER
®
calibration.”
16/31 Doc ID 2411 Rev 11
Page 17
M48T08, M48T08Y, M48T18 Clock operations
Figure 8. Crystal accuracy across temperature
ppm
20
0
-20
-40
ΔF
= -0.038 (T - T
-60
-80
-100
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
F
Figure 9. Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
ppm
2
C
T0 = 25 °C
)2 ± 10%
0
°C
AI02124
AI00594B
Doc ID 2411 Rev 11 17/31
Page 18
Clock operations M48T08, M48T08Y, M48T18
3.5 VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the V
capacitors are used to store energy which stabilizes the V
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 10) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
Schottky diode from V
to VSS (cathode connected to VCC, anode to VSS). Schottky diode
CC
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
Figure 10. Supply voltage protection
V
CC
bus. These transients can be reduced if
CC
that drive it to values below VSS by as much as
CC
V
bus. The energy stored in the
CC
CC
0.1µF DEVICE
V
SS
AI02169
18/31 Doc ID 2411 Rev 11
Page 19
M48T08, M48T08Y, M48T18 Maximum ratings
4 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 6. Absolute maximum ratings
Symbol Parameter Value Unit
T
A
T
STG
(1)(2)(3)
T
SLD
V
IO
V
CC
I
O
P
D
1. For DIP package, soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds.
Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of
wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage
to the batteries.
2. For DIP packaged devices, ultrasound vibrations should not be used for post-solder cleaning to avoid
damaging the crystal.
3. For SO package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260 °C (the time above
255 °C must not exceed 30 seconds).
Ambient operating temperature 0 to 70 °C
Storage temperature (VCC off, oscillator off) –40 to 85 °C
Lead solder temperature for 10 seconds 260 °C
Input or output voltages –0.3 to 7 V
Supply voltage –0.3 to 7 V
Output current 20 mA
Power dissipation 1 W
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT
®
sockets.
Doc ID 2411 Rev 11 19/31
Page 20
DC and AC parameters M48T08, M48T08Y, M48T18
5 DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 7. Operating and AC measurement conditions
Parameter M48T08 M48T18/T08Y Unit
Supply voltage (VCC) 4.75 to 5.5 4.5 to 5.5 V
Ambient operating temperature (T
Load capacitance (CL) 100 100 pF
Input rise and fall times ≤ 5 ≤ 5ns
Input pulse voltages 0 to 3 0 to 3 V
Input and output timing ref. voltages 1.5 1.5 V
Note: Output Hi-Z is defined as the point where data is no longer driven.
) 0 to 70 0 to 70 °C
A
Figure 11. AC testing load circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
1kΩ
CL includes JIG capacitance
OUT
CL = 100pF
Table 8. Capacitance
Symbol Parameter
C
C
IO
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz.
3. Outputs deselected.
Input capacitance - 10 pF
IN
(3)
Input / output capacitance - 10 pF
(1)(2)
Min Max Unit
AI01019
20/31 Doc ID 2411 Rev 11
Page 21
M48T08, M48T08Y, M48T18 DC and AC parameters
Table 9. DC characteristics
Symbol Parameter Test condition
(1)
M48T08/M48T18/T08Y
Unit
Min Max
I
I
LO
I
CC
I
CC1
I
CC2
V
V
V
V
OH
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. Outputs deselected.
3. Measured with control bits set as follows: R = '1'; W, ST, FT = '0.'
4. The INT pin is open drain.
Input leakage current 0V ≤ VIN ≤ V
LI
(2)
Output leakage current 0V ≤ V
OUT
≤ V
CC
CC
Supply current Outputs open 80 mA
(3)
Supply current (standby) TTL E1 = V
(3)
Supply current (standby) CMOS
Input low voltage –0.3 0.8 V
IL
Input high voltage 2.2 VCC + 0.3 V
IH
E1 = VCC – 0.2V,
E2 = V
IH,
SS
E2 = V
+ 0.2V
IL
Output low voltage IOL = 2.1 mA 0.4 V
OL
Output low voltage (INT)
(4)
IOL = 0.5 mA 0.4 V
Output high voltage IOH = –1 mA 2.4 V
±1 µA
±1 µA
3mA
3mA
Figure 12. Power down/up mode AC waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
VSO
tDR
DON'T CARE
HIGH-Z
tR
tPFH
NOTE
(PER CONTROL INPUT)
trec
RECOGNIZEDRECOGNIZED
AI00566
INT
INPUTS
OUTPUTS
tF
tPD tRB
VAL ID VAL ID
(PER CONTROL INPUT)
tFB
tPFX
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1
or E2 low as V
cycles after V
rises past V
CC
rises above V
CC
(min). Some systems may perform inadvertent WRITE
PFD
(min) but before normal system operations begin. Even
PFD
though a power on reset is being applied to the processor, a reset condition may not occur
until after the system clock is running.
Doc ID 2411 Rev 11 21/31
high
Page 22
DC and AC parameters M48T08, M48T08Y, M48T18
Table 10. Power down/up AC characteristics
Symbol Parameter
t
PD
(2)
t
F
t
FB
t
R
t
RB
t
rec
t
PFX
t
PFH
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
2. V
PFD
until 200 µs after V
3. V
PFD
E1 or W at VIH or E2 at VIL before power-down 0 µs
V
(3)
(max) to V
PFD
V
(min) to VSS VCC fall time 10 µs
PFD
V
(min) to V
PFD
VSS to V
(min) VCC rise time 1 µs
PFD
(min) VCC fall time 300 µs
PFD
(max) VCC rise time 0 µs
PFD
E1 or W at VIH or E2 at V
INT low to auto deselect 10 40 µs
V
(max) to INT high 120 µs
PFD
(max) to V
(min) to VSS fall time of less than tFB may cause corruption of RAM data.
(min) fall time of less than tF may result in deselection/write protection not occurring
PFD
passes V
CC
PFD
(min).
(1)
before power-up 1 ms
IL
Min Max Unit
Table 11. Power down/up trip points DC characteristics
Symbol Parameter
(1)(2)
Min Typ Max Unit
V
PFD
V
t
DR
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: T
noted).
3. At 55 °C, VCC = 0 V; tDR = 8.5 years (typ) at 70 °C. Requires use of M4T32-BR12SH SNAPHAT® top when
using the SOH28 package.
Power-fail deselect voltage
Battery backup switchover voltage 3.0 V
SO
Expected data retention time 10
M48T08 4.5 4.6 4.75 V
M48T18/T08Y 4.2 4.3 4.5 V
(3)
= 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
A
Ye a r s
22/31 Doc ID 2411 Rev 11
Page 23
M48T08, M48T08Y, M48T18 Package mechanical data
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Figure 13. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline
Note: Drawing is not to scale.
Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data
Symb
Typ Min Max Typ Min Max
B1 B
e3
D
N
1
mm inches
A2
A1AL
e1
E
C
eA
PCDIP
A 8.89 9.65 0.350 0.380
A1 0.38 0.76 0.015 0.030
A2 8.38 8.89 0.330 0.350
B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.31 0.008 0.012
D 39.37 39.88 1.550 1.570
E 17.83 18.34 0.702 0.722
e1 2.29 2.79 0.090 0.110
e3 33.02 1.3
eA 15.24 16.00 0.600 0.630
L 3.05 3.81 0.120 0.150
N28 28
Doc ID 2411 Rev 11 23/31
Page 24
Package mechanical data M48T08, M48T08Y, M48T18
Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT®, package
outline
Be
N
1
Note: Drawing is not to scale.
Table 13. SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT
data
Symb
Typ Min Max Typ Min Max
A3.050.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e1.27– –0.050– –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N28 28
CP 0.10 0.004
A2
CP
D
E
H
A
eB
C
LA1 α
®
, package mech.
SOH-A
mm inches
24/31 Doc ID 2411 Rev 11
Page 25
M48T08, M48T08Y, M48T18 Package mechanical data
Figure 15. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package
outline
Note: Drawing is not to scale.
Table 14. SH – 4-pin SNAPHAT
data
Symb
Typ Min Max Typ Min Max
A9.780.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
A1
A
eA
D
E
®
housing for 48 mAh battery & crystal, package mech.
B
eB
A3
A2
L
mm inches
SHTK-A
Doc ID 2411 Rev 11 25/31
Page 26
Package mechanical data M48T08, M48T08Y, M48T18
Figure 16. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package
outline
Note: Drawing is not to scale.
Table 15. SH – 4-pin SNAPHAT
mech. data
Symb
Typ Min Max Typ Min Max
A 10.54 0.415
A1 8.00 8.51 0.315 .0335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 .0710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
A1
A
eA
D
E
®
housing for 120 mAh battery & crystal, package
B
eB
A3
mm inches
A2
L
SHTK-A
26/31 Doc ID 2411 Rev 11
Page 27
M48T08, M48T08Y, M48T18 Part numbering
7 Part numbering
Table 16. Ordering information scheme
Example: M48T 18 –100 PC 1 E
Device type
M48T
Supply voltage and write protect voltage
(1)
08
= VCC = 4.75 to 5.5 V; V
18/08Y = VCC = 4.5 to 5.5 V; V
Speed
–100 = 100 ns
–150 = 150 ns
–10 = 100 ns (M48T08Y)
= 4.5 to 4.75 V
PFD
= 4.2 to 4.5 V
PFD
Package
(1)
PC
= PCDIP28
(2)
= SOH28
MH
Temperature range
1 = 0 to 70 °C
Shipping method
For SOH28:
blank = Tubes (not for new design - use E)
®
E = ECOPACK
F = ECOPACK
package, tubes
®
package, tape & reel
TR = Tape & reel (not for new design - use F)
For PCDIP28:
®
blank = ECOPACK
1. The M48T08/18 part is offered with the PCDIP28 (e.g., CAPHAT™) package only.
2. The SOIC package (SOH28) requires the SNAPHAT® battery/crystal package which is ordered separately
under the part number “M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in tape & reel form (see
Table 17). The M48T08Y part is offered in the SOH28 (SNAPHAT) package only.
package, tubes
Caution: Do not place the SNAPHAT
will drain the lithium button-cell battery.
®
battery package “M4TXX-BR12SH” in conductive foam as it
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 2411 Rev 11 27/31
Page 28
Part numbering M48T08, M48T08Y, M48T18
Table 17. SNAPHAT® battery table
Part number Description Package
M4T28-BR12SH Lithium battery (48 mAh) SNAPHAT
M4T32-BR12SH Lithium battery (120 mAh) SNAPHAT
®
®
SH
SH
28/31 Doc ID 2411 Rev 11
Page 29
M48T08, M48T08Y, M48T18 Environmental information
8 Environmental information
Figure 17. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
Doc ID 2411 Rev 11 29/31
Page 30
Revision history M48T08, M48T08Y, M48T18
9 Revision history
Table 18. Document revision history
Date Revision Changes
Dec-1999 1 First Issue
07-Feb-2000 2
11-Jul-2000 2.1 t
16-Jul-2001 3
01-Aug-2001 3.1 Reference to App. Note corrected in “Calibrating the Clock” section
21-Dec-2001 3.2 Changes to text in document to reflect addition of M48T08Y option
06-Mar-2002 3.3 Fix Ordering Information table and add to footnote (Ta bl e 1 6)
20-May-2002 3.4 Modify reflow time and temperature footnotes (Ta bl e 6 )
29-Aug-2002 3.5 tDR specification temperature updated (Ta b le 1 1 )
28-Mar-2003 4 v2.2 template applied; updated test conditions (Ta bl e 1 0 )
10-Dec-2003 5 Reformatted
30-Mar-2004 6
13-Dec-2005 7 Updated template, Lead-free information, removed footnote (Tab le 9 , 16)
04-Jul-2007 8
10-Feb-2009 9
21-Jun-2010 10 Updated Section 4, Ta b le 1 2 ; reformatted document.
07-Jun-2011 11
From Preliminary Data to Datasheet; Battery Low Flag paragraph
changed; 100ns speed class identifier changed (Ta b le 3 , 4)
changed (Ta bl e 1 0); Watchdog Timer paragraph changed
FB
Reformatted; SNAPHAT battery table added (Ta bl e 1 7 ); added
temp./voltage info. to tables (Ta bl e 8 , 9, 3, 4, 10, 11).
Reformatted; Lead-free (Pb-free) information package update (Ta bl e 6 ,
16)
Reformatted; added lead-free second level interconnect information to
cover page and Section 6: Package mechanical data.
Updated Ta b le 6 , text in Section 6: Package mechanical data; added
Section 8: Environmental information; minor formatting changes.
Updated footnote 1 of Table 6: Absolute maximum ratings; updated
Section 8: Environmental information.
30/31 Doc ID 2411 Rev 11
Page 31
M48T08, M48T08Y, M48T18
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Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
Doc ID 2411 Rev 11 31/31
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