The LZ93B53 is a CMOS synchronous signal
generator LSI which provides B/W TV synchro-
nous pulses and video signal processing pulses,
in combination with the timing signal generator
LSI (LZ93N61, LZ95F50, or LZ93F33).
FEATURES
.
Switchable
and 320000 pixels B/W CCD
.
Switchable between EIA and CCIR systems
● Single + 5 V power supply
. External synchronization is possible
. Package :
BLOCK DIAGRAM
between 270000 pixels B/W
f
8-pin MFP(MFPOI 8-P)
Vcc
VDI
VD2HDI
CCD
Synchronous Signal Generator for CCD
PIN CONNECTIONS
17
VDI
16 VD2
15
HDI
14 HD2
13 CBLK
12 HBLK
11 CSYN
[
10
BCPI
TOP VIEW
HD2
18-PIN MFP
NMD
CPMD 4
CKMD 5
CBLK
HBLKCSYN
CLKI 1
CLKO 2
3
VRI 6
TSTI 7
TST2 8
0
[
8
}
BCP
I
CLKI
I
I
)
~ ~
CLKOTVMDCPMDCKMD
&
1
~
7-BIT
COUNTER
I
&
VRITST
&
I
GATE
CONTROL
t
TST2
I
t
~ ~
GND
ABSOLUTE MAXIMUM RATINGS
PARAM~ER
voltaae
Power
Input
voltage
Output voltage
Ooeratina
temperature
Storage temperature
I
SYMBOL
Vcc
I
VI I -0.3 to
Vo
Tovr
]
Tstg
RATING
– 0.3 to 7.0
vm+o.3 /
–
0.3
to
Vcc
+ 0.3
–20 to +70‘c
\
–55 to +150
I“cl
UN~
v
v
v
LZ93B53
I
DC CHARACTERISTICS
PARAM=ER
Low level input voltage
High level input voltage
rtii~h
level threshold voltage
Low level threshold voltage
Hysteresis
Low level output voltage
High level output voltage
Low level
I
LOW level
High level input current
High level input current
NOTES :
1.
2. Applied to input
3.
Applied to all outputs (0).
4. Applied to inputs
5.
Applied to input (lCD).
6. Applied to inputs
7. Applied to inputs
voltaae
in~ut
current
input
current
Applied to inputs (IC, ICU,
(ICSU).
(IC, ICU,
(IC, ICD).
(ICU, ICSU).
ICD).
Icsu
I
SYMBOL
I
I
VT+
] IIIL21 I
).
VIL
VIH
VT+ I
VT -
–VT-
VOL
VOH
I
IIL1 I
I
IIH1 I
I
11H2 I
\
I
CONDITIONS
Schmitt buffer
Schmitt buffer
Schmitt buffer
IOL
=4
mA
IoH=–2
mA
Vl=o
v
Vl=o
v
VI= Vcc
VI= Vm
(VCC=+5 Vtl O%,
MIN. ] TYP. I MAX.
3.5
II
13.71VI
1,0
0,4
4.0
8.060
Ta=–20 to
UNIT
1,5
v
v
v
v
0.4
v
v
1.0
1.0
,uA
PA
PA
+7VC)
I
NOTE
1
2
3
4
6
7
251
PIN FUNCTION
~
r
‘DWL
10.
1
CLKI
CLKO
2
lVMD
3
CPMD
4
‘f ~
Ic
o
ICD
Icu
‘uwn’ ‘ ‘
m
lrf
—
—
r,,. ,.m,v,
L
Main clock
Clock out
TV mode select
Clamp pulse mode
select
LZ93B53
,
“,.”, ,”,.
This is a pin to input the clock which is used as
the reference of the horizontal and vertical pulses.
This pin should be connected to DO on the timing
This is a pin to control stop and continuance of
BCPI (pin 10) within the vertical blanking period.
● High level : BCPI outputs continuous pulses.
● Low level : BCP I stops outputting composite
This is an input pin to switch the frequency devision
in accordance with the area sensor as follows.
: EIA
system
CCIR
system
pulses while there is no effective
pixel within the V blanking period.
MHz(808 fH)
5
6
7
252
CKMD
VRI
TSTI
Icu
Icsu
ICD
–
Clock mode select
u
–
Vertical reset
Test
tarminal
1
Frequency division
output
CKMD
Number of pixels
This is an input pin for the external V reset pulse
which is used to apply vertical synchronization to
the counter (2 fck counter) on the synchronization.
This resetting takes priority over the internal resetting. Since the rise of input at
horizontal synchronous frequency (2 fH) which is two
times as high as the internal frequency, when the
vertical pulses which were separated in terms of
frequency from the composite synchronous signal
from other equipment are used, the fall must have
a phase difference of less than 1/2
with the start timing of the vertical synchronous
signal. When the
the High level should be selected. The input is de-
signed as a
This is an input pin for tests, Typically, this pin
should be open or at the Low level.
interal
schmitt
trigger buffer.
1/3
High
270000
VRI
synchronization is obtained,
1/4
Low
360000
is taken at the
fH
compared
LZ93B53
9
10
11
12
13
14
15
16
17
SYMBOL
TST2
GND
BCP
CSYN
HBLK
CBLK
HD2
HDI
VD2
VDI
Vcc
I
1/0
WLARITY
ICD
—
o
o
o
o
o
o
o
0
——
n
L
n
n
PIN NAME
Test
tarminal
2
Ground
Optical block clamp
pulse
Composite synchronous
signal
Horizontal blanking
pulse
Composite blanking
pulse
Horizontal drive pulse 2
Horizontal drive pulse
Vertical drive pulse 2
Vertical drive pulse
Power supply
1
1
FUNCTION
This is an input pin for tests. Typically, this pin
should be open or at the Low level.
This is a grounding pin.
This pin output pulse which is used to clamp opti-
cal black on each line of the sensor output, Typically, these are horizontal synchronization continuous
setilng
pulses. However,
level allows the composite output which becomes
the Low level while there is no effective pixel within
the vertical blanking period.
This pin outputs
synchronous signals.
●
EIA
system
CCIR system : Compatible with
.
This pin outputs a pulse to stop
fer pulses which drive the horizontal register in the
area sensor.
This pin outputs pulses which are used for video
blanking in the encoder.
EIA
system: 11.01 ps, V20 H is cleared.
.
. CCIR system :
This pin outputs pulses which are synchronous with
the start of each line and used as the H reference
of the timing
This pin outputs pulses which are synchronous with
the start of each line and used as the H reference
of external equipment.
This pin outputs pulses which are obtained at the
start of each field and used as the V reference of
the timing
This pin outputs pulses which are obtained at the
start of each field and used as the V reference of
external equipment.
supply +5 V power
LSI.
LSI.
CPMD (pin 4) to the Low
EIA
and CCIR standard composite
: Compatible with RS-170
CCIR
tie
horizontal trans-
12.12/s,
V25 H is cleared.
: lnDut Din (CMOS level).
Ic
ICU : Input pin (CMOS level with pull-up resistor).