❑ Processed with HVCMOS Technology
❑ Output voltages to -300V
❑ Source current minimum 60 mA
❑ Shift register speed 8 MHz
❑ Polarity and blanking inputs
❑ CMOS compatible inputs
❑ Forward and reverse shifting options
❑ 44-lead plastic and ceramic surface mount packages
❑ Hi-Rel processing available
❑ Can be used with the HV55 and HV56 to provide 300V
push pull operation
Absolute Maximum Ratings
Supply voltage, V
Off state output voltageHV4630+0.5V to -315V
Logic input levels+0.5V to V
Ground current
Continuous total power dissipation
Operating temperature range-40°C to +85°C
Storage temperature range-65°C to +150°C
Lead temperature 1.6mm (1/16 inch)260°C
from case for 10 seconds
Notes:
1. All voltages are referenced to V
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20mW/°C for plastic and at 15mW/°C for ceramic.
DD
HV4622+0.5V to -240V
2
3
.
SS
1
+0.5V to -16V
- 0.3V
DD
1.5A
1200mW
General Description
The HV45 and HV46 are low-voltage serial to high-voltage
parallel converters with P-Channel open drain outputs. These
devices have been designed for use as drivers for AC-electroluminescent displays. They can also be used in any application
requiring multiple output high-voltage current source capabilities
such as driving inkjet and electrostatic print heads, plasma
panels, or vacuum fluorescent displays.
These devices consist of a 32-bit shift register, 32 data latches,
and control logic to perform polarity and blanking functions. Data
is shifted through the shift register on the logic high-to-low
transition of the clock. The HV45 shifts in the counterclockwise
direction when viewed from the top of the package and the HV46
shifts in the clockwise direction. A data output buffer is provided
for cascading devices. This output reflects the current status of
the last bit of the shift register. The data in the shift register is
latched when the latch enable pin is brought to logic high and then
returned to ground. If the latch enable pin is held high, the latch
becomes transparent and the shift register data is directly reflected in the outputs.
For applications requiring active pull down as well as pull up, the
HV45 and HV46 can be paired with the HV55 and HV56 devices,
respectively.
03/13/02
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
Quiescent VDD supply current-100µAVIN = VSS or V
Off state output current-100µAAll SWS parallel
High-level logic input current-1µAVIH = V
Low-level logic input current+1µAVIL = V
High-level output data outVDD + 1.0VVI
Low-level output voltageHV
OUT
-30.0VI
Data out-1.0VI
HV
clamp voltage+1.5VIOL = +60mA
OUT
HV4530//HV4630
= 8 MHz
CLK
F
= 4 MHz
DATA
DD
SS
= -100µA
Dout
= -60mA
HVout
= -100µA
Dout
DD
AC Characteristics(V
= -12V, TC = 25°C)
DD
SymbolParameterMinMaxUnitsConditions
f
CLK
t
WH/tWL
t
SU
t
H
t
ON
t
DHL
t
DLH
t
DLE
t
WLE
t
SLE
Clock frequency8MHz
Clock width high or low62ns
Data set-up time before clock rises50ns
Data hold time after clock rises20ns
Turn ON time, HV
from enable400nsRL = 10K to VOO MAX
OUT
Delay time clock to data high to low100nsCL = 15pF
Delay time clock to data low to high100nsCL = 15pF
Delay time clock to LE low to high50ns
Width of LE pulse50ns
LE set-up time before clock falls50ns
Recommended Operating Conditions
SymbolParameterMinMaxUnits
V
DD
HV
OUT
V
IH
V
IL
f
CLK
T
A
Note: All voltages are referenced to VSS.
Logic supply voltage-10.8-13.2V
Output off voltage+0.3-300V
High-level input voltage (LOGIC “1”)VDD + 2VV
DD
Low-level input voltage (LOGIC “0”)0-2.0V
Clock frequency8MHz
Operating free-air temperature-40+85°C
V
2
Page 3
Input and Output Equivalent Circuits
HV4530//HV4630
V
SS
Input
V
DD
Logic Inputs
Switching Waveforms
Clock
50%50%50%
t
WH
V
SS
V
SS
Data Out
HV
OUT
V
DD
Logic Data Output
High Voltage Output
V
SS
Data Valid50%50%Data Input
VSS-12
t
SU
t
H
V
SS
50%
VSS-12
t
WL
Data Out
Latch Enable
HV
OUT
w/ S/R HIGH
t
DLE
t
DHL
t
DLH
50%
V
SS
50%
VSS-12
V
50%
SS
VSS-12
V
50%
SS
VSS-12
t
WLE
10%
t
ON
t
SLE
V
SS
V
OO
3
Page 4
Functional Block Diagram
V
SS
Polarity
Blanking
Latch Enable
HV4530//HV4630
Data Input
Latch
HV
OUT
1
Clock
Data Out
32-Bit
Shift
Register
Latch
(Outputs 3 to 30
Latch
Latch
HV
OUT
not shown)
HV
OUT
HV
OUT
2
31
32
Function Table
InputsOutputs
FunctionShift RegHV OutputsData Out
All onXXXLL**…*ONON…ON*
All offXXXLH**…*OFF OFF…OFF*
Invert modeXXLHL**…***…**
Load S/RH or L
Load
latches
Transparent
latch mode
Notes:
H = high level = -12V, L = low level = 0V, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transition.
* = dependent on previous stage’s state before the last CLK high-to-low transition or last LE high.