Datasheet HV300DB1 Datasheet (Supertex)

Page 1
HV300DB1
HV300DB1
Introduction
The HV300DB1 demonstration board contains all of the circuitry necessary to safely hot-plug a -48V peripheral into a live backplane. The electrolytic capacitor, Cload simulates the input filter capacitor of a DC-to-DC converter. Cload should be removed if an actual DC-to-DC converter is being used as the load.
Board Layout and Connections
V
DD
68kΩ
48V
PG
V
EE
Specifications
Input voltage range 35V to 65V
Undervoltage lockout 35V
Overvoltage lockout 65V
Maximum continuous load current 1.7A
Switch resistance 0.21Ω
Current sense resistance 0.05Ω
V
DD
Load Optional
Drain
VDD Input and Output
VDD is the positive power supply terminal. It is also connected to the output load. Resistors, R1, R2, and R3 are chosen to allow for an operating input range of 35V to 65V. The HV300LG is capable of operating up to 90V.
VEE Input
Vee is the negative power supply terminal. MOSFET, M1 is used to connect and disconnect VEE to the drain output.
Drain Output
This is the negative side for the output load. VEE is connected to this pin via MOSFET M1 controlled by the HV300LG.
PG Test Point
PG is the Power Good (PWRGD) test point, which is an open drain N-channel MOSFET with “ok” high logic. An external pull up resistor should be connected to this point. PG can withstand pull up voltages of up to 90V. To examine PG operation, a
05/16/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
resistor connected from V would be connected to an enable input on a DC-to-DC converter power supply.
UV and OV Test Point
Voltages on these test points sets the under voltage and over voltage values. These test points can be probed to examine the divided down values set by R1, R2 and R3. The window comparator works around 1.21V nominally with 100mV of hysteresis.
Ramp Test Point
This test point provides access to the ramp capacitor’s positive terminal, which is used to program the hot swap timing profile.
Gate Test Point
This is the gate voltage on MOSFET M1. The HV300LG modulates the resistance M1 by controlling its gate profile. This test point allows examination of the gate voltage.
1
to PG is acceptable. Normally PG
DD
Page 2
HV300DB1 Schematic
HV300DB1
V
EE
+
48V
Input
-
V
EE
R1
487KΩ
R2
9.09KΩ
R3
9.09KΩ
UV
HV300LG
OV
EE
Cramp
10nF
Rsense
0.05Ω
Bill of Materials for HV300DB1 Demo Board
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2RrotsiserpihcmlifkcihT%1±K90.95080K90.9FNE6JREcinosanaP
V
DD
PWRGD
GateSenseRampV
M1
IRFR120N
PG
J1
V
C
load
100µF
Drai
DD
n
+
48V
Output
-
3RrotsiserpihcmlifkcihT%1±K90.95080K90.9FNE6JREcinosanaP
R
ESNES
C
PMAR
C
DAOL
rotsiserpihcmlifkcihT%1±50.0602150.-6021LSWelaD
roticapaccitylortcelEV061,Fµ001--101GHC2-ACEcinosanaP
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003VHCIpawStoHV098-OSGL003VH.cnIxetrepuS
HV300 Typical Waveforms
Drain
50V/div
V
IN
50V/div
Gate
5.00V/div
I
inrush
500mA/div
5.00ms/div
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Notes:
1) Some versions of the HV300DB1 may include a 10nF capacitor from IC pins 5 to 6 (the MOSFET gate to source). This capacitor is used to eliminate ringing at the end of the inrush period.
2) Current can be measured with a current probe on the Vdd line. The current drawn by the load can be measured by replacing J1 with a small resistor and measuring the voltage drop. Alternatively, a current probe can be used by replacing J1 with a wire loop.
3) PG is an open drain output and will have no effect if probed without a pullup.
4. The dual plateau characteristic of the gate response is an intended result of Supertex’s closed loop hot swap solution. The steep voltage jump of the gate occurs after the MOSFET is fully on and indicates the point at which the IC goes into sleep mode (PG high).
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
PB
05/16/01
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
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