Datasheet HV430WG Datasheet (Supertex)

High Voltage Ring Generator

Ordering Information

Operating Voltage Package Options

V

PP1-VNN1

325V HV430WG

SOW-20

HV430

Features

❏ 105Vrms ring signal

❏ Output over current protection

❏ 5.0V CMOS logic control

❏ Logic enable/disable to save power

❏ Adjustable deadband in single-control mode

❏ Power-on reset

❏ Fault output for problem detection

Applications

❏ Line access cards

❏ Set-top/Street box

Absolute Maximum Ratings

V

– V

PP1

V

PP1

V

PP2

V

NN1

V

NN2

VDD, logic supply +7.5V

Storage temperature -65°C to +150°C

Power dissipation 600mW

, power supply voltage +340V

NN1

, positive high voltage supply +220V

, positive gate voltage supply +220V

, negative high voltage supply -220V

, negative gate voltage supply -220V

General Description

The Supertex HV430 is a high voltage PWM ring generator integrated circuit. The high voltage outputs, V are used to drive the gates of external high voltage P-channel and N-channel MOSFETs in a push-pull configuration. Over current protection is implemented for both the P-channel and Nchannel MOSFETs. External sense resistors set the over-current trip point.

The RESET input functions as a power-on reset when connected to an external capacitor.

The FAULT output indicates an over-current condition and is cleared after 4 consecutive cycles with no overcurrent condition. A logic low on RESET or ENABLE clears the FAULT output. It is active-low and open-drain to allow wire OR’ing of multiple drivers.

P

gate

and N

are controlled independently by logic inputs PIN and

gate

NIN when the MODE pin is at logic high. A logic high on PIN will turn on the external P-channel MOSFET. Similarly, a logic high on N will turn on the external N-channel MOSFET. Lockout circuitry prevents the N and P switches from turning on simultaneously. A pulse width limiter restricts pulse widths to no less than 100200ns.

For applications where a single control input is desired, the MODE pin should be connected to SGND. The PWM control signal is then input to the N

pin. A user-adjustable deadband in

IN

the control logic ensures break-before-make on the outputs, thus avoiding cross conduction on the high voltage output during switching. A logic high on N

will turn the external P-Channel

IN

MOSFET on and the N-Channel off, and vice versa. The IC can be powered down by applying a logic low on the ENABLE pin, placing both external MOSFETs in the off state.

PGATE

and V

NGATE

,

IN

12/13/01

Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.

1

Electrical Characteristics

(Over operating supply voltage unless otherwise specified, TA = -40°C to +85°C.)

External Supplies

Symbol Parameter Min Typ Max Unit Conditions

V

I

PP1Q

I

PP1

V

I

NN1Q

I

NN1

V

I

DDQ

I

DD

PP1

NN1

DD

High voltage positive supply 50 200 V

VPP quiescent current 250 500 µAPIN=NIN=0V

VPP operating current 2.0 mA No load

V

OUTP

High voltage negative supply V

V

quiescent current 250 500 µAPIN=NIN=0V, R

NN1

V

operating current 1.0 mA No load

NN1

-325 -50 V

PP1

V

OUTP

and V

switching at 100kHz

OUTN

=18kΩ

DB

switching at 100kHz

OUTN

Logic supply voltage 4.50 5.50 V

VDD quiescent current 300 400 µAPIN=NIN=0V, R

=18kΩ

DB

VDD operating current 1.0 mA PIN=NIN=100kHz, R

=18kΩ

DB

HV430

Internal Supplies

Symbol Parameter Min Typ Max Unit Conditions

V

PP2

V

NN2

Positive linear regulator output voltage V

Negative linear regulator output voltage V

-16 V

PP1

+10 V

NN1

-10 V

PP1

+14 V

NN1

Positive High Voltage Output

Symbol Parameter Min Typ Max Unit Conditions

V

Pgate

R

sourceP

R

sinkP

t

riseP

t

fallP

t

pwp(min)

t

delayP

V

Psen

t

shortP

Output voltage swing V

V

source resistance 12.5 Ω I

Pgate

V

sink resistance 12.5 Ω I

Pgate

V

rise time 50 ns C

Pgate

V

fall time 50 ns C

Pgate

V

minimum pulse width

Pgate

PP2

V

PP1

V No load on V

=80mA

OUT

=-80mA

OUT

=1.4nF

load

=1.4nF

load

(internally limited) 100 150 200 ns

PIN to Pgate delay time 300 ns mode=1

V

current sense voltage V

Pgate

V

current sense off time 150 ns

Pgate

-0.85 V

PP1

-1.0 V

PP1

-1.15 V

PP1

Pgate

2

Negative High Voltage Output

Symbol Parameter Min Typ Max Unit Conditions

V

Ngate

R

sourceN

R

sinkN

t

riseN

t

fallN

t

pwn(min)

Output voltage swing V

V

source resistance 15.0 Ω I

Ngate

V

sink resistance 15.0 Ω I

Ngate

V

rise time 50 ns C

Ngate

V

fall time 50 ns C

Ngate

V

minimum pulse width

Ngate

NN2

V

NN1

V No load on V

=80mA

OUT

=-80mA

OUT

=1.0nF

load

=1.0nF

load

(internally limited) 100 150 200 ns

t

delayN

V

t

shortN

Nsen

NIN to V

V

Ngate

V

Ngate

delay time 300 ns mode=1

Ngate

current sense voltage V

+0.85 V

NN1

+1.0 V

NN1

+1.15 V

NN1

current sense OFF time 150 ns

Control Circuitry

Symbol Parameter Min Typ Max Unit Conditions

HV430

Ngate

V

IL

V

IH

I

INdn

R

up

V

OL

V

OH

V

RST(OFF)

V

RST(ON)

V

RST(HYS)

I

reset

t

RST(ON)

t

RST(OFF)

t

EN(ON)

t

EN(OFF)

t

FLT(HOLD)

t

DB

t

delay(N-P)

t

delay(P-N)

∆t

delay(N-P)

∆t

delay(P-N)

Logic input low voltage 0 0.60 V VDD=5.0V

Logic input high voltage 2.7 5.0 V VDD=5.0V

Input pull-down current 0.5 1 5 µAPIN, NIN, ENABLE

Input pull-up resistance 100 200 300 kΩ MODE

Logic output low voltage 0.50 V VDD=5.0V, I

Logic output high voltage 4.50 V VDD=5.0V, I

=-0.5mA

OUT

=0.5mA

OUT

Reset voltage, device off 3.2 3.5 V VDD=5.0V

Reset voltage, device on 3.7 4.0 V VDD=5.0V

Reset hysteresis voltage 0.3 V VDD=5.0V

Reset pull-up current 7 10 13 µAV

RESET

=0-4.5V

RESET on delay 1.0 µs

RESET off delay 1.0 µs

ENABLE on delay 50 100 150 µs

ENABLE off delay 1.0 µs

N

FAULT hold time 4

Deadband time

35 50 70 ns Mode=0, Rdb=5.6kΩ

IN/PIN

cycles

ENABLE=1

105 140 175 ns Mode=0, Rdb=18kΩ

N-off to P-on transistion delay 300 ns Mode=0, Rdb<27kΩ

P-off to N-on transistion delay 300 ns Mode=0, Rdb<27kΩ

Delay difference t

- t

delayN(off)

delayP(on)

Delay difference

- t

t

delayP(off)

delayN(on)

-80 0 80 ns Mode=1

3

Truth Table

Logic Inputs* Output

N

IN

P

LLHH > V

LHH H > V

HLH H > V

HHH H > V

HXL H > V

LXL H > V

XXX L X OFF OFF

XXX X < V

* Unused logic inputs should be connected to VDD or GND.

mode EN RESET External N-Channel External P-Channel

IN

MOSFET MOSFET

reset(on)

reset(off)

OFF OFF

OFF ON

ON OFF

OFF OFF

OFF ON

ON OFF

OFF OFF

HV430

Block Diagram and Application Circuit

V

DD

FAULT

MODE

DEADBAND

N

ENABLE

RESET

De-glitcher

reset

clk

P

IN

Control

Logic

IN

V

DD

10µA

+5V

V

SIG

GND

V

Down

Translator

Up

Translator

Up

Translator

Down

Translator

PP2

Regulator

V

NN2

Regulator

DD

PWR GND

PP2

Current

Tr ip

P

Driver

N

Driver

Current

Tr ip

V

PP1

V

PSEN

V

PGATE

NC

V

NGATE

V

NSEN

V

NN1

V

PP1

R

sense

Ringer Output

R

sense

V

NN2

V

NN1

Note: PIN, NIN, and ENABLE are internally pulled low. MODE is internally pulled high. A Reset capacitor in the range of 1-10µF will yield a couple-second turn-on delay. Tantalum is recommended.

4

Single-Control Mode Timing

1

N

IN

0

t

N-Pdelay

t

P-Ndelay

V

DD

GND

HV430

ON

P

OUT

OFF

t

ON

N

OUT

OFF

t

Nfall

Dual-Control Mode Timing

1

P

IN

0

t

Pdelay(on)

ON

t

Prise

N-Pdeadband

t

Ppulse(min)

t

Pdelay(off)

t

Pfall

t

P-Ndeadband

t

Nrise

V

DD

GND

V

PP2

V

PP2

V

PP1

V

NN2

V

NN1

P

N

OUT

N

IN

OUT

OFF

ON

OFF

V

t

Prise

t

Pfall

1

0

t

Ndelay(on)

t

Nrise

t

Npulse(min)

t

Ndelay(off)

t

Nfall

PP1

V

DD

GND

V

NN2

V

NN1

5

ENABLE Timing

HV430

ENABLE

NIN/P

P

OUT

N

OUT

IN

ON

OFF

ON

OFF

1

0

1

Switching

0

t

Off

EN(ON)

Switching

t

EN(OFF)

Off

V

DD

GND

V

DD

GND

V

PP2

V

PP1

V

NN2

V

NN1

RESET Timing

RESET

1

NIN/P

P

N

IN

0

ON

OUT

OFF

ON

OUT

OFF

t

RST(ON)

Off

Switching

t

RST(OFF)

Off

V

RESET(ON)

V

RESET(OFF)

GND

V

DD

GND

V

PP2

V

PP1

V

NN2

V

NN1

6

FAULT Timing

y

HV430

ENABLE

or

RESET

N

IN

P

OUT

N

OUT

ON

OFF

ON

OFF

1

0

1

0

V

DD

GND

V

DD

GND

V

PP2

V

PP1

V

NN2

V

NN1

N

SENSE

FAU LT

w/ext pull-up

Over

OK

V

GND

DD

t

FAULT(HOLD)

Note: N

overcurrent shown. P

sense

ENABLE or RESET

clears FAULT immediatel

operates identically.

sense

7

Pin Description

HV430

V

PP1

V

PP2

V

NN1

V

NN2

V

DD

Positive high voltage supply.

Positive gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be connected between V

PP2

and V

PP1

.

Negative high voltage supply.

Negative gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be connected between V

NN2

and V

NN1

.

Logic supply voltage.

SGnd Low voltage logic ground.

PGnd High voltage power ground.

P

IN

Logic control input. When mode is high, logic input high turns ON the external high voltage P-channel MOSFET. Internally pulled low.

N

IN

Logic control input. When mode is high, logic input high turns ON the external high voltage N-channel MOSFET. Internally pulled low.

ENABLE Logic enable input. Logic high enables IC. Internally pulled low.

MODE Logic mode input.

and P

, respectively. When MODE is low, NIN controls both outputs in a complementary manner.

OUT

0=single-control; 1=dual-control. When MODE is high, NIN and PIN independently control N

OUT

(See Truth Table)

FAULT Logic output.

Fault is at logic low when either current limit sense pin, V

Psen

or V

, is activated. Remains

Nsen

active until overcurrent condition clears or ENABLE=0 or RESET=0.

RESET Power-on reset. A capacitor connected between this pin and ground determines the delay time between application

of VDD and when the device outputs are enabled. Low leakage tantalum recommended.

DEADBAND A resistor between this pin and ground sets the ‘break-before-make’ time between output transitions.

only in single-control mode. For minimum deadtime, a 5.6kΩ resistor to ground should be used. For dual-input mode, tie to Vdd.

V

Pgate

V

Ngate

V

Psen

V

Nsen

Gate drive for external P-channel MOSFET.

Gate drive for external N-channel MOSFET.

Pulse by pulse over current sensing for P-Channel MOSFET.

Pulse by pulse over current sensing for N-Channel MOSFET.

Pin Configuration

1

V

Fault

Mode

P

N

Enable

Reset

Deadband

SGND

PGND

DD

2

3

4

IN

5

IN

6

7

8

9

10

20

V

PP2

19

V

PP1

18

V

PSEN

17

V

PGATE

16

N/C

15

N/C

14

V

NGATE

13

V

NSEN

12

V

NN1

11

V

NN2

Applicable

top view

SOW 20

12/13/010

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 744-0100 • FAX: (408) 222-4895

8

www.supertex.com