The Supertex HV430 is a high voltage PWM ring generator
integrated circuit. The high voltage outputs, V
are used to drive the gates of external high voltage P-channel
and N-channel MOSFETs in a push-pull configuration. Over
current protection is implemented for both the P-channel and Nchannel MOSFETs. External sense resistors set the over-current trip point.
The RESET input functions as a power-on reset when connected
to an external capacitor.
The FAULT output indicates an over-current condition and is
cleared after 4 consecutive cycles with no overcurrent condition.
A logic low on RESET or ENABLE clears the FAULT output. It is
active-low and open-drain to allow wire OR’ing of multiple
drivers.
P
gate
and N
are controlled independently by logic inputs PIN and
gate
NIN when the MODE pin is at logic high. A logic high on PIN will turn
on the external P-channel MOSFET. Similarly, a logic high on N
will turn on the external N-channel MOSFET. Lockout circuitry
prevents the N and P switches from turning on simultaneously.
A pulse width limiter restricts pulse widths to no less than 100200ns.
For applications where a single control input is desired, the
MODE pin should be connected to SGND. The PWM control
signal is then input to the N
pin. A user-adjustable deadband in
IN
the control logic ensures break-before-make on the outputs,
thus avoiding cross conduction on the high voltage output during
switching. A logic high on N
will turn the external P-Channel
IN
MOSFET on and the N-Channel off, and vice versa. The IC can
be powered down by applying a logic low on the ENABLE pin,
placing both external MOSFETs in the off state.
PGATE
and V
NGATE
,
IN
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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Page 2
Electrical Characteristics
(Over operating supply voltage unless otherwise specified, TA = -40°C to +85°C.)
External Supplies
SymbolParameterMinTypMaxUnitConditions
V
I
PP1Q
I
PP1
V
I
NN1Q
I
NN1
V
I
DDQ
I
DD
PP1
NN1
DD
High voltage positive supply50200V
VPP quiescent current250500µAPIN=NIN=0V
VPP operating current2.0mANo load
V
OUTP
High voltage negative supplyV
V
quiescent current250500µAPIN=NIN=0V, R
NN1
V
operating current1.0mANo load
NN1
-325-50V
PP1
V
OUTP
and V
and V
switching at 100kHz
OUTN
=18kΩ
DB
switching at 100kHz
OUTN
Logic supply voltage4.505.50V
VDD quiescent current300400µAPIN=NIN=0V, R
=18kΩ
DB
VDD operating current1.0mAPIN=NIN=100kHz, R
=18kΩ
DB
HV430
Internal Supplies
SymbolParameterMinTypMaxUnitConditions
V
PP2
V
NN2
Positive linear regulator output voltageV
Negative linear regulator output voltageV
-16V
PP1
+10V
NN1
-10V
PP1
+14V
NN1
Positive High Voltage Output
SymbolParameterMinTypMaxUnitConditions
V
Pgate
R
sourceP
R
sinkP
t
riseP
t
fallP
t
pwp(min)
t
delayP
V
Psen
t
shortP
Output voltage swingV
V
source resistance12.5ΩI
Pgate
V
sink resistance12.5ΩI
Pgate
V
rise time50nsC
Pgate
V
fall time50nsC
Pgate
V
minimum pulse width
Pgate
PP2
V
PP1
VNo load on V
=80mA
OUT
=-80mA
OUT
=1.4nF
load
=1.4nF
load
(internally limited)100150200ns
PIN to Pgate delay time300nsmode=1
V
current sense voltageV
Pgate
V
current sense off time150ns
Pgate
-0.85V
PP1
-1.0V
PP1
-1.15V
PP1
Pgate
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Page 3
Negative High Voltage Output
SymbolParameterMinTypMaxUnitConditions
V
Ngate
R
sourceN
R
sinkN
t
riseN
t
fallN
t
pwn(min)
Output voltage swingV
V
source resistance15.0ΩI
Ngate
V
sink resistance15.0ΩI
Ngate
V
rise time50nsC
Ngate
V
fall time50nsC
Ngate
V
minimum pulse width
Ngate
NN2
V
NN1
VNo load on V
=80mA
OUT
=-80mA
OUT
=1.0nF
load
=1.0nF
load
(internally limited)100150200ns
t
delayN
V
t
shortN
Nsen
NIN to V
V
Ngate
V
Ngate
delay time300nsmode=1
Ngate
current sense voltageV
+0.85V
NN1
+1.0V
NN1
+1.15V
NN1
current sense OFF time150ns
Control Circuitry
SymbolParameterMinTypMaxUnitConditions
HV430
Ngate
V
IL
V
IH
I
INdn
R
up
V
OL
V
OH
V
RST(OFF)
V
RST(ON)
V
RST(HYS)
I
reset
t
RST(ON)
t
RST(OFF)
t
EN(ON)
t
EN(OFF)
t
FLT(HOLD)
t
DB
t
delay(N-P)
t
delay(P-N)
∆t
delay(N-P)
∆t
delay(P-N)
Logic input low voltage 00.60VVDD=5.0V
Logic input high voltage 2.7 5.0VVDD=5.0V
Input pull-down current0.515µAPIN, NIN, ENABLE
Input pull-up resistance100200300kΩMODE
Logic output low voltage0.50VVDD=5.0V, I
Logic output high voltage4.50VVDD=5.0V, I
=-0.5mA
OUT
=0.5mA
OUT
Reset voltage, device off3.23.5VVDD=5.0V
Reset voltage, device on3.74.0VVDD=5.0V
Reset hysteresis voltage0.3VVDD=5.0V
Reset pull-up current71013µAV
RESET
=0-4.5V
RESET on delay1.0µs
RESET off delay1.0µs
ENABLE on delay50100150µs
ENABLE off delay1.0µs
N
FAULT hold time4
Deadband time
355070nsMode=0, Rdb=5.6kΩ
IN/PIN
cycles
ENABLE=1
105140175nsMode=0, Rdb=18kΩ
N-off to P-on transistion delay300nsMode=0, Rdb<27kΩ
P-off to N-on transistion delay300nsMode=0, Rdb<27kΩ
Delay difference
t
- t
delayN(off)
delayP(on)
Delay difference
- t
t
delayP(off)
delayN(on)
-80080nsMode=1
-80080nsMode=1
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Page 4
Truth Table
Logic Inputs*Output
N
IN
P
LLHH > V
LHH H > V
HLH H > V
HHH H > V
HXL H > V
LXL H > V
XXX LXOFFOFF
XXX X < V
* Unused logic inputs should be connected to VDD or GND.
modeENRESETExternal N-ChannelExternal P-Channel
IN
MOSFETMOSFET
reset(on)
reset(on)
reset(on)
reset(on)
reset(on)
reset(on)
reset(off)
OFFOFF
OFFON
ONOFF
OFFOFF
OFFON
ONOFF
OFFOFF
HV430
Block Diagram and Application Circuit
V
DD
FAULT
MODE
DEADBAND
N
ENABLE
RESET
De-glitcher
reset
clk
P
IN
Control
Logic
IN
V
DD
10µA
+5V
V
SIG
GND
V
V
Down
Translator
Up
Translator
Up
Translator
Down
Translator
PP2
Regulator
V
NN2
Regulator
DD
PWR
GND
PP2
Current
Tr ip
P
Driver
N
Driver
Current
Tr ip
V
PP1
V
PSEN
V
PGATE
NC
NC
V
NGATE
V
NSEN
V
NN1
V
PP1
R
sense
Ringer
Output
R
sense
V
NN2
V
NN1
Note: PIN, NIN, and ENABLE are internally pulled low. MODE is internally pulled high.
A Reset capacitor in the range of 1-10µF will yield a couple-second turn-on delay. Tantalum is recommended.
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Page 5
Single-Control Mode Timing
1
N
IN
0
t
N-Pdelay
t
P-Ndelay
V
DD
GND
HV430
ON
P
OUT
OFF
t
ON
N
OUT
OFF
t
Nfall
Dual-Control Mode Timing
1
P
IN
0
t
Pdelay(on)
ON
t
Prise
N-Pdeadband
t
Ppulse(min)
t
Pdelay(off)
t
Pfall
t
P-Ndeadband
t
Nrise
V
DD
GND
V
PP2
V
PP2
V
PP1
V
NN2
V
NN1
P
N
OUT
N
IN
OUT
OFF
ON
OFF
V
t
Prise
t
Pfall
1
0
t
Ndelay(on)
t
Nrise
t
Npulse(min)
t
Ndelay(off)
t
Nfall
PP1
V
DD
GND
V
NN2
V
NN1
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Page 6
ENABLE Timing
HV430
ENABLE
NIN/P
P
OUT
N
OUT
IN
ON
OFF
ON
OFF
1
0
1
Switching
0
t
Off
Off
EN(ON)
Switching
Switching
t
EN(OFF)
Off
Off
V
DD
GND
V
DD
GND
V
PP2
V
PP1
V
NN2
V
NN1
RESET Timing
RESET
1
NIN/P
P
N
IN
0
ON
OUT
OFF
ON
OUT
OFF
t
RST(ON)
Off
Off
Switching
Switching
Switching
t
RST(OFF)
Off
Off
V
RESET(ON)
V
RESET(OFF)
GND
V
DD
GND
V
PP2
V
PP1
V
NN2
V
NN1
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Page 7
FAULT Timing
y
HV430
ENABLE
or
RESET
N
IN
P
OUT
N
OUT
ON
OFF
ON
OFF
1
0
1
0
V
DD
GND
V
DD
GND
V
PP2
V
PP1
V
NN2
V
NN1
N
SENSE
FAU LT
w/ext pull-up
Over
OK
V
GND
DD
t
FAULT(HOLD)
Note: N
overcurrent shown. P
sense
ENABLE or RESET
clears FAULT immediatel
operates identically.
sense
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Page 8
Pin Description
HV430
V
PP1
V
PP2
V
NN1
V
NN2
V
DD
Positive high voltage supply.
Positive gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be
connected between V
PP2
and V
PP1
.
Negative high voltage supply.
Negative gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be
connected between V
NN2
and V
NN1
.
Logic supply voltage.
SGndLow voltage logic ground.
PGndHigh voltage power ground.
P
IN
Logic control input. When mode is high, logic input high turns ON the external high voltage P-channel MOSFET.
Internally pulled low.
N
IN
Logic control input. When mode is high, logic input high turns ON the external high voltage N-channel MOSFET.
Internally pulled low.
ENABLELogic enable input. Logic high enables IC. Internally pulled low.
MODELogic mode input.
and P
, respectively. When MODE is low, NIN controls both outputs in a complementary manner.
OUT
0=single-control; 1=dual-control. When MODE is high, NIN and PIN independently control N
OUT
(See Truth Table)
FAULTLogic output.
Fault is at logic low when either current limit sense pin, V
Psen
or V
, is activated. Remains
Nsen
active until overcurrent condition clears or ENABLE=0 or RESET=0.
RESETPower-on reset. A capacitor connected between this pin and ground determines the delay time between application
of VDD and when the device outputs are enabled. Low leakage tantalum recommended.
DEADBAND A resistor between this pin and ground sets the ‘break-before-make’ time between output transitions.
only in single-control mode. For minimum deadtime, a 5.6kΩ resistor to ground should be used. For dual-input
mode, tie to Vdd.
V
Pgate
V
Ngate
V
Psen
V
Nsen
Gate drive for external P-channel MOSFET.
Gate drive for external N-channel MOSFET.
Pulse by pulse over current sensing for P-Channel MOSFET.
Pulse by pulse over current sensing for N-Channel MOSFET.