Datasheet HV312NG, HV302NG Datasheet (Supertex)

HV302

__________________________________________________________________________________________________________________

HV312

Initial Release

Sequencing Hotswap Controllers

(Negative Supply Rail)

Features

 -10V to 90V or +10V to +90V Operation
 Four PWRGD Flags with Programmable Delays
 Integrated “normally-on” Gate Clamp eliminates components
 UV/OV Lock Out & Power-On-Reset (POR) for Debouncing
 Sense resistor programmed Circuit Breaker & Servo Limit
 Programmable Circuit Breaker Delay
 Inrush control using either: Servo or Feedback Capacitor
 Feedback to RAMP pin saves gate protection components
 100ms Start Up Timeout Protection for Output Overload
 Programmable Inrush Current di/dt Control
 Programmable Auto-Retry (tens of seconds if desired)
 Auto-Retry or Latched Operation
 Application solution for input voltage step (diode “ORing”)
 Enable through Open Drain interface to UV or OV
 Low Power, 0.6mA Active Mode, 0.4mA Sleep Mode
 Small SOIC-14 Package

Applications

 -48V Telecom and Networking
 -24V Cellular and Fixed Wireless Systems
 -24V PBX Systems
 Power Over LAN (IEEE802.3)
 Distributed Power Systems
 Power Supply Control
 +48V Servers and SANs
 Hotswap Control of Diode ORed Multiple Power Sources
 Cooling Fan Systems

Typical Application Circuit and Waveforms

GND

-48V

14

VDD

R1

487k

6

UV

R2

6.81k
5

OV

R3

9.76k

TB TC TD

11

RTB RTC RTD

NOTES: 1. Under Voltage Shutdown (UV) set to 35V.

2. Over Voltage Shutdown (OV) set to 65V.

3. Current Limit set to -1A.

4. Circuit Breaker set to 8A.

HV302 / HV312

12 13

10nF

C1

PWRGD-D / PWRGD-D

PWRGD-C /PWRGD-C

PWRGD-B / PWRGD-B

PWRGD-A / PWRGD-A

VEE SENSE GATERAMP

810 97

R4

0.0125

________

1

________

2

________

3

________

4

Cload

100uF

C2

0.75nF ___

Q1

IRF530

___
EN / EN

DC/DC PWM
CONVERTER

___
EN / EN

DC/DC PWM
CONVERTER

___
EN / EN

DC/DC PWM
CONVERTER

EN / EN

DC/DC PWM
CONVERTER

-12V

COM

+12V

COM

+5V

COM

+3.3V

COM

General Description

The HV302 and HV312 Hotswap Controllers perform current
limiting, circuit breaker protection, over and under voltage
detection power management functions during insertion of cards or
modules into live backplanes and connectors. They may be used
in systems where active control is implemented in the negative
lead of supplies ranging from -10V to -90V or +10V to +90V.

During initial power application the external pass device is held off
by a “normally-on” circuit that clamps its gate low. Thereafter
UV/OV and power-on-reset work together to suppress gate turn on
due to contact bounce. When stable connection has been
established for the duration of a programmed time delay, the
inrush current is controlled and limited to a programmed level
using one of two possible methods; servo mode or drain to ramp
feedback capacitor mode. When charging of the load capacitor
is completed, the open drain PWRGD-A flag is asserted. Open
drain PWRGD-B, PWRGD-C and PWRGD-D flags are asserted
sequentially after the expiration of their respective programmed
time delays. Thereafter it transitions to a low power sleep mode
and continues to monitor current and input voltage. If full charging
of the load capacitor is not achieved within 100ms or the circuit
breaker is tripped at any time, the external pass device is turned
off and all four PWRGD flags are reset to the inactive state.
Thereafter a programmable auto-retry timer will hold the pass
device off to allow it to cool before resetting and initiating auto­retry. The auto-retry can be disabled using a single resistor if
desired.

1 Rev. D 04/17/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: [phone] Fax: [phone] www.supertex.com

HV302 / HV312

Absolute Maximum Ratings Ordering Information

reference to VDD pin +0.3V to -100V

V

EE

V

referenced to VEE Voltage -0.3V to +100V

PWRGD

and VOV referenced to VEE Voltage -0.3V to +12V

V

UV

Operating Ambient Temperature -40°C to +85°C
Operating Junction Temperature -40°C to +125°C
Storage Temperature Range -65°C to +150°C

Good Flags

HIGH HV302NG

LOW HV312NG

Package Options Active State of Power

14 Pin SOIC

Electrical Characteristics

Symbol Parameter Min Typ Max Units Conditions

Supply (Referenced to V

V

Supply Voltage -90 -10 V

EE

IEE Supply Current 600 700
IEE Sleep Mode Supply Current 400 450

OV and UV Control (Referenced to V

UV High Threshold 1.26 V Low to High Transition

V

UVH

V

UV Low Threshold 1.16 V High to Low Transition

UVL

V

UV Hysteresis 100 mV

UVHY

IUV UV Input Current 1.0 nA VUV = VEE + 1.9V
V

OV High Threshold 1.26 V Low to High Transition

OVH

V

OV Low Threshold 1.16 V High to Low Transition

OVL

V

OV Hysteresis 100 mV

OVHY

IOV OV Input Current 1.0 nA VOV = VEE + 0.5V

Current Limit (Referenced to V

V
V

Current Limit Threshold Voltage 40 50 60 mV VUV = VEE + 1.9V, VOV = VEE + 0.5V

SENSE-CL

Circuit Breaker Current Limit Threshold Voltage 80 100 120 mV VUV = VEE + 1.9V, VOV = VEE + 0.5V

SENSE-CB

Gate Drive Output (Referenced to V

V

Maximum Gate Drive Voltage 8.5 10 12 V VUV = VEE + 1.9V, VOV = VEE + 0.5V

GATE

I

Gate Drive Pull-Up Current 500

GATEUP

I

Gate Drive Pull-Down Current 40 mA VUV = VEE, VOV = VEE + 0.5V

GATEDOWN

Ramp Timing Control - Test Conditions: C

I

Ramp Pin Output Current 10

RAMP

t

Time from UV to Gate Turn On 2.0 ms (See Note 1)

POR

t

Time from Gate Turn On to V

RISE

t

Duration of Current Limit Mode 5.0 ms

LIMIT

t

Time from Current Limit to PWRGD-A 5.0 ms

PWRGD-A

t

Maximum Time from PWRGD-A to PWRGD-B 150 200 250 ms

PWRGD-B

t

Minimum Time from PWRGD-A to PWRGD-B 3.0 5.0 8.0 ms

PWRGD-B

t

Maximum Time from PWRGD-B to PWRGD-C 150 200 250 ms

PWRGD-C

t

Minimum Time from PWRGD-B to PWRGD-C 3.0 5.0 8.0 ms

PWRGD-C

t

Maximum Time from PWRGD-C to PWRGD-D 150 200 250 ms

PWRGD-D

t

Minimum Time from PWRGD-C to PWRGD-D 3.0 5.0 8.0 ms

PWRGD-D

V

Voltage on Ramp Pin in Current Limit Mode 3.6 V (See Note 2)

RAMP

t
t
t

Start up Time Limit 80 100 120 ms

STARTLIMIT

Circuit Breaker Delay Time 2.0 5.0

CBTRIP

Automatic Retry Delay 16 s

AUTO

DD

pin)

(-10V VIN -90V, -40°C TA +85°C unless otherwise noted)

µA
µA

pin)

EE

pin)

EE

pin)

EE

µA

=100µF, C

LOAD

=10nF, VUV = VEE + 1.9V, VOV = VEE + 0.5V, External MOSFET is IRF530*

RAMP

µA

Limit 400

SENSE

µs

µs

VEE = -48V, Mode = Limiting
VEE = -48V, Mode = Sleep

VUV = VEE + 1.9V, VOV = VEE + 0.5V

V

= 0V

SENSE

= 120kΩ

R

TB

= 3kΩ

R

TB

R

= 120kΩ

TC

= 3kΩ

R

TC

= 120kΩ

R

TD

= 3kΩ

R

TD

May be extended by external RC circuit

2 Rev. D 04/17/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: [phone] Fax: [phone] www.supertex.com

Power Good Outputs (Referenced to V

V

PWRGD-x(hi)

V

PWRGD-x(lo)

I

PWRGD-x(lk)

Power Good Pin Breakdown Voltage 90 V PWRGD-x = HI Z
Power Good Pin Output Low Voltage 0.5 0.8 V I

Maximum Leakage Current <1.0 10

Dynamic Characteristics

t

OV Comparator Transition 500 ns

GATEHLOV

t

UV Comparator Transition 500 ns

GATEHLUV

Note 1: This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this timing.
Note 2: This voltage depends on the characteristics of the external N-Channel MOSFET. V
*IRF530 is a registered trademark of International Rectifier.

Pinout

PWRGD-D (HV302)

________

PWRGD-D (HV312)

PWRGD-C (HV302)

________

PWRGD-C (HV312)

PWRGD-B (HV302)

________

PWRGD-B (HV312)

PWRGD-A (HV302)

________

PWRGD-A (HV312)

OV

UV

VEE

1

2

3

4

5

6

7

PWRGD Logic

Model Condition PWRGD-A/B/C/D

HV302

HV312

3 Rev. D 04/17/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: [phone] Fax: [phone] www.supertex.com

INACTIVE (Not Ready) 0 VEE

ACTIVE (Ready) 1 HI Z

INACTIVE (Not Ready) 1 HI Z

ACTIVE (Ready) 0 V

EE

pin)

= 1mA, PWRGD-x = LOW

PWRGD

V

µA

= 3V for an IRF530.

to

= 90V, PWRGD-x = HI Z

PWRGD

Pin Description

PWRGD-D – This Power Good Output Pin is held inactive on initial

power application and goes active a programmed time delay after

14

VDD

13

TD

12

TC

11

TB

10

RAMP

9

GATE

8

SENSE

EE

PWRGD-C goes active.

PWRGD-C – This Power Good Output Pin is held inactive on initial
power application and goes active a programmed time delay after
PWRGD-B goes active.

PWRGD-B – This Power Good Output Pin is held inactive on initial
power application and goes active a programmed time delay after
PWRGD-A goes active.

PWRGD-A – This Power Good Output Pin is held inactive on initial
power application and goes active when the external MOSFET is
fully turned on.

OV – This Over Voltage (OV) sense pin, when raised above its
high threshold will immediately cause the GATE pin to be pulled
low. The GATE pin will remain low until the voltage on this pin falls
below the low threshold limit, initiating a new start-up cycle.

UV – This Under Voltage (UV) sense pin, when below its low
threshold limit will immediately cause the GATE pin to be pulled
low. The GATE pin will remain low until the voltage on this pin
rises above the high threshold limit, initiating a new start-up cycle.

– This pin is the negative terminal of the power supply input to

V

EE

the circuit.

– This pin is the positive terminal of the power supply input to

V

DD

the circuit.

TD – The resistor connected from this pin to V

pin sets the time

EE

delay from PWRGD-C going active to PWRGD-D going active.

TC – The resistor connected from this pin to V

pin sets the time

EE

delay from PWRGD-B going active to PWRGD-C going active.

TB – The resistor connected from this pin to V

pin sets the time

EE

delay from PWRGD-A going active to PWRGD-B going active.

RAMP – This pin provides a current output so that a timing ramp
voltage is generated when a capacitor is connected.

GATE – This is the Gate Driver Output for the external N-Channel
MOSFET.

SENSE – The current sense resistor connected from this pin to V
Pin programs the servo control current limit and the circuit breaker
trip limit.

EE

Functional Block Diagram

Vint

Internal
Supply
Regulator

UVLO
and
POR

HV302 / HV312

PWRGD-D VDD

UV

OV

VEE

Band Gap
Reference

Vbg

Vbg

Programmable

Selector
Switch

Timer

Buffer

Selector
Switch

TB TC TD SENSE RAMP GATE

LOGIC

C

555 type
Auto-Retry

C

Timer

Latch High & Sleep

C

100mV

Vint-1.2V

Transconductor

gm

Vint

10uA

Transconductor

gm

2Vbg

5k 5k

Clamp Mechanism

1 : 2 Mirror

C

Circuit Breaker

PWRGD-C

PWRGD-B

PWRGD-A

Functional Description

Insertion into Hot Backplanes

Telecom, Networking, SAN and Server applications require the
ability to insert and remove circuit cards from systems without
powering down the entire system. All circuit cards have some filter
capacitance on the power rails, which is especially true in circuit
cards or network terminal equipment utilizing distributed power
systems. The insertion can result in high inrush currents that can
cause damage to connector and circuit cards and may result in
unacceptable disturbances on the system backplane power rails.

The HV302 and HV312 are designed to facilitate the insertion of
these circuit cards or connection of terminal equipment by
eliminating these inrush currents and powering up these circuits in
a controlled manner after full connector insertion has been
achieved

Description of Operation

During initial power application, a “normally-on” circuit holds off the
external MOSFET, preventing an input glitch while an integrated
regulator establishes an internal operating voltage of
approximately 10V. Until the proper internal voltage is achieved all
circuits are held reset, the PWRGD flags are inactive and the gate
to source voltage of the external MOSFET is clamped low.

Once the internal under voltage lock out (UVLO) has been
satisfied, the circuit checks the input supply under voltage (UV)
and over voltage (OV) sense circuits to ensure that the input
voltage is within programmed limits. These limits are determined
by the selected values of resistors R1, R2 and R3, which form a
voltage divider.

4 Rev. D 04/17/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: [phone] Fax: [phone] www.supertex.com

In Servo Mode operation, assuming the UV and OV limits are
satisfied and while continuing to hold the PWRGD flags inactive
and the external MOSFET GATE voltage low, the current source
feeding the RAMP pin is turned on. The external ramp capacitor
connected to it begins to charge, thus starting an initial time delay
determined by the value of the capacitor and the 2Vbg threshold
voltage of the RAMP pin. During this time if the OV or UV limits
are exceeded, an immediate reset occurs and the capacitor
connected to the RAMP pin is discharged.

When the voltage on the RAMP pin exceeds the 2Vbg threshold
voltage, the gate drive circuit begins to apply voltage to the gate of
the external MOSFET, which begins to turn on when its gate
threshold voltage is reached. The resulting output current
generates a voltage drop on the sense resistor connected between
the SENSE and V

pins, causing a decrease in the available

EE

current charging the capacitor on the RAMP pin. This continuous
feedback mechanism allows the output current to rise inverse
exponentially over a period of a few hundred microseconds to the
sense resistor programmed current limit set point.

When the voltage drop on the sense resistor reaches 50mV the
RAMP pin current is reduced to zero and the voltage on the RAMP
pin will be fixed, indicating that the circuit is in current limit mode.
Depending on the value of the load capacitor and the programmed
current limit, charging may continue for some time, but may not
exceed a nominal 100ms preset time limit. Once the load
capacitor has been charged, the output current will drop, reducing
the voltage on the SENSE pin, which in turn will increase the
RAMP pin current, thus causing the voltage on the capacitor
connected to the RAMP pin to continue rising, thereby providing
yet another programmed delay.

Functional Description - continued

In Feedback Capacitor Mode operation, assuming the UV and
OV limits are satisfied and while continuing to hold the PWRGD
flags inactive and the external MOSFET GATE voltage low, the
current source feeding the RAMP pin is turned on. The external
ramp capacitor (C
capacitor (C

) begins to discharge, thus starting an initial time

FB

delay determined by the equivalent value of the capacitors and the
2Vbg threshold voltage of the RAMP pin. During this time if the
OV or UV limits are exceeded, an immediate reset occurs, the
ramp capacitor is discharged and the feedback capacitor is
recharged.

When the voltage on the RAMP pin exceeds the 2Vbg threshold
voltage, the gate drive circuit begins to apply voltage to the gate of
the external MOSFET, which begins to turn on when its gate
threshold voltage is reached. However, the source current from
the RAMP pin limits the dv/dt of the feedback capacitor (C
which, in turn, programs the inrush current limit (I
with the relationship I
load capacitor. At this point essentially all available current from
the RAMP pin flows into the feedback capacitor, thus the voltage
on the ramp capacitor and the RAMP pin remains essentially
constant, thereby limiting and controlling the gate voltage of the
external MOSFET (See Programming Current Limit and Circuit
Breaker in Design Information section). When the load capacitor is
fully charged the current flowing into the feedback capacitor is
reduced and the voltage drop across the MOSFET essentially
drops to zero, effectively connecting the feedback capacitor in
parallel with the ramp capacitor. Now the current from the RAMP
pin flows into the parallel-connected capacitors and the voltage on
the RAMP pin begins to rise, thereby providing yet another
programmed delay.

) begins to charge and the feedback

RAMP

) in accordance

= I

RAMP

x C

LOAD/CFB

CL

CL

and thus the dv/dt of the

)

FB

HV302 / HV312

Whether operating in Servo Mode or Feedback Capacitor Mode,
when the ramp voltage is within 1.2V of the regulated internal
supply voltage, the controller will force the GATE terminal to a
nominal 10V, the PWRGD-A pin will change to an active state and
the Circuit Breaker is enabled. PWRGD-B will change to an active
state a programmed delay time after PWRGD-A went active,
PWRGD-C will change to an active state a programmed delay time
after PWRGD-B went active, PWRGD-D will change to an active
state a programmed delay time after PWRGD-C went active and
the circuit transitions to a low power sleep mode. While in sleep
mode the circuit continues to monitor the current and the OV and
UV status.

When the voltage on the SENSE pin rises to 100mV, indicating an

over current condition, the circuit breaker will trip in less than 5µs.

This time may be extended by the addition of external
components.

If due to output overload conditions during startup full charging of
the load is not achieved within 100ms or a load fault occurs at any
time the circuit breaker is tripped, the MOSFET is turned off by
pulling down the GATE to V
Thereafter an auto-retry timer, programmed by the capacitor
connected to the RAMP pin, will hold the pass device off to allow it
to cool before resetting and restarting. The auto-retry can be
disabled using a single resistor if desired (See Auto-Retry and
Auto-Retry Disable in Design Information section).

At any time during the start up cycle or thereafter, crossing the UV
and OV limits (including hysteresis) will cause an immediate reset
of all internal circuitry. When the input supply voltage returns to a
value within the programmed UV and OV limits a new start up
sequence will be immediately initiated.

and all four PWRGD flags are reset.

EE

5 Rev. D 04/17/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: [phone] Fax: [phone] www.supertex.com

Design Information

Programming Under and Over Voltage Shut Down

The UV and OV pins are connected to comparators with nominal

1.21V thresholds and 100mV of hysteresis (1.21V ± 50mV). They

are used to detect under voltage and over voltage conditions at the
input to the circuit. Whenever the OV pin rises above its high
threshold (1.26V) or the UV pin falls below its low threshold
(1.16V) the GATE voltage is immediately pulled low, the PWRGD
pin changes to its inactive state and the external capacitor
connected to the RAMP pin is discharged.

Calculations can be based on either the desired input voltage
operating limits or the input voltage shutdown limits. In the
following equations the shutdown limits are assumed.

The under voltage and over voltage shut down thresholds can be
programmed by means of the three resistor divider formed by R1,
R2 and R3. Since the input currents on the UV and OV pins are
negligible the resistor values may be calculated as follows:

V1.16VUV

×===

EEUV(off)UVLOFF

×===

V1.26VOV

EEOV(off)OVHOFF

Where V

EEUV(off)

 and V

 are Under & Over Voltage Shut

EEOV(off)

Down Threshold points.

If we select a divider current of 100µA at a nominal operating input

voltage of 50 Volts then

50V

R3R2R1 ==++

100uA

500kΩ

From the second equation for an OV shut down threshold of 65V
the value of R3 may be calculated.

×

R365

OFF

==

1.26OV
500kΩ

500KΩ1.26

R3 =

×

=

65

9.69kΩ

The closest 1% value is 9.76kΩ

From the first equation for a UV shut down threshold of 35V the
value of R2 can be calculated.

()

R3R235

+×

OFF

1.16UV

==

500KΩ

500kΩ1.16

R2 =−

×

=

35

6.81kΩ9.76kΩ

The closest 1% value is 6.81kΩ

Then

483kΩR3R2500KΩR1 =−−=

The closest 1% value is 487kΩ

R3R2

+

R3R2R1

++

R3

R3R2R1

++

HV302 / HV312

From the calculated resistor values the OV and UV start up
threshold voltages can be calculated as follows:

Where V

Up Threshold points.

Then

And

Therefore, the circuit will start when the input supply voltage is in
the range of 38.29V to 59.85V.

Under Voltage/Over Voltage Operation

V1.26VUV

EEUV(on)UVHON

V1.16VOV

EEOV(on)OVLON

EEUV(on)

EEUV(on)

EEUV(on)

EEOV(on)

EEOV(on)

 and V

1.26V

×=

1.26V

×=

×=

1.16V

×=

1.16V

 are Under & Over Voltage Start

EEOV(on)

R3R2R1

++

R3R2

+

+

++

R3R2R1

R3

9.76kΩ

R3R2

+

R3

R3R2R1

++

R3R2R1

++

×===

×===

9.76kΩ6.81kΩ487kΩ

++

9.76kΩ6.81kΩ

38.29V

=

++

9.76kΩ6.81kΩ487kΩ

59.85V

=

6 Rev. D 04/17/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: [phone] Fax: [phone] www.supertex.com

Design Information- continued

Programming Current Limit and Circuit Breaker

Feedback Capacitor Mode Operation

In this operating mode the circuit breaker trip current and the
inrush current limit can be independently programmed. In fact the
circuit breaker can be completely disabled by setting R

The circuit breaker will trip in less than 5µs when the voltage on

the SENSE pin is raised 100mV above the V

pin and the value of

EE

the sense resistor may be calculated from the following equation:

R ==

SENSE

V

CB-SENSE

I

100mV

I

CBCB

For an 8A circuit breaker:

R

SENSE

100mV

8A

==

12.5mΩ

The power rating of the sense resistor must be greater than or
equal to I

x V

CB

SENSE-CB

.

The following diagrams depict the equivalent circuitry to clarify the
feedback capacitor operation for programming the inrush current
limit.

The inrush current limit may be programmed as follows:

Choose inrush current limit, for example I

= 1A

CL

Calculate

I

SINK

×

SENSECL

=

=

k5

Ω

m5.12A1

Ω×

k5

Ω

RI

If the Circuit Breaker function is disabled by setting R
then I

= 0A. However, in this example we assume that the

SINK

Circuit Breaker function is enabled and therefore use I

A5.2

µ=

SENSE

SENSE

= 2.5µA.

SINK

= 0Ω.

= 0Ω,

HV302 / HV312

Calculate C2 (feedback capacitor) discharge current

SINK2C

If Auto-Retry is disabled an adjustment must be made to I

V

R

DISABLE

t

I

AUTO

V4

==

M5.2

Ω

A6.1

µ=

Where Vt is the maximum threshold voltage of the MOSFET.

Therefore, the adjusted value of I

is:

C2

A9.5A6.1A5.2A10I

2C

IIA10I −−µ=

AUTOSINK2C

µ=µ−µ−µ=

In this example we assume that Auto-Retry is enabled and
therefore use I

= 7.5µA.

C2

Note that

Since V

dv

across C

dt

is fixed and V

IN

2C

LOAD

=

×=I and

dt

is constant during limiting, then

RAMP

dv

across C2 as they share a common node

dt

C

LOADCL

dv

2C

and their other terminals are at fixed voltages during inrush current

I

I

limiting. Therefore,

CL2C

= or

C

2C

LOAD

2

=C .

As previously calculated and by conservation of charge on RAMP
node I

=7.5µA based on the chosen inrush current limit of I

C2

Given that C

=100µF the required value for C2 can be

LOAD

calculated.

CI

×

Therefore

2

LOAD2C

=C

=

I

CL

µ×µ

A1

Note that during initial power application the RAMP pin is voltage
protected by the capacitive AC voltage divider consisting of C
C2 and C

and the GATE pin is internally clamped.

RAMP

Servo Control Mode Operation

The circuit breaker will trip in less than 5µs when the voltage on

the SENSE pin is raised 100mV above the V
the sense resistor may be calculated from the following equation:

V

R ==

SENSE

CB-SENSE

I

100mV

I

CBCB

For a 2A circuit breaker:

R

SENSE

100mV

2A

50mΩ

==

The power rating of the sense resistor must be greater than or
equal to I

x V

CB

SENSE-CB

.

A5.7A5.2A10IA10I

µ=µ−µ=−µ=

C2

dv

×=I

dt

CI

×

LOAD2C

I

CL

F100A5.7

nF75.0

=

pin and the value of

EE

=1A.

CL

LOAD

,

7 Rev. D 04/17/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: [phone] Fax: [phone] www.supertex.com

Design Information-

continued

The inrush current limit can be calculated as follows:

I ==

CL

V

CL-SENSE

R

50mV

R

SENSESENSE

Thus the inrush current limit for a 2A circuit breaker:

50mV

I

CL

50mΩ

1A

==

Compensation components from gate to source of the external
MOSFET may be required to reduce peaking of the inrush current.

Compensation can be accomplished as follows:

1. Start with a 2nF capacitor from gate to source.

2. Increase capacitor value up to 10nF if needed.

3. If needed, add a 1kΩ resistor in series with the above

capacitor.

Servo Mode Timing

HV302 / HV312

The timing functions are defined by the following equations:

C

START

≈

t

RISE

These equations assume that the load is purely capacitive and the
following definitions apply.

C

is the external capacitor connected to the RAMP pin.

RAMP

I

is the output current from the RAMP pin, nominally

RAMP

10µA, when the voltage drop on R

V

is the internally regulated supply voltage and can range

INT

from 9V to 11V.

V

is the gate threshold voltage of the external pass

GS(th)

transistor and may be obtained from its datasheet.

V

is the external pass transistor gate-source voltage

GS(limit)

required to obtain the limit current. It is dependent on the
pass transistor’s characteristics and may be obtained from
the transfer characteristics on the transistor datasheet.

g

is the transconductance of the external pass transistor and

fs

may be obtained from its datasheet.

is the internal feedback resistor and is nominally 5KΩ.

R

FB

I

is the load current when the voltage drop on R

LIMIT

resistor is 50mV.

These equations may be used to calculate the minimum value of
C

for the most critical system performance characteristics.

RAMP

For maximum contact bounce duration protection choose a value
for t

and use the following equation:

POR

C

RAMP

If control of PWRGD active delay is the critical system parameter,
then choose a value for t

C

RAMP

RAMP

4.2t =

I

RAMP

C

RAMP

Vt =

)th(GSTH

I

RAMP

ttt +=

THSTARTPOR

C

RAMP



I

RAMP



g

fs




C

Vt ≈

INLIMIT

()

−

=

=

LOAD

I

LIMIT

+

I9.0

LIMIT

It

×

RAMPPOR

V4.2

PWRGD-A

−

−

×



R

SENSE




R

FB



C

RAMP

2.1VVt −−=

)LIMIT(GSINTAPWRGD

SENSE

)it(limGS

I

RAMP

resistor is zero.

and use the following equation:

It

RAMPAPWRGD

2.1VV

−−

)it(limGSINT

SENSE

8 Rev. D 04/17/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: [phone] Fax: [phone] www.supertex.com

HV302 / HV312

Design Information - continued

Start up Overload Protection

Start up must be achieved within a nominal 100ms as indicated by
the PWRGD-A pin transition to the active state or the circuit will
reset and an Auto-Retry will initiate. If there is an output overload
or short circuit during start up, the circuit will be in current limit
mode for the 100ms time limit (in servo mode). In feedback
capacitor mode the circuit breaker will shutdown the MOSFET
before 100ms.

Circuit Breaker Delay

The circuit breaker will trip in less than 5µs when the voltage on

the SENSE pin reaches a nominal 100mV. A resistor in series with
the SENSE pin and a capacitor connected between the SENSE
and VEE pins may be added to delay the rate of voltage rise on the
SENSE pin, thus permitting a current overshoot and delaying
Circuit Breaker activation. This method is particularly useful when
operating in Feedback Capacitor Mode. However, in Servo Mode
operation it will result in a current limit leading edge overshoot.

Auto-Retry and Auto-Retry Disable

The Auto-Retry delay time is directly proportional to the
capacitance at the RAMP pin. Auto-Retry sequence is activated
whenever the 100ms timeout is reached during start up or the
Circuit Breaker is tripped.

Auto-Retry can be approximated as a 555-timer with 2.5µA charge

up and charge down currents through 8V, to a count of 256.

Therefore,

25682

For C

t ×

−

= 10nF

RAMP

t

tryReAuto

−

××

=

=

C

RAMPtryReAuto

A5.2

µ

25682

××

A5.2

µ

s4.16nF10

=×

Due to the 2.5µA maximum charge current a resistor which draws
more than 2.5µA below 8V will disable Auto-Retry. Try to keep this
resistor as big as possible, e.g. 2.5MΩ. For most MOSFETs with
maximum Vt of 4V, this will vary the 10µA RAMP current source by

only

V4
M5.2

Ω

A6.1

µ=

PWRGD Flag Delay Programming

Shortly after current limiting ends, PWRGD-A becomes active
indicating successful completion of the Hotswap operation.
PWRGD-B will change to an active state a programmed delay time
after PWRGD-A went active, PWRGD-C will change to an active
state a programmed delay time after PWRGD-B went active and
PWRGD-D will change to an active state a programmed delay time
after PWRGD-C went active. Resistors connected from the
respective TB, TC and TD pins to V

pin are used to program the

EE

delay times between the PWRGD flags sequentially going active.

9 Rev. D 04/17/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: [phone] Fax: [phone] www.supertex.com

The following waveforms demonstrate the sequencing of the
PWRGD flags. These results were obtained with R

= 60kΩ and R

= 3kΩ

TD

= 120kΩ, R

TB

The value of the resistors determines the capacitor charging and
discharging current of a triangle wave oscillator. The oscillator
output is fed to an 8-bit counter to generate the desired time delay.

The respective delay time is defined by the following equation:

VC2255

×××

t

=

TX

I

CD

PPOSC

and

V

bg

I =

CD

R4

TX

Where t
C
V
I

= Delay Time between respective PWRGD flags

TX

= 120pF (Internal oscillator capacitor)

OSC

= 8.2V (Peak-to-Peak voltage swing of oscillator)

PP

= Charge and Discharge current of oscillator

CD

Vbg = 1.2V (Internal Band Gap Reference)
R

= Programming resistor at TB, TC or TD pin

TX

Combining the above two equations and solving for R

yields:

TX

tB

×

R

=

TX

TXbg

=

VC2040

××

PPPP

tV2.1

×

TX

V2.8pF1202040

××

6

TX

t106.0R ××=

TX

For a delay time of 200ms we get:

−

()( )

TX

36

Ω=×××=

k12010200106.0R

For a delay time of 5ms we get:

−

()()

TX

36

Ω=×××=

k3105106.0R

TC

Design Information - continued

Supported External Pass Devices

The HV302 and HV312 are designed to support N-Channel
MOSFETs and IGBTs.

Selection of External Pass Devices

The R
allowable voltage drop at maximum load (I
Hotswap action has been completed. Thus the required
continuous power dissipation rating (P
determined from the following equation:

The peak power rating (P
current level, which is always the circuit breaker trip set point (I
and on the assumption that a output is shorted. The peak power
rating may be calculated from the following equation:

Given these values an external pass transistor may be selected
from the manufacturers data sheet.

Paralleling External Pass Transistors

Due to variations in threshold voltages and transconductance
characteristics between samples of MOSFETs, reliable 50%
current sharing is not achievable. Some measure of paralleling
may be accomplished by adding resistors in series with the source
of each device; however, it will cause increased voltage drop and
power dissipation.

Paralleling of external Pass devices is not recommended!

If a sufficiently high current rated external pass transistor cannot
be found then increased current capability may be achieved by
connecting independent Hotswap circuits in parallel, since they act
as current sources during the load capacitor charging time when
the circuits are in current limit. For this application the HV302 with
active high PWRGD is recommended where the PWRGD pins of
multiple Hotswap circuits can be connected in a wired OR
configuration.

Kelvin Connection to Sense Resistor

Physical layout of the printed circuit board is critical for correct
current sensing. Ideally trace routing between the current sense
resistor and the V
as possible with zero current in the sense traces. The use of
Kelvin connection from SENSE pin and V
ends of the current sense resistor is recommended.

of the device is likely to be selected based on

DS(ON)

) of the device can be

CONT

2

IRP ×=

)ON(DSCONT

PEAK

IVP ×=

CBINPEAK

and SENSE pins should be direct and as short

EE

To Negative
Terminal of
Power Source

)MAX(LOAD

) should be based on the highest

pin to the respective

EE

To

To

SENSE

VEE

Pin

Pin

Sense Resistor

LOAD(MAX)

To Source
of MOSFET

) after the

),

CB

HV302 / HV312

10 Rev. D 04/17/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: [phone] Fax: [phone] www.supertex.com